DBGFDisas.cpp@ 41674

Last change on this file since 41674 was 41674, checked in by vboxsync, 12 years ago
DISCoreOne* -> DISCore*.
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1	/* $Id: DBGFDisas.cpp 41674 2012-06-12 20:16:31Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/vmm/dbgf.h>
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/cpum.h>
27	#include "DBGFInternal.h"
28	#include <VBox/dis.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <VBox/vmm/vm.h>
32	#include "internal/pgm.h"
33
34	#include <VBox/log.h>
35	#include <iprt/assert.h>
36	#include <iprt/string.h>
37	#include <iprt/alloca.h>
38	#include <iprt/ctype.h>
39
40
41	/*******************************************************************************
42	* Structures and Typedefs *
43	*******************************************************************************/
44	/**
45	* Structure used when disassembling and instructions in DBGF.
46	* This is used so the reader function can get the stuff it needs.
47	*/
48	typedef struct
49	{
50	/** The core structure. */
51	DISCPUSTATE Cpu;
52	/** The VM handle. */
53	PVM pVM;
54	/** The VMCPU handle. */
55	PVMCPU pVCpu;
56	/** The address space for resolving symbol. */
57	RTDBGAS hAs;
58	/** Pointer to the first byte in the segment. */
59	RTGCUINTPTR GCPtrSegBase;
60	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
61	RTGCUINTPTR GCPtrSegEnd;
62	/** The size of the segment minus 1. */
63	RTGCUINTPTR cbSegLimit;
64	/** The guest paging mode. */
65	PGMMODE enmMode;
66	/** Pointer to the current page - R3 Ptr. */
67	void const *pvPageR3;
68	/** Pointer to the current page - GC Ptr. */
69	RTGCPTR pvPageGC;
70	/** Pointer to the next instruction (relative to GCPtrSegBase). */
71	RTGCUINTPTR GCPtrNext;
72	/** The lock information that PGMPhysReleasePageMappingLock needs. */
73	PGMPAGEMAPLOCK PageMapLock;
74	/** Whether the PageMapLock is valid or not. */
75	bool fLocked;
76	/** 64 bits mode or not. */
77	bool f64Bits;
78	} DBGFDISASSTATE, *PDBGFDISASSTATE;
79
80
81	/*******************************************************************************
82	* Internal Functions *
83	*******************************************************************************/
84	static FNDISREADBYTES dbgfR3DisasInstrRead;
85
86
87
88	/**
89	* Calls the disassembler with the proper reader functions and such for disa
90	*
91	* @returns VBox status code.
92	* @param pVM VM handle
93	* @param pVCpu VMCPU handle
94	* @param pSelInfo The selector info.
95	* @param enmMode The guest paging mode.
96	* @param fFlags DBGF_DISAS_FLAGS_XXX.
97	* @param GCPtr The GC pointer (selector offset).
98	* @param pState The disas CPU state.
99	*/
100	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
101	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
102	{
103	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
104	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
105	pState->cbSegLimit = pSelInfo->cbLimit;
106	pState->enmMode = enmMode;
107	pState->pvPageGC = 0;
108	pState->pvPageR3 = NULL;
109	pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas. /
110	? DBGF_AS_RC_AND_GC_GLOBAL
111	: DBGF_AS_GLOBAL;
112	pState->pVM = pVM;
113	pState->pVCpu = pVCpu;
114	pState->fLocked = false;
115	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
116
117	DISCPUMODE enmCpuMode;
118	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
119	{
120	default:
121	AssertFailed();
122	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
123	enmCpuMode = pState->f64Bits
124	? CPUMODE_64BIT
125	: pSelInfo->u.Raw.Gen.u1DefBig
126	? CPUMODE_32BIT
127	: CPUMODE_16BIT;
128	break;
129	case DBGF_DISAS_FLAGS_16BIT_MODE:
130	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
131	enmCpuMode = CPUMODE_16BIT;
132	break;
133	case DBGF_DISAS_FLAGS_32BIT_MODE:
134	enmCpuMode = CPUMODE_32BIT;
135	break;
136	case DBGF_DISAS_FLAGS_64BIT_MODE:
137	enmCpuMode = CPUMODE_64BIT;
138	break;
139	}
140
141	uint32_t cbInstr;
142	int rc = DISInstrWithReader(GCPtr,
143	enmCpuMode,
144	dbgfR3DisasInstrRead,
145	&pState->Cpu,
146	&pState->Cpu,
147	&cbInstr);
148	if (RT_SUCCESS(rc))
149	{
150	pState->GCPtrNext = GCPtr + cbInstr;
151	return VINF_SUCCESS;
152	}
153
154	/* cleanup */
155	if (pState->fLocked)
156	{
157	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
158	pState->fLocked = false;
159	}
160	return rc;
161	}
162
163
164	#if 0
165	/**
166	* Calls the disassembler for disassembling the next instruction.
167	*
168	* @returns VBox status code.
169	* @param pState The disas CPU state.
170	*/
171	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
172	{
173	uint32_t cbInstr;
174	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
175	if (RT_SUCCESS(rc))
176	{
177	pState->GCPtrNext = GCPtr + cbInstr;
178	return VINF_SUCCESS;
179	}
180	return rc;
181	}
182	#endif
183
184
185	/**
186	* Done with the disassembler state, free associated resources.
187	*
188	* @param pState The disas CPU state ++.
189	*/
190	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
191	{
192	if (pState->fLocked)
193	{
194	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
195	pState->fLocked = false;
196	}
197	}
198
199
200	/**
201	* @callback_method_impl{FNDISREADBYTES}
202	*
203	* @remarks @a uSrcAddr is relative to the base address indicated by
204	* DBGFDISASSTATE::GCPtrSegBase.
205	*/
206	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDisState, uint8_t *pbDst, RTUINTPTR uSrcAddr, uint32_t cbToRead)
207	{
208	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDisState;
209	Assert(cbToRead > 0);
210	for (;;)
211	{
212	RTGCUINTPTR GCPtr = uSrcAddr + pState->GCPtrSegBase;
213
214	/* Need to update the page translation? */
215	if ( !pState->pvPageR3
216	\|\| (GCPtr >> PAGE_SHIFT) != (pState->pvPageGC >> PAGE_SHIFT))
217	{
218	int rc = VINF_SUCCESS;
219
220	/* translate the address */
221	pState->pvPageGC = GCPtr & PAGE_BASE_GC_MASK;
222	if (MMHyperIsInsideArea(pState->pVM, pState->pvPageGC))
223	{
224	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->pvPageGC);
225	if (!pState->pvPageR3)
226	rc = VERR_INVALID_POINTER;
227	}
228	else
229	{
230	if (pState->fLocked)
231	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
232
233	if (pState->enmMode <= PGMMODE_PROTECTED)
234	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
235	else
236	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->pvPageGC, &pState->pvPageR3, &pState->PageMapLock);
237	pState->fLocked = RT_SUCCESS_NP(rc);
238	}
239	if (RT_FAILURE(rc))
240	{
241	pState->pvPageR3 = NULL;
242	return rc;
243	}
244	}
245
246	/* check the segment limit */
247	if (!pState->f64Bits && uSrcAddr > pState->cbSegLimit)
248	return VERR_OUT_OF_SELECTOR_BOUNDS;
249
250	/* calc how much we can read */
251	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
252	if (!pState->f64Bits)
253	{
254	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
255	if (cb > cbSeg && cbSeg)
256	cb = cbSeg;
257	}
258	if (cb > cbToRead)
259	cb = cbToRead;
260
261	/* read and advance */
262	memcpy(pbDst, (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
263	cbToRead -= cb;
264	if (!cbToRead)
265	return VINF_SUCCESS;
266	pbDst += cb;
267	uSrcAddr += cb;
268	}
269	}
270
271
272	/**
273	* @copydoc FNDISGETSYMBOL
274	*/
275	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
276	{
277	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
278	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
279	DBGFADDRESS Addr;
280	RTDBGSYMBOL Sym;
281	RTGCINTPTR off;
282	int rc;
283
284	if ( DIS_FMT_SEL_IS_REG(u32Sel)
285	? DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS
286	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
287	{
288	rc = DBGFR3AddrFromSelInfoOff(pState->pVM, &Addr, pSelInfo, uAddress);
289	if (RT_SUCCESS(rc))
290	rc = DBGFR3AsSymbolByAddr(pState->pVM, pState->hAs, &Addr, &off, &Sym, NULL /phMod/);
291	}
292	else
293	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
294	if (RT_SUCCESS(rc))
295	{
296	size_t cchName = strlen(Sym.szName);
297	if (cchName >= cchBuf)
298	cchName = cchBuf - 1;
299	memcpy(pszBuf, Sym.szName, cchName);
300	pszBuf[cchName] = '\0';
301
302	*poff = off;
303	}
304
305	return rc;
306	}
307
308
309	/**
310	* Disassembles the one instruction according to the specified flags and
311	* address, internal worker executing on the EMT of the specified virtual CPU.
312	*
313	* @returns VBox status code.
314	* @param pVM The VM handle.
315	* @param pVCpu The virtual CPU handle.
316	* @param Sel The code selector. This used to determine the 32/16 bit ness and
317	* calculation of the actual instruction address.
318	* @param pGCPtr Pointer to the variable holding the code address
319	* relative to the base of Sel.
320	* @param fFlags Flags controlling where to start and how to format.
321	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
322	* @param pszOutput Output buffer.
323	* @param cbOutput Size of the output buffer.
324	* @param pcbInstr Where to return the size of the instruction.
325	*/
326	static DECLCALLBACK(int)
327	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
328	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
329	{
330	VMCPU_ASSERT_EMT(pVCpu);
331	RTGCPTR GCPtr = *pGCPtr;
332
333	/*
334	* Get the Sel and GCPtr if fFlags requests that.
335	*/
336	PCCPUMCTXCORE pCtxCore = NULL;
337	PCPUMSELREGHID pHiddenSel = NULL;
338	int rc;
339	if (fFlags & (DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_CURRENT_HYPER))
340	{
341	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
342	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
343	else
344	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
345	Sel = pCtxCore->cs;
346	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
347	GCPtr = pCtxCore->rip;
348	}
349
350	/*
351	* Read the selector info - assume no stale selectors and nasty stuff like that.
352	* Since the selector flags in the CPUMCTX structures aren't up to date unless
353	* we recently visited REM, we'll not search for the selector there.
354	*/
355	DBGFSELINFO SelInfo;
356	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
357	bool fRealModeAddress = false;
358
359	if ( pHiddenSel
360	&& ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID)
361	\|\| CPUMAreHiddenSelRegsValid(pVCpu)))
362	{
363	SelInfo.Sel = Sel;
364	SelInfo.SelGate = 0;
365	SelInfo.GCPtrBase = pHiddenSel->u64Base;
366	SelInfo.cbLimit = pHiddenSel->u32Limit;
367	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
368	? DBGFSELINFO_FLAGS_LONG_MODE
369	: enmMode != PGMMODE_REAL && (!pCtxCore \|\| !pCtxCore->eflags.Bits.u1VM)
370	? DBGFSELINFO_FLAGS_PROT_MODE
371	: DBGFSELINFO_FLAGS_REAL_MODE;
372
373	SelInfo.u.Raw.au32[0] = 0;
374	SelInfo.u.Raw.au32[1] = 0;
375	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
376	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
377	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
378	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
379	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
380	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
381	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
382	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
383	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
384	}
385	else if (Sel == DBGF_SEL_FLAT)
386	{
387	SelInfo.Sel = Sel;
388	SelInfo.SelGate = 0;
389	SelInfo.GCPtrBase = 0;
390	SelInfo.cbLimit = ~0;
391	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
392	? DBGFSELINFO_FLAGS_LONG_MODE
393	: enmMode != PGMMODE_REAL
394	? DBGFSELINFO_FLAGS_PROT_MODE
395	: DBGFSELINFO_FLAGS_REAL_MODE;
396	SelInfo.u.Raw.au32[0] = 0;
397	SelInfo.u.Raw.au32[1] = 0;
398	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
399	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
400
401	if ( (fFlags & DBGF_DISAS_FLAGS_HID_SEL_REGS_VALID)
402	\|\| CPUMAreHiddenSelRegsValid(pVCpu))
403	{ /* Assume the current CS defines the execution mode. */
404	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
405	pHiddenSel = (CPUMSELREGHID *)&pCtxCore->csHid;
406
407	SelInfo.u.Raw.Gen.u1Present = pHiddenSel->Attr.n.u1Present;
408	SelInfo.u.Raw.Gen.u1Granularity = pHiddenSel->Attr.n.u1Granularity;;
409	SelInfo.u.Raw.Gen.u1DefBig = pHiddenSel->Attr.n.u1DefBig;
410	SelInfo.u.Raw.Gen.u1Long = pHiddenSel->Attr.n.u1Long;
411	SelInfo.u.Raw.Gen.u1DescType = pHiddenSel->Attr.n.u1DescType;
412	SelInfo.u.Raw.Gen.u4Type = pHiddenSel->Attr.n.u4Type;
413	}
414	else
415	{
416	SelInfo.u.Raw.Gen.u1Present = 1;
417	SelInfo.u.Raw.Gen.u1Granularity = 1;
418	SelInfo.u.Raw.Gen.u1DefBig = 1;
419	SelInfo.u.Raw.Gen.u1DescType = 1;
420	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
421	}
422	}
423	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
424	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
425	\|\| enmMode == PGMMODE_REAL
426	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
427	)
428	)
429	{ /* V86 mode or real mode - real mode addressing */
430	SelInfo.Sel = Sel;
431	SelInfo.SelGate = 0;
432	SelInfo.GCPtrBase = Sel * 16;
433	SelInfo.cbLimit = ~0;
434	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
435	SelInfo.u.Raw.au32[0] = 0;
436	SelInfo.u.Raw.au32[1] = 0;
437	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
438	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
439	SelInfo.u.Raw.Gen.u1Present = 1;
440	SelInfo.u.Raw.Gen.u1Granularity = 1;
441	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
442	SelInfo.u.Raw.Gen.u1DescType = 1;
443	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
444	fRealModeAddress = true;
445	}
446	else
447	{
448	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
449	if (RT_FAILURE(rc))
450	{
451	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
452	return rc;
453	}
454	}
455
456	/*
457	* Disassemble it.
458	*/
459	DBGFDISASSTATE State;
460	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
461	if (RT_FAILURE(rc))
462	{
463	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
464	return rc;
465	}
466
467	/*
468	* Format it.
469	*/
470	char szBuf[512];
471	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
472	DIS_FMT_FLAGS_RELATIVE_BRANCH,
473	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
474	&SelInfo);
475
476	/*
477	* Print it to the user specified buffer.
478	*/
479	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
480	{
481	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
482	RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
483	else if (fRealModeAddress)
484	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
485	else if (Sel == DBGF_SEL_FLAT)
486	{
487	if (enmMode >= PGMMODE_AMD64)
488	RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
489	else
490	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
491	}
492	else
493	{
494	if (enmMode >= PGMMODE_AMD64)
495	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
496	else
497	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
498	}
499	}
500	else
501	{
502	uint32_t cbBits = State.Cpu.opsize;
503	uint8_t pau8Bits = (uint8_t )alloca(cbBits);
504	rc = dbgfR3DisasInstrRead(&State.Cpu, pau8Bits, GCPtr, cbBits);
505	AssertRC(rc);
506	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
507	RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
508	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
509	szBuf);
510	else if (fRealModeAddress)
511	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
512	Sel, (unsigned)GCPtr,
513	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
514	szBuf);
515	else if (Sel == DBGF_SEL_FLAT)
516	{
517	if (enmMode >= PGMMODE_AMD64)
518	RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
519	GCPtr,
520	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
521	szBuf);
522	else
523	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
524	(uint32_t)GCPtr,
525	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
526	szBuf);
527	}
528	else
529	{
530	if (enmMode >= PGMMODE_AMD64)
531	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
532	Sel, GCPtr,
533	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
534	szBuf);
535	else
536	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
537	Sel, (uint32_t)GCPtr,
538	cbBits, pau8Bits, cbBits < 8 ? (8 - cbBits) * 3 : 0, "",
539	szBuf);
540	}
541	}
542
543	if (pcbInstr)
544	*pcbInstr = State.Cpu.opsize;
545
546	dbgfR3DisasInstrDone(&State);
547	return VINF_SUCCESS;
548	}
549
550
551	/**
552	* Disassembles the one instruction according to the specified flags and address.
553	*
554	* @returns VBox status code.
555	* @param pVM VM handle.
556	* @param idCpu The ID of virtual CPU.
557	* @param Sel The code selector. This used to determine the 32/16 bit ness and
558	* calculation of the actual instruction address.
559	* @param GCPtr The code address relative to the base of Sel.
560	* @param fFlags Flags controlling where to start and how to format.
561	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
562	* @param pszOutput Output buffer. This will always be properly
563	* terminated if @a cbOutput is greater than zero.
564	* @param cbOutput Size of the output buffer.
565	* @param pcbInstr Where to return the size of the instruction.
566	*
567	* @remarks May have to switch to the EMT of the virtual CPU in order to do
568	* address conversion.
569	*/
570	VMMR3DECL(int) DBGFR3DisasInstrEx(PVM pVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
571	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
572	{
573	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
574	*pszOutput = '\0';
575	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
576	AssertReturn(idCpu < pVM->cCpus, VERR_INVALID_CPU_ID);
577	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
578	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
579
580	/*
581	* Optimize the common case where we're called on the EMT of idCpu since
582	* we're using this all the time when logging.
583	*/
584	int rc;
585	PVMCPU pVCpu = VMMGetCpu(pVM);
586	if ( pVCpu
587	&& pVCpu->idCpu == idCpu)
588	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
589	else
590	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
591	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
592	return rc;
593	}
594
595
596	/**
597	* Disassembles the current guest context instruction.
598	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
599	*
600	* @returns VBox status code.
601	* @param pVCpu VMCPU handle.
602	* @param pszOutput Output buffer. This will always be properly
603	* terminated if @a cbOutput is greater than zero.
604	* @param cbOutput Size of the output buffer.
605	*/
606	VMMR3DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
607	{
608	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
609	*pszOutput = '\0';
610	AssertReturn(pVCpu, VERR_INVALID_CONTEXT);
611	return DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, 0, 0,
612	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
613	pszOutput, cbOutput, NULL);
614	}
615
616
617	/**
618	* Disassembles the current guest context instruction and writes it to the log.
619	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
620	*
621	* @returns VBox status code.
622	* @param pVCpu VMCPU handle.
623	* @param pszPrefix Short prefix string to the disassembly string. (optional)
624	*/
625	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
626	{
627	char szBuf[256];
628	szBuf[0] = '\0';
629	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
630	if (RT_FAILURE(rc))
631	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
632	if (pszPrefix && *pszPrefix)
633	RTLogPrintf("%s-CPU%d: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
634	else
635	RTLogPrintf("%s\n", szBuf);
636	return rc;
637	}
638
639
640
641	/**
642	* Disassembles the specified guest context instruction and writes it to the log.
643	* Addresses will be attempted resolved to symbols.
644	*
645	* @returns VBox status code.
646	* @param pVM VM handle.
647	* @param pVCpu The virtual CPU handle, defaults to CPU 0 if NULL.
648	* @param Sel The code selector. This used to determine the 32/16 bit-ness and
649	* calculation of the actual instruction address.
650	* @param GCPtr The code address relative to the base of Sel.
651	*/
652	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr)
653	{
654	char szBuf[256];
655	int rc = DBGFR3DisasInstrEx(pVCpu->pVMR3, pVCpu->idCpu, Sel, GCPtr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
656	&szBuf[0], sizeof(szBuf), NULL);
657	if (RT_FAILURE(rc))
658	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
659	RTLogPrintf("%s\n", szBuf);
660	return rc;
661	}
662

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 41674

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