VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 61744

Last change on this file since 61744 was 61703, checked in by vboxsync, 9 years ago

VMX: Keep using 64-bit switcher to preserve guest CPU state on 32-bit hosts, bugref:8432 (undoing r108051).

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File size: 156.7 KB
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1/* $Id: HM.cpp 61703 2016-06-15 09:24:43Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#define LOG_GROUP LOG_GROUP_HM
39#include <VBox/vmm/cpum.h>
40#include <VBox/vmm/stam.h>
41#include <VBox/vmm/mm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/pgm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/trpm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/iom.h>
48#include <VBox/vmm/patm.h>
49#include <VBox/vmm/csam.h>
50#include <VBox/vmm/selm.h>
51#ifdef VBOX_WITH_REM
52# include <VBox/vmm/rem.h>
53#endif
54#include <VBox/vmm/hm_vmx.h>
55#include <VBox/vmm/hm_svm.h>
56#include "HMInternal.h"
57#include <VBox/vmm/vm.h>
58#include <VBox/vmm/uvm.h>
59#include <VBox/err.h>
60#include <VBox/param.h>
61
62#include <iprt/assert.h>
63#include <VBox/log.h>
64#include <iprt/asm.h>
65#include <iprt/asm-amd64-x86.h>
66#include <iprt/env.h>
67#include <iprt/thread.h>
68
69
70/*********************************************************************************************************************************
71* Global Variables *
72*********************************************************************************************************************************/
73#define EXIT_REASON(def, val, str) #def " - " #val " - " str
74#define EXIT_REASON_NIL() NULL
75/** Exit reason descriptions for VT-x, used to describe statistics. */
76static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
77{
78 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
79 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
80 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
81 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
82 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
83 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
84 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
85 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
86 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
87 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
88 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
89 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
90 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
91 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
92 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
93 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
94 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
95 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
96 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
97 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
98 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
99 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
100 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
101 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
102 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
103 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
104 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
105 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
106 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
107 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
108 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
109 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
110 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
111 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
112 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
113 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
114 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
115 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
116 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
117 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
120 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
121 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
122 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
123 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
124 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
125 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
126 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
127 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
128 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
129 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
130 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
131 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
132 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
133 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
134 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
135 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
136 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
137 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
138 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
139 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
140};
141/** Array index of the last valid VT-x exit reason. */
142#define MAX_EXITREASON_VTX 64
143
144/** A partial list of Exit reason descriptions for AMD-V, used to describe
145 * statistics.
146 *
147 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
148 * this array doesn't contain the entire set of exit reasons, we
149 * handle them via hmSvmGetSpecialExitReasonDesc(). */
150static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
151{
152 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
153 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
154 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
155 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
156 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
157 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
158 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
159 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
160 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
161 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
162 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
163 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
164 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
165 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
166 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
167 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
168 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
169 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
170 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
171 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
173 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
184 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
185 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
186 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
187 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
188 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
189 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
190 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
191 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
192 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
193 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
194 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
195 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
196 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
197 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
198 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
199 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
200 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
201 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
202 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
203 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
205 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
248 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
249 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
250 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
251 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
252 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
253 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
254 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
255 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
256 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
257 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
258 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
259 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
260 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
261 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
262 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
263 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
264 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
265 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
266 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
267 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
268 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
269 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
270 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
271 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
272 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
273 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
274 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
275 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
276 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
277 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
278 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
279 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
280 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
281 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
282 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
283 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
284 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
285 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
286 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
287 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
288 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
289 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
290 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
291 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
292 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
293 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
294};
295/** Array index of the last valid AMD-V exit reason. */
296#define MAX_EXITREASON_AMDV 141
297
298/** Special exit reasons not covered in the array above. */
299#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
300#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
301#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
302
303/**
304 * Gets the SVM exit reason if it's one of the reasons not present in the @c
305 * g_apszAmdVExitReasons array.
306 *
307 * @returns The exit reason or NULL if unknown.
308 * @param uExit The exit.
309 */
310DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
311{
312 switch (uExit)
313 {
314 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
315 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
316 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
317 }
318 return EXIT_REASON_NIL();
319}
320#undef EXIT_REASON_NIL
321#undef EXIT_REASON
322
323/** @def HMVMX_REPORT_FEATURE
324 * Reports VT-x feature to the release log.
325 *
326 * @param allowed1 Mask of allowed feature bits.
327 * @param disallowed0 Mask of disallowed feature bits.
328 * @param strdesc The description string to report.
329 * @param featflag Mask of the feature to report.
330 */
331#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
332 do { \
333 if ((allowed1) & (featflag)) \
334 { \
335 if ((disallowed0) & (featflag)) \
336 LogRel(("HM: " strdesc " (must be set)\n")); \
337 else \
338 LogRel(("HM: " strdesc "\n")); \
339 } \
340 else \
341 LogRel(("HM: " strdesc " (must be cleared)\n")); \
342 } while (0)
343
344/** @def HMVMX_REPORT_ALLOWED_FEATURE
345 * Reports an allowed VT-x feature to the release log.
346 *
347 * @param allowed1 Mask of allowed feature bits.
348 * @param strdesc The description string to report.
349 * @param featflag Mask of the feature to report.
350 */
351#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
352 do { \
353 if ((allowed1) & (featflag)) \
354 LogRel(("HM: " strdesc "\n")); \
355 else \
356 LogRel(("HM: " strdesc " not supported\n")); \
357 } while (0)
358
359/** @def HMVMX_REPORT_MSR_CAPABILITY
360 * Reports MSR feature capability.
361 *
362 * @param msrcap Mask of MSR feature bits.
363 * @param strdesc The description string to report.
364 * @param featflag Mask of the feature to report.
365 */
366#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
367 do { \
368 if ((msrcaps) & (cap)) \
369 LogRel(("HM: " strdesc "\n")); \
370 } while (0)
371
372
373/*********************************************************************************************************************************
374* Internal Functions *
375*********************************************************************************************************************************/
376static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
377static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
378static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
379static int hmR3InitCPU(PVM pVM);
380static int hmR3InitFinalizeR0(PVM pVM);
381static int hmR3InitFinalizeR0Intel(PVM pVM);
382static int hmR3InitFinalizeR0Amd(PVM pVM);
383static int hmR3TermCPU(PVM pVM);
384
385
386
387/**
388 * Initializes the HM.
389 *
390 * This reads the config and check whether VT-x or AMD-V hardware is available
391 * if configured to use it. This is one of the very first components to be
392 * initialized after CFGM, so that we can fall back to raw-mode early in the
393 * initialization process.
394 *
395 * Note that a lot of the set up work is done in ring-0 and thus postponed till
396 * the ring-3 and ring-0 callback to HMR3InitCompleted.
397 *
398 * @returns VBox status code.
399 * @param pVM The cross context VM structure.
400 *
401 * @remarks Be careful with what we call here, since most of the VMM components
402 * are uninitialized.
403 */
404VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
405{
406 LogFlow(("HMR3Init\n"));
407
408 /*
409 * Assert alignment and sizes.
410 */
411 AssertCompileMemberAlignment(VM, hm.s, 32);
412 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
413
414 /*
415 * Register the saved state data unit.
416 */
417 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
418 NULL, NULL, NULL,
419 NULL, hmR3Save, NULL,
420 NULL, hmR3Load, NULL);
421 if (RT_FAILURE(rc))
422 return rc;
423
424 /*
425 * Register info handlers.
426 */
427 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
428 DBGFINFO_FLAGS_ALL_EMTS);
429 AssertRCReturn(rc, rc);
430
431 /*
432 * Read configuration.
433 */
434 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
435
436 /*
437 * Validate the HM settings.
438 */
439 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
440 "HMForced"
441 "|EnableNestedPaging"
442 "|EnableUX"
443 "|EnableLargePages"
444 "|EnableVPID"
445 "|TPRPatchingEnabled"
446 "|64bitEnabled"
447 "|VmxPleGap"
448 "|VmxPleWindow"
449 "|SvmPauseFilter"
450 "|SvmPauseFilterThreshold"
451 "|Exclusive"
452 "|MaxResumeLoops"
453 "|UseVmxPreemptTimer",
454 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
455 if (RT_FAILURE(rc))
456 return rc;
457
458 /** @cfgm{/HM/HMForced, bool, false}
459 * Forces hardware virtualization, no falling back on raw-mode. HM must be
460 * enabled, i.e. /HMEnabled must be true. */
461 bool fHMForced;
462#ifdef VBOX_WITH_RAW_MODE
463 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
464 AssertRCReturn(rc, rc);
465 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
466 VERR_INVALID_PARAMETER);
467# if defined(RT_OS_DARWIN)
468 if (pVM->fHMEnabled)
469 fHMForced = true;
470# endif
471 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
472 VERR_INVALID_PARAMETER);
473 if (pVM->cCpus > 1)
474 fHMForced = true;
475#else /* !VBOX_WITH_RAW_MODE */
476 AssertRelease(pVM->fHMEnabled);
477 fHMForced = true;
478#endif /* !VBOX_WITH_RAW_MODE */
479
480 /** @cfgm{/HM/EnableNestedPaging, bool, false}
481 * Enables nested paging (aka extended page tables). */
482 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
483 AssertRCReturn(rc, rc);
484
485 /** @cfgm{/HM/EnableUX, bool, true}
486 * Enables the VT-x unrestricted execution feature. */
487 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
488 AssertRCReturn(rc, rc);
489
490 /** @cfgm{/HM/EnableLargePages, bool, false}
491 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
492 * page table walking and maybe better TLB hit rate in some cases. */
493 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
494 AssertRCReturn(rc, rc);
495
496 /** @cfgm{/HM/EnableVPID, bool, false}
497 * Enables the VT-x VPID feature. */
498 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
499 AssertRCReturn(rc, rc);
500
501 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
502 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
503 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
504 AssertRCReturn(rc, rc);
505
506 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
507 * Enables AMD64 cpu features.
508 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
509 * already have the support. */
510#ifdef VBOX_ENABLE_64_BITS_GUESTS
511 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
512 AssertLogRelRCReturn(rc, rc);
513#else
514 pVM->hm.s.fAllow64BitGuests = false;
515#endif
516
517 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
518 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
519 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
520 * latest PAUSE instruction to be start of a new PAUSE loop.
521 */
522 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
523 AssertRCReturn(rc, rc);
524
525 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
526 * The pause-filter exiting window in TSC ticks. When the number of ticks
527 * between the current PAUSE instruction and first PAUSE of a loop exceeds
528 * VmxPleWindow, a VM-exit is triggered.
529 *
530 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
531 */
532 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
533 AssertRCReturn(rc, rc);
534
535 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
536 * A counter that is decrement each time a PAUSE instruction is executed by the
537 * guest. When the counter is 0, a \#VMEXIT is triggered.
538 */
539 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
540 AssertRCReturn(rc, rc);
541
542 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
543 * The pause filter threshold in ticks. When the elapsed time between two
544 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
545 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
546 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
547 *
548 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
549 * pause-filter exiting.
550 */
551 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
552 AssertRCReturn(rc, rc);
553
554 /** @cfgm{/HM/Exclusive, bool}
555 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
556 * global init for each host CPU. If false, we do local init each time we wish
557 * to execute guest code.
558 *
559 * On Windows, default is false due to the higher risk of conflicts with other
560 * hypervisors.
561 *
562 * On Mac OS X, this setting is ignored since the code does not handle local
563 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
564 */
565#if defined(RT_OS_DARWIN)
566 pVM->hm.s.fGlobalInit = true;
567#else
568 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
569# if defined(RT_OS_WINDOWS)
570 false
571# else
572 true
573# endif
574 );
575 AssertLogRelRCReturn(rc, rc);
576#endif
577
578 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
579 * The number of times to resume guest execution before we forcibly return to
580 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
581 * determines the default value. */
582 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
583 AssertLogRelRCReturn(rc, rc);
584
585 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
586 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
587 * available. */
588 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
589 AssertLogRelRCReturn(rc, rc);
590
591 /*
592 * Check if VT-x or AMD-v support according to the users wishes.
593 */
594 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
595 * VERR_SVM_IN_USE. */
596 if (pVM->fHMEnabled)
597 {
598 uint32_t fCaps;
599 rc = SUPR3QueryVTCaps(&fCaps);
600 if (RT_SUCCESS(rc))
601 {
602 if (fCaps & SUPVTCAPS_AMD_V)
603 {
604 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
605 pVM->hm.s.svm.fSupported = true;
606 }
607 else if (fCaps & SUPVTCAPS_VT_X)
608 {
609 rc = SUPR3QueryVTxSupported();
610 if (RT_SUCCESS(rc))
611 {
612 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
613 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
614 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
615 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
616 pVM->hm.s.vmx.fSupported = true;
617 }
618 else
619 {
620#ifdef RT_OS_LINUX
621 const char *pszMinReq = " Linux 2.6.13 or newer required!";
622#else
623 const char *pszMinReq = "";
624#endif
625 if (fHMForced)
626 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
627
628 /* Fall back to raw-mode. */
629 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
630 pVM->fHMEnabled = false;
631 }
632 }
633 else
634 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
635 VERR_INTERNAL_ERROR_5);
636
637 /*
638 * Do we require a little bit or raw-mode for 64-bit guest execution?
639 */
640 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
641 && pVM->fHMEnabled
642 && pVM->hm.s.fAllow64BitGuests;
643
644 /*
645 * Disable nested paging and unrestricted guest execution now if they're
646 * configured so that CPUM can make decisions based on our configuration.
647 */
648 Assert(!pVM->hm.s.fNestedPaging);
649 if (pVM->hm.s.fAllowNestedPaging)
650 {
651 if (fCaps & SUPVTCAPS_NESTED_PAGING)
652 pVM->hm.s.fNestedPaging = true;
653 else
654 pVM->hm.s.fAllowNestedPaging = false;
655 }
656
657 if (fCaps & SUPVTCAPS_VT_X)
658 {
659 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
660 if (pVM->hm.s.vmx.fAllowUnrestricted)
661 {
662 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
663 && pVM->hm.s.fNestedPaging)
664 pVM->hm.s.vmx.fUnrestrictedGuest = true;
665 else
666 pVM->hm.s.vmx.fAllowUnrestricted = false;
667 }
668 }
669 }
670 else
671 {
672 const char *pszMsg;
673 switch (rc)
674 {
675 case VERR_UNSUPPORTED_CPU:
676 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
677 break;
678
679 case VERR_VMX_NO_VMX:
680 pszMsg = "VT-x is not available";
681 break;
682
683 case VERR_VMX_MSR_VMX_DISABLED:
684 pszMsg = "VT-x is disabled in the BIOS";
685 break;
686
687 case VERR_VMX_MSR_ALL_VMX_DISABLED:
688 pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
689 break;
690
691 case VERR_VMX_MSR_LOCKING_FAILED:
692 pszMsg = "Failed to enable and lock VT-x features";
693 break;
694
695 case VERR_SVM_NO_SVM:
696 pszMsg = "AMD-V is not available";
697 break;
698
699 case VERR_SVM_DISABLED:
700 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
701 break;
702
703 default:
704 pszMsg = NULL;
705 break;
706 }
707 if (fHMForced && pszMsg)
708 return VM_SET_ERROR(pVM, rc, pszMsg);
709 if (!pszMsg)
710 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
711
712 /* Fall back to raw-mode. */
713 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
714 pVM->fHMEnabled = false;
715 }
716 }
717
718 /* It's now OK to use the predicate function. */
719 pVM->fHMEnabledFixed = true;
720 return VINF_SUCCESS;
721}
722
723
724/**
725 * Initializes the per-VCPU HM.
726 *
727 * @returns VBox status code.
728 * @param pVM The cross context VM structure.
729 */
730static int hmR3InitCPU(PVM pVM)
731{
732 LogFlow(("HMR3InitCPU\n"));
733
734 if (!HMIsEnabled(pVM))
735 return VINF_SUCCESS;
736
737 for (VMCPUID i = 0; i < pVM->cCpus; i++)
738 {
739 PVMCPU pVCpu = &pVM->aCpus[i];
740 pVCpu->hm.s.fActive = false;
741 }
742
743#ifdef VBOX_WITH_STATISTICS
744 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
745 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
746 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
747 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
748 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
749#endif
750
751 /*
752 * Statistics.
753 */
754 for (VMCPUID i = 0; i < pVM->cCpus; i++)
755 {
756 PVMCPU pVCpu = &pVM->aCpus[i];
757 int rc;
758
759#ifdef VBOX_WITH_STATISTICS
760 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
761 "Profiling of RTMpPokeCpu",
762 "/PROF/CPU%d/HM/Poke", i);
763 AssertRC(rc);
764 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
765 "Profiling of poke wait",
766 "/PROF/CPU%d/HM/PokeWait", i);
767 AssertRC(rc);
768 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
769 "Profiling of poke wait when RTMpPokeCpu fails",
770 "/PROF/CPU%d/HM/PokeWaitFailed", i);
771 AssertRC(rc);
772 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
773 "Profiling of VMXR0RunGuestCode entry",
774 "/PROF/CPU%d/HM/StatEntry", i);
775 AssertRC(rc);
776 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
777 "Profiling of VMXR0RunGuestCode exit part 1",
778 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
779 AssertRC(rc);
780 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
781 "Profiling of VMXR0RunGuestCode exit part 2",
782 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
783 AssertRC(rc);
784
785 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
786 "I/O",
787 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
788 AssertRC(rc);
789 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
790 "MOV CRx",
791 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
792 AssertRC(rc);
793 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
794 "Exceptions, NMIs",
795 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
796 AssertRC(rc);
797
798 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
799 "Profiling of VMXR0LoadGuestState",
800 "/PROF/CPU%d/HM/StatLoadGuestState", i);
801 AssertRC(rc);
802 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
803 "Profiling of VMLAUNCH/VMRESUME.",
804 "/PROF/CPU%d/HM/InGC", i);
805 AssertRC(rc);
806
807# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
808 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
809 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
810 "/PROF/CPU%d/HM/Switcher3264", i);
811 AssertRC(rc);
812# endif
813
814# ifdef HM_PROFILE_EXIT_DISPATCH
815 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
816 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
817 "/PROF/CPU%d/HM/ExitDispatch", i);
818 AssertRC(rc);
819# endif
820
821#endif
822# define HM_REG_COUNTER(a, b, desc) \
823 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
824 AssertRC(rc);
825
826#ifdef VBOX_WITH_STATISTICS
827 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
828 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
829 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
830 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
831 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
832 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
833 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
834 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
835 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
836 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
837 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
839 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
840 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
841 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
842 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
843 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
844 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
845 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
846 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
847 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
848 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
849 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
850 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
851 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
852 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
853 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
854 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
855 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
856 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
857 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
858 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
859 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
860 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
861 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
862 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
863 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
864 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
865 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
866 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
867 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
868 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
869 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
870 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
871 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
872 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
873 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
874#endif
875 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
876#ifdef VBOX_WITH_STATISTICS
877 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
878 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
879 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
880 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
881 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
882
883 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
884 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
885 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
886 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
887 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
888 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
889 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
890 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
891 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
892#endif
893 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
894#ifdef VBOX_WITH_STATISTICS
895 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
896
897 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
898 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
899 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
900 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
901
902 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
903 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
904 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
905 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
906 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
907 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
908 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
909 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
910 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
911 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
912 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
913 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
914 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
915 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
916
917 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
918 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
919 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
920
921 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
922 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
923 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
924
925 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
926 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
927
928 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
929 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
930 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
932 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
933 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
934 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
935 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
936
937#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
938 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
940#endif
941
942 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
943 {
944 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
945 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
946 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
947 AssertRC(rc);
948 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
949 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
950 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
951 AssertRC(rc);
952 }
953
954#undef HM_REG_COUNTER
955
956 pVCpu->hm.s.paStatExitReason = NULL;
957
958 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
959 (void **)&pVCpu->hm.s.paStatExitReason);
960 AssertRC(rc);
961 if (RT_SUCCESS(rc))
962 {
963 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
964 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
965 {
966 if (papszDesc[j])
967 {
968 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
969 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
970 AssertRC(rc);
971 }
972 }
973 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
974 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
975 AssertRC(rc);
976 }
977 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
978# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
979 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
980# else
981 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
982# endif
983
984 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
985 AssertRCReturn(rc, rc);
986 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
987# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
988 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
989# else
990 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
991# endif
992 for (unsigned j = 0; j < 255; j++)
993 {
994 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
995 "Injected event.",
996 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
997 }
998
999#endif /* VBOX_WITH_STATISTICS */
1000 }
1001
1002#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1003 /*
1004 * Magic marker for searching in crash dumps.
1005 */
1006 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1007 {
1008 PVMCPU pVCpu = &pVM->aCpus[i];
1009
1010 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1011 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1012 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1013 }
1014#endif
1015
1016 return VINF_SUCCESS;
1017}
1018
1019
1020/**
1021 * Called when a init phase has completed.
1022 *
1023 * @returns VBox status code.
1024 * @param pVM The cross context VM structure.
1025 * @param enmWhat The phase that completed.
1026 */
1027VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1028{
1029 switch (enmWhat)
1030 {
1031 case VMINITCOMPLETED_RING3:
1032 return hmR3InitCPU(pVM);
1033 case VMINITCOMPLETED_RING0:
1034 return hmR3InitFinalizeR0(pVM);
1035 default:
1036 return VINF_SUCCESS;
1037 }
1038}
1039
1040
1041/**
1042 * Turns off normal raw mode features.
1043 *
1044 * @param pVM The cross context VM structure.
1045 */
1046static void hmR3DisableRawMode(PVM pVM)
1047{
1048 /* Reinit the paging mode to force the new shadow mode. */
1049 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1050 {
1051 PVMCPU pVCpu = &pVM->aCpus[i];
1052
1053 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1054 }
1055}
1056
1057
1058/**
1059 * Initialize VT-x or AMD-V.
1060 *
1061 * @returns VBox status code.
1062 * @param pVM The cross context VM structure.
1063 */
1064static int hmR3InitFinalizeR0(PVM pVM)
1065{
1066 int rc;
1067
1068 if (!HMIsEnabled(pVM))
1069 return VINF_SUCCESS;
1070
1071 /*
1072 * Hack to allow users to work around broken BIOSes that incorrectly set
1073 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1074 */
1075 if ( !pVM->hm.s.vmx.fSupported
1076 && !pVM->hm.s.svm.fSupported
1077 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1078 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1079 {
1080 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1081 pVM->hm.s.svm.fSupported = true;
1082 pVM->hm.s.svm.fIgnoreInUseError = true;
1083 pVM->hm.s.lLastError = VINF_SUCCESS;
1084 }
1085
1086 /*
1087 * Report ring-0 init errors.
1088 */
1089 if ( !pVM->hm.s.vmx.fSupported
1090 && !pVM->hm.s.svm.fSupported)
1091 {
1092 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1093 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1094 switch (pVM->hm.s.lLastError)
1095 {
1096 case VERR_VMX_IN_VMX_ROOT_MODE:
1097 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1098 case VERR_VMX_NO_VMX:
1099 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1100 case VERR_VMX_MSR_VMX_DISABLED:
1101 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1102 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1103 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1104 case VERR_VMX_MSR_LOCKING_FAILED:
1105 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1106 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1107 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1108 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1109 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1110
1111 case VERR_SVM_IN_USE:
1112 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1113 case VERR_SVM_NO_SVM:
1114 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1115 case VERR_SVM_DISABLED:
1116 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1117 }
1118 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1119 }
1120
1121 /*
1122 * Enable VT-x or AMD-V on all host CPUs.
1123 */
1124 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1125 if (RT_FAILURE(rc))
1126 {
1127 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1128 HMR3CheckError(pVM, rc);
1129 return rc;
1130 }
1131
1132 /*
1133 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1134 * (Main should have taken care of this already)
1135 */
1136 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
1137 if (!pVM->hm.s.fHasIoApic)
1138 {
1139 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1140 pVM->hm.s.fTprPatchingAllowed = false;
1141 }
1142
1143 /*
1144 * Do the vendor specific initialization .
1145 * .
1146 * Note! We disable release log buffering here since we're doing relatively .
1147 * lot of logging and doesn't want to hit the disk with each LogRel .
1148 * statement.
1149 */
1150 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1151 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1152 if (pVM->hm.s.vmx.fSupported)
1153 rc = hmR3InitFinalizeR0Intel(pVM);
1154 else
1155 rc = hmR3InitFinalizeR0Amd(pVM);
1156 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1157 RTLogRelSetBuffering(fOldBuffered);
1158 pVM->hm.s.fInitialized = true;
1159
1160 return rc;
1161}
1162
1163
1164/**
1165 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1166 */
1167static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1168{
1169 NOREF(pVM);
1170 NOREF(pvAllocation);
1171 NOREF(GCPhysAllocation);
1172}
1173
1174
1175/**
1176 * Finish VT-x initialization (after ring-0 init).
1177 *
1178 * @returns VBox status code.
1179 * @param pVM The cross context VM structure.
1180 */
1181static int hmR3InitFinalizeR0Intel(PVM pVM)
1182{
1183 int rc;
1184
1185 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1186 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1187
1188 uint64_t val;
1189 uint64_t zap;
1190 RTGCPHYS GCPhys = 0;
1191
1192 LogRel(("HM: Using VT-x implementation 2.0\n"));
1193 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1194 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1195 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1196 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1197 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1198 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1199 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1200 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1201 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1202 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1203 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1204 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1205 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1206 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1207
1208 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1209 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1210 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1211 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1212 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1213 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1214 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1215 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1216
1217 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1218 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1219 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1220 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1221 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1222 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1223 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1224 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1225 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1226 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1227 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1228 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1229 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1230 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1231 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1232 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1233 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1234 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1235 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1236 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1237 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1238 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1239 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1240 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1241 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1242 {
1243 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1244 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1245 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1246 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1247 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1248 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1249 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1250 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1251 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1252 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1253 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1254 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1255 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1256 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1257 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1258 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1259 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1260 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1261 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1262 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1263 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1264 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1265 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1266 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1267 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1268 }
1269
1270 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1271 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1272 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1273 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1274 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1275 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1276 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1277 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1278 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1279 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1280
1281 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1282 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1283 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1284 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1285 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1286 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1287 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1288 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1289 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1290 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1291 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1292 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1293
1294 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1295 {
1296 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1297 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1298 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1299 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1300 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1301 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1302 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1303 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1304 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1305 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1306 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1307 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1308 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1309 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1310 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1311 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1312 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1313 }
1314
1315 val = pVM->hm.s.vmx.Msrs.u64Misc;
1316 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1317 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1318 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1319 else
1320 {
1321 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1322 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1323 }
1324
1325 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1326 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1327 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1328 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1329 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1330 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1331 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1332 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1333
1334 /* Paranoia */
1335 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1336
1337 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1338 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1339 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1340 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1341
1342 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1343 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1344 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1345
1346 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1347 if (val)
1348 {
1349 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1350 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1351 }
1352
1353 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1354
1355 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1356 {
1357 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1358 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1359 }
1360
1361 /*
1362 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1363 */
1364 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1365 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1366 VERR_HM_IPE_1);
1367 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1368 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1369 && pVM->hm.s.fNestedPaging),
1370 VERR_HM_IPE_1);
1371
1372 /*
1373 * Enable VPID if configured and supported.
1374 */
1375 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1376 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1377
1378#ifdef VBOX_WITH_NEW_APIC
1379#if 0
1380 /*
1381 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1382 */
1383 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1384 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1385 pVM->hm.s.fVirtApicRegs = true;
1386
1387 /*
1388 * Enable posted-interrupt processing if supported.
1389 */
1390 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1391 * here. */
1392 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1393 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1394 pVM->hm.s.fPostedIntrs = true;
1395#endif
1396#endif
1397
1398 /*
1399 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1400 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1401 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1402 */
1403 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1404 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1405 {
1406 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1407 LogRel(("HM: Disabled RDTSCP\n"));
1408 }
1409
1410 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1411 {
1412 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1413 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1414 if (RT_SUCCESS(rc))
1415 {
1416 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1417 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1418 esp. Figure 20-5.*/
1419 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1420 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1421
1422 /* Bit set to 0 means software interrupts are redirected to the
1423 8086 program interrupt handler rather than switching to
1424 protected-mode handler. */
1425 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1426
1427 /* Allow all port IO, so that port IO instructions do not cause
1428 exceptions and would instead cause a VM-exit (based on VT-x's
1429 IO bitmap which we currently configure to always cause an exit). */
1430 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1431 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1432
1433 /*
1434 * Construct a 1024 element page directory with 4 MB pages for
1435 * the identity mapped page table used in real and protected mode
1436 * without paging with EPT.
1437 */
1438 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1439 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1440 {
1441 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1442 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1443 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1444 | X86_PDE4M_G;
1445 }
1446
1447 /* We convert it here every time as PCI regions could be reconfigured. */
1448 if (PDMVmmDevHeapIsEnabled(pVM))
1449 {
1450 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1451 AssertRCReturn(rc, rc);
1452 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1453
1454 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1455 AssertRCReturn(rc, rc);
1456 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1457 }
1458 }
1459 else
1460 {
1461 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1462 pVM->hm.s.vmx.pRealModeTSS = NULL;
1463 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1464 return VMSetError(pVM, rc, RT_SRC_POS,
1465 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1466 }
1467 }
1468
1469 LogRel((pVM->hm.s.fAllow64BitGuests
1470 ? "HM: Guest support: 32-bit and 64-bit\n"
1471 : "HM: Guest support: 32-bit only\n"));
1472
1473 /*
1474 * Call ring-0 to set up the VM.
1475 */
1476 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1477 if (rc != VINF_SUCCESS)
1478 {
1479 AssertMsgFailed(("%Rrc\n", rc));
1480 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1481 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1482 {
1483 PVMCPU pVCpu = &pVM->aCpus[i];
1484 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1485 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1486 }
1487 HMR3CheckError(pVM, rc);
1488 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1489 }
1490
1491 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1492 LogRel(("HM: Enabled VMX\n"));
1493 pVM->hm.s.vmx.fEnabled = true;
1494
1495 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1496
1497 /*
1498 * Change the CPU features.
1499 */
1500 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1501 if (pVM->hm.s.fAllow64BitGuests)
1502 {
1503 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1504 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1505 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1506 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1507 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1508 }
1509 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1510 (we reuse the host EFER in the switcher). */
1511 /** @todo this needs to be fixed properly!! */
1512 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1513 {
1514 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1515 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1516 else
1517 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1518 }
1519
1520 /*
1521 * Log configuration details.
1522 */
1523 if (pVM->hm.s.fNestedPaging)
1524 {
1525 LogRel(("HM: Enabled nested paging\n"));
1526 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1527 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1528 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1529 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1530 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1531 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1532 else
1533 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1534
1535 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1536 LogRel(("HM: Enabled unrestricted guest execution\n"));
1537
1538#if HC_ARCH_BITS == 64
1539 if (pVM->hm.s.fLargePages)
1540 {
1541 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1542 PGMSetLargePageUsage(pVM, true);
1543 LogRel(("HM: Enabled large page support\n"));
1544 }
1545#endif
1546 }
1547 else
1548 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1549
1550 if (pVM->hm.s.fVirtApicRegs)
1551 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1552
1553 if (pVM->hm.s.fPostedIntrs)
1554 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1555
1556 if (pVM->hm.s.vmx.fVpid)
1557 {
1558 LogRel(("HM: Enabled VPID\n"));
1559 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1560 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1561 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1562 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1563 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1564 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1565 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1566 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1567 else
1568 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1569 }
1570 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1571 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1572
1573 if (pVM->hm.s.vmx.fUsePreemptTimer)
1574 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1575 else
1576 LogRel(("HM: Disabled VMX-preemption timer\n"));
1577
1578 return VINF_SUCCESS;
1579}
1580
1581
1582/**
1583 * Finish AMD-V initialization (after ring-0 init).
1584 *
1585 * @returns VBox status code.
1586 * @param pVM The cross context VM structure.
1587 */
1588static int hmR3InitFinalizeR0Amd(PVM pVM)
1589{
1590 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1591
1592 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1593
1594 uint32_t u32Family;
1595 uint32_t u32Model;
1596 uint32_t u32Stepping;
1597 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1598 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1599 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1600 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1601 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1602 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1603 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1604 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1605 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1606
1607 /*
1608 * Enumerate AMD-V features.
1609 */
1610 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1611 {
1612#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1613 HMSVM_REPORT_FEATURE("NESTED_PAGING", AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1614 HMSVM_REPORT_FEATURE("LBR_VIRT", AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1615 HMSVM_REPORT_FEATURE("SVM_LOCK", AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1616 HMSVM_REPORT_FEATURE("NRIP_SAVE", AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1617 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1618 HMSVM_REPORT_FEATURE("VMCB_CLEAN", AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1619 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1620 HMSVM_REPORT_FEATURE("DECODE_ASSIST", AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1621 HMSVM_REPORT_FEATURE("PAUSE_FILTER", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1622 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1623 HMSVM_REPORT_FEATURE("AVIC", AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1624#undef HMSVM_REPORT_FEATURE
1625 };
1626
1627 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1628 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1629 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1630 {
1631 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1632 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1633 }
1634 if (fSvmFeatures)
1635 for (unsigned iBit = 0; iBit < 32; iBit++)
1636 if (RT_BIT_32(iBit) & fSvmFeatures)
1637 LogRel(("HM: Reserved bit %u\n", iBit));
1638
1639 /*
1640 * Nested paging is determined in HMR3Init, verify the sanity of that.
1641 */
1642 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1643 || (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1644 VERR_HM_IPE_1);
1645
1646#if 0
1647 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1648 * here. */
1649 if (RTR0IsPostIpiSupport())
1650 pVM->hm.s.fPostedIntrs = true;
1651#endif
1652
1653 /*
1654 * Call ring-0 to set up the VM.
1655 */
1656 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1657 if (rc != VINF_SUCCESS)
1658 {
1659 AssertMsgFailed(("%Rrc\n", rc));
1660 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1661 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1662 }
1663
1664 LogRel(("HM: Enabled SVM\n"));
1665 pVM->hm.s.svm.fEnabled = true;
1666
1667 if (pVM->hm.s.fNestedPaging)
1668 {
1669 LogRel(("HM: Enabled nested paging\n"));
1670
1671 /*
1672 * Enable large pages (2 MB) if applicable.
1673 */
1674#if HC_ARCH_BITS == 64
1675 if (pVM->hm.s.fLargePages)
1676 {
1677 PGMSetLargePageUsage(pVM, true);
1678 LogRel(("HM: Enabled large page support\n"));
1679 }
1680#endif
1681 }
1682
1683 if (pVM->hm.s.fVirtApicRegs)
1684 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1685
1686 if (pVM->hm.s.fPostedIntrs)
1687 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1688
1689 hmR3DisableRawMode(pVM);
1690
1691 /*
1692 * Change the CPU features.
1693 */
1694 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1695 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1696 if (pVM->hm.s.fAllow64BitGuests)
1697 {
1698 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1699 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1700 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1701 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1702 }
1703 /* Turn on NXE if PAE has been enabled. */
1704 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1705 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1706
1707 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1708
1709 LogRel((pVM->hm.s.fAllow64BitGuests
1710 ? "HM: Guest support: 32-bit and 64-bit\n"
1711 : "HM: Guest support: 32-bit only\n"));
1712
1713 return VINF_SUCCESS;
1714}
1715
1716
1717/**
1718 * Applies relocations to data and code managed by this
1719 * component. This function will be called at init and
1720 * whenever the VMM need to relocate it self inside the GC.
1721 *
1722 * @param pVM The cross context VM structure.
1723 */
1724VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1725{
1726 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1727
1728 /* Fetch the current paging mode during the relocate callback during state loading. */
1729 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1730 {
1731 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1732 {
1733 PVMCPU pVCpu = &pVM->aCpus[i];
1734 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1735 }
1736 }
1737#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1738 if (HMIsEnabled(pVM))
1739 {
1740 switch (PGMGetHostMode(pVM))
1741 {
1742 case PGMMODE_32_BIT:
1743 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1744 break;
1745
1746 case PGMMODE_PAE:
1747 case PGMMODE_PAE_NX:
1748 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1749 break;
1750
1751 default:
1752 AssertFailed();
1753 break;
1754 }
1755 }
1756#endif
1757 return;
1758}
1759
1760
1761/**
1762 * Notification callback which is called whenever there is a chance that a CR3
1763 * value might have changed.
1764 *
1765 * This is called by PGM.
1766 *
1767 * @param pVM The cross context VM structure.
1768 * @param pVCpu The cross context virtual CPU structure.
1769 * @param enmShadowMode New shadow paging mode.
1770 * @param enmGuestMode New guest paging mode.
1771 */
1772VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1773{
1774 /* Ignore page mode changes during state loading. */
1775 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1776 return;
1777
1778 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1779
1780 /*
1781 * If the guest left protected mode VMX execution, we'll have to be
1782 * extra careful if/when the guest switches back to protected mode.
1783 */
1784 if (enmGuestMode == PGMMODE_REAL)
1785 {
1786 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1787 pVCpu->hm.s.vmx.fWasInRealMode = true;
1788 }
1789}
1790
1791
1792/**
1793 * Terminates the HM.
1794 *
1795 * Termination means cleaning up and freeing all resources,
1796 * the VM itself is, at this point, powered off or suspended.
1797 *
1798 * @returns VBox status code.
1799 * @param pVM The cross context VM structure.
1800 */
1801VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1802{
1803 if (pVM->hm.s.vmx.pRealModeTSS)
1804 {
1805 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1806 pVM->hm.s.vmx.pRealModeTSS = 0;
1807 }
1808 hmR3TermCPU(pVM);
1809 return 0;
1810}
1811
1812
1813/**
1814 * Terminates the per-VCPU HM.
1815 *
1816 * @returns VBox status code.
1817 * @param pVM The cross context VM structure.
1818 */
1819static int hmR3TermCPU(PVM pVM)
1820{
1821 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1822 {
1823 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1824
1825#ifdef VBOX_WITH_STATISTICS
1826 if (pVCpu->hm.s.paStatExitReason)
1827 {
1828 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1829 pVCpu->hm.s.paStatExitReason = NULL;
1830 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1831 }
1832 if (pVCpu->hm.s.paStatInjectedIrqs)
1833 {
1834 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1835 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1836 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1837 }
1838#endif
1839
1840#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1841 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1842 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1843 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1844#endif
1845 }
1846 return 0;
1847}
1848
1849
1850/**
1851 * Resets a virtual CPU.
1852 *
1853 * Used by HMR3Reset and CPU hot plugging.
1854 *
1855 * @param pVCpu The cross context virtual CPU structure to reset.
1856 */
1857VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1858{
1859 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1860 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1861 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1862
1863 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1864 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1865 pVCpu->hm.s.fActive = false;
1866 pVCpu->hm.s.Event.fPending = false;
1867 pVCpu->hm.s.vmx.fWasInRealMode = true;
1868 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1869 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
1870
1871
1872
1873 /* Reset the contents of the read cache. */
1874 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1875 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1876 pCache->Read.aFieldVal[j] = 0;
1877
1878#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1879 /* Magic marker for searching in crash dumps. */
1880 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1881 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1882#endif
1883}
1884
1885
1886/**
1887 * The VM is being reset.
1888 *
1889 * For the HM component this means that any GDT/LDT/TSS monitors
1890 * needs to be removed.
1891 *
1892 * @param pVM The cross context VM structure.
1893 */
1894VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1895{
1896 LogFlow(("HMR3Reset:\n"));
1897
1898 if (HMIsEnabled(pVM))
1899 hmR3DisableRawMode(pVM);
1900
1901 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1902 {
1903 PVMCPU pVCpu = &pVM->aCpus[i];
1904
1905 HMR3ResetCpu(pVCpu);
1906 }
1907
1908 /* Clear all patch information. */
1909 pVM->hm.s.pGuestPatchMem = 0;
1910 pVM->hm.s.pFreeGuestPatchMem = 0;
1911 pVM->hm.s.cbGuestPatchMem = 0;
1912 pVM->hm.s.cPatches = 0;
1913 pVM->hm.s.PatchTree = 0;
1914 pVM->hm.s.fTPRPatchingActive = false;
1915 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1916}
1917
1918
1919/**
1920 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1921 *
1922 * @returns VBox strict status code.
1923 * @param pVM The cross context VM structure.
1924 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1925 * @param pvUser Unused.
1926 */
1927static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1928{
1929 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1930
1931 /* Only execute the handler on the VCPU the original patch request was issued. */
1932 if (pVCpu->idCpu != idCpu)
1933 return VINF_SUCCESS;
1934
1935 Log(("hmR3RemovePatches\n"));
1936 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1937 {
1938 uint8_t abInstr[15];
1939 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1940 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1941 int rc;
1942
1943#ifdef LOG_ENABLED
1944 char szOutput[256];
1945
1946 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1947 szOutput, sizeof(szOutput), NULL);
1948 if (RT_SUCCESS(rc))
1949 Log(("Patched instr: %s\n", szOutput));
1950#endif
1951
1952 /* Check if the instruction is still the same. */
1953 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1954 if (rc != VINF_SUCCESS)
1955 {
1956 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1957 continue; /* swapped out or otherwise removed; skip it. */
1958 }
1959
1960 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1961 {
1962 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1963 continue; /* skip it. */
1964 }
1965
1966 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1967 AssertRC(rc);
1968
1969#ifdef LOG_ENABLED
1970 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1971 szOutput, sizeof(szOutput), NULL);
1972 if (RT_SUCCESS(rc))
1973 Log(("Original instr: %s\n", szOutput));
1974#endif
1975 }
1976 pVM->hm.s.cPatches = 0;
1977 pVM->hm.s.PatchTree = 0;
1978 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1979 pVM->hm.s.fTPRPatchingActive = false;
1980 return VINF_SUCCESS;
1981}
1982
1983
1984/**
1985 * Worker for enabling patching in a VT-x/AMD-V guest.
1986 *
1987 * @returns VBox status code.
1988 * @param pVM The cross context VM structure.
1989 * @param idCpu VCPU to execute hmR3RemovePatches on.
1990 * @param pPatchMem Patch memory range.
1991 * @param cbPatchMem Size of the memory range.
1992 */
1993static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1994{
1995 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1996 AssertRC(rc);
1997
1998 pVM->hm.s.pGuestPatchMem = pPatchMem;
1999 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2000 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2001 return VINF_SUCCESS;
2002}
2003
2004
2005/**
2006 * Enable patching in a VT-x/AMD-V guest
2007 *
2008 * @returns VBox status code.
2009 * @param pVM The cross context VM structure.
2010 * @param pPatchMem Patch memory range.
2011 * @param cbPatchMem Size of the memory range.
2012 */
2013VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2014{
2015 VM_ASSERT_EMT(pVM);
2016 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2017 if (pVM->cCpus > 1)
2018 {
2019 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2020 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2021 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2022 AssertRC(rc);
2023 return rc;
2024 }
2025 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2026}
2027
2028
2029/**
2030 * Disable patching in a VT-x/AMD-V guest.
2031 *
2032 * @returns VBox status code.
2033 * @param pVM The cross context VM structure.
2034 * @param pPatchMem Patch memory range.
2035 * @param cbPatchMem Size of the memory range.
2036 */
2037VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2038{
2039 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2040
2041 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2042 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2043
2044 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2045 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2046 (void *)(uintptr_t)VMMGetCpuId(pVM));
2047 AssertRC(rc);
2048
2049 pVM->hm.s.pGuestPatchMem = 0;
2050 pVM->hm.s.pFreeGuestPatchMem = 0;
2051 pVM->hm.s.cbGuestPatchMem = 0;
2052 pVM->hm.s.fTPRPatchingActive = false;
2053 return VINF_SUCCESS;
2054}
2055
2056
2057/**
2058 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2059 *
2060 * @returns VBox strict status code.
2061 * @param pVM The cross context VM structure.
2062 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2063 * @param pvUser User specified CPU context.
2064 *
2065 */
2066static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2067{
2068 /*
2069 * Only execute the handler on the VCPU the original patch request was
2070 * issued. (The other CPU(s) might not yet have switched to protected
2071 * mode, nor have the correct memory context.)
2072 */
2073 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2074 if (pVCpu->idCpu != idCpu)
2075 return VINF_SUCCESS;
2076
2077 /*
2078 * We're racing other VCPUs here, so don't try patch the instruction twice
2079 * and make sure there is still room for our patch record.
2080 */
2081 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2082 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2083 if (pPatch)
2084 {
2085 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2086 return VINF_SUCCESS;
2087 }
2088 uint32_t const idx = pVM->hm.s.cPatches;
2089 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2090 {
2091 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2092 return VINF_SUCCESS;
2093 }
2094 pPatch = &pVM->hm.s.aPatches[idx];
2095
2096 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2097
2098 /*
2099 * Disassembler the instruction and get cracking.
2100 */
2101 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2102 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2103 uint32_t cbOp;
2104 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2105 AssertRC(rc);
2106 if ( rc == VINF_SUCCESS
2107 && pDis->pCurInstr->uOpcode == OP_MOV
2108 && cbOp >= 3)
2109 {
2110 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2111
2112 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2113 AssertRC(rc);
2114
2115 pPatch->cbOp = cbOp;
2116
2117 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2118 {
2119 /* write. */
2120 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2121 {
2122 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2123 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2124 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2125 }
2126 else
2127 {
2128 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2129 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2130 pPatch->uSrcOperand = pDis->Param2.uValue;
2131 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2132 }
2133 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2134 AssertRC(rc);
2135
2136 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2137 pPatch->cbNewOp = sizeof(s_abVMMCall);
2138 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2139 }
2140 else
2141 {
2142 /*
2143 * TPR Read.
2144 *
2145 * Found:
2146 * mov eax, dword [fffe0080] (5 bytes)
2147 * Check if next instruction is:
2148 * shr eax, 4
2149 */
2150 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2151
2152 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2153 uint8_t const cbOpMmio = cbOp;
2154 uint64_t const uSavedRip = pCtx->rip;
2155
2156 pCtx->rip += cbOp;
2157 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2158 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2159 pCtx->rip = uSavedRip;
2160
2161 if ( rc == VINF_SUCCESS
2162 && pDis->pCurInstr->uOpcode == OP_SHR
2163 && pDis->Param1.fUse == DISUSE_REG_GEN32
2164 && pDis->Param1.Base.idxGenReg == idxMmioReg
2165 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2166 && pDis->Param2.uValue == 4
2167 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2168 {
2169 uint8_t abInstr[15];
2170
2171 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2172 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2173 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2174 AssertRC(rc);
2175
2176 pPatch->cbOp = cbOpMmio + cbOp;
2177
2178 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2179 abInstr[0] = 0xF0;
2180 abInstr[1] = 0x0F;
2181 abInstr[2] = 0x20;
2182 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2183 for (unsigned i = 4; i < pPatch->cbOp; i++)
2184 abInstr[i] = 0x90; /* nop */
2185
2186 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2187 AssertRC(rc);
2188
2189 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2190 pPatch->cbNewOp = pPatch->cbOp;
2191 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2192
2193 Log(("Acceptable read/shr candidate!\n"));
2194 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2195 }
2196 else
2197 {
2198 pPatch->enmType = HMTPRINSTR_READ;
2199 pPatch->uDstOperand = idxMmioReg;
2200
2201 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2202 AssertRC(rc);
2203
2204 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2205 pPatch->cbNewOp = sizeof(s_abVMMCall);
2206 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2207 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2208 }
2209 }
2210
2211 pPatch->Core.Key = pCtx->eip;
2212 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2213 AssertRC(rc);
2214
2215 pVM->hm.s.cPatches++;
2216 return VINF_SUCCESS;
2217 }
2218
2219 /*
2220 * Save invalid patch, so we will not try again.
2221 */
2222 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2223 pPatch->Core.Key = pCtx->eip;
2224 pPatch->enmType = HMTPRINSTR_INVALID;
2225 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2226 AssertRC(rc);
2227 pVM->hm.s.cPatches++;
2228 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2229 return VINF_SUCCESS;
2230}
2231
2232
2233/**
2234 * Callback to patch a TPR instruction (jump to generated code).
2235 *
2236 * @returns VBox strict status code.
2237 * @param pVM The cross context VM structure.
2238 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2239 * @param pvUser User specified CPU context.
2240 *
2241 */
2242static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2243{
2244 /*
2245 * Only execute the handler on the VCPU the original patch request was
2246 * issued. (The other CPU(s) might not yet have switched to protected
2247 * mode, nor have the correct memory context.)
2248 */
2249 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2250 if (pVCpu->idCpu != idCpu)
2251 return VINF_SUCCESS;
2252
2253 /*
2254 * We're racing other VCPUs here, so don't try patch the instruction twice
2255 * and make sure there is still room for our patch record.
2256 */
2257 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2258 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2259 if (pPatch)
2260 {
2261 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2262 return VINF_SUCCESS;
2263 }
2264 uint32_t const idx = pVM->hm.s.cPatches;
2265 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2266 {
2267 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2268 return VINF_SUCCESS;
2269 }
2270 pPatch = &pVM->hm.s.aPatches[idx];
2271
2272 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2273 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2274
2275 /*
2276 * Disassemble the instruction and get cracking.
2277 */
2278 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2279 uint32_t cbOp;
2280 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2281 AssertRC(rc);
2282 if ( rc == VINF_SUCCESS
2283 && pDis->pCurInstr->uOpcode == OP_MOV
2284 && cbOp >= 5)
2285 {
2286 uint8_t aPatch[64];
2287 uint32_t off = 0;
2288
2289 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2290 AssertRC(rc);
2291
2292 pPatch->cbOp = cbOp;
2293 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2294
2295 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2296 {
2297 /*
2298 * TPR write:
2299 *
2300 * push ECX [51]
2301 * push EDX [52]
2302 * push EAX [50]
2303 * xor EDX,EDX [31 D2]
2304 * mov EAX,EAX [89 C0]
2305 * or
2306 * mov EAX,0000000CCh [B8 CC 00 00 00]
2307 * mov ECX,0C0000082h [B9 82 00 00 C0]
2308 * wrmsr [0F 30]
2309 * pop EAX [58]
2310 * pop EDX [5A]
2311 * pop ECX [59]
2312 * jmp return_address [E9 return_address]
2313 *
2314 */
2315 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2316
2317 aPatch[off++] = 0x51; /* push ecx */
2318 aPatch[off++] = 0x52; /* push edx */
2319 if (!fUsesEax)
2320 aPatch[off++] = 0x50; /* push eax */
2321 aPatch[off++] = 0x31; /* xor edx, edx */
2322 aPatch[off++] = 0xD2;
2323 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2324 {
2325 if (!fUsesEax)
2326 {
2327 aPatch[off++] = 0x89; /* mov eax, src_reg */
2328 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2329 }
2330 }
2331 else
2332 {
2333 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2334 aPatch[off++] = 0xB8; /* mov eax, immediate */
2335 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2336 off += sizeof(uint32_t);
2337 }
2338 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2339 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2340 off += sizeof(uint32_t);
2341
2342 aPatch[off++] = 0x0F; /* wrmsr */
2343 aPatch[off++] = 0x30;
2344 if (!fUsesEax)
2345 aPatch[off++] = 0x58; /* pop eax */
2346 aPatch[off++] = 0x5A; /* pop edx */
2347 aPatch[off++] = 0x59; /* pop ecx */
2348 }
2349 else
2350 {
2351 /*
2352 * TPR read:
2353 *
2354 * push ECX [51]
2355 * push EDX [52]
2356 * push EAX [50]
2357 * mov ECX,0C0000082h [B9 82 00 00 C0]
2358 * rdmsr [0F 32]
2359 * mov EAX,EAX [89 C0]
2360 * pop EAX [58]
2361 * pop EDX [5A]
2362 * pop ECX [59]
2363 * jmp return_address [E9 return_address]
2364 *
2365 */
2366 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2367
2368 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2369 aPatch[off++] = 0x51; /* push ecx */
2370 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2371 aPatch[off++] = 0x52; /* push edx */
2372 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2373 aPatch[off++] = 0x50; /* push eax */
2374
2375 aPatch[off++] = 0x31; /* xor edx, edx */
2376 aPatch[off++] = 0xD2;
2377
2378 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2379 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2380 off += sizeof(uint32_t);
2381
2382 aPatch[off++] = 0x0F; /* rdmsr */
2383 aPatch[off++] = 0x32;
2384
2385 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2386 {
2387 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2388 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2389 }
2390
2391 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2392 aPatch[off++] = 0x58; /* pop eax */
2393 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2394 aPatch[off++] = 0x5A; /* pop edx */
2395 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2396 aPatch[off++] = 0x59; /* pop ecx */
2397 }
2398 aPatch[off++] = 0xE9; /* jmp return_address */
2399 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2400 off += sizeof(RTRCUINTPTR);
2401
2402 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2403 {
2404 /* Write new code to the patch buffer. */
2405 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2406 AssertRC(rc);
2407
2408#ifdef LOG_ENABLED
2409 uint32_t cbCurInstr;
2410 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2411 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2412 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2413 {
2414 char szOutput[256];
2415 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2416 szOutput, sizeof(szOutput), &cbCurInstr);
2417 if (RT_SUCCESS(rc))
2418 Log(("Patch instr %s\n", szOutput));
2419 else
2420 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2421 }
2422#endif
2423
2424 pPatch->aNewOpcode[0] = 0xE9;
2425 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2426
2427 /* Overwrite the TPR instruction with a jump. */
2428 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2429 AssertRC(rc);
2430
2431 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2432
2433 pVM->hm.s.pFreeGuestPatchMem += off;
2434 pPatch->cbNewOp = 5;
2435
2436 pPatch->Core.Key = pCtx->eip;
2437 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2438 AssertRC(rc);
2439
2440 pVM->hm.s.cPatches++;
2441 pVM->hm.s.fTPRPatchingActive = true;
2442 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2443 return VINF_SUCCESS;
2444 }
2445
2446 Log(("Ran out of space in our patch buffer!\n"));
2447 }
2448 else
2449 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2450
2451
2452 /*
2453 * Save invalid patch, so we will not try again.
2454 */
2455 pPatch = &pVM->hm.s.aPatches[idx];
2456 pPatch->Core.Key = pCtx->eip;
2457 pPatch->enmType = HMTPRINSTR_INVALID;
2458 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2459 AssertRC(rc);
2460 pVM->hm.s.cPatches++;
2461 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2462 return VINF_SUCCESS;
2463}
2464
2465
2466/**
2467 * Attempt to patch TPR mmio instructions.
2468 *
2469 * @returns VBox status code.
2470 * @param pVM The cross context VM structure.
2471 * @param pVCpu The cross context virtual CPU structure.
2472 * @param pCtx Pointer to the guest CPU context.
2473 */
2474VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2475{
2476 NOREF(pCtx);
2477 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2478 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2479 (void *)(uintptr_t)pVCpu->idCpu);
2480 AssertRC(rc);
2481 return rc;
2482}
2483
2484
2485/**
2486 * Checks if a code selector (CS) is suitable for execution
2487 * within VMX when unrestricted execution isn't available.
2488 *
2489 * @returns true if selector is suitable for VMX, otherwise
2490 * false.
2491 * @param pSel Pointer to the selector to check (CS).
2492 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2493 */
2494static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2495{
2496 /*
2497 * Segment must be an accessed code segment, it must be present and it must
2498 * be usable.
2499 * Note! These are all standard requirements and if CS holds anything else
2500 * we've got buggy code somewhere!
2501 */
2502 AssertCompile(X86DESCATTR_TYPE == 0xf);
2503 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2504 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2505 ("%#x\n", pSel->Attr.u),
2506 false);
2507
2508 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2509 must equal SS.DPL for non-confroming segments.
2510 Note! This is also a hard requirement like above. */
2511 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2512 ? pSel->Attr.n.u2Dpl <= uStackDpl
2513 : pSel->Attr.n.u2Dpl == uStackDpl,
2514 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2515 false);
2516
2517 /*
2518 * The following two requirements are VT-x specific:
2519 * - G bit must be set if any high limit bits are set.
2520 * - G bit must be clear if any low limit bits are clear.
2521 */
2522 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2523 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2524 return true;
2525 return false;
2526}
2527
2528
2529/**
2530 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2531 * execution within VMX when unrestricted execution isn't
2532 * available.
2533 *
2534 * @returns true if selector is suitable for VMX, otherwise
2535 * false.
2536 * @param pSel Pointer to the selector to check
2537 * (DS/ES/FS/GS).
2538 */
2539static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2540{
2541 /*
2542 * Unusable segments are OK. These days they should be marked as such, as
2543 * but as an alternative we for old saved states and AMD<->VT-x migration
2544 * we also treat segments with all the attributes cleared as unusable.
2545 */
2546 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2547 return true;
2548
2549 /** @todo tighten these checks. Will require CPUM load adjusting. */
2550
2551 /* Segment must be accessed. */
2552 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2553 {
2554 /* Code segments must also be readable. */
2555 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2556 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2557 {
2558 /* The S bit must be set. */
2559 if (pSel->Attr.n.u1DescType)
2560 {
2561 /* Except for conforming segments, DPL >= RPL. */
2562 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2563 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2564 {
2565 /* Segment must be present. */
2566 if (pSel->Attr.n.u1Present)
2567 {
2568 /*
2569 * The following two requirements are VT-x specific:
2570 * - G bit must be set if any high limit bits are set.
2571 * - G bit must be clear if any low limit bits are clear.
2572 */
2573 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2574 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2575 return true;
2576 }
2577 }
2578 }
2579 }
2580 }
2581
2582 return false;
2583}
2584
2585
2586/**
2587 * Checks if the stack selector (SS) is suitable for execution
2588 * within VMX when unrestricted execution isn't available.
2589 *
2590 * @returns true if selector is suitable for VMX, otherwise
2591 * false.
2592 * @param pSel Pointer to the selector to check (SS).
2593 */
2594static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2595{
2596 /*
2597 * Unusable segments are OK. These days they should be marked as such, as
2598 * but as an alternative we for old saved states and AMD<->VT-x migration
2599 * we also treat segments with all the attributes cleared as unusable.
2600 */
2601 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2602 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2603 return true;
2604
2605 /*
2606 * Segment must be an accessed writable segment, it must be present.
2607 * Note! These are all standard requirements and if SS holds anything else
2608 * we've got buggy code somewhere!
2609 */
2610 AssertCompile(X86DESCATTR_TYPE == 0xf);
2611 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2612 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2613 ("%#x\n", pSel->Attr.u),
2614 false);
2615
2616 /* DPL must equal RPL.
2617 Note! This is also a hard requirement like above. */
2618 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2619 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2620 false);
2621
2622 /*
2623 * The following two requirements are VT-x specific:
2624 * - G bit must be set if any high limit bits are set.
2625 * - G bit must be clear if any low limit bits are clear.
2626 */
2627 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2628 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2629 return true;
2630 return false;
2631}
2632
2633
2634/**
2635 * Force execution of the current IO code in the recompiler.
2636 *
2637 * @returns VBox status code.
2638 * @param pVM The cross context VM structure.
2639 * @param pCtx Partial VM execution context.
2640 */
2641VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2642{
2643 PVMCPU pVCpu = VMMGetCpu(pVM);
2644
2645 Assert(HMIsEnabled(pVM));
2646 Log(("HMR3EmulateIoBlock\n"));
2647
2648 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2649 if (HMCanEmulateIoBlockEx(pCtx))
2650 {
2651 Log(("HMR3EmulateIoBlock -> enabled\n"));
2652 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2653 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2654 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2655 return VINF_EM_RESCHEDULE_REM;
2656 }
2657 return VINF_SUCCESS;
2658}
2659
2660
2661/**
2662 * Checks if we can currently use hardware accelerated raw mode.
2663 *
2664 * @returns true if we can currently use hardware acceleration, otherwise false.
2665 * @param pVM The cross context VM structure.
2666 * @param pCtx Partial VM execution context.
2667 */
2668VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2669{
2670 PVMCPU pVCpu = VMMGetCpu(pVM);
2671
2672 Assert(HMIsEnabled(pVM));
2673
2674 /* If we're still executing the IO code, then return false. */
2675 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2676 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2677 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2678 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2679 return false;
2680
2681 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2682
2683 /* AMD-V supports real & protected mode with or without paging. */
2684 if (pVM->hm.s.svm.fEnabled)
2685 {
2686 pVCpu->hm.s.fActive = true;
2687 return true;
2688 }
2689
2690 pVCpu->hm.s.fActive = false;
2691
2692 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2693 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2694 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2695
2696 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2697 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2698 {
2699 /*
2700 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2701 * guest execution feature is missing (VT-x only).
2702 */
2703 if (fSupportsRealMode)
2704 {
2705 if (CPUMIsGuestInRealModeEx(pCtx))
2706 {
2707 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2708 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2709 * If this is not true, we cannot execute real mode as V86 and have to fall
2710 * back to emulation.
2711 */
2712 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2713 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2714 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2715 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2716 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2717 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2718 {
2719 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2720 return false;
2721 }
2722 if ( (pCtx->cs.u32Limit != 0xffff)
2723 || (pCtx->ds.u32Limit != 0xffff)
2724 || (pCtx->es.u32Limit != 0xffff)
2725 || (pCtx->ss.u32Limit != 0xffff)
2726 || (pCtx->fs.u32Limit != 0xffff)
2727 || (pCtx->gs.u32Limit != 0xffff))
2728 {
2729 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2730 return false;
2731 }
2732 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2733 }
2734 else
2735 {
2736 /* Verify the requirements for executing code in protected
2737 mode. VT-x can't handle the CPU state right after a switch
2738 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2739 if (pVCpu->hm.s.vmx.fWasInRealMode)
2740 {
2741 /** @todo If guest is in V86 mode, these checks should be different! */
2742 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2743 {
2744 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2745 return false;
2746 }
2747 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2748 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2749 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2750 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2751 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2752 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2753 {
2754 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2755 return false;
2756 }
2757 }
2758 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2759 if (pCtx->gdtr.cbGdt)
2760 {
2761 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2762 {
2763 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2764 return false;
2765 }
2766 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2767 {
2768 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2769 return false;
2770 }
2771 }
2772 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2773 }
2774 }
2775 else
2776 {
2777 if ( !CPUMIsGuestInLongModeEx(pCtx)
2778 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2779 {
2780 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2781 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2782 return false;
2783
2784 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2785 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2786 return false;
2787
2788 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2789 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2790 * hidden registers (possible recompiler bug; see load_seg_vm) */
2791 if (pCtx->cs.Attr.n.u1Present == 0)
2792 return false;
2793 if (pCtx->ss.Attr.n.u1Present == 0)
2794 return false;
2795
2796 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2797 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2798 /** @todo This check is actually wrong, it doesn't take the direction of the
2799 * stack segment into account. But, it does the job for now. */
2800 if (pCtx->rsp >= pCtx->ss.u32Limit)
2801 return false;
2802 }
2803 }
2804 }
2805
2806 if (pVM->hm.s.vmx.fEnabled)
2807 {
2808 uint32_t mask;
2809
2810 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2811 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2812 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2813 mask &= ~X86_CR0_NE;
2814
2815 if (fSupportsRealMode)
2816 {
2817 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2818 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2819 }
2820 else
2821 {
2822 /* We support protected mode without paging using identity mapping. */
2823 mask &= ~X86_CR0_PG;
2824 }
2825 if ((pCtx->cr0 & mask) != mask)
2826 return false;
2827
2828 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2829 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2830 if ((pCtx->cr0 & mask) != 0)
2831 return false;
2832
2833 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2834 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2835 mask &= ~X86_CR4_VMXE;
2836 if ((pCtx->cr4 & mask) != mask)
2837 return false;
2838
2839 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2840 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2841 if ((pCtx->cr4 & mask) != 0)
2842 return false;
2843
2844 pVCpu->hm.s.fActive = true;
2845 return true;
2846 }
2847
2848 return false;
2849}
2850
2851
2852/**
2853 * Checks if we need to reschedule due to VMM device heap changes.
2854 *
2855 * @returns true if a reschedule is required, otherwise false.
2856 * @param pVM The cross context VM structure.
2857 * @param pCtx VM execution context.
2858 */
2859VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2860{
2861 /*
2862 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2863 * when the unrestricted guest execution feature is missing (VT-x only).
2864 */
2865 if ( pVM->hm.s.vmx.fEnabled
2866 && !pVM->hm.s.vmx.fUnrestrictedGuest
2867 && CPUMIsGuestInRealModeEx(pCtx)
2868 && !PDMVmmDevHeapIsEnabled(pVM))
2869 {
2870 return true;
2871 }
2872
2873 return false;
2874}
2875
2876
2877/**
2878 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2879 * event settings changes.
2880 *
2881 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2882 * function is just updating the VM globals.
2883 *
2884 * @param pVM The VM cross context VM structure.
2885 * @thread EMT(0)
2886 */
2887VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2888{
2889 /* Interrupts. */
2890 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2891 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2892
2893 /* CPU Exceptions. */
2894 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2895 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2896 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2897 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2898
2899 /* Common VM exits. */
2900 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2901 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2902 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2903 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2904
2905 /* Vendor specific VM exits. */
2906 if (HMR3IsVmxEnabled(pVM->pUVM))
2907 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2908 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2909 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2910 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2911 else
2912 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2913 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2914 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2915 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2916
2917 /* Done. */
2918 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2919}
2920
2921
2922/**
2923 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2924 *
2925 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2926 * per CPU settings.
2927 *
2928 * @param pVM The VM cross context VM structure.
2929 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2930 */
2931VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2932{
2933 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2934}
2935
2936
2937/**
2938 * Notification from EM about a rescheduling into hardware assisted execution
2939 * mode.
2940 *
2941 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2942 */
2943VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2944{
2945 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2946}
2947
2948
2949/**
2950 * Notification from EM about returning from instruction emulation (REM / EM).
2951 *
2952 * @param pVCpu The cross context virtual CPU structure.
2953 */
2954VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2955{
2956 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2957}
2958
2959
2960/**
2961 * Checks if we are currently using hardware acceleration.
2962 *
2963 * @returns true if hardware acceleration is being used, otherwise false.
2964 * @param pVCpu The cross context virtual CPU structure.
2965 */
2966VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2967{
2968 return pVCpu->hm.s.fActive;
2969}
2970
2971
2972/**
2973 * External interface for querying whether hardware acceleration is enabled.
2974 *
2975 * @returns true if VT-x or AMD-V is being used, otherwise false.
2976 * @param pUVM The user mode VM handle.
2977 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2978 */
2979VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2980{
2981 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2982 PVM pVM = pUVM->pVM;
2983 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2984 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2985}
2986
2987
2988/**
2989 * External interface for querying whether VT-x is being used.
2990 *
2991 * @returns true if VT-x is being used, otherwise false.
2992 * @param pUVM The user mode VM handle.
2993 * @sa HMR3IsSvmEnabled, HMIsEnabled
2994 */
2995VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2996{
2997 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2998 PVM pVM = pUVM->pVM;
2999 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3000 return pVM->hm.s.vmx.fEnabled
3001 && pVM->hm.s.vmx.fSupported
3002 && pVM->fHMEnabled;
3003}
3004
3005
3006/**
3007 * External interface for querying whether AMD-V is being used.
3008 *
3009 * @returns true if VT-x is being used, otherwise false.
3010 * @param pUVM The user mode VM handle.
3011 * @sa HMR3IsVmxEnabled, HMIsEnabled
3012 */
3013VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3014{
3015 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3016 PVM pVM = pUVM->pVM;
3017 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3018 return pVM->hm.s.svm.fEnabled
3019 && pVM->hm.s.svm.fSupported
3020 && pVM->fHMEnabled;
3021}
3022
3023
3024/**
3025 * Checks if we are currently using nested paging.
3026 *
3027 * @returns true if nested paging is being used, otherwise false.
3028 * @param pUVM The user mode VM handle.
3029 */
3030VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3031{
3032 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3033 PVM pVM = pUVM->pVM;
3034 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3035 return pVM->hm.s.fNestedPaging;
3036}
3037
3038
3039/**
3040 * Checks if virtualized APIC registers is enabled.
3041 *
3042 * When enabled this feature allows the hardware to access most of the
3043 * APIC registers in the virtual-APIC page without causing VM-exits. See
3044 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3045 *
3046 * @returns true if virtualized APIC registers is enabled, otherwise
3047 * false.
3048 * @param pUVM The user mode VM handle.
3049 */
3050VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3051{
3052 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3053 PVM pVM = pUVM->pVM;
3054 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3055 return pVM->hm.s.fVirtApicRegs;
3056}
3057
3058
3059/**
3060 * Checks if APIC posted-interrupt processing is enabled.
3061 *
3062 * This returns whether we can deliver interrupts to the guest without
3063 * leaving guest-context by updating APIC state from host-context.
3064 *
3065 * @returns true if APIC posted-interrupt processing is enabled,
3066 * otherwise false.
3067 * @param pUVM The user mode VM handle.
3068 */
3069VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3070{
3071 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3072 PVM pVM = pUVM->pVM;
3073 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3074 return pVM->hm.s.fPostedIntrs;
3075}
3076
3077
3078/**
3079 * Checks if we are currently using VPID in VT-x mode.
3080 *
3081 * @returns true if VPID is being used, otherwise false.
3082 * @param pUVM The user mode VM handle.
3083 */
3084VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3085{
3086 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3087 PVM pVM = pUVM->pVM;
3088 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3089 return pVM->hm.s.vmx.fVpid;
3090}
3091
3092
3093/**
3094 * Checks if we are currently using VT-x unrestricted execution,
3095 * aka UX.
3096 *
3097 * @returns true if UX is being used, otherwise false.
3098 * @param pUVM The user mode VM handle.
3099 */
3100VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3101{
3102 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3103 PVM pVM = pUVM->pVM;
3104 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3105 return pVM->hm.s.vmx.fUnrestrictedGuest;
3106}
3107
3108
3109/**
3110 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3111 *
3112 * @returns true if an internal event is pending, otherwise false.
3113 * @param pVCpu The cross context virtual CPU structure.
3114 */
3115VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3116{
3117 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3118}
3119
3120
3121/**
3122 * Checks if the VMX-preemption timer is being used.
3123 *
3124 * @returns true if the VMX-preemption timer is being used, otherwise false.
3125 * @param pVM The cross context VM structure.
3126 */
3127VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3128{
3129 return HMIsEnabled(pVM)
3130 && pVM->hm.s.vmx.fEnabled
3131 && pVM->hm.s.vmx.fUsePreemptTimer;
3132}
3133
3134
3135/**
3136 * Restart an I/O instruction that was refused in ring-0
3137 *
3138 * @returns Strict VBox status code. Informational status codes other than the one documented
3139 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3140 * @retval VINF_SUCCESS Success.
3141 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3142 * status code must be passed on to EM.
3143 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3144 *
3145 * @param pVM The cross context VM structure.
3146 * @param pVCpu The cross context virtual CPU structure.
3147 * @param pCtx Pointer to the guest CPU context.
3148 */
3149VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3150{
3151 /*
3152 * Check if we've got relevant data pending.
3153 */
3154 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3155 if (enmType == HMPENDINGIO_INVALID)
3156 return VERR_NOT_FOUND;
3157 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3158 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3159 return VERR_NOT_FOUND;
3160
3161 /*
3162 * Execute pending I/O.
3163 */
3164 VBOXSTRICTRC rcStrict;
3165 switch (enmType)
3166 {
3167 case HMPENDINGIO_PORT_READ:
3168 {
3169 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3170 uint32_t u32Val = 0;
3171
3172 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3173 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3174 if (IOM_SUCCESS(rcStrict))
3175 {
3176 /* Write back to the EAX register. */
3177 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3178 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3179 }
3180 break;
3181 }
3182
3183 default:
3184 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3185 }
3186
3187 if (IOM_SUCCESS(rcStrict))
3188 {
3189 /*
3190 * Check for I/O breakpoints.
3191 */
3192 uint32_t const uDr7 = pCtx->dr[7];
3193 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3194 && X86_DR7_ANY_RW_IO(uDr7)
3195 && (pCtx->cr4 & X86_CR4_DE))
3196 || DBGFBpIsHwIoArmed(pVM))
3197 {
3198 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3199 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3200 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3201 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3202 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3203 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3204 rcStrict = rcStrict2;
3205 }
3206 }
3207 return rcStrict;
3208}
3209
3210
3211/**
3212 * Check fatal VT-x/AMD-V error and produce some meaningful
3213 * log release message.
3214 *
3215 * @param pVM The cross context VM structure.
3216 * @param iStatusCode VBox status code.
3217 */
3218VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3219{
3220 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3221 {
3222 PVMCPU pVCpu = &pVM->aCpus[i];
3223 switch (iStatusCode)
3224 {
3225 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3226 * might be getting inaccurate values for non-guru'ing EMTs. */
3227 case VERR_VMX_INVALID_VMCS_FIELD:
3228 break;
3229
3230 case VERR_VMX_INVALID_VMCS_PTR:
3231 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3232 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3233 pVCpu->hm.s.vmx.HCPhysVmcs));
3234 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3235 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3236 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3237 break;
3238
3239 case VERR_VMX_UNABLE_TO_START_VM:
3240 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3241 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3242 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3243
3244 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3245 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3246 {
3247 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3248 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3249 }
3250 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3251 {
3252 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3253 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3254 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3255 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3256 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3257 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3258 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3259 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3260 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3261 }
3262 /** @todo Log VM-entry event injection control fields
3263 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3264 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3265 break;
3266
3267 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3268 case VERR_VMX_INVALID_VMXON_PTR:
3269 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3270 case VERR_VMX_INVALID_GUEST_STATE:
3271 case VERR_VMX_UNEXPECTED_EXIT:
3272 case VERR_SVM_UNKNOWN_EXIT:
3273 case VERR_SVM_UNEXPECTED_EXIT:
3274 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3275 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3276 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3277 break;
3278 }
3279 }
3280
3281 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3282 {
3283 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3284 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3285 }
3286 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3287 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3288}
3289
3290
3291/**
3292 * Execute state save operation.
3293 *
3294 * @returns VBox status code.
3295 * @param pVM The cross context VM structure.
3296 * @param pSSM SSM operation handle.
3297 */
3298static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3299{
3300 int rc;
3301
3302 Log(("hmR3Save:\n"));
3303
3304 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3305 {
3306 /*
3307 * Save the basic bits - fortunately all the other things can be resynced on load.
3308 */
3309 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3310 AssertRCReturn(rc, rc);
3311 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3312 AssertRCReturn(rc, rc);
3313 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3314 AssertRCReturn(rc, rc);
3315 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3316
3317 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3318 * perhaps not even that (the initial value of @c true is safe. */
3319 uint32_t u32Dummy = PGMMODE_REAL;
3320 rc = SSMR3PutU32(pSSM, u32Dummy);
3321 AssertRCReturn(rc, rc);
3322 rc = SSMR3PutU32(pSSM, u32Dummy);
3323 AssertRCReturn(rc, rc);
3324 rc = SSMR3PutU32(pSSM, u32Dummy);
3325 AssertRCReturn(rc, rc);
3326 }
3327
3328#ifdef VBOX_HM_WITH_GUEST_PATCHING
3329 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3330 AssertRCReturn(rc, rc);
3331 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3332 AssertRCReturn(rc, rc);
3333 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3334 AssertRCReturn(rc, rc);
3335
3336 /* Store all the guest patch records too. */
3337 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3338 AssertRCReturn(rc, rc);
3339
3340 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3341 {
3342 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3343
3344 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3345 AssertRCReturn(rc, rc);
3346
3347 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3348 AssertRCReturn(rc, rc);
3349
3350 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3351 AssertRCReturn(rc, rc);
3352
3353 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3354 AssertRCReturn(rc, rc);
3355
3356 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3357 AssertRCReturn(rc, rc);
3358
3359 AssertCompileSize(HMTPRINSTR, 4);
3360 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3361 AssertRCReturn(rc, rc);
3362
3363 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3364 AssertRCReturn(rc, rc);
3365
3366 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3367 AssertRCReturn(rc, rc);
3368
3369 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3370 AssertRCReturn(rc, rc);
3371
3372 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3373 AssertRCReturn(rc, rc);
3374 }
3375#endif
3376 return VINF_SUCCESS;
3377}
3378
3379
3380/**
3381 * Execute state load operation.
3382 *
3383 * @returns VBox status code.
3384 * @param pVM The cross context VM structure.
3385 * @param pSSM SSM operation handle.
3386 * @param uVersion Data layout version.
3387 * @param uPass The data pass.
3388 */
3389static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3390{
3391 int rc;
3392
3393 Log(("hmR3Load:\n"));
3394 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3395
3396 /*
3397 * Validate version.
3398 */
3399 if ( uVersion != HM_SAVED_STATE_VERSION
3400 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3401 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3402 {
3403 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3404 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3405 }
3406 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3407 {
3408 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3409 AssertRCReturn(rc, rc);
3410 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3411 AssertRCReturn(rc, rc);
3412 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3413 AssertRCReturn(rc, rc);
3414
3415 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3416 {
3417 uint32_t val;
3418 /** @todo See note in hmR3Save(). */
3419 rc = SSMR3GetU32(pSSM, &val);
3420 AssertRCReturn(rc, rc);
3421 rc = SSMR3GetU32(pSSM, &val);
3422 AssertRCReturn(rc, rc);
3423 rc = SSMR3GetU32(pSSM, &val);
3424 AssertRCReturn(rc, rc);
3425 }
3426 }
3427#ifdef VBOX_HM_WITH_GUEST_PATCHING
3428 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3429 {
3430 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3431 AssertRCReturn(rc, rc);
3432 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3433 AssertRCReturn(rc, rc);
3434 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3435 AssertRCReturn(rc, rc);
3436
3437 /* Fetch all TPR patch records. */
3438 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3439 AssertRCReturn(rc, rc);
3440
3441 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3442 {
3443 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3444
3445 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3446 AssertRCReturn(rc, rc);
3447
3448 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3449 AssertRCReturn(rc, rc);
3450
3451 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3452 AssertRCReturn(rc, rc);
3453
3454 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3455 AssertRCReturn(rc, rc);
3456
3457 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3458 AssertRCReturn(rc, rc);
3459
3460 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3461 AssertRCReturn(rc, rc);
3462
3463 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3464 pVM->hm.s.fTPRPatchingActive = true;
3465
3466 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3467
3468 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3469 AssertRCReturn(rc, rc);
3470
3471 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3472 AssertRCReturn(rc, rc);
3473
3474 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3475 AssertRCReturn(rc, rc);
3476
3477 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3478 AssertRCReturn(rc, rc);
3479
3480 Log(("hmR3Load: patch %d\n", i));
3481 Log(("Key = %x\n", pPatch->Core.Key));
3482 Log(("cbOp = %d\n", pPatch->cbOp));
3483 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3484 Log(("type = %d\n", pPatch->enmType));
3485 Log(("srcop = %d\n", pPatch->uSrcOperand));
3486 Log(("dstop = %d\n", pPatch->uDstOperand));
3487 Log(("cFaults = %d\n", pPatch->cFaults));
3488 Log(("target = %x\n", pPatch->pJumpTarget));
3489 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3490 AssertRC(rc);
3491 }
3492 }
3493#endif
3494
3495 return VINF_SUCCESS;
3496}
3497
3498
3499/**
3500 * Displays the guest VM-exit history.
3501 *
3502 * @param pVM The cross context VM structure.
3503 * @param pHlp The info helper functions.
3504 * @param pszArgs Arguments, ignored.
3505 */
3506static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3507{
3508 NOREF(pszArgs);
3509 PVMCPU pVCpu = VMMGetCpu(pVM);
3510 if (!pVCpu)
3511 pVCpu = &pVM->aCpus[0];
3512
3513 if (HMIsEnabled(pVM))
3514 {
3515 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3516 const char * const *papszDesc;
3517 unsigned cMaxExitDesc;
3518 if (fIsVtx)
3519 {
3520 cMaxExitDesc = MAX_EXITREASON_VTX;
3521 papszDesc = &g_apszVTxExitReasons[0];
3522 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3523 }
3524 else
3525 {
3526 cMaxExitDesc = MAX_EXITREASON_AMDV;
3527 papszDesc = &g_apszAmdVExitReasons[0];
3528 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3529 }
3530
3531 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3532 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3533 pVCpu->hm.s.idxExitHistoryFree - 1 :
3534 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3535 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3536 {
3537 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3538 const char *pszExit = NULL;
3539 if (uExit <= cMaxExitDesc)
3540 pszExit = papszDesc[uExit];
3541 else if (!fIsVtx)
3542 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3543 else
3544 pszExit = NULL;
3545
3546 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3547 idxLast == i ? "<-- Latest exit" : "");
3548 }
3549 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3550 }
3551 else
3552 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3553}
3554
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