VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 96335

Last change on this file since 96335 was 95561, checked in by vboxsync, 2 years ago

VMM/IEM: Some crude exception/interrupt stats and history, take two. bugref:9898
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 24.3 KB
Line 
1/* $Id: IEMR3.cpp 95561 2022-07-07 23:56:09Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/iem.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/dbgf.h>
26#include <VBox/vmm/mm.h>
27#include "IEMInternal.h"
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmapi.h>
30#include <VBox/err.h>
31#ifdef VBOX_WITH_DEBUGGER
32# include <VBox/dbg.h>
33#endif
34
35#include <iprt/assert.h>
36#include <iprt/getopt.h>
37#include <iprt/string.h>
38
39
40/*********************************************************************************************************************************
41* Internal Functions *
42*********************************************************************************************************************************/
43static FNDBGFINFOARGVINT iemR3InfoITlb;
44static FNDBGFINFOARGVINT iemR3InfoDTlb;
45#ifdef VBOX_WITH_DEBUGGER
46static void iemR3RegisterDebuggerCommands(void);
47#endif
48
49
50static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
51{
52 switch (enmTargetCpu)
53 {
54#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
55 CASE_RET_STR(IEMTARGETCPU_8086);
56 CASE_RET_STR(IEMTARGETCPU_V20);
57 CASE_RET_STR(IEMTARGETCPU_186);
58 CASE_RET_STR(IEMTARGETCPU_286);
59 CASE_RET_STR(IEMTARGETCPU_386);
60 CASE_RET_STR(IEMTARGETCPU_486);
61 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
62 CASE_RET_STR(IEMTARGETCPU_PPRO);
63 CASE_RET_STR(IEMTARGETCPU_CURRENT);
64#undef CASE_RET_STR
65 default: return "Unknown";
66 }
67}
68
69
70/**
71 * Initializes the interpreted execution manager.
72 *
73 * This must be called after CPUM as we're quering information from CPUM about
74 * the guest and host CPUs.
75 *
76 * @returns VBox status code.
77 * @param pVM The cross context VM structure.
78 */
79VMMR3DECL(int) IEMR3Init(PVM pVM)
80{
81 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
82 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
83
84 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
85 {
86 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
87 AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
88
89 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
90 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
91
92 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
93 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
94 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
95 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
96 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
97 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
98 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
99 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
100 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
101 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
102 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
103 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
104 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
105 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
106 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
107 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
108 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
109 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
110
111#ifdef VBOX_WITH_STATISTICS
112 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
113 "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
114 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
115 "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
116#endif
117 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
118 "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
119 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
120 "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
121 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
122 "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
123 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
124 "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
125
126 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
127 "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
128 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
129 "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
130 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
131 "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
132
133 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
134 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
135 "", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
136 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
137 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
138 "", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
139
140#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
141 /* Instruction statistics: */
142# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
143 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
144 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
145 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
146 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
147# include "IEMInstructionStatisticsTmpl.h"
148# undef IEM_DO_INSTR_STAT
149#endif
150
151 /*
152 * Host and guest CPU information.
153 */
154 if (idCpu == 0)
155 {
156 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
157 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
158 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
159 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /*??*/
160 ? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
161#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
162 if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
163 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
164 else
165#endif
166 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
167
168#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
169 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
170 {
171 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
172 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
173 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
174 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
175 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
176 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
177 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
178 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
179 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
180 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
181 }
182 LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
183 iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
184 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
185#else
186 LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
187 CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
188 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
189#endif
190 }
191 else
192 {
193 pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
194 pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
195 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
196 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
197#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
198 pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
199#endif
200 }
201
202 /*
203 * Mark all buffers free.
204 */
205 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
206 while (iMemMap-- > 0)
207 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
208 }
209
210#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
211 /*
212 * Register the per-VM VMX APIC-access page handler type.
213 */
214 if (pVM->cpum.ro.GuestFeatures.fVmx)
215 {
216 int rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, 0 /*fFlags*/,
217 iemVmxApicAccessPageHandler,
218 "VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
219 AssertLogRelRCReturn(rc, rc);
220 }
221#endif
222
223 DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
224 DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
225#ifdef VBOX_WITH_DEBUGGER
226 iemR3RegisterDebuggerCommands();
227#endif
228
229 return VINF_SUCCESS;
230}
231
232
233VMMR3DECL(int) IEMR3Term(PVM pVM)
234{
235 NOREF(pVM);
236 return VINF_SUCCESS;
237}
238
239
240VMMR3DECL(void) IEMR3Relocate(PVM pVM)
241{
242 RT_NOREF(pVM);
243}
244
245
246/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
247static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, bool *pfHeader)
248{
249 if (*pfHeader)
250 return;
251 pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
252 *pfHeader = true;
253}
254
255
256/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
257static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, IEMTLBENTRY const *pTlbe, uint32_t uSlot)
258{
259 pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
260 uSlot,
261 (pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
262 : (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
263 : "expired",
264 (pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
265 pTlbe->GCPhys, pTlbe->pbMappingR3,
266 (uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
267 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
268 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
269 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
270 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
271 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
272 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
273 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
274 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
275 (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
276 : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
277}
278
279
280/** Displays one or more TLB slots. */
281static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
282 uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
283{
284 if (uSlot < RT_ELEMENTS(pTlb->aEntries))
285 {
286 if (cSlots > RT_ELEMENTS(pTlb->aEntries))
287 {
288 pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
289 cSlots, RT_ELEMENTS(pTlb->aEntries));
290 cSlots = RT_ELEMENTS(pTlb->aEntries);
291 }
292
293 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
294 while (cSlots-- > 0)
295 {
296 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
297 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
298 uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
299 }
300 }
301 else
302 pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
303 uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
304}
305
306
307/** Displays the TLB slot for the given address. */
308static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
309 uint64_t uAddress, bool *pfHeader)
310{
311 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
312
313 uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
314 uint32_t const uSlot = (uint8_t)uTag;
315 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
316 pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
317 Tlbe.uTag == (uTag | pTlb->uTlbRevision) ? "match"
318 : (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
319 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
320}
321
322
323/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
324static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
325{
326 /*
327 * This is entirely argument driven.
328 */
329 static RTGETOPTDEF const s_aOptions[] =
330 {
331 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
332 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
333 { "all", 'A', RTGETOPT_REQ_NOTHING },
334 { "--all", 'A', RTGETOPT_REQ_NOTHING },
335 { "--address", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
336 { "--range", 'r', RTGETOPT_REQ_UINT32_PAIR | RTGETOPT_FLAG_HEX },
337 { "--slot", 's', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
338 };
339
340 char szDefault[] = "-A";
341 char *papszDefaults[2] = { szDefault, NULL };
342 if (cArgs == 0)
343 {
344 cArgs = 1;
345 papszArgs = papszDefaults;
346 }
347
348 RTGETOPTSTATE State;
349 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
350 AssertRCReturnVoid(rc);
351
352 bool fNeedHeader = true;
353 bool fAddressMode = true;
354 PVMCPU pVCpu = VMMGetCpu(pVM);
355 if (!pVCpu)
356 pVCpu = VMMGetCpuById(pVM, 0);
357
358 RTGETOPTUNION ValueUnion;
359 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
360 {
361 switch (rc)
362 {
363 case 'c':
364 if (ValueUnion.u32 >= pVM->cCpus)
365 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
366 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
367 {
368 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
369 fNeedHeader = true;
370 }
371 break;
372
373 case 'a':
374 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
375 ValueUnion.u64, &fNeedHeader);
376 fAddressMode = true;
377 break;
378
379 case 'A':
380 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
381 0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
382 break;
383
384 case 'r':
385 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
386 ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
387 fAddressMode = false;
388 break;
389
390 case 's':
391 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
392 ValueUnion.u32, 1, &fNeedHeader);
393 fAddressMode = false;
394 break;
395
396 case VINF_GETOPT_NOT_OPTION:
397 if (fAddressMode)
398 {
399 uint64_t uAddr;
400 rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
401 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
402 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
403 uAddr, &fNeedHeader);
404 else
405 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
406 }
407 else
408 {
409 uint32_t uSlot;
410 rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
411 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
412 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
413 uSlot, 1, &fNeedHeader);
414 else
415 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
416 }
417 break;
418
419 case 'h':
420 pHlp->pfnPrintf(pHlp,
421 "Usage: info %ctlb [options]\n"
422 "\n"
423 "Options:\n"
424 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
425 " Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
426 " -A, --all, all\n"
427 " Display all the TLB entries (default if no other args).\n"
428 " -a<virt>, --address=<virt>\n"
429 " Shows the TLB entry for the specified guest virtual address.\n"
430 " -r<slot:count>, --range=<slot:count>\n"
431 " Shows the TLB entries for the specified slot range.\n"
432 " -s<slot>,--slot=<slot>\n"
433 " Shows the given TLB slot.\n"
434 "\n"
435 "Non-options are interpreted according to the last -a, -r or -s option,\n"
436 "defaulting to addresses if not preceeded by any of those options.\n"
437 , fITlb ? 'i' : 'd');
438 return;
439
440 default:
441 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
442 return;
443 }
444 }
445}
446
447
448/**
449 * @callback_method_impl{FNDBGFINFOARGVINT, itlb}
450 */
451static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
452{
453 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /*fITlb*/);
454}
455
456
457/**
458 * @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
459 */
460static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
461{
462 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /*fITlb*/);
463}
464
465
466#ifdef VBOX_WITH_DEBUGGER
467
468/** @callback_method_impl{FNDBGCCMD,
469 * Implements the '.alliem' command. }
470 */
471static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
472{
473 VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
474 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
475 if (pVCpu)
476 {
477 VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
478 return VINF_SUCCESS;
479 }
480 RT_NOREF(paArgs, cArgs);
481 return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
482}
483
484
485/**
486 * Called by IEMR3Init to register debugger commands.
487 */
488static void iemR3RegisterDebuggerCommands(void)
489{
490 /*
491 * Register debugger commands.
492 */
493 static DBGCCMD const s_aCmds[] =
494 {
495 {
496 /* .pszCmd = */ "iemflushtlb",
497 /* .cArgsMin = */ 0,
498 /* .cArgsMax = */ 0,
499 /* .paArgDescs = */ NULL,
500 /* .cArgDescs = */ 0,
501 /* .fFlags = */ 0,
502 /* .pfnHandler = */ iemR3DbgFlushTlbs,
503 /* .pszSyntax = */ "",
504 /* .pszDescription = */ "Flushed the code and data TLBs"
505 },
506 };
507
508 int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
509 AssertLogRelRC(rc);
510}
511
512#endif
513
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette