NEMR3.cpp@ 95843

Last change on this file since 95843 was 95256, checked in by vboxsync, 2 years ago
VMM/CFGM,NEM,HM,ConsoleImpl2: Let CPUM take care of enabling 64-bit guest supported in the CPU features, rather than HM, NEM and other main execution engines. bugref:9898
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1	/* $Id: NEMR3.cpp 95256 2022-06-13 10:44:19Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager.
4	*/
5
6	/*
7	* Copyright (C) 2018-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_nem NEM - Native Execution Manager.
19	*
20	* This is an alternative execution manage to HM and raw-mode. On one host
21	* (Windows) we're forced to use this, on the others we just do it because we
22	* can. Since this is host specific in nature, information about an
23	* implementation is contained in the NEMR3Native-xxxx.cpp files.
24	*
25	* @ref pg_nem_win
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_NEM
33	#include <VBox/vmm/dbgf.h>
34	#include <VBox/vmm/nem.h>
35	#include <VBox/vmm/gim.h>
36	#include "NEMInternal.h"
37	#include <VBox/vmm/vm.h>
38	#include <VBox/vmm/uvm.h>
39	#include <VBox/err.h>
40
41	#include <iprt/asm.h>
42
43
44
45	/**
46	* Basic init and configuration reading.
47	*
48	* Always call NEMR3Term after calling this.
49	*
50	* @returns VBox status code.
51	* @param pVM The cross context VM structure.
52	*/
53	VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
54	{
55	LogFlow(("NEMR3Init\n"));
56
57	/*
58	* Assert alignment and sizes.
59	*/
60	AssertCompileMemberAlignment(VM, nem.s, 64);
61	AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
62
63	/*
64	* Initialize state info so NEMR3Term will always be happy.
65	* No returning prior to setting magics!
66	*/
67	pVM->nem.s.u32Magic = NEM_MAGIC;
68	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
69	{
70	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
71	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
72	}
73
74	/*
75	* Read configuration.
76	*/
77	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
78
79	/*
80	* Validate the NEM settings.
81	*/
82	int rc = CFGMR3ValidateConfig(pCfgNem,
83	"/NEM/",
84	"Enabled"
85	"\|Allow64BitGuests"
86	"\|LovelyMesaDrvWorkaround"
87	#ifdef RT_OS_WINDOWS
88	"\|UseRing0Runloop"
89	#elif defined(RT_OS_DARWIN)
90	"\|VmxPleGap"
91	"\|VmxPleWindow"
92	"\|VmxLbr"
93	#endif
94	,
95	"" /* pszValidNodes /, "NEM" / pszWho /, 0 / uInstance */);
96	if (RT_FAILURE(rc))
97	return rc;
98
99	/** @cfgm{/NEM/NEMEnabled, bool, true}
100	* Whether NEM is enabled. */
101	rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
102	AssertLogRelRCReturn(rc, rc);
103
104
105	#ifdef VBOX_WITH_64_BITS_GUESTS
106	/** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
107	* Enables AMD64 CPU features.
108	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
109	* already have the support. */
110	rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
111	AssertLogRelRCReturn(rc, rc);
112	#else
113	pVM->nem.s.fAllow64BitGuests = false;
114	#endif
115
116	/** @cfgm{/NEM/LovelyMesaDrvWorkaround, bool, false}
117	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
118	* the hypervisor it is running under. */
119	bool f;
120	rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
121	AssertLogRelRCReturn(rc, rc);
122	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
123	{
124	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
125	pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
126	}
127
128	return VINF_SUCCESS;
129	}
130
131
132	/**
133	* This is called by HMR3Init() when HM cannot be used.
134	*
135	* Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
136	* native hypervisor API to execute the VM.
137	*
138	* @returns VBox status code.
139	* @param pVM The cross context VM structure.
140	* @param fFallback Whether this is a fallback call. Cleared if the VM is
141	* configured to use NEM instead of HM.
142	* @param fForced Whether /HM/HMForced was set. If set and we fail to
143	* enable NEM, we'll return a failure status code.
144	* Otherwise we'll assume HMR3Init falls back on raw-mode.
145	*/
146	VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
147	{
148	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
149	int rc;
150	if (pVM->nem.s.fEnabled)
151	{
152	#ifdef VBOX_WITH_NATIVE_NEM
153	rc = nemR3NativeInit(pVM, fFallback, fForced);
154	ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
155	#else
156	RT_NOREF(fFallback);
157	rc = VINF_SUCCESS;
158	#endif
159	if (RT_SUCCESS(rc))
160	{
161	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
162	{
163	#ifdef RT_OS_WINDOWS /* The WHv* API is extremely slow at handling VM exits. The AppleHv and
164	KVM APIs are much faster, thus the different mode name. :-) */
165	LogRel(("NEM:\n"
166	"NEM: NEMR3Init: Snail execution mode is active!\n"
167	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
168	"NEM: To see VirtualBox run at max speed you need to disable all Windows features\n"
169	"NEM: making use of Hyper-V. That is a moving target, so google how and carefully\n"
170	"NEM: consider the consequences of disabling these features.\n"
171	"NEM:\n"));
172	#else
173	LogRel(("NEM:\n"
174	"NEM: NEMR3Init: Turtle execution mode is active!\n"
175	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
176	"NEM:\n"));
177	#endif
178	}
179	else
180	{
181	LogRel(("NEM: NEMR3Init: Not available.\n"));
182	if (fForced)
183	rc = VERR_NEM_NOT_AVAILABLE;
184	}
185	}
186	else
187	LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
188	}
189	else
190	{
191	LogRel(("NEM: NEMR3Init: Disabled.\n"));
192	rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
193	}
194	return rc;
195	}
196
197
198	/**
199	* Perform initialization that depends on CPUM working.
200	*
201	* This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
202	*
203	* @returns VBox status code.
204	* @param pVM The cross context VM structure.
205	*/
206	VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
207	{
208	int rc = VINF_SUCCESS;
209	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
210	{
211	/*
212	* Do native after-CPUM init.
213	*/
214	#ifdef VBOX_WITH_NATIVE_NEM
215	rc = nemR3NativeInitAfterCPUM(pVM);
216	#else
217	RT_NOREF(pVM);
218	#endif
219	}
220	return rc;
221	}
222
223
224	/**
225	* Called when a init phase has completed.
226	*
227	* @returns VBox status code.
228	* @param pVM The cross context VM structure.
229	* @param enmWhat The phase that completed.
230	*/
231	VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
232	{
233	/*
234	* Check if GIM needs #UD, since that applies to everyone.
235	*/
236	if (enmWhat == VMINITCOMPLETED_RING3)
237	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
238	{
239	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
240	pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
241	}
242
243	/*
244	* Call native code.
245	*/
246	int rc = VINF_SUCCESS;
247	#ifdef VBOX_WITH_NATIVE_NEM
248	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
249	rc = nemR3NativeInitCompleted(pVM, enmWhat);
250	#else
251	RT_NOREF(pVM, enmWhat);
252	#endif
253	return rc;
254	}
255
256
257	/**
258	*
259	* @returns VBox status code.
260	* @param pVM The cross context VM structure.
261	*/
262	VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
263	{
264	AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
265	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
266	AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
267
268	/* Do native termination. */
269	int rc = VINF_SUCCESS;
270	#ifdef VBOX_WITH_NATIVE_NEM
271	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
272	rc = nemR3NativeTerm(pVM);
273	#endif
274
275	/* Mark it as terminated. */
276	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
277	{
278	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
279	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
280	}
281	pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
282	return rc;
283	}
284
285	/**
286	* External interface for querying whether native execution API is used.
287	*
288	* @returns true if NEM is being used, otherwise false.
289	* @param pUVM The user mode VM handle.
290	* @sa HMR3IsEnabled
291	*/
292	VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
293	{
294	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
295	PVM pVM = pUVM->pVM;
296	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
297	return VM_IS_NEM_ENABLED(pVM);
298	}
299
300
301	/**
302	* The VM is being reset.
303	*
304	* @param pVM The cross context VM structure.
305	*/
306	VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
307	{
308	#ifdef VBOX_WITH_NATIVE_NEM
309	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
310	nemR3NativeReset(pVM);
311	#else
312	RT_NOREF(pVM);
313	#endif
314	}
315
316
317	/**
318	* Resets a virtual CPU.
319	*
320	* Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
321	*
322	* @param pVCpu The cross context virtual CPU structure to reset.
323	* @param fInitIpi Set if being reset due to INIT IPI.
324	*/
325	VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
326	{
327	#ifdef VBOX_WITH_NATIVE_NEM
328	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
329	nemR3NativeResetCpu(pVCpu, fInitIpi);
330	#else
331	RT_NOREF(pVCpu, fInitIpi);
332	#endif
333	}
334
335
336	/**
337	* Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
338	*
339	* @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
340	* @param pVM The cross context VM structure.
341	*/
342	VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
343	{
344	#ifdef VBOX_WITH_NATIVE_NEM
345	if (VM_IS_NEM_ENABLED(pVM))
346	return true;
347	#else
348	RT_NOREF(pVM);
349	#endif
350	return false;
351	}
352
353
354	/**
355	* Gets the name of a generic NEM exit code.
356	*
357	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
358	* @param uExit The NEM exit to name.
359	*/
360	VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
361	{
362	switch ((NEMEXITTYPE)uExit)
363	{
364	case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
365	case NEMEXITTYPE_HALT: return "NEM halt";
366
367	case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
368	case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
369	case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
370	case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
371	case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
372	case NEMEXITTYPE_CANCELED: return "NEM canceled";
373	case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
374
375	case NEMEXITTYPE_INTERNAL_ERROR_EMULATION: return "NEM emulation IPE";
376	case NEMEXITTYPE_INTERNAL_ERROR_FATAL: return "NEM fatal IPE";
377	case NEMEXITTYPE_INTERRUPTED: return "NEM interrupted";
378	case NEMEXITTYPE_FAILED_ENTRY: return "NEM failed VT-x/AMD-V entry";
379
380	case NEMEXITTYPE_INVALID:
381	case NEMEXITTYPE_END:
382	break;
383	}
384
385	return NULL;
386	}
387
388
389	VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
390	{
391	Assert(VM_IS_NEM_ENABLED(pVM));
392	#ifdef VBOX_WITH_NATIVE_NEM
393	return nemR3NativeRunGC(pVM, pVCpu);
394	#else
395	NOREF(pVM); NOREF(pVCpu);
396	return VERR_INTERNAL_ERROR_3;
397	#endif
398	}
399
400
401	#ifndef VBOX_WITH_NATIVE_NEM
402	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
403	{
404	RT_NOREF(pVM, pVCpu);
405	return false;
406	}
407	#endif
408
409
410	VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
411	{
412	Assert(VM_IS_NEM_ENABLED(pVM));
413	#ifdef VBOX_WITH_NATIVE_NEM
414	return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
415	#else
416	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
417	return false;
418	#endif
419	}
420
421
422	VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
423	{
424	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
425	#ifdef VBOX_WITH_NATIVE_NEM
426	nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
427	#else
428	RT_NOREF(pVM, pVCpu, fFlags);
429	#endif
430	}
431
432	#ifndef VBOX_WITH_NATIVE_NEM
433
434	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
435	{
436	RT_NOREF(pVCpu, fEnabled);
437	}
438
439	# ifdef VBOX_WITH_PGM_NEM_MODE
440
441	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
442	{
443	RT_NOREF(pVM);
444	return false;
445	}
446
447
448	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
449	void *pvBitmap, size_t cbBitmap)
450	{
451	RT_NOREF(pVM, GCPhys, cb, uNemRange, pvBitmap, cbBitmap);
452	AssertFailed();
453	return VERR_INTERNAL_ERROR_2;
454	}
455
456
457	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
458	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
459	{
460	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange);
461	AssertFailed();
462	return VERR_INTERNAL_ERROR_2;
463	}
464
465	# endif /* VBOX_WITH_PGM_NEM_MODE */
466	#endif /* !VBOX_WITH_NATIVE_NEM */
467
468	/**
469	* Notification callback from DBGF when interrupt breakpoints or generic debug
470	* event settings changes.
471	*
472	* DBGF will call NEMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
473	* function is just updating the VM globals.
474	*
475	* @param pVM The VM cross context VM structure.
476	* @thread EMT(0)
477	*/
478	VMMR3_INT_DECL(void) NEMR3NotifyDebugEventChanged(PVM pVM)
479	{
480	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
481
482	#ifdef VBOX_WITH_NATIVE_NEM
483	/* Interrupts. */
484	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
485	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
486
487	/* CPU Exceptions. */
488	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
489	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
490	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
491	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
492
493	/* Common VM exits. */
494	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
495	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
496	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
497	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
498
499	/* Done. */
500	pVM->nem.s.fUseDebugLoop = nemR3NativeNotifyDebugEventChanged(pVM, fUseDebugLoop);
501	#else
502	RT_NOREF(pVM);
503	#endif
504	}
505
506
507	/**
508	* Follow up notification callback to NEMR3NotifyDebugEventChanged for each CPU.
509	*
510	* NEM uses this to combine the decision made NEMR3NotifyDebugEventChanged with
511	* per CPU settings.
512	*
513	* @param pVM The VM cross context VM structure.
514	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
515	*/
516	VMMR3_INT_DECL(void) NEMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
517	{
518	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
519
520	#ifdef VBOX_WITH_NATIVE_NEM
521	pVCpu->nem.s.fUseDebugLoop = nemR3NativeNotifyDebugEventChangedPerCpu(pVM, pVCpu,
522	pVCpu->nem.s.fSingleInstruction \| pVM->nem.s.fUseDebugLoop);
523	#else
524	RT_NOREF(pVM, pVCpu);
525	#endif
526	}

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 95843

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