SELM.cpp@ 61744

Last change on this file since 61744 was 60824, checked in by vboxsync, 9 years ago
SELM: Added a LogFlow to each of the FF responders.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 106.9 KB

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1	/* $Id: SELM.cpp 60824 2016-05-04 11:29:55Z vboxsync $ */
2	/** @file
3	* SELM - The Selector Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_selm SELM - The Selector Manager
19	*
20	* SELM takes care of GDT, LDT and TSS shadowing in raw-mode, and the injection
21	* of a few hyper selector for the raw-mode context. In the hardware assisted
22	* virtualization mode its only task is to decode entries in the guest GDT or
23	* LDT once in a while.
24	*
25	* @see grp_selm
26	*
27	*
28	* @section seg_selm_shadowing Shadowing
29	*
30	* SELMR3UpdateFromCPUM() and SELMR3SyncTSS() does the bulk synchronization
31	* work. The three structures (GDT, LDT, TSS) are all shadowed wholesale atm.
32	* The idea is to do it in a more on-demand fashion when we get time. There
33	* also a whole bunch of issues with the current synchronization of all three
34	* tables, see notes and todos in the code.
35	*
36	* When the guest makes changes to the GDT we will try update the shadow copy
37	* without involving SELMR3UpdateFromCPUM(), see selmGCSyncGDTEntry().
38	*
39	* When the guest make LDT changes we'll trigger a full resync of the LDT
40	* (SELMR3UpdateFromCPUM()), which, needless to say, isn't optimal.
41	*
42	* The TSS shadowing is limited to the fields we need to care about, namely SS0
43	* and ESP0. The Patch Manager makes use of these. We monitor updates to the
44	* guest TSS and will try keep our SS0 and ESP0 copies up to date this way
45	* rather than go the SELMR3SyncTSS() route.
46	*
47	* When in raw-mode SELM also injects a few extra GDT selectors which are used
48	* by the raw-mode (hyper) context. These start their life at the high end of
49	* the table and will be relocated when the guest tries to make use of them...
50	* Well, that was that idea at least, only the code isn't quite there yet which
51	* is why we have trouble with guests which actually have a full sized GDT.
52	*
53	* So, the summary of the current GDT, LDT and TSS shadowing is that there is a
54	* lot of relatively simple and enjoyable work to be done, see @bugref{3267}.
55	*
56	*/
57
58
59	/*********************************************************************************************************************************
60	* Header Files *
61	*********************************************************************************************************************************/
62	#define LOG_GROUP LOG_GROUP_SELM
63	#include <VBox/vmm/selm.h>
64	#include <VBox/vmm/cpum.h>
65	#include <VBox/vmm/stam.h>
66	#include <VBox/vmm/em.h>
67	#include <VBox/vmm/hm.h>
68	#include <VBox/vmm/mm.h>
69	#include <VBox/vmm/ssm.h>
70	#include <VBox/vmm/pgm.h>
71	#include <VBox/vmm/trpm.h>
72	#include <VBox/vmm/dbgf.h>
73	#include "SELMInternal.h"
74	#include <VBox/vmm/vm.h>
75	#include <VBox/err.h>
76	#include <VBox/param.h>
77
78	#include <iprt/assert.h>
79	#include <VBox/log.h>
80	#include <iprt/asm.h>
81	#include <iprt/string.h>
82	#include <iprt/thread.h>
83	#include <iprt/string.h>
84
85	#include "SELMInline.h"
86
87
88	/** SELM saved state version. */
89	#define SELM_SAVED_STATE_VERSION 5
90
91
92	/*********************************************************************************************************************************
93	* Internal Functions *
94	*********************************************************************************************************************************/
95	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM);
96	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
97	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM);
98	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
99	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
100	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
101	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
102	//static DECLCALLBACK(void) selmR3InfoTss(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
103	//static DECLCALLBACK(void) selmR3InfoTssGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
104
105
106	/*********************************************************************************************************************************
107	* Global Variables *
108	*********************************************************************************************************************************/
109	#ifdef LOG_ENABLED
110	/** Segment register names. */
111	static char const g_aszSRegNms[X86_SREG_COUNT][4] = { "ES", "CS", "SS", "DS", "FS", "GS" };
112	#endif
113
114
115	/**
116	* Initializes the SELM.
117	*
118	* @returns VBox status code.
119	* @param pVM The cross context VM structure.
120	*/
121	VMMR3DECL(int) SELMR3Init(PVM pVM)
122	{
123	int rc;
124	LogFlow(("SELMR3Init\n"));
125
126	/*
127	* Assert alignment and sizes.
128	* (The TSS block requires contiguous back.)
129	*/
130	AssertCompile(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding)); AssertRelease(sizeof(pVM->selm.s) <= sizeof(pVM->selm.padding));
131	AssertCompileMemberAlignment(VM, selm.s, 32); AssertRelease(!(RT_OFFSETOF(VM, selm.s) & 31));
132	#if 0 /* doesn't work */
133	AssertCompile((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
134	AssertCompile((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
135	#endif
136	AssertRelease((RT_OFFSETOF(VM, selm.s.Tss) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.Tss));
137	AssertRelease((RT_OFFSETOF(VM, selm.s.TssTrap08) & PAGE_OFFSET_MASK) <= PAGE_SIZE - sizeof(pVM->selm.s.TssTrap08));
138	AssertRelease(sizeof(pVM->selm.s.Tss.IntRedirBitmap) == 0x20);
139
140	/*
141	* Init the structure.
142	*/
143	pVM->selm.s.offVM = RT_OFFSETOF(VM, selm);
144	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = (SELM_GDT_ELEMENTS - 0x1) << 3;
145	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = (SELM_GDT_ELEMENTS - 0x2) << 3;
146	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = (SELM_GDT_ELEMENTS - 0x3) << 3;
147	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = (SELM_GDT_ELEMENTS - 0x4) << 3;
148	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = (SELM_GDT_ELEMENTS - 0x5) << 3;
149
150	if (HMIsRawModeCtxNeeded(pVM))
151	{
152	/*
153	* Allocate GDT table.
154	*/
155	rc = MMR3HyperAllocOnceNoRel(pVM, sizeof(pVM->selm.s.paGdtR3[0]) * SELM_GDT_ELEMENTS,
156	PAGE_SIZE, MM_TAG_SELM, (void **)&pVM->selm.s.paGdtR3);
157	AssertRCReturn(rc, rc);
158
159	/*
160	* Allocate LDT area.
161	*/
162	rc = MMR3HyperAllocOnceNoRel(pVM, _64K + PAGE_SIZE, PAGE_SIZE, MM_TAG_SELM, &pVM->selm.s.pvLdtR3);
163	AssertRCReturn(rc, rc);
164	}
165
166	/*
167	* Init Guest's and Shadow GDT, LDT, TSS changes control variables.
168	*/
169	pVM->selm.s.cbEffGuestGdtLimit = 0;
170	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
171	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
172	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
173
174	pVM->selm.s.paGdtRC = NIL_RTRCPTR; /* Must be set in SELMR3Relocate because of monitoring. */
175	pVM->selm.s.pvLdtRC = RTRCPTR_MAX;
176	pVM->selm.s.pvMonShwTssRC = RTRCPTR_MAX;
177	pVM->selm.s.GCSelTss = RTSEL_MAX;
178
179	pVM->selm.s.fSyncTSSRing0Stack = false;
180
181	/* The I/O bitmap starts right after the virtual interrupt redirection
182	bitmap. Outside the TSS on purpose; the CPU will not check it for
183	I/O operations. */
184	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
185	/* bit set to 1 means no redirection */
186	memset(pVM->selm.s.Tss.IntRedirBitmap, 0xff, sizeof(pVM->selm.s.Tss.IntRedirBitmap));
187
188	/*
189	* Register the virtual access handlers.
190	*/
191	pVM->selm.s.hShadowGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
192	pVM->selm.s.hShadowLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
193	pVM->selm.s.hShadowTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
194	pVM->selm.s.hGuestGdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
195	pVM->selm.s.hGuestLdtWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
196	pVM->selm.s.hGuestTssWriteHandlerType = NIL_PGMVIRTHANDLERTYPE;
197	#ifdef VBOX_WITH_RAW_MODE
198	if (!HMIsEnabled(pVM))
199	{
200	# ifdef SELM_TRACK_SHADOW_GDT_CHANGES
201	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
202	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
203	NULL /pszHandlerRC/, "selmRCShadowGDTWritePfHandler",
204	"Shadow GDT write access handler", &pVM->selm.s.hShadowGdtWriteHandlerType);
205	AssertRCReturn(rc, rc);
206	# endif
207	# ifdef SELM_TRACK_SHADOW_TSS_CHANGES
208	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
209	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
210	NULL /pszHandlerRC/, "selmRCShadowTSSWritePfHandler",
211	"Shadow TSS write access handler", &pVM->selm.s.hShadowTssWriteHandlerType);
212	AssertRCReturn(rc, rc);
213	# endif
214	# ifdef SELM_TRACK_SHADOW_LDT_CHANGES
215	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_HYPERVISOR, false /fRelocUserRC/,
216	NULL /pfnInvalidateR3/, NULL /pfnHandlerR3/,
217	NULL /pszHandlerRC/, "selmRCShadowLDTWritePfHandler",
218	"Shadow LDT write access handler", &pVM->selm.s.hShadowLdtWriteHandlerType);
219	AssertRCReturn(rc, rc);
220	# endif
221	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
222	NULL /pfnInvalidateR3/, selmGuestGDTWriteHandler,
223	"selmGuestGDTWriteHandler", "selmRCGuestGDTWritePfHandler",
224	"Guest GDT write access handler", &pVM->selm.s.hGuestGdtWriteHandlerType);
225	AssertRCReturn(rc, rc);
226	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
227	NULL /pfnInvalidateR3/, selmGuestLDTWriteHandler,
228	"selmGuestLDTWriteHandler", "selmRCGuestLDTWritePfHandler",
229	"Guest LDT write access handler", &pVM->selm.s.hGuestLdtWriteHandlerType);
230	AssertRCReturn(rc, rc);
231	rc = PGMR3HandlerVirtualTypeRegister(pVM, PGMVIRTHANDLERKIND_WRITE, false /fRelocUserRC/,
232	NULL /pfnInvalidateR3/, selmGuestTSSWriteHandler,
233	"selmGuestTSSWriteHandler", "selmRCGuestTSSWritePfHandler",
234	"Guest TSS write access handler", &pVM->selm.s.hGuestTssWriteHandlerType);
235	AssertRCReturn(rc, rc);
236	}
237	#endif /* VBOX_WITH_RAW_MODE */
238
239	/*
240	* Register the saved state data unit.
241	*/
242	rc = SSMR3RegisterInternal(pVM, "selm", 1, SELM_SAVED_STATE_VERSION, sizeof(SELM),
243	NULL, NULL, NULL,
244	NULL, selmR3Save, NULL,
245	NULL, selmR3Load, selmR3LoadDone);
246	if (RT_FAILURE(rc))
247	return rc;
248
249	/*
250	* Statistics.
251	*/
252	if (!HMIsEnabled(pVM))
253	{
254	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest GDT.");
255	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestGDTUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/GDTEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest GDT.");
256	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestLDT, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/LDT", STAMUNIT_OCCURENCES, "The number of writes to the Guest LDT was detected.");
257	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSInt", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS.");
258	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSRedir, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSRedir",STAMUNIT_OCCURENCES, "The number of handled redir bitmap writes to the Guest TSS.");
259	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSHandledChanged,STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSIntChg", STAMUNIT_OCCURENCES, "The number of handled writes to the Guest TSS where the R0 stack changed.");
260	STAM_REG(pVM, &pVM->selm.s.StatRCWriteGuestTSSUnhandled, STAMTYPE_COUNTER, "/SELM/GC/Write/Guest/TSSEmu", STAMUNIT_OCCURENCES, "The number of unhandled writes to the Guest TSS.");
261	STAM_REG(pVM, &pVM->selm.s.StatTSSSync, STAMTYPE_PROFILE, "/PROF/SELM/TSSSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3SyncTSS() body.");
262	STAM_REG(pVM, &pVM->selm.s.StatUpdateFromCPUM, STAMTYPE_PROFILE, "/PROF/SELM/UpdateFromCPUM", STAMUNIT_TICKS_PER_CALL, "Profiling of the SELMR3UpdateFromCPUM() body.");
263
264	STAM_REL_REG(pVM, &pVM->selm.s.StatHyperSelsChanged, STAMTYPE_COUNTER, "/SELM/HyperSels/Changed", STAMUNIT_OCCURENCES, "The number of times we had to relocate our hypervisor selectors.");
265	STAM_REL_REG(pVM, &pVM->selm.s.StatScanForHyperSels, STAMTYPE_COUNTER, "/SELM/HyperSels/Scan", STAMUNIT_OCCURENCES, "The number of times we had find free hypervisor selectors.");
266
267	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleES", STAMUNIT_OCCURENCES, "Stale ES was detected in UpdateFromCPUM.");
268	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleCS", STAMUNIT_OCCURENCES, "Stale CS was detected in UpdateFromCPUM.");
269	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleSS", STAMUNIT_OCCURENCES, "Stale SS was detected in UpdateFromCPUM.");
270	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleDS", STAMUNIT_OCCURENCES, "Stale DS was detected in UpdateFromCPUM.");
271	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleFS", STAMUNIT_OCCURENCES, "Stale FS was detected in UpdateFromCPUM.");
272	STAM_REL_REG(pVM, &pVM->selm.s.aStatDetectedStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/DetectedStaleGS", STAMUNIT_OCCURENCES, "Stale GS was detected in UpdateFromCPUM.");
273
274	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleES", STAMUNIT_OCCURENCES, "Already stale ES in UpdateFromCPUM.");
275	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleCS", STAMUNIT_OCCURENCES, "Already stale CS in UpdateFromCPUM.");
276	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleSS", STAMUNIT_OCCURENCES, "Already stale SS in UpdateFromCPUM.");
277	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleDS", STAMUNIT_OCCURENCES, "Already stale DS in UpdateFromCPUM.");
278	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleFS", STAMUNIT_OCCURENCES, "Already stale FS in UpdateFromCPUM.");
279	STAM_REL_REG(pVM, &pVM->selm.s.aStatAlreadyStaleSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/AlreadyStaleGS", STAMUNIT_OCCURENCES, "Already stale GS in UpdateFromCPUM.");
280
281	STAM_REL_REG(pVM, &pVM->selm.s.StatStaleToUnstaleSReg, STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/StaleToUnstale", STAMUNIT_OCCURENCES, "Transitions from stale to unstale UpdateFromCPUM.");
282
283	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_ES], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedES", STAMUNIT_OCCURENCES, "Updated hidden ES values in UpdateFromCPUM.");
284	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_CS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedCS", STAMUNIT_OCCURENCES, "Updated hidden CS values in UpdateFromCPUM.");
285	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_SS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedSS", STAMUNIT_OCCURENCES, "Updated hidden SS values in UpdateFromCPUM.");
286	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_DS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedDS", STAMUNIT_OCCURENCES, "Updated hidden DS values in UpdateFromCPUM.");
287	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_FS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedFS", STAMUNIT_OCCURENCES, "Updated hidden FS values in UpdateFromCPUM.");
288	STAM_REG( pVM, &pVM->selm.s.aStatUpdatedSReg[X86_SREG_GS], STAMTYPE_COUNTER, "/SELM/UpdateFromCPUM/UpdatedGS", STAMUNIT_OCCURENCES, "Updated hidden GS values in UpdateFromCPUM.");
289	}
290
291	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelGst, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from guest tables.");
292	STAM_REG( pVM, &pVM->selm.s.StatLoadHidSelShw, STAMTYPE_COUNTER, "/SELM/LoadHidSel/LoadedShadow", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Loaded from shadow tables.");
293	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelReadErrors, STAMTYPE_COUNTER, "/SELM/LoadHidSel/GstReadErrors", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: Guest table read errors.");
294	STAM_REL_REG(pVM, &pVM->selm.s.StatLoadHidSelGstNoGood, STAMTYPE_COUNTER, "/SELM/LoadHidSel/NoGoodGuest", STAMUNIT_OCCURENCES, "SELMLoadHiddenSelectorReg: No good guest table entry.");
295
296	#ifdef VBOX_WITH_RAW_MODE
297	/*
298	* Default action when entering raw mode for the first time
299	*/
300	if (!HMIsEnabled(pVM))
301	{
302	PVMCPU pVCpu = &pVM->aCpus[0]; /* raw mode implies on VCPU */
303	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
304	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
305	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
306	}
307	#endif
308
309	/*
310	* Register info handlers.
311	*/
312	if (HMIsRawModeCtxNeeded(pVM))
313	{
314	DBGFR3InfoRegisterInternal(pVM, "gdt", "Displays the shadow GDT. No arguments.", &selmR3InfoGdt);
315	DBGFR3InfoRegisterInternal(pVM, "ldt", "Displays the shadow LDT. No arguments.", &selmR3InfoLdt);
316	//DBGFR3InfoRegisterInternal(pVM, "tss", "Displays the shadow TSS. No arguments.", &selmR3InfoTss);
317	}
318	DBGFR3InfoRegisterInternal(pVM, "gdtguest", "Displays the guest GDT. No arguments.", &selmR3InfoGdtGuest);
319	DBGFR3InfoRegisterInternal(pVM, "ldtguest", "Displays the guest LDT. No arguments.", &selmR3InfoLdtGuest);
320	//DBGFR3InfoRegisterInternal(pVM, "tssguest", "Displays the guest TSS. No arguments.", &selmR3InfoTssGuest);
321
322	return rc;
323	}
324
325
326	/**
327	* Finalizes HMA page attributes.
328	*
329	* @returns VBox status code.
330	* @param pVM The cross context VM structure.
331	*/
332	VMMR3DECL(int) SELMR3InitFinalize(PVM pVM)
333	{
334	#ifdef VBOX_WITH_RAW_MODE
335	/** @cfgm{/DoubleFault,bool,false}
336	* Enables catching of double faults in the raw-mode context VMM code. This can
337	* be used when the triple faults or hangs occur and one suspect an unhandled
338	* double fault. This is not enabled by default because it means making the
339	* hyper selectors writeable for all supervisor code, including the guest's.
340	* The double fault is a task switch and thus requires write access to the GDT
341	* of the TSS (to set it busy), to the old TSS (to store state), and to the Trap
342	* 8 TSS for the back link.
343	*/
344	bool f;
345	# if defined(DEBUG_bird)
346	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, true);
347	# else
348	int rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "DoubleFault", &f, false);
349	# endif
350	AssertLogRelRCReturn(rc, rc);
351	if (f && HMIsRawModeCtxNeeded(pVM))
352	{
353	PX86DESC paGdt = pVM->selm.s.paGdtR3;
354	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3]), sizeof(paGdt[0]),
355	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
356	AssertRC(rc);
357	rc = PGMMapSetPage(pVM, MMHyperR3ToRC(pVM, &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3]), sizeof(paGdt[0]),
358	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
359	AssertRC(rc);
360	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]),
361	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
362	AssertRC(rc);
363	rc = PGMMapSetPage(pVM, VM_RC_ADDR(pVM, &pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]), sizeof(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]),
364	X86_PTE_RW \| X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
365	AssertRC(rc);
366	}
367	#endif /* VBOX_WITH_RAW_MODE */
368	return VINF_SUCCESS;
369	}
370
371
372	/**
373	* Setup the hypervisor GDT selectors in our shadow table
374	*
375	* @param pVM The cross context VM structure.
376	*/
377	static void selmR3SetupHyperGDTSelectors(PVM pVM)
378	{
379	PX86DESC paGdt = pVM->selm.s.paGdtR3;
380
381	/*
382	* Set up global code and data descriptors for use in the guest context.
383	* Both are wide open (base 0, limit 4GB)
384	*/
385	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> 3];
386	pDesc->Gen.u16LimitLow = 0xffff;
387	pDesc->Gen.u4LimitHigh = 0xf;
388	pDesc->Gen.u16BaseLow = 0;
389	pDesc->Gen.u8BaseHigh1 = 0;
390	pDesc->Gen.u8BaseHigh2 = 0;
391	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
392	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
393	pDesc->Gen.u2Dpl = 0; /* supervisor */
394	pDesc->Gen.u1Present = 1;
395	pDesc->Gen.u1Available = 0;
396	pDesc->Gen.u1Long = 0;
397	pDesc->Gen.u1DefBig = 1; /* def 32 bit */
398	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
399
400	/* data */
401	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> 3];
402	pDesc->Gen.u16LimitLow = 0xffff;
403	pDesc->Gen.u4LimitHigh = 0xf;
404	pDesc->Gen.u16BaseLow = 0;
405	pDesc->Gen.u8BaseHigh1 = 0;
406	pDesc->Gen.u8BaseHigh2 = 0;
407	pDesc->Gen.u4Type = X86_SEL_TYPE_RW_ACC;
408	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
409	pDesc->Gen.u2Dpl = 0; /* supervisor */
410	pDesc->Gen.u1Present = 1;
411	pDesc->Gen.u1Available = 0;
412	pDesc->Gen.u1Long = 0;
413	pDesc->Gen.u1DefBig = 1; /* big */
414	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
415
416	/* 64-bit mode code (& data?) */
417	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> 3];
418	pDesc->Gen.u16LimitLow = 0xffff;
419	pDesc->Gen.u4LimitHigh = 0xf;
420	pDesc->Gen.u16BaseLow = 0;
421	pDesc->Gen.u8BaseHigh1 = 0;
422	pDesc->Gen.u8BaseHigh2 = 0;
423	pDesc->Gen.u4Type = X86_SEL_TYPE_ER_ACC;
424	pDesc->Gen.u1DescType = 1; /* not system, but code/data */
425	pDesc->Gen.u2Dpl = 0; /* supervisor */
426	pDesc->Gen.u1Present = 1;
427	pDesc->Gen.u1Available = 0;
428	pDesc->Gen.u1Long = 1; /* The Long (L) attribute bit. */
429	pDesc->Gen.u1DefBig = 0; /* With L=1 this must be 0. */
430	pDesc->Gen.u1Granularity = 1; /* 4KB limit */
431
432	/*
433	* TSS descriptor
434	*/
435	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
436	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
437	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
438	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
439	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
440	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
441	pDesc->Gen.u4LimitHigh = 0;
442	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
443	pDesc->Gen.u1DescType = 0; /* system */
444	pDesc->Gen.u2Dpl = 0; /* supervisor */
445	pDesc->Gen.u1Present = 1;
446	pDesc->Gen.u1Available = 0;
447	pDesc->Gen.u1Long = 0;
448	pDesc->Gen.u1DefBig = 0;
449	pDesc->Gen.u1Granularity = 0; /* byte limit */
450
451	/*
452	* TSS descriptor for trap 08
453	*/
454	pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> 3];
455	pDesc->Gen.u16LimitLow = sizeof(VBOXTSS) - 1;
456	pDesc->Gen.u4LimitHigh = 0;
457	RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.TssTrap08);
458	pDesc->Gen.u16BaseLow = RT_LOWORD(RCPtrTSS);
459	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(RCPtrTSS);
460	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(RCPtrTSS);
461	pDesc->Gen.u4Type = X86_SEL_TYPE_SYS_386_TSS_AVAIL;
462	pDesc->Gen.u1DescType = 0; /* system */
463	pDesc->Gen.u2Dpl = 0; /* supervisor */
464	pDesc->Gen.u1Present = 1;
465	pDesc->Gen.u1Available = 0;
466	pDesc->Gen.u1Long = 0;
467	pDesc->Gen.u1DefBig = 0;
468	pDesc->Gen.u1Granularity = 0; /* byte limit */
469	}
470
471	/**
472	* Applies relocations to data and code managed by this
473	* component. This function will be called at init and
474	* whenever the VMM need to relocate it self inside the GC.
475	*
476	* @param pVM The cross context VM structure.
477	*/
478	VMMR3DECL(void) SELMR3Relocate(PVM pVM)
479	{
480	PX86DESC paGdt = pVM->selm.s.paGdtR3;
481	LogFlow(("SELMR3Relocate\n"));
482
483	if (HMIsRawModeCtxNeeded(pVM))
484	{
485	for (VMCPUID i = 0; i < pVM->cCpus; i++)
486	{
487	PVMCPU pVCpu = &pVM->aCpus[i];
488
489	/*
490	* Update GDTR and selector.
491	*/
492	CPUMSetHyperGDTR(pVCpu, MMHyperR3ToRC(pVM, paGdt), SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1);
493
494	/** @todo selector relocations should be a separate operation? */
495	CPUMSetHyperCS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]);
496	CPUMSetHyperDS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
497	CPUMSetHyperES(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
498	CPUMSetHyperSS(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]);
499	CPUMSetHyperTR(pVCpu, pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]);
500	}
501
502	selmR3SetupHyperGDTSelectors(pVM);
503
504	/** @todo SELM must be called when any of the CR3s changes during a cpu mode change. */
505	/** @todo PGM knows the proper CR3 values these days, not CPUM. */
506	/*
507	* Update the TSSes.
508	*/
509	/* Only applies to raw mode which supports only 1 VCPU */
510	PVMCPU pVCpu = &pVM->aCpus[0];
511
512	/* Current TSS */
513	pVM->selm.s.Tss.cr3 = PGMGetHyperCR3(pVCpu);
514	pVM->selm.s.Tss.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
515	pVM->selm.s.Tss.esp0 = VMMGetStackRC(pVCpu);
516	pVM->selm.s.Tss.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
517	pVM->selm.s.Tss.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
518	pVM->selm.s.Tss.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
519	pVM->selm.s.Tss.offIoBitmap = sizeof(VBOXTSS);
520
521	/* trap 08 */
522	pVM->selm.s.TssTrap08.cr3 = PGMGetInterRCCR3(pVM, pVCpu); /* this should give use better survival chances. */
523	pVM->selm.s.TssTrap08.ss0 = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
524	pVM->selm.s.TssTrap08.ss = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
525	pVM->selm.s.TssTrap08.esp0 = VMMGetStackRC(pVCpu) - PAGE_SIZE / 2; /* upper half can be analysed this way. */
526	pVM->selm.s.TssTrap08.esp = pVM->selm.s.TssTrap08.esp0;
527	pVM->selm.s.TssTrap08.ebp = pVM->selm.s.TssTrap08.esp0;
528	pVM->selm.s.TssTrap08.cs = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS];
529	pVM->selm.s.TssTrap08.ds = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
530	pVM->selm.s.TssTrap08.es = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS];
531	pVM->selm.s.TssTrap08.fs = 0;
532	pVM->selm.s.TssTrap08.gs = 0;
533	pVM->selm.s.TssTrap08.selLdt = 0;
534	pVM->selm.s.TssTrap08.eflags = 0x2; /* all cleared */
535	pVM->selm.s.TssTrap08.ecx = VM_RC_ADDR(pVM, &pVM->selm.s.Tss); /* setup ecx to normal Hypervisor TSS address. */
536	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.ecx;
537	pVM->selm.s.TssTrap08.eax = pVM->selm.s.TssTrap08.ecx;
538	pVM->selm.s.TssTrap08.edx = VM_RC_ADDR(pVM, pVM); /* setup edx VM address. */
539	pVM->selm.s.TssTrap08.edi = pVM->selm.s.TssTrap08.edx;
540	pVM->selm.s.TssTrap08.ebx = pVM->selm.s.TssTrap08.edx;
541	pVM->selm.s.TssTrap08.offIoBitmap = sizeof(VBOXTSS);
542	/* TRPM will be updating the eip */
543	}
544
545	if (!HMIsEnabled(pVM))
546	{
547	/*
548	* Update shadow GDT/LDT/TSS write access handlers.
549	*/
550	PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
551	int rc; NOREF(rc);
552	#ifdef SELM_TRACK_SHADOW_GDT_CHANGES
553	if (pVM->selm.s.paGdtRC != NIL_RTRCPTR)
554	{
555	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.paGdtRC, true /fHypervisor/);
556	AssertRC(rc);
557	}
558	pVM->selm.s.paGdtRC = MMHyperR3ToRC(pVM, paGdt);
559	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowGdtWriteHandlerType,
560	pVM->selm.s.paGdtRC,
561	pVM->selm.s.paGdtRC + SELM_GDT_ELEMENTS * sizeof(paGdt[0]) - 1,
562	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
563	AssertRC(rc);
564	#endif
565	#ifdef SELM_TRACK_SHADOW_TSS_CHANGES
566	if (pVM->selm.s.pvMonShwTssRC != RTRCPTR_MAX)
567	{
568	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvMonShwTssRC, true /fHypervisor/);
569	AssertRC(rc);
570	}
571	pVM->selm.s.pvMonShwTssRC = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
572	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowTssWriteHandlerType,
573	pVM->selm.s.pvMonShwTssRC,
574	pVM->selm.s.pvMonShwTssRC + sizeof(pVM->selm.s.Tss) - 1,
575	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
576	AssertRC(rc);
577	#endif
578
579	/*
580	* Update the GC LDT region handler and address.
581	*/
582	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
583	if (pVM->selm.s.pvLdtRC != RTRCPTR_MAX)
584	{
585	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.pvLdtRC, true /fHypervisor/);
586	AssertRC(rc);
587	}
588	#endif
589	pVM->selm.s.pvLdtRC = MMHyperR3ToRC(pVM, pVM->selm.s.pvLdtR3);
590	#ifdef SELM_TRACK_SHADOW_LDT_CHANGES
591	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hShadowLdtWriteHandlerType,
592	pVM->selm.s.pvLdtRC,
593	pVM->selm.s.pvLdtRC + _64K + PAGE_SIZE - 1,
594	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
595	AssertRC(rc);
596	#endif
597	}
598	}
599
600
601	/**
602	* Terminates the SELM.
603	*
604	* Termination means cleaning up and freeing all resources,
605	* the VM it self is at this point powered off or suspended.
606	*
607	* @returns VBox status code.
608	* @param pVM The cross context VM structure.
609	*/
610	VMMR3DECL(int) SELMR3Term(PVM pVM)
611	{
612	NOREF(pVM);
613	return VINF_SUCCESS;
614	}
615
616
617	/**
618	* The VM is being reset.
619	*
620	* For the SELM component this means that any GDT/LDT/TSS monitors
621	* needs to be removed.
622	*
623	* @param pVM The cross context VM structure.
624	*/
625	VMMR3DECL(void) SELMR3Reset(PVM pVM)
626	{
627	LogFlow(("SELMR3Reset:\n"));
628	VM_ASSERT_EMT(pVM);
629
630	/*
631	* Uninstall guest GDT/LDT/TSS write access handlers.
632	*/
633	PVMCPU pVCpu = VMMGetCpu(pVM); NOREF(pVCpu);
634	int rc = VINF_SUCCESS;
635	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
636	{
637	#ifdef SELM_TRACK_GUEST_GDT_CHANGES
638	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /fHypervisor/);
639	AssertRC(rc);
640	#endif
641	pVM->selm.s.GuestGdtr.pGdt = RTRCPTR_MAX;
642	pVM->selm.s.GuestGdtr.cbGdt = 0;
643	}
644	pVM->selm.s.fGDTRangeRegistered = false;
645	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
646	{
647	#ifdef SELM_TRACK_GUEST_LDT_CHANGES
648	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
649	AssertRC(rc);
650	#endif
651	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
652	}
653	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
654	{
655	#ifdef SELM_TRACK_GUEST_TSS_CHANGES
656	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /fHypervisor/);
657	AssertRC(rc);
658	#endif
659	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
660	pVM->selm.s.GCSelTss = RTSEL_MAX;
661	}
662
663	/*
664	* Re-initialize other members.
665	*/
666	pVM->selm.s.cbLdtLimit = 0;
667	pVM->selm.s.offLdtHyper = 0;
668	pVM->selm.s.cbMonitoredGuestTss = 0;
669
670	pVM->selm.s.fSyncTSSRing0Stack = false;
671
672	#ifdef VBOX_WITH_RAW_MODE
673	if (!HMIsEnabled(pVM))
674	{
675	/*
676	* Default action when entering raw mode for the first time
677	*/
678	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
679	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
680	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
681	}
682	#endif
683	}
684
685
686	/**
687	* Execute state save operation.
688	*
689	* @returns VBox status code.
690	* @param pVM The cross context VM structure.
691	* @param pSSM SSM operation handle.
692	*/
693	static DECLCALLBACK(int) selmR3Save(PVM pVM, PSSMHANDLE pSSM)
694	{
695	LogFlow(("selmR3Save:\n"));
696
697	/*
698	* Save the basic bits - fortunately all the other things can be resynced on load.
699	*/
700	PSELM pSelm = &pVM->selm.s;
701
702	SSMR3PutBool(pSSM, HMIsEnabled(pVM));
703	SSMR3PutBool(pSSM, pSelm->fSyncTSSRing0Stack);
704	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS]);
705	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_DS]);
706	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]);
707	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_CS64]); /* reserved for DS64. */
708	SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS]);
709	return SSMR3PutSel(pSSM, pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08]);
710	}
711
712
713	/**
714	* Execute state load operation.
715	*
716	* @returns VBox status code.
717	* @param pVM The cross context VM structure.
718	* @param pSSM SSM operation handle.
719	* @param uVersion Data layout version.
720	* @param uPass The data pass.
721	*/
722	static DECLCALLBACK(int) selmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
723	{
724	LogFlow(("selmR3Load:\n"));
725	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
726
727	/*
728	* Validate version.
729	*/
730	if (uVersion != SELM_SAVED_STATE_VERSION)
731	{
732	AssertMsgFailed(("selmR3Load: Invalid version uVersion=%d!\n", uVersion));
733	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
734	}
735
736	/*
737	* Do a reset.
738	*/
739	SELMR3Reset(pVM);
740
741	/* Get the monitoring flag. */
742	bool fIgnored;
743	SSMR3GetBool(pSSM, &fIgnored);
744
745	/* Get the TSS state flag. */
746	SSMR3GetBool(pSSM, &pVM->selm.s.fSyncTSSRing0Stack);
747
748	/*
749	* Get the selectors.
750	*/
751	RTSEL SelCS;
752	SSMR3GetSel(pSSM, &SelCS);
753	RTSEL SelDS;
754	SSMR3GetSel(pSSM, &SelDS);
755	RTSEL SelCS64;
756	SSMR3GetSel(pSSM, &SelCS64);
757	RTSEL SelDS64;
758	SSMR3GetSel(pSSM, &SelDS64);
759	RTSEL SelTSS;
760	SSMR3GetSel(pSSM, &SelTSS);
761	RTSEL SelTSSTrap08;
762	SSMR3GetSel(pSSM, &SelTSSTrap08);
763
764	/* Copy the selectors; they will be checked during relocation. */
765	PSELM pSelm = &pVM->selm.s;
766	pSelm->aHyperSel[SELM_HYPER_SEL_CS] = SelCS;
767	pSelm->aHyperSel[SELM_HYPER_SEL_DS] = SelDS;
768	pSelm->aHyperSel[SELM_HYPER_SEL_CS64] = SelCS64;
769	pSelm->aHyperSel[SELM_HYPER_SEL_TSS] = SelTSS;
770	pSelm->aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SelTSSTrap08;
771
772	return VINF_SUCCESS;
773	}
774
775
776	/**
777	* Sync the GDT, LDT and TSS after loading the state.
778	*
779	* Just to play save, we set the FFs to force syncing before
780	* executing GC code.
781	*
782	* @returns VBox status code.
783	* @param pVM The cross context VM structure.
784	* @param pSSM SSM operation handle.
785	*/
786	static DECLCALLBACK(int) selmR3LoadDone(PVM pVM, PSSMHANDLE pSSM)
787	{
788	#ifdef VBOX_WITH_RAW_MODE
789	if (!HMIsEnabled(pVM))
790	{
791	PVMCPU pVCpu = VMMGetCpu(pVM);
792
793	LogFlow(("selmR3LoadDone:\n"));
794
795	/*
796	* Don't do anything if it's a load failure.
797	*/
798	int rc = SSMR3HandleGetStatus(pSSM);
799	if (RT_FAILURE(rc))
800	return VINF_SUCCESS;
801
802	/*
803	* Do the syncing if we're in protected mode and using raw-mode.
804	*/
805	if (PGMGetGuestMode(pVCpu) != PGMMODE_REAL)
806	{
807	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
808	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
809	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
810	SELMR3UpdateFromCPUM(pVM, pVCpu);
811	}
812
813	/*
814	* Flag everything for resync on next raw mode entry.
815	*/
816	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
817	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
818	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
819	}
820	#endif /VBOX_WITH_RAW_MODE/
821	return VINF_SUCCESS;
822	}
823
824	#ifdef VBOX_WITH_RAW_MODE
825
826	/**
827	* Updates (syncs) the shadow GDT.
828	*
829	* @returns VBox status code.
830	* @param pVM The cross context VM structure.
831	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
832	*/
833	static int selmR3UpdateShadowGdt(PVM pVM, PVMCPU pVCpu)
834	{
835	LogFlow(("selmR3UpdateShadowGdt\n"));
836	Assert(!HMIsEnabled(pVM));
837
838	/*
839	* Always assume the best...
840	*/
841	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_GDT);
842
843	/* If the GDT was changed, then make sure the LDT is checked too */
844	/** @todo only do this if the actual ldtr selector was changed; this is a bit excessive */
845	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
846	/* Same goes for the TSS selector */
847	VMCPU_FF_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
848
849	/*
850	* Get the GDTR and check if there is anything to do (there usually is).
851	*/
852	VBOXGDTR GDTR;
853	CPUMGetGuestGDTR(pVCpu, &GDTR);
854	if (GDTR.cbGdt < sizeof(X86DESC))
855	{
856	Log(("No GDT entries...\n"));
857	return VINF_SUCCESS;
858	}
859
860	/*
861	* Read the Guest GDT.
862	* ASSUMES that the entire GDT is in memory.
863	*/
864	RTUINT cbEffLimit = GDTR.cbGdt;
865	PX86DESC pGDTE = &pVM->selm.s.paGdtR3[1];
866	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pGDTE, GDTR.pGdt + sizeof(X86DESC), cbEffLimit + 1 - sizeof(X86DESC));
867	if (RT_FAILURE(rc))
868	{
869	/*
870	* Read it page by page.
871	*
872	* Keep track of the last valid page and delay memsets and
873	* adjust cbEffLimit to reflect the effective size. The latter
874	* is something we do in the belief that the guest will probably
875	* never actually commit the last page, thus allowing us to keep
876	* our selectors in the high end of the GDT.
877	*/
878	RTUINT cbLeft = cbEffLimit + 1 - sizeof(X86DESC);
879	RTGCPTR GCPtrSrc = (RTGCPTR)GDTR.pGdt + sizeof(X86DESC);
880	uint8_t pu8Dst = (uint8_t )&pVM->selm.s.paGdtR3[1];
881	uint8_t *pu8DstInvalid = pu8Dst;
882
883	while (cbLeft)
884	{
885	RTUINT cb = PAGE_SIZE - (GCPtrSrc & PAGE_OFFSET_MASK);
886	cb = RT_MIN(cb, cbLeft);
887	rc = PGMPhysSimpleReadGCPtr(pVCpu, pu8Dst, GCPtrSrc, cb);
888	if (RT_SUCCESS(rc))
889	{
890	if (pu8DstInvalid != pu8Dst)
891	RT_BZERO(pu8DstInvalid, pu8Dst - pu8DstInvalid);
892	GCPtrSrc += cb;
893	pu8Dst += cb;
894	pu8DstInvalid = pu8Dst;
895	}
896	else if ( rc == VERR_PAGE_NOT_PRESENT
897	\|\| rc == VERR_PAGE_TABLE_NOT_PRESENT)
898	{
899	GCPtrSrc += cb;
900	pu8Dst += cb;
901	}
902	else
903	{
904	AssertLogRelMsgFailed(("Couldn't read GDT at %016RX64, rc=%Rrc!\n", GDTR.pGdt, rc));
905	return VERR_SELM_GDT_READ_ERROR;
906	}
907	cbLeft -= cb;
908	}
909
910	/* any invalid pages at the end? */
911	if (pu8DstInvalid != pu8Dst)
912	{
913	cbEffLimit = pu8DstInvalid - (uint8_t *)pVM->selm.s.paGdtR3 - 1;
914	/* If any GDTEs was invalidated, zero them. */
915	if (cbEffLimit < pVM->selm.s.cbEffGuestGdtLimit)
916	RT_BZERO(pu8DstInvalid + cbEffLimit + 1, pVM->selm.s.cbEffGuestGdtLimit - cbEffLimit);
917	}
918
919	/* keep track of the effective limit. */
920	if (cbEffLimit != pVM->selm.s.cbEffGuestGdtLimit)
921	{
922	Log(("SELMR3UpdateFromCPUM: cbEffGuestGdtLimit=%#x -> %#x (actual %#x)\n",
923	pVM->selm.s.cbEffGuestGdtLimit, cbEffLimit, GDTR.cbGdt));
924	pVM->selm.s.cbEffGuestGdtLimit = cbEffLimit;
925	}
926	}
927
928	/*
929	* Check if the Guest GDT intrudes on our GDT entries.
930	*/
931	/** @todo we should try to minimize relocations by making sure our current selectors can be reused. */
932	RTSEL aHyperSel[SELM_HYPER_SEL_MAX];
933	if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
934	{
935	PX86DESC pGDTEStart = pVM->selm.s.paGdtR3;
936	PX86DESC pGDTECur = (PX86DESC)((char *)pGDTEStart + GDTR.cbGdt + 1 - sizeof(X86DESC));
937	int iGDT = 0;
938
939	Log(("Internal SELM GDT conflict: use non-present entries\n"));
940	STAM_REL_COUNTER_INC(&pVM->selm.s.StatScanForHyperSels);
941	while ((uintptr_t)pGDTECur > (uintptr_t)pGDTEStart)
942	{
943	/* We can reuse non-present entries */
944	if (!pGDTECur->Gen.u1Present)
945	{
946	aHyperSel[iGDT] = ((uintptr_t)pGDTECur - (uintptr_t)pVM->selm.s.paGdtR3) / sizeof(X86DESC);
947	aHyperSel[iGDT] = aHyperSel[iGDT] << X86_SEL_SHIFT;
948	Log(("SELM: Found unused GDT %04X\n", aHyperSel[iGDT]));
949	iGDT++;
950	if (iGDT >= SELM_HYPER_SEL_MAX)
951	break;
952	}
953
954	pGDTECur--;
955	}
956	if (iGDT != SELM_HYPER_SEL_MAX)
957	{
958	AssertLogRelMsgFailed(("Internal SELM GDT conflict.\n"));
959	return VERR_SELM_GDT_TOO_FULL;
960	}
961	}
962	else
963	{
964	aHyperSel[SELM_HYPER_SEL_CS] = SELM_HYPER_DEFAULT_SEL_CS;
965	aHyperSel[SELM_HYPER_SEL_DS] = SELM_HYPER_DEFAULT_SEL_DS;
966	aHyperSel[SELM_HYPER_SEL_CS64] = SELM_HYPER_DEFAULT_SEL_CS64;
967	aHyperSel[SELM_HYPER_SEL_TSS] = SELM_HYPER_DEFAULT_SEL_TSS;
968	aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = SELM_HYPER_DEFAULT_SEL_TSS_TRAP08;
969	}
970
971	# ifdef VBOX_WITH_SAFE_STR
972	/* Use the guest's TR selector to plug the str virtualization hole. */
973	if (CPUMGetGuestTR(pVCpu, NULL) != 0)
974	{
975	Log(("SELM: Use guest TSS selector %x\n", CPUMGetGuestTR(pVCpu, NULL)));
976	aHyperSel[SELM_HYPER_SEL_TSS] = CPUMGetGuestTR(pVCpu, NULL);
977	}
978	# endif
979
980	/*
981	* Work thru the copied GDT entries adjusting them for correct virtualization.
982	*/
983	PX86DESC pGDTEEnd = (PX86DESC)((char *)pGDTE + cbEffLimit + 1 - sizeof(X86DESC));
984	while (pGDTE < pGDTEEnd)
985	{
986	if (pGDTE->Gen.u1Present)
987	selmGuestToShadowDesc(pVM, pGDTE);
988
989	/* Next GDT entry. */
990	pGDTE++;
991	}
992
993	/*
994	* Check if our hypervisor selectors were changed.
995	*/
996	if ( aHyperSel[SELM_HYPER_SEL_CS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS]
997	\|\| aHyperSel[SELM_HYPER_SEL_DS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS]
998	\|\| aHyperSel[SELM_HYPER_SEL_CS64] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64]
999	\|\| aHyperSel[SELM_HYPER_SEL_TSS] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS]
1000	\|\| aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] != pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08])
1001	{
1002	/* Reinitialize our hypervisor GDTs */
1003	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] = aHyperSel[SELM_HYPER_SEL_CS];
1004	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] = aHyperSel[SELM_HYPER_SEL_DS];
1005	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] = aHyperSel[SELM_HYPER_SEL_CS64];
1006	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] = aHyperSel[SELM_HYPER_SEL_TSS];
1007	pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] = aHyperSel[SELM_HYPER_SEL_TSS_TRAP08];
1008
1009	STAM_REL_COUNTER_INC(&pVM->selm.s.StatHyperSelsChanged);
1010
1011	/*
1012	* Do the relocation callbacks to let everyone update their hyper selector dependencies.
1013	* (SELMR3Relocate will call selmR3SetupHyperGDTSelectors() for us.)
1014	*/
1015	VMR3Relocate(pVM, 0);
1016	}
1017	# ifdef VBOX_WITH_SAFE_STR
1018	else if ( cbEffLimit >= SELM_HYPER_DEFAULT_BASE
1019	\|\| CPUMGetGuestTR(pVCpu, NULL) != 0) /* Our shadow TR entry was overwritten when we synced the guest's GDT. */
1020	# else
1021	else if (cbEffLimit >= SELM_HYPER_DEFAULT_BASE)
1022	# endif
1023	/* We overwrote all entries above, so we have to save them again. */
1024	selmR3SetupHyperGDTSelectors(pVM);
1025
1026	/*
1027	* Adjust the cached GDT limit.
1028	* Any GDT entries which have been removed must be cleared.
1029	*/
1030	if (pVM->selm.s.GuestGdtr.cbGdt != GDTR.cbGdt)
1031	{
1032	if (pVM->selm.s.GuestGdtr.cbGdt > GDTR.cbGdt)
1033	RT_BZERO(pGDTE, pVM->selm.s.GuestGdtr.cbGdt - GDTR.cbGdt);
1034	}
1035
1036	/*
1037	* Check if Guest's GDTR is changed.
1038	*/
1039	if ( GDTR.pGdt != pVM->selm.s.GuestGdtr.pGdt
1040	\|\| GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1041	{
1042	Log(("SELMR3UpdateFromCPUM: Guest's GDT is changed to pGdt=%016RX64 cbGdt=%08X\n", GDTR.pGdt, GDTR.cbGdt));
1043
1044	# ifdef SELM_TRACK_GUEST_GDT_CHANGES
1045	/*
1046	* [Re]Register write virtual handler for guest's GDT.
1047	*/
1048	if (pVM->selm.s.GuestGdtr.pGdt != RTRCPTR_MAX && pVM->selm.s.fGDTRangeRegistered)
1049	{
1050	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GuestGdtr.pGdt, false /fHypervisor/);
1051	AssertRC(rc);
1052	}
1053	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1054	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1055	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1056	# ifdef VBOX_WITH_RAW_RING1
1057	/** @todo !HACK ALERT!
1058	* Some guest OSes (QNX) share code and the GDT on the same page;
1059	* PGMR3HandlerVirtualRegister doesn't support more than one handler,
1060	* so we kick out the PATM handler as this one is more important. Fix this
1061	* properly in PGMR3HandlerVirtualRegister?
1062	*/
1063	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1064	{
1065	LogRel(("selmR3UpdateShadowGdt: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority GDT page monitor\n", GDTR.pGdt));
1066	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GDTR.pGdt & PAGE_BASE_GC_MASK, false /fHypervisor/);
1067	AssertRC(rc);
1068	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestGdtWriteHandlerType,
1069	GDTR.pGdt, GDTR.pGdt + GDTR.cbGdt /* already inclusive */,
1070	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1071	}
1072	# endif
1073	if (RT_FAILURE(rc))
1074	return rc;
1075	# endif /* SELM_TRACK_GUEST_GDT_CHANGES */
1076
1077	/* Update saved Guest GDTR. */
1078	pVM->selm.s.GuestGdtr = GDTR;
1079	pVM->selm.s.fGDTRangeRegistered = true;
1080	}
1081
1082	return VINF_SUCCESS;
1083	}
1084
1085
1086	/**
1087	* Updates (syncs) the shadow LDT.
1088	*
1089	* @returns VBox status code.
1090	* @param pVM The cross context VM structure.
1091	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1092	*/
1093	static int selmR3UpdateShadowLdt(PVM pVM, PVMCPU pVCpu)
1094	{
1095	LogFlow(("selmR3UpdateShadowLdt\n"));
1096	int rc = VINF_SUCCESS;
1097	Assert(!HMIsEnabled(pVM));
1098
1099	/*
1100	* Always assume the best...
1101	*/
1102	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_LDT);
1103
1104	/*
1105	* LDT handling is done similarly to the GDT handling with a shadow
1106	* array. However, since the LDT is expected to be swappable (at least
1107	* some ancient OSes makes it swappable) it must be floating and
1108	* synced on a per-page basis.
1109	*
1110	* Eventually we will change this to be fully on demand. Meaning that
1111	* we will only sync pages containing LDT selectors actually used and
1112	* let the #PF handler lazily sync pages as they are used.
1113	* (This applies to GDT too, when we start making OS/2 fast.)
1114	*/
1115
1116	/*
1117	* First, determine the current LDT selector.
1118	*/
1119	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1120	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
1121	{
1122	/* ldtr = 0 - update hyper LDTR and deregister any active handler. */
1123	CPUMSetHyperLDTR(pVCpu, 0);
1124	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1125	{
1126	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1127	AssertRC(rc);
1128	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1129	}
1130	pVM->selm.s.cbLdtLimit = 0;
1131	return VINF_SUCCESS;
1132	}
1133
1134	/*
1135	* Get the LDT selector.
1136	*/
1137	/** @todo this is wrong, use CPUMGetGuestLdtrEx */
1138	PX86DESC pDesc = &pVM->selm.s.paGdtR3[SelLdt >> X86_SEL_SHIFT];
1139	RTGCPTR GCPtrLdt = X86DESC_BASE(pDesc);
1140	uint32_t cbLdt = X86DESC_LIMIT_G(pDesc);
1141
1142	/*
1143	* Validate it.
1144	*/
1145	if ( !cbLdt
1146	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt
1147	\|\| pDesc->Gen.u1DescType
1148	\|\| pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1149	{
1150	AssertMsg(!cbLdt, ("Invalid LDT %04x!\n", SelLdt));
1151
1152	/* cbLdt > 0:
1153	* This is quite impossible, so we do as most people do when faced with
1154	* the impossible, we simply ignore it.
1155	*/
1156	CPUMSetHyperLDTR(pVCpu, 0);
1157	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1158	{
1159	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1160	AssertRC(rc);
1161	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1162	}
1163	return VINF_SUCCESS;
1164	}
1165	/** @todo check what intel does about odd limits. */
1166	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1167
1168	/*
1169	* Use the cached guest ldt address if the descriptor has already been modified (see below)
1170	* (this is necessary due to redundant LDT updates; see todo above at GDT sync)
1171	*/
1172	if (MMHyperIsInsideArea(pVM, GCPtrLdt))
1173	GCPtrLdt = pVM->selm.s.GCPtrGuestLdt; /* use the old one */
1174
1175
1176	/** @todo Handle only present LDT segments. */
1177	// if (pDesc->Gen.u1Present)
1178	{
1179	/*
1180	* Check if Guest's LDT address/limit is changed.
1181	*/
1182	if ( GCPtrLdt != pVM->selm.s.GCPtrGuestLdt
1183	\|\| cbLdt != pVM->selm.s.cbLdtLimit)
1184	{
1185	Log(("SELMR3UpdateFromCPUM: Guest LDT changed to from %RGv:%04x to %RGv:%04x. (GDTR=%016RX64:%04x)\n",
1186	pVM->selm.s.GCPtrGuestLdt, pVM->selm.s.cbLdtLimit, GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1187
1188	# ifdef SELM_TRACK_GUEST_LDT_CHANGES
1189	/*
1190	* [Re]Register write virtual handler for guest's GDT.
1191	* In the event of LDT overlapping something, don't install it just assume it's being updated.
1192	*/
1193	if (pVM->selm.s.GCPtrGuestLdt != RTRCPTR_MAX)
1194	{
1195	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestLdt, false /fHypervisor/);
1196	AssertRC(rc);
1197	}
1198	# ifdef LOG_ENABLED
1199	if (pDesc->Gen.u1Present)
1200	Log(("LDT selector marked not present!!\n"));
1201	# endif
1202	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestLdtWriteHandlerType,
1203	GCPtrLdt, GCPtrLdt + cbLdt /* already inclusive */,
1204	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1205	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1206	{
1207	/** @todo investigate the various cases where conflicts happen and try avoid them by enh. the instruction emulation. */
1208	pVM->selm.s.GCPtrGuestLdt = RTRCPTR_MAX;
1209	Log(("WARNING: Guest LDT (%RGv:%04x) conflicted with existing access range!! Assumes LDT is begin updated. (GDTR=%016RX64:%04x)\n",
1210	GCPtrLdt, cbLdt, pVM->selm.s.GuestGdtr.pGdt, pVM->selm.s.GuestGdtr.cbGdt));
1211	}
1212	else if (RT_SUCCESS(rc))
1213	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1214	else
1215	{
1216	CPUMSetHyperLDTR(pVCpu, 0);
1217	return rc;
1218	}
1219	# else
1220	pVM->selm.s.GCPtrGuestLdt = GCPtrLdt;
1221	# endif
1222	pVM->selm.s.cbLdtLimit = cbLdt;
1223	}
1224	}
1225
1226	/*
1227	* Calc Shadow LDT base.
1228	*/
1229	unsigned off;
1230	pVM->selm.s.offLdtHyper = off = (GCPtrLdt & PAGE_OFFSET_MASK);
1231	RTGCPTR GCPtrShadowLDT = (RTGCPTR)((RTGCUINTPTR)pVM->selm.s.pvLdtRC + off);
1232	PX86DESC pShadowLDT = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1233
1234	/*
1235	* Enable the LDT selector in the shadow GDT.
1236	*/
1237	pDesc->Gen.u1Present = 1;
1238	pDesc->Gen.u16BaseLow = RT_LOWORD(GCPtrShadowLDT);
1239	pDesc->Gen.u8BaseHigh1 = RT_BYTE3(GCPtrShadowLDT);
1240	pDesc->Gen.u8BaseHigh2 = RT_BYTE4(GCPtrShadowLDT);
1241	pDesc->Gen.u1Available = 0;
1242	pDesc->Gen.u1Long = 0;
1243	if (cbLdt > 0xffff)
1244	{
1245	cbLdt = 0xffff;
1246	pDesc->Gen.u4LimitHigh = 0;
1247	pDesc->Gen.u16LimitLow = pDesc->Gen.u1Granularity ? 0xf : 0xffff;
1248	}
1249
1250	/*
1251	* Set Hyper LDTR and notify TRPM.
1252	*/
1253	CPUMSetHyperLDTR(pVCpu, SelLdt);
1254	LogFlow(("selmR3UpdateShadowLdt: Hyper LDTR %#x\n", SelLdt));
1255
1256	/*
1257	* Loop synchronising the LDT page by page.
1258	*/
1259	/** @todo investigate how intel handle various operations on half present cross page entries. */
1260	off = GCPtrLdt & (sizeof(X86DESC) - 1);
1261	AssertMsg(!off, ("LDT is not aligned on entry size! GCPtrLdt=%08x\n", GCPtrLdt));
1262
1263	/* Note: Do not skip the first selector; unlike the GDT, a zero LDT selector is perfectly valid. */
1264	unsigned cbLeft = cbLdt + 1;
1265	PX86DESC pLDTE = pShadowLDT;
1266	while (cbLeft)
1267	{
1268	/*
1269	* Read a chunk.
1270	*/
1271	unsigned cbChunk = PAGE_SIZE - ((RTGCUINTPTR)GCPtrLdt & PAGE_OFFSET_MASK);
1272	if (cbChunk > cbLeft)
1273	cbChunk = cbLeft;
1274	rc = PGMPhysSimpleReadGCPtr(pVCpu, pShadowLDT, GCPtrLdt, cbChunk);
1275	if (RT_SUCCESS(rc))
1276	{
1277	/*
1278	* Mark page
1279	*/
1280	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, X86_PTE_P \| X86_PTE_A \| X86_PTE_D);
1281	AssertRC(rc);
1282
1283	/*
1284	* Loop thru the available LDT entries.
1285	* Figure out where to start and end and the potential cross pageness of
1286	* things adds a little complexity. pLDTE is updated there and not in the
1287	* 'next' part of the loop. The pLDTEEnd is inclusive.
1288	*/
1289	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pShadowLDT + cbChunk) - 1;
1290	if (pLDTE + 1 < pShadowLDT)
1291	pLDTE = (PX86DESC)((uintptr_t)pShadowLDT + off);
1292	while (pLDTE <= pLDTEEnd)
1293	{
1294	if (pLDTE->Gen.u1Present)
1295	selmGuestToShadowDesc(pVM, pLDTE);
1296
1297	/* Next LDT entry. */
1298	pLDTE++;
1299	}
1300	}
1301	else
1302	{
1303	RT_BZERO(pShadowLDT, cbChunk);
1304	AssertMsg(rc == VERR_PAGE_NOT_PRESENT \|\| rc == VERR_PAGE_TABLE_NOT_PRESENT, ("rc=%Rrc\n", rc));
1305	rc = PGMMapSetPage(pVM, GCPtrShadowLDT & PAGE_BASE_GC_MASK, PAGE_SIZE, 0);
1306	AssertRC(rc);
1307	}
1308
1309	/*
1310	* Advance to the next page.
1311	*/
1312	cbLeft -= cbChunk;
1313	GCPtrShadowLDT += cbChunk;
1314	pShadowLDT = (PX86DESC)((char *)pShadowLDT + cbChunk);
1315	GCPtrLdt += cbChunk;
1316	}
1317
1318	return VINF_SUCCESS;
1319	}
1320
1321
1322	/**
1323	* Checks and updates segment selector registers.
1324	*
1325	* @returns VBox strict status code.
1326	* @retval VINF_EM_RESCHEDULE_REM if a stale register was found.
1327	*
1328	* @param pVM The cross context VM structure.
1329	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
1330	*/
1331	static VBOXSTRICTRC selmR3UpdateSegmentRegisters(PVM pVM, PVMCPU pVCpu)
1332	{
1333	Assert(CPUMIsGuestInProtectedMode(pVCpu));
1334	Assert(!HMIsEnabled(pVM));
1335
1336	/*
1337	* No stale selectors in V8086 mode.
1338	*/
1339	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1340	if (pCtx->eflags.Bits.u1VM)
1341	return VINF_SUCCESS;
1342
1343	/*
1344	* Check for stale selectors and load hidden register bits where they
1345	* are missing.
1346	*/
1347	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
1348	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1349	PCPUMSELREG paSReg = CPUMCTX_FIRST_SREG(pCtx);
1350	for (uint32_t iSReg = 0; iSReg < X86_SREG_COUNT; iSReg++)
1351	{
1352	RTSEL const Sel = paSReg[iSReg].Sel;
1353	if (Sel & X86_SEL_MASK_OFF_RPL)
1354	{
1355	/* Get the shadow descriptor entry corresponding to this. */
1356	static X86DESC const s_NotPresentDesc = { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } };
1357	PCX86DESC pDesc;
1358	if (!(Sel & X86_SEL_LDT))
1359	{
1360	if ((Sel \| (sizeof(*pDesc) - 1)) <= pCtx->gdtr.cbGdt)
1361	pDesc = &pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
1362	else
1363	pDesc = &s_NotPresentDesc;
1364	}
1365	else
1366	{
1367	if ((Sel \| (sizeof(*pDesc) - 1)) <= pVM->selm.s.cbLdtLimit)
1368	pDesc = &((PCX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper))[Sel >> X86_SEL_SHIFT];
1369	else
1370	pDesc = &s_NotPresentDesc;
1371	}
1372
1373	/* Check the segment register. */
1374	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &paSReg[iSReg]))
1375	{
1376	if (!(paSReg[iSReg].fFlags & CPUMSELREG_FLAGS_STALE))
1377	{
1378	/* Did it go stale? */
1379	if (selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1380	{
1381	Log2(("SELM: Detected stale %s=%#x (was valid)\n", g_aszSRegNms[iSReg], Sel));
1382	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1383	paSReg[iSReg].fFlags \|= CPUMSELREG_FLAGS_STALE;
1384	rcStrict = VINF_EM_RESCHEDULE_REM;
1385	}
1386	}
1387	else
1388	{
1389	/* Did it stop being stale? I.e. did the guest change it things
1390	back to the way they were? */
1391	if (!selmIsSRegStale32(&paSReg[iSReg], pDesc, iSReg))
1392	{
1393	STAM_REL_COUNTER_INC(&pVM->selm.s.StatStaleToUnstaleSReg);
1394	paSReg[iSReg].fFlags &= CPUMSELREG_FLAGS_STALE;
1395	}
1396	else
1397	{
1398	Log2(("SELM: Already stale %s=%#x\n", g_aszSRegNms[iSReg], Sel));
1399	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatAlreadyStaleSReg[iSReg]);
1400	rcStrict = VINF_EM_RESCHEDULE_REM;
1401	}
1402	}
1403	}
1404	/* Load the hidden registers if it's a valid descriptor for the
1405	current segment register. */
1406	else if (selmIsShwDescGoodForSReg(&paSReg[iSReg], pDesc, iSReg, uCpl))
1407	{
1408	selmLoadHiddenSRegFromShadowDesc(&paSReg[iSReg], pDesc);
1409	STAM_COUNTER_INC(&pVM->selm.s.aStatUpdatedSReg[iSReg]);
1410	}
1411	/* It's stale. */
1412	else
1413	{
1414	Log2(("SELM: Detected stale %s=%#x (wasn't valid)\n", g_aszSRegNms[iSReg], Sel));
1415	STAM_REL_COUNTER_INC(&pVM->selm.s.aStatDetectedStaleSReg[iSReg]);
1416	paSReg[iSReg].fFlags = CPUMSELREG_FLAGS_STALE;
1417	rcStrict = VINF_EM_RESCHEDULE_REM;
1418	}
1419	}
1420	/* else: 0 selector, ignore. */
1421	}
1422
1423	return rcStrict;
1424	}
1425
1426
1427	/**
1428	* Updates the Guest GDT & LDT virtualization based on current CPU state.
1429	*
1430	* @returns VBox status code.
1431	* @param pVM The cross context VM structure.
1432	* @param pVCpu The cross context virtual CPU structure.
1433	*/
1434	VMMR3DECL(VBOXSTRICTRC) SELMR3UpdateFromCPUM(PVM pVM, PVMCPU pVCpu)
1435	{
1436	STAM_PROFILE_START(&pVM->selm.s.StatUpdateFromCPUM, a);
1437	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1438
1439	/*
1440	* GDT sync
1441	*/
1442	int rc;
1443	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT))
1444	{
1445	rc = selmR3UpdateShadowGdt(pVM, pVCpu);
1446	if (RT_FAILURE(rc))
1447	return rc; /* We're toast, so forget the profiling. */
1448	AssertRCSuccess(rc);
1449	}
1450
1451	/*
1452	* TSS sync
1453	*/
1454	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1455	{
1456	rc = SELMR3SyncTSS(pVM, pVCpu);
1457	if (RT_FAILURE(rc))
1458	return rc;
1459	AssertRCSuccess(rc);
1460	}
1461
1462	/*
1463	* LDT sync
1464	*/
1465	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_LDT))
1466	{
1467	rc = selmR3UpdateShadowLdt(pVM, pVCpu);
1468	if (RT_FAILURE(rc))
1469	return rc;
1470	AssertRCSuccess(rc);
1471	}
1472
1473	/*
1474	* Check selector registers.
1475	*/
1476	VBOXSTRICTRC rcStrict = selmR3UpdateSegmentRegisters(pVM, pVCpu);
1477
1478	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1479	return rcStrict;
1480	}
1481
1482
1483	/**
1484	* Synchronize the shadowed fields in the TSS.
1485	*
1486	* At present we're shadowing the ring-0 stack selector & pointer, and the
1487	* interrupt redirection bitmap (if present). We take the lazy approach wrt to
1488	* REM and this function is called both if REM made any changes to the TSS or
1489	* loaded TR.
1490	*
1491	* @returns VBox status code.
1492	* @param pVM The cross context VM structure.
1493	* @param pVCpu The cross context virtual CPU structure.
1494	*/
1495	VMMR3DECL(int) SELMR3SyncTSS(PVM pVM, PVMCPU pVCpu)
1496	{
1497	LogFlow(("SELMR3SyncTSS\n"));
1498	int rc;
1499	AssertReturnStmt(!HMIsEnabled(pVM), VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS), VINF_SUCCESS);
1500
1501	STAM_PROFILE_START(&pVM->selm.s.StatTSSSync, a);
1502	Assert(VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS));
1503
1504	/*
1505	* Get TR and extract and store the basic info.
1506	*
1507	* Note! The TSS limit is not checked by the LTR code, so we
1508	* have to be a bit careful with it. We make sure cbTss
1509	* won't be zero if TR is valid and if it's NULL we'll
1510	* make sure cbTss is 0.
1511	*/
1512	/** @todo use the hidden bits, not shadow GDT. */
1513	CPUMSELREGHID trHid;
1514	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1515	RTGCPTR GCPtrTss = trHid.u64Base;
1516	uint32_t cbTss = trHid.u32Limit;
1517	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1518	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1519	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1520	if (SelTss & X86_SEL_MASK_OFF_RPL)
1521	{
1522	Assert(!(SelTss & X86_SEL_LDT));
1523	Assert(trHid.Attr.n.u1DescType == 0);
1524	Assert( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1525	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY);
1526	if (!++cbTss)
1527	cbTss = UINT32_MAX;
1528	}
1529	else
1530	{
1531	Assert( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1532	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1533	cbTss = 0; /* the reset case. */
1534	}
1535	pVM->selm.s.cbGuestTss = cbTss;
1536	pVM->selm.s.fGuestTss32Bit = trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1537	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY;
1538
1539	/*
1540	* Figure out the size of what need to monitor.
1541	*/
1542	/* We're not interested in any 16-bit TSSes. */
1543	uint32_t cbMonitoredTss = cbTss;
1544	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1545	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1546	cbMonitoredTss = 0;
1547
1548	pVM->selm.s.offGuestIoBitmap = 0;
1549	bool fNoRing1Stack = true;
1550	if (cbMonitoredTss)
1551	{
1552	/*
1553	* 32-bit TSS. What we're really keen on is the SS0 and ESP0 fields.
1554	* If VME is enabled we also want to keep an eye on the interrupt
1555	* redirection bitmap.
1556	*/
1557	VBOXTSS Tss;
1558	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1559	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1560	if ( !(cr4 & X86_CR4_VME)
1561	\|\| ( RT_SUCCESS(rc)
1562	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1563	&& Tss.offIoBitmap > cbTss) /* beyond the end / /* @todo not sure how the partial case is handled; probably not allowed. */
1564	)
1565	/* No interrupt redirection bitmap, just ESP0 and SS0. */
1566	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1567	else if (RT_SUCCESS(rc))
1568	{
1569	/*
1570	* Everything up to and including the interrupt redirection bitmap. Unfortunately
1571	* this can be quite a large chunk. We use to skip it earlier and just hope it
1572	* was kind of static...
1573	*
1574	* Update the virtual interrupt redirection bitmap while we're here.
1575	* (It is located in the 32 bytes before TR:offIoBitmap.)
1576	*/
1577	cbMonitoredTss = Tss.offIoBitmap;
1578	pVM->selm.s.offGuestIoBitmap = Tss.offIoBitmap;
1579
1580	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1581	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pVM->selm.s.Tss.IntRedirBitmap,
1582	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1583	AssertRC(rc);
1584	/** @todo memset the bitmap on failure? */
1585	Log2(("Redirection bitmap:\n"));
1586	Log2(("%.*Rhxd\n", sizeof(Tss.IntRedirBitmap), &pVM->selm.s.Tss.IntRedirBitmap));
1587	}
1588	else
1589	{
1590	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1591	pVM->selm.s.offGuestIoBitmap = 0;
1592	/** @todo memset the bitmap? */
1593	}
1594
1595	/*
1596	* Update the ring 0 stack selector and base address.
1597	*/
1598	if (RT_SUCCESS(rc))
1599	{
1600	# ifdef LOG_ENABLED
1601	if (LogIsEnabled())
1602	{
1603	uint32_t ssr0, espr0;
1604	SELMGetRing1Stack(pVM, &ssr0, &espr0);
1605	if ((ssr0 & ~1) != Tss.ss0 \|\| espr0 != Tss.esp0)
1606	{
1607	RTGCPHYS GCPhys = NIL_RTGCPHYS;
1608	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1609	Log(("SELMR3SyncTSS: Updating TSS ring 0 stack to %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1610	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1611	AssertMsg(ssr0 != Tss.ss0,
1612	("ring-1 leak into TSS.SS0! %04X:%08X from %04X:%08X; TSS Phys=%RGp)\n",
1613	Tss.ss0, Tss.esp0, (ssr0 & ~1), espr0, GCPhys));
1614	}
1615	Log(("offIoBitmap=%#x\n", Tss.offIoBitmap));
1616	}
1617	# endif /* LOG_ENABLED */
1618	AssertMsg(!(Tss.ss0 & 3), ("ring-1 leak into TSS.SS0? %04X:%08X\n", Tss.ss0, Tss.esp0));
1619
1620	/* Update our TSS structure for the guest's ring 1 stack */
1621	selmSetRing1Stack(pVM, Tss.ss0 \| 1, Tss.esp0);
1622	pVM->selm.s.fSyncTSSRing0Stack = fNoRing1Stack = false;
1623
1624	# ifdef VBOX_WITH_RAW_RING1
1625	/* Update our TSS structure for the guest's ring 2 stack */
1626	if (EMIsRawRing1Enabled(pVM))
1627	{
1628	if ( (pVM->selm.s.Tss.ss2 != ((Tss.ss1 & ~2) \| 1))
1629	\|\| pVM->selm.s.Tss.esp2 != Tss.esp1)
1630	Log(("SELMR3SyncTSS: Updating TSS ring 1 stack to %04X:%08X from %04X:%08X\n", Tss.ss1, Tss.esp1, (pVM->selm.s.Tss.ss2 & ~2) \| 1, pVM->selm.s.Tss.esp2));
1631	selmSetRing2Stack(pVM, (Tss.ss1 & ~1) \| 2, Tss.esp1);
1632	}
1633	# endif
1634	}
1635	}
1636
1637	/*
1638	* Flush the ring-1 stack and the direct syscall dispatching if we
1639	* cannot obtain SS0:ESP0.
1640	*/
1641	if (fNoRing1Stack)
1642	{
1643	selmSetRing1Stack(pVM, 0 /* invalid SS */, 0);
1644	pVM->selm.s.fSyncTSSRing0Stack = cbMonitoredTss != 0;
1645
1646	/** @todo handle these dependencies better! */
1647	TRPMR3SetGuestTrapHandler(pVM, 0x2E, TRPM_INVALID_HANDLER);
1648	TRPMR3SetGuestTrapHandler(pVM, 0x80, TRPM_INVALID_HANDLER);
1649	}
1650
1651	/*
1652	* Check for monitor changes and apply them.
1653	*/
1654	if ( GCPtrTss != pVM->selm.s.GCPtrGuestTss
1655	\|\| cbMonitoredTss != pVM->selm.s.cbMonitoredGuestTss)
1656	{
1657	Log(("SELMR3SyncTSS: Guest's TSS is changed to pTss=%RGv cbMonitoredTss=%08X cbGuestTss=%#08x\n",
1658	GCPtrTss, cbMonitoredTss, pVM->selm.s.cbGuestTss));
1659
1660	/* Release the old range first. */
1661	if (pVM->selm.s.GCPtrGuestTss != RTRCPTR_MAX)
1662	{
1663	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, pVM->selm.s.GCPtrGuestTss, false /fHypervisor/);
1664	AssertRC(rc);
1665	}
1666
1667	/* Register the write handler if TS != 0. */
1668	if (cbMonitoredTss != 0)
1669	{
1670	# ifdef SELM_TRACK_GUEST_TSS_CHANGES
1671	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1672	GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1673	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1674	if (RT_FAILURE(rc))
1675	{
1676	# ifdef VBOX_WITH_RAW_RING1
1677	/** @todo !HACK ALERT!
1678	* Some guest OSes (QNX) share code and the TSS on the same page;
1679	* PGMR3HandlerVirtualRegister doesn't support more than one
1680	* handler, so we kick out the PATM handler as this one is more
1681	* important. Fix this properly in PGMR3HandlerVirtualRegister?
1682	*/
1683	if (rc == VERR_PGM_HANDLER_VIRTUAL_CONFLICT)
1684	{
1685	LogRel(("SELMR3SyncTSS: Virtual handler conflict %RGv -> kick out PATM handler for the higher priority TSS page monitor\n", GCPtrTss));
1686	rc = PGMHandlerVirtualDeregister(pVM, pVCpu, GCPtrTss & PAGE_BASE_GC_MASK, false /fHypervisor/);
1687	AssertRC(rc);
1688
1689	rc = PGMR3HandlerVirtualRegister(pVM, pVCpu, pVM->selm.s.hGuestTssWriteHandlerType,
1690	GCPtrTss, GCPtrTss + cbMonitoredTss - 1,
1691	NULL /pvUserR3/, NIL_RTR0PTR /pvUserRC/, NULL /pszDesc/);
1692	if (RT_FAILURE(rc))
1693	{
1694	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1695	return rc;
1696	}
1697	}
1698	# else
1699	STAM_PROFILE_STOP(&pVM->selm.s.StatUpdateFromCPUM, a);
1700	return rc;
1701	# endif
1702	}
1703	# endif /* SELM_TRACK_GUEST_TSS_CHANGES */
1704
1705	/* Update saved Guest TSS info. */
1706	pVM->selm.s.GCPtrGuestTss = GCPtrTss;
1707	pVM->selm.s.cbMonitoredGuestTss = cbMonitoredTss;
1708	pVM->selm.s.GCSelTss = SelTss;
1709	}
1710	else
1711	{
1712	pVM->selm.s.GCPtrGuestTss = RTRCPTR_MAX;
1713	pVM->selm.s.cbMonitoredGuestTss = 0;
1714	pVM->selm.s.GCSelTss = 0;
1715	}
1716	}
1717
1718	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_SELM_SYNC_TSS);
1719
1720	STAM_PROFILE_STOP(&pVM->selm.s.StatTSSSync, a);
1721	return VINF_SUCCESS;
1722	}
1723
1724
1725	/**
1726	* Compares the Guest GDT and LDT with the shadow tables.
1727	* This is a VBOX_STRICT only function.
1728	*
1729	* @returns VBox status code.
1730	* @param pVM The cross context VM structure.
1731	*/
1732	VMMR3DECL(int) SELMR3DebugCheck(PVM pVM)
1733	{
1734	# ifdef VBOX_STRICT
1735	PVMCPU pVCpu = VMMGetCpu(pVM);
1736	AssertReturn(!HMIsEnabled(pVM), VERR_SELM_HM_IPE);
1737
1738	/*
1739	* Get GDTR and check for conflict.
1740	*/
1741	VBOXGDTR GDTR;
1742	CPUMGetGuestGDTR(pVCpu, &GDTR);
1743	if (GDTR.cbGdt == 0)
1744	return VINF_SUCCESS;
1745
1746	if (GDTR.cbGdt >= (unsigned)(pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
1747	Log(("SELMR3DebugCheck: guest GDT size forced us to look for unused selectors.\n"));
1748
1749	if (GDTR.cbGdt != pVM->selm.s.GuestGdtr.cbGdt)
1750	Log(("SELMR3DebugCheck: limits have changed! new=%d old=%d\n", GDTR.cbGdt, pVM->selm.s.GuestGdtr.cbGdt));
1751
1752	/*
1753	* Loop thru the GDT checking each entry.
1754	*/
1755	RTGCPTR GCPtrGDTEGuest = GDTR.pGdt;
1756	PX86DESC pGDTE = pVM->selm.s.paGdtR3;
1757	PX86DESC pGDTEEnd = (PX86DESC)((uintptr_t)pGDTE + GDTR.cbGdt);
1758	while (pGDTE < pGDTEEnd)
1759	{
1760	X86DESC GDTEGuest;
1761	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTEGuest, GCPtrGDTEGuest, sizeof(GDTEGuest));
1762	if (RT_SUCCESS(rc))
1763	{
1764	if (pGDTE->Gen.u1DescType \|\| pGDTE->Gen.u4Type != X86_SEL_TYPE_SYS_LDT)
1765	{
1766	if ( pGDTE->Gen.u16LimitLow != GDTEGuest.Gen.u16LimitLow
1767	\|\| pGDTE->Gen.u4LimitHigh != GDTEGuest.Gen.u4LimitHigh
1768	\|\| pGDTE->Gen.u16BaseLow != GDTEGuest.Gen.u16BaseLow
1769	\|\| pGDTE->Gen.u8BaseHigh1 != GDTEGuest.Gen.u8BaseHigh1
1770	\|\| pGDTE->Gen.u8BaseHigh2 != GDTEGuest.Gen.u8BaseHigh2
1771	\|\| pGDTE->Gen.u1DefBig != GDTEGuest.Gen.u1DefBig
1772	\|\| pGDTE->Gen.u1DescType != GDTEGuest.Gen.u1DescType)
1773	{
1774	unsigned iGDT = pGDTE - pVM->selm.s.paGdtR3;
1775	SELMR3DumpDescriptor(*pGDTE, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, shadow");
1776	SELMR3DumpDescriptor(GDTEGuest, iGDT << 3, "SELMR3DebugCheck: GDT mismatch, guest");
1777	}
1778	}
1779	}
1780
1781	/* Advance to the next descriptor. */
1782	GCPtrGDTEGuest += sizeof(X86DESC);
1783	pGDTE++;
1784	}
1785
1786
1787	/*
1788	* LDT?
1789	*/
1790	RTSEL SelLdt = CPUMGetGuestLDTR(pVCpu);
1791	if ((SelLdt & X86_SEL_MASK_OFF_RPL) == 0)
1792	return VINF_SUCCESS;
1793	Assert(!(SelLdt & X86_SEL_LDT));
1794	if (SelLdt > GDTR.cbGdt)
1795	{
1796	Log(("SELMR3DebugCheck: ldt is out of bound SelLdt=%#x\n", SelLdt));
1797	return VERR_SELM_LDT_OUT_OF_BOUNDS;
1798	}
1799	X86DESC LDTDesc;
1800	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTDesc, GDTR.pGdt + (SelLdt & X86_SEL_MASK), sizeof(LDTDesc));
1801	if (RT_FAILURE(rc))
1802	{
1803	Log(("SELMR3DebugCheck: Failed to read LDT descriptor. rc=%d\n", rc));
1804	return rc;
1805	}
1806	RTGCPTR GCPtrLDTEGuest = X86DESC_BASE(&LDTDesc);
1807	uint32_t cbLdt = X86DESC_LIMIT_G(&LDTDesc);
1808
1809	/*
1810	* Validate it.
1811	*/
1812	if (!cbLdt)
1813	return VINF_SUCCESS;
1814	/** @todo check what intel does about odd limits. */
1815	AssertMsg(RT_ALIGN(cbLdt + 1, sizeof(X86DESC)) == cbLdt + 1 && cbLdt <= 0xffff, ("cbLdt=%d\n", cbLdt));
1816	if ( LDTDesc.Gen.u1DescType
1817	\|\| LDTDesc.Gen.u4Type != X86_SEL_TYPE_SYS_LDT
1818	\|\| SelLdt >= pVM->selm.s.GuestGdtr.cbGdt)
1819	{
1820	Log(("SELmR3DebugCheck: Invalid LDT %04x!\n", SelLdt));
1821	return VERR_SELM_INVALID_LDT;
1822	}
1823
1824	/*
1825	* Loop thru the LDT checking each entry.
1826	*/
1827	unsigned off = (GCPtrLDTEGuest & PAGE_OFFSET_MASK);
1828	PX86DESC pLDTE = (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1829	PX86DESC pLDTEEnd = (PX86DESC)((uintptr_t)pGDTE + cbLdt);
1830	while (pLDTE < pLDTEEnd)
1831	{
1832	X86DESC LDTEGuest;
1833	rc = PGMPhysSimpleReadGCPtr(pVCpu, &LDTEGuest, GCPtrLDTEGuest, sizeof(LDTEGuest));
1834	if (RT_SUCCESS(rc))
1835	{
1836	if ( pLDTE->Gen.u16LimitLow != LDTEGuest.Gen.u16LimitLow
1837	\|\| pLDTE->Gen.u4LimitHigh != LDTEGuest.Gen.u4LimitHigh
1838	\|\| pLDTE->Gen.u16BaseLow != LDTEGuest.Gen.u16BaseLow
1839	\|\| pLDTE->Gen.u8BaseHigh1 != LDTEGuest.Gen.u8BaseHigh1
1840	\|\| pLDTE->Gen.u8BaseHigh2 != LDTEGuest.Gen.u8BaseHigh2
1841	\|\| pLDTE->Gen.u1DefBig != LDTEGuest.Gen.u1DefBig
1842	\|\| pLDTE->Gen.u1DescType != LDTEGuest.Gen.u1DescType)
1843	{
1844	unsigned iLDT = pLDTE - (PX86DESC)((uintptr_t)pVM->selm.s.pvLdtR3 + off);
1845	SELMR3DumpDescriptor(*pLDTE, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, shadow");
1846	SELMR3DumpDescriptor(LDTEGuest, iLDT << 3, "SELMR3DebugCheck: LDT mismatch, guest");
1847	}
1848	}
1849
1850	/* Advance to the next descriptor. */
1851	GCPtrLDTEGuest += sizeof(X86DESC);
1852	pLDTE++;
1853	}
1854
1855	# else /* !VBOX_STRICT */
1856	NOREF(pVM);
1857	# endif /* !VBOX_STRICT */
1858
1859	return VINF_SUCCESS;
1860	}
1861
1862
1863	/**
1864	* Validates the RawR0 TSS values against the one in the Guest TSS.
1865	*
1866	* @returns true if it matches.
1867	* @returns false and assertions on mismatch..
1868	* @param pVM The cross context VM structure.
1869	*/
1870	VMMR3DECL(bool) SELMR3CheckTSS(PVM pVM)
1871	{
1872	# if defined(VBOX_STRICT) && defined(SELM_TRACK_GUEST_TSS_CHANGES)
1873	PVMCPU pVCpu = VMMGetCpu(pVM);
1874
1875	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1876	return true;
1877
1878	/*
1879	* Get TR and extract the basic info.
1880	*/
1881	CPUMSELREGHID trHid;
1882	RTSEL SelTss = CPUMGetGuestTR(pVCpu, &trHid);
1883	RTGCPTR GCPtrTss = trHid.u64Base;
1884	uint32_t cbTss = trHid.u32Limit;
1885	Assert( (SelTss & X86_SEL_MASK_OFF_RPL)
1886	\|\| (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1887	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */));
1888	if (SelTss & X86_SEL_MASK_OFF_RPL)
1889	{
1890	AssertReturn(!(SelTss & X86_SEL_LDT), false);
1891	AssertReturn(trHid.Attr.n.u1DescType == 0, false);
1892	AssertReturn( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_286_TSS_BUSY
1893	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY,
1894	false);
1895	if (!++cbTss)
1896	cbTss = UINT32_MAX;
1897	}
1898	else
1899	{
1900	AssertReturn( (cbTss == 0 && GCPtrTss == 0 && trHid.Attr.u == 0 /* TR=0 */)
1901	\|\| (cbTss == 0xffff && GCPtrTss == 0 && trHid.Attr.n.u1Present && trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY /* RESET */),
1902	false);
1903	cbTss = 0; /* the reset case. */
1904	}
1905	AssertMsgReturn(pVM->selm.s.cbGuestTss == cbTss, ("%#x %#x\n", pVM->selm.s.cbGuestTss, cbTss), false);
1906	AssertMsgReturn(pVM->selm.s.fGuestTss32Bit == ( trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_AVAIL
1907	\|\| trHid.Attr.n.u4Type == X86_SEL_TYPE_SYS_386_TSS_BUSY),
1908	("%RTbool u4Type=%d\n", pVM->selm.s.fGuestTss32Bit, trHid.Attr.n.u4Type),
1909	false);
1910	AssertMsgReturn( pVM->selm.s.GCSelTss == SelTss
1911	\|\| (!pVM->selm.s.GCSelTss && !(SelTss & X86_SEL_LDT)),
1912	("%#x %#x\n", pVM->selm.s.GCSelTss, SelTss),
1913	false);
1914	AssertMsgReturn( pVM->selm.s.GCPtrGuestTss == GCPtrTss
1915	\|\| (pVM->selm.s.GCPtrGuestTss == RTRCPTR_MAX && !GCPtrTss),
1916	("%#RGv %#RGv\n", pVM->selm.s.GCPtrGuestTss, GCPtrTss),
1917	false);
1918
1919
1920	/*
1921	* Figure out the size of what need to monitor.
1922	*/
1923	/* We're not interested in any 16-bit TSSes. */
1924	uint32_t cbMonitoredTss = cbTss;
1925	if ( trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL
1926	&& trHid.Attr.n.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
1927	cbMonitoredTss = 0;
1928	if (cbMonitoredTss)
1929	{
1930	VBOXTSS Tss;
1931	uint32_t cr4 = CPUMGetGuestCR4(pVCpu);
1932	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss, GCPtrTss, RT_OFFSETOF(VBOXTSS, IntRedirBitmap));
1933	AssertReturn( rc == VINF_SUCCESS
1934	/* Happens early in XP boot during page table switching. */
1935	\|\| ( (rc == VERR_PAGE_TABLE_NOT_PRESENT \|\| rc == VERR_PAGE_NOT_PRESENT)
1936	&& !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF)),
1937	false);
1938	if ( !(cr4 & X86_CR4_VME)
1939	\|\| ( RT_SUCCESS(rc)
1940	&& Tss.offIoBitmap < sizeof(VBOXTSS) /* too small */
1941	&& Tss.offIoBitmap > cbTss)
1942	)
1943	cbMonitoredTss = RT_UOFFSETOF(VBOXTSS, padding_ss0);
1944	else if (RT_SUCCESS(rc))
1945	{
1946	cbMonitoredTss = Tss.offIoBitmap;
1947	AssertMsgReturn(pVM->selm.s.offGuestIoBitmap == Tss.offIoBitmap,
1948	("%#x %#x\n", pVM->selm.s.offGuestIoBitmap, Tss.offIoBitmap),
1949	false);
1950
1951	/* check the bitmap */
1952	uint32_t offRedirBitmap = Tss.offIoBitmap - sizeof(Tss.IntRedirBitmap);
1953	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Tss.IntRedirBitmap,
1954	GCPtrTss + offRedirBitmap, sizeof(Tss.IntRedirBitmap));
1955	AssertRCReturn(rc, false);
1956	AssertMsgReturn(!memcmp(&Tss.IntRedirBitmap[0], &pVM->selm.s.Tss.IntRedirBitmap[0], sizeof(Tss.IntRedirBitmap)),
1957	("offIoBitmap=%#x cbTss=%#x\n"
1958	" Guest: %.32Rhxs\n"
1959	"Shadow: %.32Rhxs\n",
1960	Tss.offIoBitmap, cbTss,
1961	&Tss.IntRedirBitmap[0],
1962	&pVM->selm.s.Tss.IntRedirBitmap[0]),
1963	false);
1964	}
1965	else
1966	cbMonitoredTss = RT_OFFSETOF(VBOXTSS, IntRedirBitmap);
1967
1968	/*
1969	* Check SS0 and ESP0.
1970	*/
1971	if ( !pVM->selm.s.fSyncTSSRing0Stack
1972	&& RT_SUCCESS(rc))
1973	{
1974	if ( Tss.esp0 != pVM->selm.s.Tss.esp1
1975	\|\| Tss.ss0 != (pVM->selm.s.Tss.ss1 & ~1))
1976	{
1977	RTGCPHYS GCPhys;
1978	rc = PGMGstGetPage(pVCpu, GCPtrTss, NULL, &GCPhys); AssertRC(rc);
1979	AssertMsgFailed(("TSS out of sync!! (%04X:%08X vs %04X:%08X (guest)) Tss=%RGv Phys=%RGp\n",
1980	(pVM->selm.s.Tss.ss1 & ~1), pVM->selm.s.Tss.esp1,
1981	Tss.ss1, Tss.esp1, GCPtrTss, GCPhys));
1982	return false;
1983	}
1984	}
1985	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1986	}
1987	else
1988	{
1989	AssertMsgReturn(pVM->selm.s.Tss.ss1 == 0 && pVM->selm.s.Tss.esp1 == 0, ("%04x:%08x\n", pVM->selm.s.Tss.ss1, pVM->selm.s.Tss.esp1), false);
1990	AssertReturn(!pVM->selm.s.fSyncTSSRing0Stack, false);
1991	AssertMsgReturn(pVM->selm.s.cbMonitoredGuestTss == cbMonitoredTss, ("%#x %#x\n", pVM->selm.s.cbMonitoredGuestTss, cbMonitoredTss), false);
1992	}
1993
1994
1995
1996	return true;
1997
1998	# else /* !VBOX_STRICT */
1999	NOREF(pVM);
2000	return true;
2001	# endif /* !VBOX_STRICT */
2002	}
2003
2004
2005	# ifdef VBOX_WITH_SAFE_STR
2006	/**
2007	* Validates the RawR0 TR shadow GDT entry.
2008	*
2009	* @returns true if it matches.
2010	* @returns false and assertions on mismatch..
2011	* @param pVM The cross context VM structure.
2012	*/
2013	VMMR3DECL(bool) SELMR3CheckShadowTR(PVM pVM)
2014	{
2015	# ifdef VBOX_STRICT
2016	PX86DESC paGdt = pVM->selm.s.paGdtR3;
2017
2018	/*
2019	* TSS descriptor
2020	*/
2021	PX86DESC pDesc = &paGdt[pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> 3];
2022	RTRCPTR RCPtrTSS = VM_RC_ADDR(pVM, &pVM->selm.s.Tss);
2023
2024	if ( pDesc->Gen.u16BaseLow != RT_LOWORD(RCPtrTSS)
2025	\|\| pDesc->Gen.u8BaseHigh1 != RT_BYTE3(RCPtrTSS)
2026	\|\| pDesc->Gen.u8BaseHigh2 != RT_BYTE4(RCPtrTSS)
2027	\|\| pDesc->Gen.u16LimitLow != sizeof(VBOXTSS) - 1
2028	\|\| pDesc->Gen.u4LimitHigh != 0
2029	\|\| (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_AVAIL && pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_386_TSS_BUSY)
2030	\|\| pDesc->Gen.u1DescType != 0 /* system */
2031	\|\| pDesc->Gen.u2Dpl != 0 /* supervisor */
2032	\|\| pDesc->Gen.u1Present != 1
2033	\|\| pDesc->Gen.u1Available != 0
2034	\|\| pDesc->Gen.u1Long != 0
2035	\|\| pDesc->Gen.u1DefBig != 0
2036	\|\| pDesc->Gen.u1Granularity != 0 /* byte limit */
2037	)
2038	{
2039	AssertFailed();
2040	return false;
2041	}
2042	# endif
2043	return true;
2044	}
2045	# endif /* VBOX_WITH_SAFE_STR */
2046
2047	#endif /* VBOX_WITH_RAW_MODE */
2048
2049	/**
2050	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2051	*
2052	* See SELMR3GetSelectorInfo for details.
2053	*
2054	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2055	*
2056	* @param pVCpu The cross context virtual CPU structure.
2057	* @param Sel The selector to get info about.
2058	* @param pSelInfo Where to store the information.
2059	*/
2060	static int selmR3GetSelectorInfo64(PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2061	{
2062	/*
2063	* Read it from the guest descriptor table.
2064	*/
2065	/** @todo this is bogus wrt the LDT/GDT limit on long selectors. */
2066	X86DESC64 Desc;
2067	RTGCPTR GCPtrDesc;
2068	if (!(Sel & X86_SEL_LDT))
2069	{
2070	/* GDT */
2071	VBOXGDTR Gdtr;
2072	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2073	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2074	return VERR_INVALID_SELECTOR;
2075	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2076	}
2077	else
2078	{
2079	/* LDT */
2080	uint64_t GCPtrBase;
2081	uint32_t cbLimit;
2082	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2083	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2084	return VERR_INVALID_SELECTOR;
2085
2086	/* calc the descriptor location. */
2087	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2088	}
2089
2090	/* read the descriptor. */
2091	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2092	if (RT_FAILURE(rc))
2093	{
2094	rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(X86DESC));
2095	if (RT_FAILURE(rc))
2096	return rc;
2097	Desc.au64[1] = 0;
2098	}
2099
2100	/*
2101	* Extract the base and limit
2102	* (We ignore the present bit here, which is probably a bit silly...)
2103	*/
2104	pSelInfo->Sel = Sel;
2105	pSelInfo->fFlags = DBGFSELINFO_FLAGS_LONG_MODE;
2106	pSelInfo->u.Raw64 = Desc;
2107	if (Desc.Gen.u1DescType)
2108	{
2109	/*
2110	* 64-bit code selectors are wide open, it's not possible to detect
2111	* 64-bit data or stack selectors without also dragging in assumptions
2112	* about current CS (i.e. that's we're executing in 64-bit mode). So,
2113	* the selinfo user needs to deal with this in the context the info is
2114	* used unfortunately.
2115	*/
2116	if ( Desc.Gen.u1Long
2117	&& !Desc.Gen.u1DefBig
2118	&& (Desc.Gen.u4Type & X86_SEL_TYPE_CODE))
2119	{
2120	/* Note! We ignore the segment limit hacks that was added by AMD. */
2121	pSelInfo->GCPtrBase = 0;
2122	pSelInfo->cbLimit = ~(RTGCUINTPTR)0;
2123	}
2124	else
2125	{
2126	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2127	pSelInfo->GCPtrBase = X86DESC_BASE(&Desc);
2128	}
2129	pSelInfo->SelGate = 0;
2130	}
2131	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_LDT
2132	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_AVAIL
2133	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TSS_BUSY)
2134	{
2135	/* Note. LDT descriptors are weird in long mode, we ignore the footnote
2136	in the AMD manual here as a simplification. */
2137	pSelInfo->GCPtrBase = X86DESC64_BASE(&Desc);
2138	pSelInfo->cbLimit = X86DESC_LIMIT_G(&Desc);
2139	pSelInfo->SelGate = 0;
2140	}
2141	else if ( Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_CALL_GATE
2142	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_TRAP_GATE
2143	\|\| Desc.Gen.u4Type == AMD64_SEL_TYPE_SYS_INT_GATE)
2144	{
2145	pSelInfo->cbLimit = X86DESC64_BASE(&Desc);
2146	pSelInfo->GCPtrBase = Desc.Gate.u16OffsetLow
2147	\| ((uint32_t)Desc.Gate.u16OffsetHigh << 16)
2148	\| ((uint64_t)Desc.Gate.u32OffsetTop << 32);
2149	pSelInfo->SelGate = Desc.Gate.u16Sel;
2150	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2151	}
2152	else
2153	{
2154	pSelInfo->cbLimit = 0;
2155	pSelInfo->GCPtrBase = 0;
2156	pSelInfo->SelGate = 0;
2157	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2158	}
2159	if (!Desc.Gen.u1Present)
2160	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2161
2162	return VINF_SUCCESS;
2163	}
2164
2165
2166	/**
2167	* Worker for selmR3GetSelectorInfo32 and SELMR3GetShadowSelectorInfo that
2168	* interprets a legacy descriptor table entry and fills in the selector info
2169	* structure from it.
2170	*
2171	* @param pSelInfo Where to store the selector info. Only the fFlags and
2172	* Sel members have been initialized.
2173	* @param pDesc The legacy descriptor to parse.
2174	*/
2175	DECLINLINE(void) selmR3SelInfoFromDesc32(PDBGFSELINFO pSelInfo, PCX86DESC pDesc)
2176	{
2177	pSelInfo->u.Raw64.au64[1] = 0;
2178	pSelInfo->u.Raw = *pDesc;
2179	if ( pDesc->Gen.u1DescType
2180	\|\| !(pDesc->Gen.u4Type & 4))
2181	{
2182	pSelInfo->cbLimit = X86DESC_LIMIT_G(pDesc);
2183	pSelInfo->GCPtrBase = X86DESC_BASE(pDesc);
2184	pSelInfo->SelGate = 0;
2185	}
2186	else if (pDesc->Gen.u4Type != X86_SEL_TYPE_SYS_UNDEFINED4)
2187	{
2188	pSelInfo->cbLimit = 0;
2189	if (pDesc->Gen.u4Type == X86_SEL_TYPE_SYS_TASK_GATE)
2190	pSelInfo->GCPtrBase = 0;
2191	else
2192	pSelInfo->GCPtrBase = pDesc->Gate.u16OffsetLow
2193	\| (uint32_t)pDesc->Gate.u16OffsetHigh << 16;
2194	pSelInfo->SelGate = pDesc->Gate.u16Sel;
2195	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_GATE;
2196	}
2197	else
2198	{
2199	pSelInfo->cbLimit = 0;
2200	pSelInfo->GCPtrBase = 0;
2201	pSelInfo->SelGate = 0;
2202	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_INVALID;
2203	}
2204	if (!pDesc->Gen.u1Present)
2205	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_NOT_PRESENT;
2206	}
2207
2208
2209	/**
2210	* Gets information about a 64-bit selector, SELMR3GetSelectorInfo helper.
2211	*
2212	* See SELMR3GetSelectorInfo for details.
2213	*
2214	* @returns VBox status code, see SELMR3GetSelectorInfo for details.
2215	*
2216	* @param pVM The cross context VM structure.
2217	* @param pVCpu The cross context virtual CPU structure.
2218	* @param Sel The selector to get info about.
2219	* @param pSelInfo Where to store the information.
2220	*/
2221	static int selmR3GetSelectorInfo32(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2222	{
2223	/*
2224	* Read the descriptor entry
2225	*/
2226	pSelInfo->fFlags = 0;
2227	X86DESC Desc;
2228	if ( !(Sel & X86_SEL_LDT)
2229	&& ( pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_RPL_LDT)
2230	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_RPL_LDT)
2231	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_RPL_LDT)
2232	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_RPL_LDT)
2233	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_RPL_LDT))
2234	)
2235	{
2236	/*
2237	* Hypervisor descriptor.
2238	*/
2239	pSelInfo->fFlags = DBGFSELINFO_FLAGS_HYPER;
2240	if (CPUMIsGuestInProtectedMode(pVCpu))
2241	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2242	else
2243	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2244
2245	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2246	}
2247	else if (CPUMIsGuestInProtectedMode(pVCpu))
2248	{
2249	/*
2250	* Read it from the guest descriptor table.
2251	*/
2252	pSelInfo->fFlags = DBGFSELINFO_FLAGS_PROT_MODE;
2253
2254	RTGCPTR GCPtrDesc;
2255	if (!(Sel & X86_SEL_LDT))
2256	{
2257	/* GDT */
2258	VBOXGDTR Gdtr;
2259	CPUMGetGuestGDTR(pVCpu, &Gdtr);
2260	if ((Sel \| X86_SEL_RPL_LDT) > Gdtr.cbGdt)
2261	return VERR_INVALID_SELECTOR;
2262	GCPtrDesc = Gdtr.pGdt + (Sel & X86_SEL_MASK);
2263	}
2264	else
2265	{
2266	/* LDT */
2267	uint64_t GCPtrBase;
2268	uint32_t cbLimit;
2269	CPUMGetGuestLdtrEx(pVCpu, &GCPtrBase, &cbLimit);
2270	if ((Sel \| X86_SEL_RPL_LDT) > cbLimit)
2271	return VERR_INVALID_SELECTOR;
2272
2273	/* calc the descriptor location. */
2274	GCPtrDesc = GCPtrBase + (Sel & X86_SEL_MASK);
2275	}
2276
2277	/* read the descriptor. */
2278	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &Desc, GCPtrDesc, sizeof(Desc));
2279	if (RT_FAILURE(rc))
2280	return rc;
2281	}
2282	else
2283	{
2284	/*
2285	* We're in real mode.
2286	*/
2287	pSelInfo->Sel = Sel;
2288	pSelInfo->GCPtrBase = Sel << 4;
2289	pSelInfo->cbLimit = 0xffff;
2290	pSelInfo->fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
2291	pSelInfo->u.Raw64.au64[0] = 0;
2292	pSelInfo->u.Raw64.au64[1] = 0;
2293	pSelInfo->SelGate = 0;
2294	return VINF_SUCCESS;
2295	}
2296
2297	/*
2298	* Extract the base and limit or sel:offset for gates.
2299	*/
2300	pSelInfo->Sel = Sel;
2301	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2302
2303	return VINF_SUCCESS;
2304	}
2305
2306
2307	/**
2308	* Gets information about a selector.
2309	*
2310	* Intended for the debugger mostly and will prefer the guest descriptor tables
2311	* over the shadow ones.
2312	*
2313	* @retval VINF_SUCCESS on success.
2314	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2315	* descriptor table.
2316	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2317	* is not returned if the selector itself isn't present, you have to
2318	* check that for yourself (see DBGFSELINFO::fFlags).
2319	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2320	* pagetable or page backing the selector table wasn't present.
2321	* @returns Other VBox status code on other errors.
2322	*
2323	* @param pVM The cross context VM structure.
2324	* @param pVCpu The cross context virtual CPU structure.
2325	* @param Sel The selector to get info about.
2326	* @param pSelInfo Where to store the information.
2327	*/
2328	VMMR3DECL(int) SELMR3GetSelectorInfo(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PDBGFSELINFO pSelInfo)
2329	{
2330	AssertPtr(pSelInfo);
2331	if (CPUMIsGuestInLongMode(pVCpu))
2332	return selmR3GetSelectorInfo64(pVCpu, Sel, pSelInfo);
2333	return selmR3GetSelectorInfo32(pVM, pVCpu, Sel, pSelInfo);
2334	}
2335
2336
2337	/**
2338	* Gets information about a selector from the shadow tables.
2339	*
2340	* This is intended to be faster than the SELMR3GetSelectorInfo() method, but
2341	* requires that the caller ensures that the shadow tables are up to date.
2342	*
2343	* @retval VINF_SUCCESS on success.
2344	* @retval VERR_INVALID_SELECTOR if the selector isn't fully inside the
2345	* descriptor table.
2346	* @retval VERR_SELECTOR_NOT_PRESENT if the LDT is invalid or not present. This
2347	* is not returned if the selector itself isn't present, you have to
2348	* check that for yourself (see DBGFSELINFO::fFlags).
2349	* @retval VERR_PAGE_TABLE_NOT_PRESENT or VERR_PAGE_NOT_PRESENT if the
2350	* pagetable or page backing the selector table wasn't present.
2351	* @returns Other VBox status code on other errors.
2352	*
2353	* @param pVM The cross context VM structure.
2354	* @param Sel The selector to get info about.
2355	* @param pSelInfo Where to store the information.
2356	*
2357	* @remarks Don't use this when in hardware assisted virtualization mode.
2358	*/
2359	VMMR3DECL(int) SELMR3GetShadowSelectorInfo(PVM pVM, RTSEL Sel, PDBGFSELINFO pSelInfo)
2360	{
2361	Assert(pSelInfo);
2362
2363	/*
2364	* Read the descriptor entry
2365	*/
2366	X86DESC Desc;
2367	if (!(Sel & X86_SEL_LDT))
2368	{
2369	/*
2370	* Global descriptor.
2371	*/
2372	Desc = pVM->selm.s.paGdtR3[Sel >> X86_SEL_SHIFT];
2373	pSelInfo->fFlags = pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] == (Sel & X86_SEL_MASK_OFF_RPL)
2374	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] == (Sel & X86_SEL_MASK_OFF_RPL)
2375	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] == (Sel & X86_SEL_MASK_OFF_RPL)
2376	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] == (Sel & X86_SEL_MASK_OFF_RPL)
2377	\|\| pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] == (Sel & X86_SEL_MASK_OFF_RPL)
2378	? DBGFSELINFO_FLAGS_HYPER
2379	: 0;
2380	/** @todo check that the GDT offset is valid. */
2381	}
2382	else
2383	{
2384	/*
2385	* Local Descriptor.
2386	*/
2387	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2388	Desc = paLDT[Sel >> X86_SEL_SHIFT];
2389	/** @todo check if the LDT page is actually available. */
2390	/** @todo check that the LDT offset is valid. */
2391	pSelInfo->fFlags = 0;
2392	}
2393	if (CPUMIsGuestInProtectedMode(VMMGetCpu0(pVM)))
2394	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_PROT_MODE;
2395	else
2396	pSelInfo->fFlags \|= DBGFSELINFO_FLAGS_REAL_MODE;
2397
2398	/*
2399	* Extract the base and limit or sel:offset for gates.
2400	*/
2401	pSelInfo->Sel = Sel;
2402	selmR3SelInfoFromDesc32(pSelInfo, &Desc);
2403
2404	return VINF_SUCCESS;
2405	}
2406
2407
2408	/**
2409	* Formats a descriptor.
2410	*
2411	* @param Desc Descriptor to format.
2412	* @param Sel Selector number.
2413	* @param pszOutput Output buffer.
2414	* @param cchOutput Size of output buffer.
2415	*/
2416	static void selmR3FormatDescriptor(X86DESC Desc, RTSEL Sel, char *pszOutput, size_t cchOutput)
2417	{
2418	/*
2419	* Make variable description string.
2420	*/
2421	static struct
2422	{
2423	unsigned cch;
2424	const char *psz;
2425	} const aTypes[32] =
2426	{
2427	#define STRENTRY(str) { sizeof(str) - 1, str }
2428	/* system */
2429	STRENTRY("Reserved0 "), /* 0x00 */
2430	STRENTRY("TSS16Avail "), /* 0x01 */
2431	STRENTRY("LDT "), /* 0x02 */
2432	STRENTRY("TSS16Busy "), /* 0x03 */
2433	STRENTRY("Call16 "), /* 0x04 */
2434	STRENTRY("Task "), /* 0x05 */
2435	STRENTRY("Int16 "), /* 0x06 */
2436	STRENTRY("Trap16 "), /* 0x07 */
2437	STRENTRY("Reserved8 "), /* 0x08 */
2438	STRENTRY("TSS32Avail "), /* 0x09 */
2439	STRENTRY("ReservedA "), /* 0x0a */
2440	STRENTRY("TSS32Busy "), /* 0x0b */
2441	STRENTRY("Call32 "), /* 0x0c */
2442	STRENTRY("ReservedD "), /* 0x0d */
2443	STRENTRY("Int32 "), /* 0x0e */
2444	STRENTRY("Trap32 "), /* 0x0f */
2445	/* non system */
2446	STRENTRY("DataRO "), /* 0x10 */
2447	STRENTRY("DataRO Accessed "), /* 0x11 */
2448	STRENTRY("DataRW "), /* 0x12 */
2449	STRENTRY("DataRW Accessed "), /* 0x13 */
2450	STRENTRY("DataDownRO "), /* 0x14 */
2451	STRENTRY("DataDownRO Accessed "), /* 0x15 */
2452	STRENTRY("DataDownRW "), /* 0x16 */
2453	STRENTRY("DataDownRW Accessed "), /* 0x17 */
2454	STRENTRY("CodeEO "), /* 0x18 */
2455	STRENTRY("CodeEO Accessed "), /* 0x19 */
2456	STRENTRY("CodeER "), /* 0x1a */
2457	STRENTRY("CodeER Accessed "), /* 0x1b */
2458	STRENTRY("CodeConfEO "), /* 0x1c */
2459	STRENTRY("CodeConfEO Accessed "), /* 0x1d */
2460	STRENTRY("CodeConfER "), /* 0x1e */
2461	STRENTRY("CodeConfER Accessed ") /* 0x1f */
2462	#undef SYSENTRY
2463	};
2464	#define ADD_STR(psz, pszAdd) do { strcpy(psz, pszAdd); psz += strlen(pszAdd); } while (0)
2465	char szMsg[128];
2466	char *psz = &szMsg[0];
2467	unsigned i = Desc.Gen.u1DescType << 4 \| Desc.Gen.u4Type;
2468	memcpy(psz, aTypes[i].psz, aTypes[i].cch);
2469	psz += aTypes[i].cch;
2470
2471	if (Desc.Gen.u1Present)
2472	ADD_STR(psz, "Present ");
2473	else
2474	ADD_STR(psz, "Not-Present ");
2475	if (Desc.Gen.u1Granularity)
2476	ADD_STR(psz, "Page ");
2477	if (Desc.Gen.u1DefBig)
2478	ADD_STR(psz, "32-bit ");
2479	else
2480	ADD_STR(psz, "16-bit ");
2481	#undef ADD_STR
2482	*psz = '\0';
2483
2484	/*
2485	* Limit and Base and format the output.
2486	*/
2487	uint32_t u32Limit = X86DESC_LIMIT_G(&Desc);
2488	uint32_t u32Base = X86DESC_BASE(&Desc);
2489
2490	RTStrPrintf(pszOutput, cchOutput, "%04x - %08x %08x - base=%08x limit=%08x dpl=%d %s",
2491	Sel, Desc.au32[0], Desc.au32[1], u32Base, u32Limit, Desc.Gen.u2Dpl, szMsg);
2492	}
2493
2494
2495	/**
2496	* Dumps a descriptor.
2497	*
2498	* @param Desc Descriptor to dump.
2499	* @param Sel Selector number.
2500	* @param pszMsg Message to prepend the log entry with.
2501	*/
2502	VMMR3DECL(void) SELMR3DumpDescriptor(X86DESC Desc, RTSEL Sel, const char *pszMsg)
2503	{
2504	char szOutput[128];
2505	selmR3FormatDescriptor(Desc, Sel, &szOutput[0], sizeof(szOutput));
2506	Log(("%s: %s\n", pszMsg, szOutput));
2507	NOREF(szOutput[0]);
2508	}
2509
2510
2511	/**
2512	* Display the shadow gdt.
2513	*
2514	* @param pVM The cross context VM structure.
2515	* @param pHlp The info helpers.
2516	* @param pszArgs Arguments, ignored.
2517	*/
2518	static DECLCALLBACK(void) selmR3InfoGdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2519	{
2520	NOREF(pszArgs);
2521	pHlp->pfnPrintf(pHlp, "Shadow GDT (GCAddr=%RRv):\n", MMHyperR3ToRC(pVM, pVM->selm.s.paGdtR3));
2522	for (unsigned iGDT = 0; iGDT < SELM_GDT_ELEMENTS; iGDT++)
2523	{
2524	if (pVM->selm.s.paGdtR3[iGDT].Gen.u1Present)
2525	{
2526	char szOutput[128];
2527	selmR3FormatDescriptor(pVM->selm.s.paGdtR3[iGDT], iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2528	const char *psz = "";
2529	if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS] >> X86_SEL_SHIFT))
2530	psz = " HyperCS";
2531	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_DS] >> X86_SEL_SHIFT))
2532	psz = " HyperDS";
2533	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_CS64] >> X86_SEL_SHIFT))
2534	psz = " HyperCS64";
2535	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS] >> X86_SEL_SHIFT))
2536	psz = " HyperTSS";
2537	else if (iGDT == ((unsigned)pVM->selm.s.aHyperSel[SELM_HYPER_SEL_TSS_TRAP08] >> X86_SEL_SHIFT))
2538	psz = " HyperTSSTrap08";
2539	pHlp->pfnPrintf(pHlp, "%s%s\n", szOutput, psz);
2540	}
2541	}
2542	}
2543
2544
2545	/**
2546	* Display the guest gdt.
2547	*
2548	* @param pVM The cross context VM structure.
2549	* @param pHlp The info helpers.
2550	* @param pszArgs Arguments, ignored.
2551	*/
2552	static DECLCALLBACK(void) selmR3InfoGdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2553	{
2554	/** @todo SMP support! */
2555	PVMCPU pVCpu = &pVM->aCpus[0];
2556
2557	VBOXGDTR GDTR;
2558	CPUMGetGuestGDTR(pVCpu, &GDTR);
2559	RTGCPTR GCPtrGDT = GDTR.pGdt;
2560	unsigned cGDTs = ((unsigned)GDTR.cbGdt + 1) / sizeof(X86DESC);
2561
2562	pHlp->pfnPrintf(pHlp, "Guest GDT (GCAddr=%RGv limit=%x):\n", GCPtrGDT, GDTR.cbGdt);
2563	for (unsigned iGDT = 0; iGDT < cGDTs; iGDT++, GCPtrGDT += sizeof(X86DESC))
2564	{
2565	X86DESC GDTE;
2566	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &GDTE, GCPtrGDT, sizeof(GDTE));
2567	if (RT_SUCCESS(rc))
2568	{
2569	if (GDTE.Gen.u1Present)
2570	{
2571	char szOutput[128];
2572	selmR3FormatDescriptor(GDTE, iGDT << X86_SEL_SHIFT, &szOutput[0], sizeof(szOutput));
2573	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2574	}
2575	}
2576	else if (rc == VERR_PAGE_NOT_PRESENT)
2577	{
2578	if ((GCPtrGDT & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2579	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", iGDT << X86_SEL_SHIFT, GCPtrGDT);
2580	}
2581	else
2582	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", iGDT << X86_SEL_SHIFT, rc, GCPtrGDT);
2583	}
2584	NOREF(pszArgs);
2585	}
2586
2587
2588	/**
2589	* Display the shadow ldt.
2590	*
2591	* @param pVM The cross context VM structure.
2592	* @param pHlp The info helpers.
2593	* @param pszArgs Arguments, ignored.
2594	*/
2595	static DECLCALLBACK(void) selmR3InfoLdt(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2596	{
2597	unsigned cLDTs = ((unsigned)pVM->selm.s.cbLdtLimit + 1) >> X86_SEL_SHIFT;
2598	PX86DESC paLDT = (PX86DESC)((char *)pVM->selm.s.pvLdtR3 + pVM->selm.s.offLdtHyper);
2599	pHlp->pfnPrintf(pHlp, "Shadow LDT (GCAddr=%RRv limit=%#x):\n", pVM->selm.s.pvLdtRC + pVM->selm.s.offLdtHyper, pVM->selm.s.cbLdtLimit);
2600	for (unsigned iLDT = 0; iLDT < cLDTs; iLDT++)
2601	{
2602	if (paLDT[iLDT].Gen.u1Present)
2603	{
2604	char szOutput[128];
2605	selmR3FormatDescriptor(paLDT[iLDT], (iLDT << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2606	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2607	}
2608	}
2609	NOREF(pszArgs);
2610	}
2611
2612
2613	/**
2614	* Display the guest ldt.
2615	*
2616	* @param pVM The cross context VM structure.
2617	* @param pHlp The info helpers.
2618	* @param pszArgs Arguments, ignored.
2619	*/
2620	static DECLCALLBACK(void) selmR3InfoLdtGuest(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2621	{
2622	/** @todo SMP support! */
2623	PVMCPU pVCpu = &pVM->aCpus[0];
2624
2625	uint64_t GCPtrLdt;
2626	uint32_t cbLdt;
2627	RTSEL SelLdt = CPUMGetGuestLdtrEx(pVCpu, &GCPtrLdt, &cbLdt);
2628	if (!(SelLdt & X86_SEL_MASK_OFF_RPL))
2629	{
2630	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x): Null-Selector\n", SelLdt);
2631	return;
2632	}
2633
2634	pHlp->pfnPrintf(pHlp, "Guest LDT (Sel=%x GCAddr=%RX64 limit=%x):\n", SelLdt, GCPtrLdt, cbLdt);
2635	unsigned cLdts = (cbLdt + 1) >> X86_SEL_SHIFT;
2636	for (unsigned iLdt = 0; iLdt < cLdts; iLdt++, GCPtrLdt += sizeof(X86DESC))
2637	{
2638	X86DESC LdtE;
2639	int rc = PGMPhysSimpleReadGCPtr(pVCpu, &LdtE, GCPtrLdt, sizeof(LdtE));
2640	if (RT_SUCCESS(rc))
2641	{
2642	if (LdtE.Gen.u1Present)
2643	{
2644	char szOutput[128];
2645	selmR3FormatDescriptor(LdtE, (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, &szOutput[0], sizeof(szOutput));
2646	pHlp->pfnPrintf(pHlp, "%s\n", szOutput);
2647	}
2648	}
2649	else if (rc == VERR_PAGE_NOT_PRESENT)
2650	{
2651	if ((GCPtrLdt & PAGE_OFFSET_MASK) + sizeof(X86DESC) - 1 < sizeof(X86DESC))
2652	pHlp->pfnPrintf(pHlp, "%04x - page not present (GCAddr=%RGv)\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, GCPtrLdt);
2653	}
2654	else
2655	pHlp->pfnPrintf(pHlp, "%04x - read error rc=%Rrc GCAddr=%RGv\n", (iLdt << X86_SEL_SHIFT) \| X86_SEL_LDT, rc, GCPtrLdt);
2656	}
2657	NOREF(pszArgs);
2658	}
2659
2660
2661	/**
2662	* Dumps the hypervisor GDT
2663	*
2664	* @param pVM The cross context VM structure.
2665	*/
2666	VMMR3DECL(void) SELMR3DumpHyperGDT(PVM pVM)
2667	{
2668	DBGFR3Info(pVM->pUVM, "gdt", NULL, NULL);
2669	}
2670
2671
2672	/**
2673	* Dumps the hypervisor LDT
2674	*
2675	* @param pVM The cross context VM structure.
2676	*/
2677	VMMR3DECL(void) SELMR3DumpHyperLDT(PVM pVM)
2678	{
2679	DBGFR3Info(pVM->pUVM, "ldt", NULL, NULL);
2680	}
2681
2682
2683	/**
2684	* Dumps the guest GDT
2685	*
2686	* @param pVM The cross context VM structure.
2687	*/
2688	VMMR3DECL(void) SELMR3DumpGuestGDT(PVM pVM)
2689	{
2690	DBGFR3Info(pVM->pUVM, "gdtguest", NULL, NULL);
2691	}
2692
2693
2694	/**
2695	* Dumps the guest LDT
2696	*
2697	* @param pVM The cross context VM structure.
2698	*/
2699	VMMR3DECL(void) SELMR3DumpGuestLDT(PVM pVM)
2700	{
2701	DBGFR3Info(pVM->pUVM, "ldtguest", NULL, NULL);
2702	}
2703

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source: vbox/trunk/src/VBox/VMM/VMMR3/SELM.cpp@ 61744

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