| 1 | ; $Id: CPUMRZA.asm 80020 2019-07-26 18:49:57Z vboxsync $
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| 2 | ;; @file
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| 3 | ; CPUM - Raw-mode and Ring-0 Context Assembly Routines.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2006-2019 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 |
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| 18 |
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| 19 | ;*******************************************************************************
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| 20 | ;* Header Files *
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| 21 | ;*******************************************************************************
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| 22 | %define RT_ASM_WITH_SEH64
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| 23 | %include "VBox/asmdefs.mac"
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| 24 | %include "CPUMInternal.mac"
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| 25 | %include "iprt/x86.mac"
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| 26 | %include "VBox/vmm/cpum.mac"
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| 27 | %include "VBox/err.mac"
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| 28 |
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| 29 |
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| 30 |
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| 31 | BEGINCODE
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| 32 |
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| 33 |
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| 34 | ;;
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| 35 | ; Saves the host FPU/SSE/AVX state.
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| 36 | ;
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| 37 | ; Will return with CR0.EM and CR0.TS cleared! This is the normal state in ring-0.
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| 38 | ;
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| 39 | ; @returns VINF_SUCCESS (0) or VINF_CPUM_HOST_CR0_MODIFIED. (EAX)
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| 40 | ; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
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| 41 | ;
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| 42 | align 16
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| 43 | BEGINPROC cpumRZSaveHostFPUState
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| 44 | push xBP
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| 45 | SEH64_PUSH_xBP
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| 46 | mov xBP, xSP
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| 47 | SEH64_SET_FRAME_xBP 0
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| 48 | SEH64_END_PROLOGUE
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| 49 |
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| 50 | ;
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| 51 | ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
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| 52 | ;
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| 53 | %ifdef RT_ARCH_AMD64
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| 54 | %ifdef ASM_CALL64_MSC
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| 55 | mov r11, rcx
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| 56 | %else
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| 57 | mov r11, rdi
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| 58 | %endif
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| 59 | %define pCpumCpu r11
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| 60 | %define pXState r10
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| 61 | %else
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| 62 | push ebx
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| 63 | push esi
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| 64 | mov ebx, dword [ebp + 8]
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| 65 | %define pCpumCpu ebx
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| 66 | %define pXState esi
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| 67 | %endif
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| 68 |
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| 69 | pushf ; The darwin kernel can get upset or upset things if an
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| 70 | cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
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| 71 |
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| 72 | ;
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| 73 | ; We may have to update CR0, indirectly or directly. We must report any
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| 74 | ; changes to the VT-x code.
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| 75 | ;
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| 76 | CPUMRZ_TOUCH_FPU_CLEAR_CR0_FPU_TRAPS_SET_RC xCX, xAX, pCpumCpu ; xCX is the return value (xAX scratch)
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| 77 |
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| 78 | ;
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| 79 | ; Save the host state (xsave/fxsave will cause thread FPU state to be
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| 80 | ; loaded on systems where we are allowed to use it in ring-0.
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| 81 | ;
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| 82 | CPUMR0_SAVE_HOST
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| 83 |
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| 84 | or dword [pCpumCpu + CPUMCPU.fUseFlags], (CPUM_USED_FPU_HOST | CPUM_USED_FPU_SINCE_REM) ; Latter is not necessarily true, but normally yes.
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| 85 | popf
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| 86 |
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| 87 | mov eax, ecx ; The return value from above.
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| 88 | %ifdef RT_ARCH_X86
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| 89 | pop esi
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| 90 | pop ebx
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| 91 | %endif
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| 92 | leave
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| 93 | ret
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| 94 | %undef pCpumCpu
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| 95 | %undef pXState
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| 96 | ENDPROC cpumRZSaveHostFPUState
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| 97 |
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| 98 |
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| 99 | ;;
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| 100 | ; Saves the guest FPU/SSE/AVX state.
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| 101 | ;
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| 102 | ; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
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| 103 | ; @param fLeaveFpuAccessible x86:[ebp+c] gcc:sil msc:dl Whether to restore CR0 and XCR0 on
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| 104 | ; the way out. Only really applicable to RC.
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| 105 | ;
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| 106 | ; @remarks 64-bit Windows drivers shouldn't use AVX registers without saving+loading:
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| 107 | ; https://msdn.microsoft.com/en-us/library/windows/hardware/ff545910%28v=vs.85%29.aspx?f=255&MSPPError=-2147217396
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| 108 | ; However the compiler docs have different idea:
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| 109 | ; https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
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| 110 | ; We'll go with the former for now.
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| 111 | ;
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| 112 | align 16
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| 113 | BEGINPROC cpumRZSaveGuestFpuState
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| 114 | push xBP
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| 115 | SEH64_PUSH_xBP
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| 116 | mov xBP, xSP
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| 117 | SEH64_SET_FRAME_xBP 0
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| 118 | SEH64_END_PROLOGUE
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| 119 |
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| 120 | ;
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| 121 | ; Prologue - xAX+xDX must be free for XSAVE/XRSTOR input.
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| 122 | ;
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| 123 | %ifdef RT_ARCH_AMD64
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| 124 | %ifdef ASM_CALL64_MSC
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| 125 | mov r11, rcx
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| 126 | %else
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| 127 | mov r11, rdi
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| 128 | %endif
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| 129 | %define pCpumCpu r11
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| 130 | %define pXState r10
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| 131 | %else
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| 132 | push ebx
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| 133 | push esi
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| 134 | mov ebx, dword [ebp + 8]
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| 135 | %define pCpumCpu ebx
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| 136 | %define pXState esi
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| 137 | %endif
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| 138 | pushf ; The darwin kernel can get upset or upset things if an
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| 139 | cli ; interrupt occurs while we're doing fxsave/fxrstor/cr0.
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| 140 |
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| 141 | %ifdef IN_RC
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| 142 | mov ecx, cr0 ; ecx = saved cr0
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| 143 | test ecx, X86_CR0_TS | X86_CR0_EM
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| 144 | jz .skip_cr0_write
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| 145 | mov eax, ecx
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| 146 | and eax, ~(X86_CR0_TS | X86_CR0_EM)
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| 147 | mov cr0, eax
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| 148 | .skip_cr0_write:
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| 149 | %endif
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| 150 |
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| 151 | %ifndef VBOX_WITH_KERNEL_USING_XMM
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| 152 | CPUMR0_SAVE_GUEST
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| 153 | %else
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| 154 | ;
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| 155 | ; The XMM0..XMM15 registers have been saved already. We exploit the
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| 156 | ; host state here to temporarly save the non-volatile XMM registers,
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| 157 | ; so we can load the guest ones while saving. This is safe.
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| 158 | ;
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| 159 |
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| 160 | ; Save caller's XMM registers.
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| 161 | mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
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| 162 | movdqa [pXState + X86FXSTATE.xmm6 ], xmm6
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| 163 | movdqa [pXState + X86FXSTATE.xmm7 ], xmm7
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| 164 | movdqa [pXState + X86FXSTATE.xmm8 ], xmm8
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| 165 | movdqa [pXState + X86FXSTATE.xmm9 ], xmm9
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| 166 | movdqa [pXState + X86FXSTATE.xmm10], xmm10
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| 167 | movdqa [pXState + X86FXSTATE.xmm11], xmm11
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| 168 | movdqa [pXState + X86FXSTATE.xmm12], xmm12
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| 169 | movdqa [pXState + X86FXSTATE.xmm13], xmm13
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| 170 | movdqa [pXState + X86FXSTATE.xmm14], xmm14
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| 171 | movdqa [pXState + X86FXSTATE.xmm15], xmm15
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| 172 | stmxcsr [pXState + X86FXSTATE.MXCSR]
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| 173 |
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| 174 | ; Load the guest XMM register values we already saved in HMR0VMXStartVMWrapXMM.
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| 175 | mov pXState, [pCpumCpu + CPUMCPU.Guest.pXStateR0]
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| 176 | movdqa xmm0, [pXState + X86FXSTATE.xmm0]
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| 177 | movdqa xmm1, [pXState + X86FXSTATE.xmm1]
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| 178 | movdqa xmm2, [pXState + X86FXSTATE.xmm2]
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| 179 | movdqa xmm3, [pXState + X86FXSTATE.xmm3]
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| 180 | movdqa xmm4, [pXState + X86FXSTATE.xmm4]
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| 181 | movdqa xmm5, [pXState + X86FXSTATE.xmm5]
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| 182 | movdqa xmm6, [pXState + X86FXSTATE.xmm6]
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| 183 | movdqa xmm7, [pXState + X86FXSTATE.xmm7]
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| 184 | movdqa xmm8, [pXState + X86FXSTATE.xmm8]
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| 185 | movdqa xmm9, [pXState + X86FXSTATE.xmm9]
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| 186 | movdqa xmm10, [pXState + X86FXSTATE.xmm10]
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| 187 | movdqa xmm11, [pXState + X86FXSTATE.xmm11]
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| 188 | movdqa xmm12, [pXState + X86FXSTATE.xmm12]
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| 189 | movdqa xmm13, [pXState + X86FXSTATE.xmm13]
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| 190 | movdqa xmm14, [pXState + X86FXSTATE.xmm14]
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| 191 | movdqa xmm15, [pXState + X86FXSTATE.xmm15]
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| 192 | ldmxcsr [pXState + X86FXSTATE.MXCSR]
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| 193 |
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| 194 | CPUMR0_SAVE_GUEST
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| 195 |
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| 196 | ; Restore caller's XMM registers.
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| 197 | mov pXState, [pCpumCpu + CPUMCPU.Host.pXStateR0]
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| 198 | movdqa xmm6, [pXState + X86FXSTATE.xmm6 ]
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| 199 | movdqa xmm7, [pXState + X86FXSTATE.xmm7 ]
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| 200 | movdqa xmm8, [pXState + X86FXSTATE.xmm8 ]
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| 201 | movdqa xmm9, [pXState + X86FXSTATE.xmm9 ]
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| 202 | movdqa xmm10, [pXState + X86FXSTATE.xmm10]
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| 203 | movdqa xmm11, [pXState + X86FXSTATE.xmm11]
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| 204 | movdqa xmm12, [pXState + X86FXSTATE.xmm12]
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| 205 | movdqa xmm13, [pXState + X86FXSTATE.xmm13]
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| 206 | movdqa xmm14, [pXState + X86FXSTATE.xmm14]
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| 207 | movdqa xmm15, [pXState + X86FXSTATE.xmm15]
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| 208 | ldmxcsr [pXState + X86FXSTATE.MXCSR]
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| 209 |
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| 210 | %endif
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| 211 |
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| 212 | and dword [pCpumCpu + CPUMCPU.fUseFlags], ~CPUM_USED_FPU_GUEST
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| 213 | %ifdef IN_RC
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| 214 | test byte [ebp + 0ch], 1 ; fLeaveFpuAccessible
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| 215 | jz .no_cr0_restore
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| 216 | CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET ecx
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| 217 | .no_cr0_restore:
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| 218 | %endif
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| 219 | popf
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| 220 | %ifdef RT_ARCH_X86
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| 221 | pop esi
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| 222 | pop ebx
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| 223 | %endif
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| 224 | leave
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| 225 | ret
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| 226 | %undef pCpumCpu
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| 227 | %undef pXState
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| 228 | ENDPROC cpumRZSaveGuestFpuState
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| 229 |
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| 230 |
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| 231 | ;;
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| 232 | ; Saves the guest XMM0..15 registers and MXCSR.
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| 233 | ;
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| 234 | ; The purpose is to actualize the register state for read-only use, so CR0 is
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| 235 | ; restored in raw-mode context (so, the FPU/SSE/AVX CPU features can be
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| 236 | ; inaccessible upon return).
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| 237 | ;
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| 238 | ; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
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| 239 | ;
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| 240 | align 16
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| 241 | BEGINPROC cpumRZSaveGuestSseRegisters
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| 242 | push xBP
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| 243 | SEH64_PUSH_xBP
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| 244 | mov xBP, xSP
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| 245 | SEH64_SET_FRAME_xBP 0
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| 246 | SEH64_END_PROLOGUE
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| 247 |
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| 248 | %ifndef VBOX_WITH_KERNEL_USING_XMM
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| 249 | ;
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| 250 | ; Load xCX with the guest pXStateR0.
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| 251 | ;
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| 252 | %ifdef ASM_CALL64_GCC
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| 253 | mov xCX, rdi
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| 254 | %elifdef RT_ARCH_X86
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| 255 | mov xCX, dword [ebp + 8]
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| 256 | %endif
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| 257 | %ifdef IN_RING0
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| 258 | mov xCX, [xCX + CPUMCPU.Guest.pXStateR0]
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| 259 | %elifdef IN_RC
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| 260 | mov xCX, [xCX + CPUMCPU.Guest.pXStateRC]
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| 261 | %else
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| 262 | %error "Invalid context!"
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| 263 | %endif
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| 264 |
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| 265 | %ifdef IN_RC
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| 266 | ; Temporarily grant access to the SSE state. xDX must be preserved until CR0 is restored!
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| 267 | mov edx, cr0
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| 268 | test edx, X86_CR0_TS | X86_CR0_EM
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| 269 | jz .skip_cr0_write
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| 270 | mov eax, edx
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| 271 | and eax, ~(X86_CR0_TS | X86_CR0_EM)
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| 272 | mov cr0, eax
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| 273 | .skip_cr0_write:
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| 274 | %endif
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| 275 |
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| 276 | ;
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| 277 | ; Do the job.
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| 278 | ;
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| 279 | stmxcsr [xCX + X86FXSTATE.MXCSR]
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| 280 | movdqa [xCX + X86FXSTATE.xmm0 ], xmm0
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| 281 | movdqa [xCX + X86FXSTATE.xmm1 ], xmm1
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| 282 | movdqa [xCX + X86FXSTATE.xmm2 ], xmm2
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| 283 | movdqa [xCX + X86FXSTATE.xmm3 ], xmm3
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| 284 | movdqa [xCX + X86FXSTATE.xmm4 ], xmm4
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| 285 | movdqa [xCX + X86FXSTATE.xmm5 ], xmm5
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| 286 | movdqa [xCX + X86FXSTATE.xmm6 ], xmm6
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| 287 | movdqa [xCX + X86FXSTATE.xmm7 ], xmm7
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| 288 | %if ARCH_BITS == 64
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| 289 | movdqa [xCX + X86FXSTATE.xmm8 ], xmm8
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| 290 | movdqa [xCX + X86FXSTATE.xmm9 ], xmm9
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| 291 | movdqa [xCX + X86FXSTATE.xmm10], xmm10
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| 292 | movdqa [xCX + X86FXSTATE.xmm11], xmm11
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| 293 | movdqa [xCX + X86FXSTATE.xmm12], xmm12
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| 294 | movdqa [xCX + X86FXSTATE.xmm13], xmm13
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| 295 | movdqa [xCX + X86FXSTATE.xmm14], xmm14
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| 296 | movdqa [xCX + X86FXSTATE.xmm15], xmm15
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| 297 | %endif
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| 298 |
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| 299 | %ifdef IN_RC
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| 300 | CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET edx ; Restore CR0 if we changed it above.
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| 301 | %endif
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| 302 |
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| 303 | %endif ; !VBOX_WITH_KERNEL_USING_XMM
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| 304 |
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| 305 | leave
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| 306 | ret
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| 307 | ENDPROC cpumRZSaveGuestSseRegisters
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| 308 |
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| 309 | ;;
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| 310 | ; Saves the guest YMM0..15 registers.
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| 311 | ;
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| 312 | ; The purpose is to actualize the register state for read-only use, so CR0 is
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| 313 | ; restored in raw-mode context (so, the FPU/SSE/AVX CPU features can be
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| 314 | ; inaccessible upon return).
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| 315 | ;
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| 316 | ; @param pCpumCpu x86:[ebp+8] gcc:rdi msc:rcx CPUMCPU pointer
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| 317 | ;
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| 318 | align 16
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| 319 | BEGINPROC cpumRZSaveGuestAvxRegisters
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| 320 | push xBP
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| 321 | SEH64_PUSH_xBP
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| 322 | mov xBP, xSP
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| 323 | SEH64_SET_FRAME_xBP 0
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| 324 | %ifdef IN_RC
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| 325 | push xBX
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| 326 | %endif
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| 327 | SEH64_END_PROLOGUE
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| 328 |
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| 329 | ;
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| 330 | ; Load xCX with the guest pXStateR0.
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| 331 | ;
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| 332 | %ifdef ASM_CALL64_GCC
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| 333 | mov xCX, rdi
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| 334 | %elifdef RT_ARCH_X86
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| 335 | mov xCX, dword [ebp + 8]
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| 336 | %endif
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| 337 | %ifdef IN_RING0
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| 338 | mov xCX, [xCX + CPUMCPU.Guest.pXStateR0]
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| 339 | %elifdef IN_RC
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| 340 | mov xCX, [xCX + CPUMCPU.Guest.pXStateRC]
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| 341 | %else
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| 342 | %error "Invalid context!"
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| 343 | %endif
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| 344 |
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| 345 | %ifdef IN_RC
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| 346 | ; Temporarily grant access to the SSE state. xBX must be preserved until CR0 is restored!
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| 347 | mov ebx, cr0
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| 348 | test ebx, X86_CR0_TS | X86_CR0_EM
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| 349 | jz .skip_cr0_write
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| 350 | mov eax, ebx
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| 351 | and eax, ~(X86_CR0_TS | X86_CR0_EM)
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| 352 | mov cr0, eax
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| 353 | .skip_cr0_write:
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| 354 | %endif
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| 355 |
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| 356 | ;
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| 357 | ; Use XSAVE to do the job.
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| 358 | ;
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| 359 | ; Drivers shouldn't use AVX registers without saving+loading:
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| 360 | ; https://msdn.microsoft.com/en-us/library/windows/hardware/ff545910%28v=vs.85%29.aspx?f=255&MSPPError=-2147217396
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| 361 | ; However the compiler docs have different idea:
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| 362 | ; https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
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| 363 | ; We'll go with the former for now.
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| 364 | ;
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| 365 | %ifdef VBOX_WITH_KERNEL_USING_XMM
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| 366 | mov eax, XSAVE_C_YMM
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| 367 | %else
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| 368 | mov eax, XSAVE_C_YMM | XSAVE_C_SSE ; The SSE component includes MXCSR.
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| 369 | %endif
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| 370 | xor edx, edx
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| 371 | %if ARCH_BITS == 64
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| 372 | o64 xsave [xCX]
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| 373 | %else
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| 374 | xsave [xCX]
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| 375 | %endif
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| 376 |
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| 377 | %ifdef IN_RC
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| 378 | CPUMRZ_RESTORE_CR0_IF_TS_OR_EM_SET ebx ; Restore CR0 if we changed it above.
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| 379 | pop xBX
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| 380 | %endif
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| 381 | leave
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| 382 | ret
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| 383 | ENDPROC cpumRZSaveGuestAvxRegisters
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| 384 |
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