VirtualBox

source: vbox/trunk/src/VBox/VMM/include/HMInternal.h@ 87559

Last change on this file since 87559 was 87559, checked in by vboxsync, 4 years ago

VMM/HMVMX: Tidied up HM::vmx and HM::svm a little. bugref:9217
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File size: 71.8 KB
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1/* $Id: HMInternal.h 87559 2021-02-03 11:32:52Z vboxsync $ */
2/** @file
3 * HM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_HMInternal_h
19#define VMM_INCLUDED_SRC_include_HMInternal_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <VBox/cdefs.h>
25#include <VBox/types.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/dis.h>
28#include <VBox/vmm/hm.h>
29#include <VBox/vmm/hm_vmx.h>
30#include <VBox/vmm/hm_svm.h>
31#include <VBox/vmm/pgm.h>
32#include <VBox/vmm/cpum.h>
33#include <VBox/vmm/trpm.h>
34#include <iprt/memobj.h>
35#include <iprt/cpuset.h>
36#include <iprt/mp.h>
37#include <iprt/avl.h>
38#include <iprt/string.h>
39
40#if HC_ARCH_BITS == 32
41# error "32-bit hosts are no longer supported. Go back to 6.0 or earlier!"
42#endif
43
44/** @def HM_PROFILE_EXIT_DISPATCH
45 * Enables profiling of the VM exit handler dispatching. */
46#if 0 || defined(DOXYGEN_RUNNING)
47# define HM_PROFILE_EXIT_DISPATCH
48#endif
49
50RT_C_DECLS_BEGIN
51
52
53/** @defgroup grp_hm_int Internal
54 * @ingroup grp_hm
55 * @internal
56 * @{
57 */
58
59/** @name HM_CHANGED_XXX
60 * HM CPU-context changed flags.
61 *
62 * These flags are used to keep track of which registers and state has been
63 * modified since they were imported back into the guest-CPU context.
64 *
65 * @{
66 */
67#define HM_CHANGED_HOST_CONTEXT UINT64_C(0x0000000000000001)
68#define HM_CHANGED_GUEST_RIP UINT64_C(0x0000000000000004)
69#define HM_CHANGED_GUEST_RFLAGS UINT64_C(0x0000000000000008)
70
71#define HM_CHANGED_GUEST_RAX UINT64_C(0x0000000000000010)
72#define HM_CHANGED_GUEST_RCX UINT64_C(0x0000000000000020)
73#define HM_CHANGED_GUEST_RDX UINT64_C(0x0000000000000040)
74#define HM_CHANGED_GUEST_RBX UINT64_C(0x0000000000000080)
75#define HM_CHANGED_GUEST_RSP UINT64_C(0x0000000000000100)
76#define HM_CHANGED_GUEST_RBP UINT64_C(0x0000000000000200)
77#define HM_CHANGED_GUEST_RSI UINT64_C(0x0000000000000400)
78#define HM_CHANGED_GUEST_RDI UINT64_C(0x0000000000000800)
79#define HM_CHANGED_GUEST_R8_R15 UINT64_C(0x0000000000001000)
80#define HM_CHANGED_GUEST_GPRS_MASK UINT64_C(0x0000000000001ff0)
81
82#define HM_CHANGED_GUEST_ES UINT64_C(0x0000000000002000)
83#define HM_CHANGED_GUEST_CS UINT64_C(0x0000000000004000)
84#define HM_CHANGED_GUEST_SS UINT64_C(0x0000000000008000)
85#define HM_CHANGED_GUEST_DS UINT64_C(0x0000000000010000)
86#define HM_CHANGED_GUEST_FS UINT64_C(0x0000000000020000)
87#define HM_CHANGED_GUEST_GS UINT64_C(0x0000000000040000)
88#define HM_CHANGED_GUEST_SREG_MASK UINT64_C(0x000000000007e000)
89
90#define HM_CHANGED_GUEST_GDTR UINT64_C(0x0000000000080000)
91#define HM_CHANGED_GUEST_IDTR UINT64_C(0x0000000000100000)
92#define HM_CHANGED_GUEST_LDTR UINT64_C(0x0000000000200000)
93#define HM_CHANGED_GUEST_TR UINT64_C(0x0000000000400000)
94#define HM_CHANGED_GUEST_TABLE_MASK UINT64_C(0x0000000000780000)
95
96#define HM_CHANGED_GUEST_CR0 UINT64_C(0x0000000000800000)
97#define HM_CHANGED_GUEST_CR2 UINT64_C(0x0000000001000000)
98#define HM_CHANGED_GUEST_CR3 UINT64_C(0x0000000002000000)
99#define HM_CHANGED_GUEST_CR4 UINT64_C(0x0000000004000000)
100#define HM_CHANGED_GUEST_CR_MASK UINT64_C(0x0000000007800000)
101
102#define HM_CHANGED_GUEST_APIC_TPR UINT64_C(0x0000000008000000)
103#define HM_CHANGED_GUEST_EFER_MSR UINT64_C(0x0000000010000000)
104
105#define HM_CHANGED_GUEST_DR0_DR3 UINT64_C(0x0000000020000000)
106#define HM_CHANGED_GUEST_DR6 UINT64_C(0x0000000040000000)
107#define HM_CHANGED_GUEST_DR7 UINT64_C(0x0000000080000000)
108#define HM_CHANGED_GUEST_DR_MASK UINT64_C(0x00000000e0000000)
109
110#define HM_CHANGED_GUEST_X87 UINT64_C(0x0000000100000000)
111#define HM_CHANGED_GUEST_SSE_AVX UINT64_C(0x0000000200000000)
112#define HM_CHANGED_GUEST_OTHER_XSAVE UINT64_C(0x0000000400000000)
113#define HM_CHANGED_GUEST_XCRx UINT64_C(0x0000000800000000)
114
115#define HM_CHANGED_GUEST_KERNEL_GS_BASE UINT64_C(0x0000001000000000)
116#define HM_CHANGED_GUEST_SYSCALL_MSRS UINT64_C(0x0000002000000000)
117#define HM_CHANGED_GUEST_SYSENTER_CS_MSR UINT64_C(0x0000004000000000)
118#define HM_CHANGED_GUEST_SYSENTER_EIP_MSR UINT64_C(0x0000008000000000)
119#define HM_CHANGED_GUEST_SYSENTER_ESP_MSR UINT64_C(0x0000010000000000)
120#define HM_CHANGED_GUEST_SYSENTER_MSR_MASK UINT64_C(0x000001c000000000)
121#define HM_CHANGED_GUEST_TSC_AUX UINT64_C(0x0000020000000000)
122#define HM_CHANGED_GUEST_OTHER_MSRS UINT64_C(0x0000040000000000)
123#define HM_CHANGED_GUEST_ALL_MSRS ( HM_CHANGED_GUEST_EFER \
124 | HM_CHANGED_GUEST_KERNEL_GS_BASE \
125 | HM_CHANGED_GUEST_SYSCALL_MSRS \
126 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
127 | HM_CHANGED_GUEST_TSC_AUX \
128 | HM_CHANGED_GUEST_OTHER_MSRS)
129
130#define HM_CHANGED_GUEST_HWVIRT UINT64_C(0x0000080000000000)
131#define HM_CHANGED_GUEST_MASK UINT64_C(0x00000ffffffffffc)
132
133#define HM_CHANGED_KEEPER_STATE_MASK UINT64_C(0xffff000000000000)
134
135#define HM_CHANGED_VMX_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
136#define HM_CHANGED_VMX_GUEST_AUTO_MSRS UINT64_C(0x0002000000000000)
137#define HM_CHANGED_VMX_GUEST_LAZY_MSRS UINT64_C(0x0004000000000000)
138#define HM_CHANGED_VMX_ENTRY_EXIT_CTLS UINT64_C(0x0008000000000000)
139#define HM_CHANGED_VMX_MASK UINT64_C(0x000f000000000000)
140#define HM_CHANGED_VMX_HOST_GUEST_SHARED_STATE ( HM_CHANGED_GUEST_DR_MASK \
141 | HM_CHANGED_VMX_GUEST_LAZY_MSRS)
142
143#define HM_CHANGED_SVM_XCPT_INTERCEPTS UINT64_C(0x0001000000000000)
144#define HM_CHANGED_SVM_MASK UINT64_C(0x0001000000000000)
145#define HM_CHANGED_SVM_HOST_GUEST_SHARED_STATE HM_CHANGED_GUEST_DR_MASK
146
147#define HM_CHANGED_ALL_GUEST ( HM_CHANGED_GUEST_MASK \
148 | HM_CHANGED_KEEPER_STATE_MASK)
149
150/** Mask of what state might have changed when IEM raised an exception.
151 * This is a based on IEM_CPUMCTX_EXTRN_XCPT_MASK. */
152#define HM_CHANGED_RAISED_XCPT_MASK ( HM_CHANGED_GUEST_GPRS_MASK \
153 | HM_CHANGED_GUEST_RIP \
154 | HM_CHANGED_GUEST_RFLAGS \
155 | HM_CHANGED_GUEST_SS \
156 | HM_CHANGED_GUEST_CS \
157 | HM_CHANGED_GUEST_CR0 \
158 | HM_CHANGED_GUEST_CR3 \
159 | HM_CHANGED_GUEST_CR4 \
160 | HM_CHANGED_GUEST_APIC_TPR \
161 | HM_CHANGED_GUEST_EFER_MSR \
162 | HM_CHANGED_GUEST_DR7 \
163 | HM_CHANGED_GUEST_CR2 \
164 | HM_CHANGED_GUEST_SREG_MASK \
165 | HM_CHANGED_GUEST_TABLE_MASK)
166
167#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
168/** Mask of what state might have changed when \#VMEXIT is emulated. */
169# define HM_CHANGED_SVM_VMEXIT_MASK ( HM_CHANGED_GUEST_RSP \
170 | HM_CHANGED_GUEST_RAX \
171 | HM_CHANGED_GUEST_RIP \
172 | HM_CHANGED_GUEST_RFLAGS \
173 | HM_CHANGED_GUEST_CS \
174 | HM_CHANGED_GUEST_SS \
175 | HM_CHANGED_GUEST_DS \
176 | HM_CHANGED_GUEST_ES \
177 | HM_CHANGED_GUEST_GDTR \
178 | HM_CHANGED_GUEST_IDTR \
179 | HM_CHANGED_GUEST_CR_MASK \
180 | HM_CHANGED_GUEST_EFER_MSR \
181 | HM_CHANGED_GUEST_DR6 \
182 | HM_CHANGED_GUEST_DR7 \
183 | HM_CHANGED_GUEST_OTHER_MSRS \
184 | HM_CHANGED_GUEST_HWVIRT \
185 | HM_CHANGED_SVM_MASK \
186 | HM_CHANGED_GUEST_APIC_TPR)
187
188/** Mask of what state might have changed when VMRUN is emulated. */
189# define HM_CHANGED_SVM_VMRUN_MASK HM_CHANGED_SVM_VMEXIT_MASK
190#endif
191#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
192/** Mask of what state might have changed when VM-exit is emulated.
193 *
194 * This is currently unused, but keeping it here in case we can get away a bit more
195 * fine-grained state handling.
196 *
197 * @note Update IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK when this changes. */
198# define HM_CHANGED_VMX_VMEXIT_MASK ( HM_CHANGED_GUEST_CR0 | HM_CHANGED_GUEST_CR3 | HM_CHANGED_GUEST_CR4 \
199 | HM_CHANGED_GUEST_DR7 | HM_CHANGED_GUEST_DR6 \
200 | HM_CHANGED_GUEST_EFER_MSR \
201 | HM_CHANGED_GUEST_SYSENTER_MSR_MASK \
202 | HM_CHANGED_GUEST_OTHER_MSRS /* for PAT MSR */ \
203 | HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RSP | HM_CHANGED_GUEST_RFLAGS \
204 | HM_CHANGED_GUEST_SREG_MASK \
205 | HM_CHANGED_GUEST_TR \
206 | HM_CHANGED_GUEST_LDTR | HM_CHANGED_GUEST_GDTR | HM_CHANGED_GUEST_IDTR \
207 | HM_CHANGED_GUEST_HWVIRT )
208#endif
209/** @} */
210
211/** Maximum number of exit reason statistics counters. */
212#define MAX_EXITREASON_STAT 0x100
213#define MASK_EXITREASON_STAT 0xff
214#define MASK_INJECT_IRQ_STAT 0xff
215
216/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
217#define HM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
218/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
219#define HM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2 * PAGE_SIZE + 1)
220/** Total guest mapped memory needed. */
221#define HM_VTX_TOTAL_DEVHEAP_MEM (HM_EPT_IDENTITY_PG_TABLE_SIZE + HM_VTX_TSS_SIZE)
222
223
224/** @name Macros for enabling and disabling preemption.
225 * These are really just for hiding the RTTHREADPREEMPTSTATE and asserting that
226 * preemption has already been disabled when there is no context hook.
227 * @{ */
228#ifdef VBOX_STRICT
229# define HM_DISABLE_PREEMPT(a_pVCpu) \
230 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
231 Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD) || VMMR0ThreadCtxHookIsEnabled((a_pVCpu))); \
232 RTThreadPreemptDisable(&PreemptStateInternal)
233#else
234# define HM_DISABLE_PREEMPT(a_pVCpu) \
235 RTTHREADPREEMPTSTATE PreemptStateInternal = RTTHREADPREEMPTSTATE_INITIALIZER; \
236 RTThreadPreemptDisable(&PreemptStateInternal)
237#endif /* VBOX_STRICT */
238#define HM_RESTORE_PREEMPT() do { RTThreadPreemptRestore(&PreemptStateInternal); } while(0)
239/** @} */
240
241
242/** @name HM saved state versions.
243 * @{
244 */
245#define HM_SAVED_STATE_VERSION HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
246#define HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT 6
247#define HM_SAVED_STATE_VERSION_TPR_PATCHING 5
248#define HM_SAVED_STATE_VERSION_NO_TPR_PATCHING 4
249#define HM_SAVED_STATE_VERSION_2_0_X 3
250/** @} */
251
252
253/**
254 * HM physical (host) CPU information.
255 */
256typedef struct HMPHYSCPU
257{
258 /** The CPU ID. */
259 RTCPUID idCpu;
260 /** The VM_HSAVE_AREA (AMD-V) / VMXON region (Intel) memory backing. */
261 RTR0MEMOBJ hMemObj;
262 /** The physical address of the first page in hMemObj (it's a
263 * physcially contigous allocation if it spans multiple pages). */
264 RTHCPHYS HCPhysMemObj;
265 /** The address of the memory (for pfnEnable). */
266 void *pvMemObj;
267 /** Current ASID (AMD-V) / VPID (Intel). */
268 uint32_t uCurrentAsid;
269 /** TLB flush count. */
270 uint32_t cTlbFlushes;
271 /** Whether to flush each new ASID/VPID before use. */
272 bool fFlushAsidBeforeUse;
273 /** Configured for VT-x or AMD-V. */
274 bool fConfigured;
275 /** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
276 bool fIgnoreAMDVInUseError;
277 /** Whether CR4.VMXE was already enabled prior to us enabling it. */
278 bool fVmxeAlreadyEnabled;
279 /** In use by our code. (for power suspend) */
280 bool volatile fInUse;
281#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
282 /** Nested-guest union (put data common to SVM/VMX outside the union). */
283 union
284 {
285 /** Nested-guest SVM data. */
286 struct
287 {
288 /** The active nested-guest MSR permission bitmap memory backing. */
289 RTR0MEMOBJ hNstGstMsrpm;
290 /** The physical address of the first page in hNstGstMsrpm (physcially
291 * contiguous allocation). */
292 RTHCPHYS HCPhysNstGstMsrpm;
293 /** The address of the active nested-guest MSRPM. */
294 void *pvNstGstMsrpm;
295 } svm;
296 /** @todo Nested-VMX. */
297 } n;
298#endif
299} HMPHYSCPU;
300/** Pointer to HMPHYSCPU struct. */
301typedef HMPHYSCPU *PHMPHYSCPU;
302/** Pointer to a const HMPHYSCPU struct. */
303typedef const HMPHYSCPU *PCHMPHYSCPU;
304
305/**
306 * TPR-instruction type.
307 */
308typedef enum
309{
310 HMTPRINSTR_INVALID,
311 HMTPRINSTR_READ,
312 HMTPRINSTR_READ_SHR4,
313 HMTPRINSTR_WRITE_REG,
314 HMTPRINSTR_WRITE_IMM,
315 HMTPRINSTR_JUMP_REPLACEMENT,
316 /** The usual 32-bit paranoia. */
317 HMTPRINSTR_32BIT_HACK = 0x7fffffff
318} HMTPRINSTR;
319
320/**
321 * TPR patch information.
322 */
323typedef struct
324{
325 /** The key is the address of patched instruction. (32 bits GC ptr) */
326 AVLOU32NODECORE Core;
327 /** Original opcode. */
328 uint8_t aOpcode[16];
329 /** Instruction size. */
330 uint32_t cbOp;
331 /** Replacement opcode. */
332 uint8_t aNewOpcode[16];
333 /** Replacement instruction size. */
334 uint32_t cbNewOp;
335 /** Instruction type. */
336 HMTPRINSTR enmType;
337 /** Source operand. */
338 uint32_t uSrcOperand;
339 /** Destination operand. */
340 uint32_t uDstOperand;
341 /** Number of times the instruction caused a fault. */
342 uint32_t cFaults;
343 /** Patch address of the jump replacement. */
344 RTGCPTR32 pJumpTarget;
345} HMTPRPATCH;
346/** Pointer to HMTPRPATCH. */
347typedef HMTPRPATCH *PHMTPRPATCH;
348/** Pointer to a const HMTPRPATCH. */
349typedef const HMTPRPATCH *PCHMTPRPATCH;
350
351
352/**
353 * Makes a HMEXITSTAT::uKey value from a program counter and an exit code.
354 *
355 * @returns 64-bit key
356 * @param a_uPC The RIP + CS.BASE value of the exit.
357 * @param a_uExit The exit code.
358 * @todo Add CPL?
359 */
360#define HMEXITSTAT_MAKE_KEY(a_uPC, a_uExit) (((a_uPC) & UINT64_C(0x0000ffffffffffff)) | (uint64_t)(a_uExit) << 48)
361
362typedef struct HMEXITINFO
363{
364 /** See HMEXITSTAT_MAKE_KEY(). */
365 uint64_t uKey;
366 /** Number of recent hits (depreciates with time). */
367 uint32_t volatile cHits;
368 /** The age + lock. */
369 uint16_t volatile uAge;
370 /** Action or action table index. */
371 uint16_t iAction;
372} HMEXITINFO;
373AssertCompileSize(HMEXITINFO, 16); /* Lots of these guys, so don't add any unnecessary stuff! */
374
375typedef struct HMEXITHISTORY
376{
377 /** The exit timestamp. */
378 uint64_t uTscExit;
379 /** The index of the corresponding HMEXITINFO entry.
380 * UINT32_MAX if none (too many collisions, race, whatever). */
381 uint32_t iExitInfo;
382 /** Figure out later, needed for padding now. */
383 uint32_t uSomeClueOrSomething;
384} HMEXITHISTORY;
385
386/**
387 * Switcher function, HC to the special 64-bit RC.
388 *
389 * @param pVM The cross context VM structure.
390 * @param offCpumVCpu Offset from pVM->cpum to pVM->aCpus[idCpu].cpum.
391 * @returns Return code indicating the action to take.
392 */
393typedef DECLCALLBACKTYPE(int, FNHMSWITCHERHC,(PVM pVM, uint32_t offCpumVCpu));
394/** Pointer to switcher function. */
395typedef FNHMSWITCHERHC *PFNHMSWITCHERHC;
396
397
398/**
399 * HM event.
400 *
401 * VT-x and AMD-V common event injection structure.
402 */
403typedef struct HMEVENT
404{
405 /** Whether the event is pending. */
406 uint32_t fPending;
407 /** The error-code associated with the event. */
408 uint32_t u32ErrCode;
409 /** The length of the instruction in bytes (only relevant for software
410 * interrupts or software exceptions). */
411 uint32_t cbInstr;
412 /** Alignment. */
413 uint32_t u32Padding;
414 /** The encoded event (VM-entry interruption-information for VT-x or EVENTINJ
415 * for SVM). */
416 uint64_t u64IntInfo;
417 /** Guest virtual address if this is a page-fault event. */
418 RTGCUINTPTR GCPtrFaultAddress;
419} HMEVENT;
420/** Pointer to a HMEVENT struct. */
421typedef HMEVENT *PHMEVENT;
422/** Pointer to a const HMEVENT struct. */
423typedef const HMEVENT *PCHMEVENT;
424AssertCompileSizeAlignment(HMEVENT, 8);
425
426/**
427 * HM VM Instance data.
428 * Changes to this must checked against the padding of the hm union in VM!
429 */
430typedef struct HM
431{
432 /** Set if nested paging is enabled.
433 * Config value that is copied to HMR0PERVM::fNestedPaging on setup. */
434 bool fNestedPagingCfg;
435 /** Set when we've finalized the VMX / SVM initialization in ring-3
436 * (hmR3InitFinalizeR0Intel / hmR3InitFinalizeR0Amd). */
437 bool fInitialized;
438 /** Set if large pages are enabled (requires nested paging).
439 * Config only, passed on the PGM where it really belongs.
440 * @todo move to PGM */
441 bool fLargePages;
442 /** Set if we can support 64-bit guests or not.
443 * Config value that is copied to HMR0PERVM::fAllow64BitGuests on setup. */
444 bool fAllow64BitGuestsCfg;
445 /** Set when we initialize VT-x or AMD-V once for all CPUs. */
446 bool fGlobalInit;
447 /** Set when TPR patching is allowed. */
448 bool fTprPatchingAllowed;
449 /** Set when TPR patching is active. */
450 bool fTPRPatchingActive;
451 /** Set when the debug facility has breakpoints/events enabled that requires
452 * us to use the debug execution loop in ring-0. */
453 bool fUseDebugLoop;
454 /** Set if hardware APIC virtualization is enabled.
455 * @todo Not really used by HM, move to APIC where it's actually used. */
456 bool fVirtApicRegs;
457 /** Set if posted interrupt processing is enabled.
458 * @todo Not really used by HM, move to APIC where it's actually used. */
459 bool fPostedIntrs;
460
461 /** @name Processed into HMR0PERVCPU::fWorldSwitcher by ring-0 on VM init.
462 * @{ */
463 /** Set if indirect branch prediction barrier on VM exit. */
464 bool fIbpbOnVmExit;
465 /** Set if indirect branch prediction barrier on VM entry. */
466 bool fIbpbOnVmEntry;
467 /** Set if level 1 data cache should be flushed on VM entry. */
468 bool fL1dFlushOnVmEntry;
469 /** Set if level 1 data cache should be flushed on EMT scheduling. */
470 bool fL1dFlushOnSched;
471 /** Set if MDS related buffers should be cleared on VM entry. */
472 bool fMdsClearOnVmEntry;
473 /** Set if MDS related buffers should be cleared on EMT scheduling. */
474 bool fMdsClearOnSched;
475 /** Set if host manages speculation control settings.
476 * @todo doesn't do anything ... */
477 bool fSpecCtrlByHost;
478 /** @} */
479
480 /** Alignment padding. */
481 bool afPaddingMinus1[3];
482
483 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
484 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
485 uint32_t cMaxResumeLoopsCfg;
486
487 struct
488 {
489 /** Set by the ring-0 side of HM to indicate VMX is supported by the CPU. */
490 bool fSupported;
491 /** Set when we've enabled VMX. */
492 bool fEnabled;
493 /** The shift mask employed by the VMX-Preemption timer (set by ring-0). */
494 uint8_t cPreemptTimerShift;
495 bool afAlignment1[5];
496
497 /** Pause-loop exiting (PLE) gap in ticks. */
498 uint32_t cPleGapTicks;
499 /** Pause-loop exiting (PLE) window in ticks. */
500 uint32_t cPleWindowTicks;
501
502 /** Virtual address of the TSS page used for real mode emulation. */
503 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
504 /** Virtual address of the identity page table used for real mode and protected
505 * mode without paging emulation in EPT mode. */
506 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
507
508 /** @name Configuration (gets copied if problematic)
509 * @{ */
510 /** Set if Last Branch Record (LBR) is enabled. */
511 bool fLbrCfg;
512 /** Set if VT-x VPID is allowed. */
513 bool fAllowVpid;
514 /** Set if unrestricted guest execution is in use (real and protected mode
515 * without paging). */
516 bool fUnrestrictedGuestCfg;
517 /** Set if the preemption timer should be used if available. Ring-0
518 * quietly clears this if the hardware doesn't support the preemption timer. */
519 bool fUsePreemptTimerCfg;
520 /** @} */
521
522 /** @name For ring-3 consumption
523 * @{ */
524 /** Set if VPID is supported (ring-3 copy). */
525 bool fVpidForRing3;
526 /** Whether the CPU supports VMCS fields for swapping EFER (set by ring-0 VMX
527 * init, for logging). */
528 bool fSupportsVmcsEferForRing3;
529 /** Whether to use VMCS shadowing. */
530 bool fUseVmcsShadowingForRing3;
531 bool fAlignment2;
532
533 /** Host CR4 value (set by ring-0 VMX init, for logging). */
534 uint64_t u64HostCr4ForRing3;
535 /** Host SMM monitor control (set by ring-0 VMX init, for logging). */
536 uint64_t u64HostSmmMonitorCtlForRing3;
537 /** Host EFER value (set by ring-0 VMX init, for logging and guest NX). */
538 uint64_t u64HostMsrEferForRing3;
539
540 /** The first valid host LBR branch-from-IP stack range. */
541 uint32_t idLbrFromIpMsrFirstForRing3;
542 /** The last valid host LBR branch-from-IP stack range. */
543 uint32_t idLbrFromIpMsrLastForRing3;
544
545 /** The first valid host LBR branch-to-IP stack range. */
546 uint32_t idLbrToIpMsrFirstForRing3;
547 /** The last valid host LBR branch-to-IP stack range. */
548 uint32_t idLbrToIpMsrLastForRing3;
549
550 /** Host-physical address for a failing VMXON instruction (for diagnostics, ring-3). */
551 RTHCPHYS HCPhysVmxEnableError;
552 /** VMX MSR values (only for ring-3 consumption). */
553 VMXMSRS MsrsForRing3;
554
555 /** Tagged-TLB flush type (only for ring-3 consumption). */
556 VMXTLBFLUSHTYPE enmTlbFlushTypeForRing3;
557 /** Flush type to use for INVEPT (only for ring-3 consumption). */
558 VMXTLBFLUSHEPT enmTlbFlushEptForRing3;
559 /** Flush type to use for INVVPID (only for ring-3 consumption). */
560 VMXTLBFLUSHVPID enmTlbFlushVpidForRing3;
561 /** @} */
562 } vmx;
563
564 struct
565 {
566 /** Set by the ring-0 side of HM to indicate SVM is supported by the CPU. */
567 bool fSupported;
568 /** Set when we've enabled SVM. */
569 bool fEnabled;
570 /** Set when the hack to ignore VERR_SVM_IN_USE is active.
571 * @todo Safe? */
572 bool fIgnoreInUseError;
573 /** Whether to use virtualized VMSAVE/VMLOAD feature. */
574 bool fVirtVmsaveVmload;
575 /** Whether to use virtual GIF feature. */
576 bool fVGif;
577 /** Whether to use LBR virtualization feature. */
578 bool fLbrVirt;
579 bool afAlignment1[2];
580
581 /** Pause filter counter. */
582 uint16_t cPauseFilter;
583 /** Pause filter treshold in ticks. */
584 uint16_t cPauseFilterThresholdTicks;
585 uint32_t u32Alignment2;
586
587 /** @name For ring-3 consumption
588 * @{ */
589 /** SVM revision. */
590 uint32_t u32Rev;
591 /** SVM feature bits from cpuid 0x8000000a, ring-3 copy. */
592 uint32_t fFeaturesForRing3;
593 /** HWCR MSR (for diagnostics). */
594 uint64_t u64MsrHwcr;
595 /** @} */
596 } svm;
597
598 /** AVL tree with all patches (active or disabled) sorted by guest instruction address.
599 * @todo For @bugref{9217} this AVL tree must be eliminated and instead
600 * sort aPatches by address and do a safe binary search on it. */
601 AVLOU32TREE PatchTree;
602 uint32_t cPatches;
603 HMTPRPATCH aPatches[64];
604
605 /** Guest allocated memory for patching purposes. */
606 RTGCPTR pGuestPatchMem;
607 /** Current free pointer inside the patch block. */
608 RTGCPTR pFreeGuestPatchMem;
609 /** Size of the guest patch memory block. */
610 uint32_t cbGuestPatchMem;
611
612 /** Last recorded error code during HM ring-0 init. */
613 int32_t rcInit;
614 /** Maximum ASID allowed.
615 * This is mainly for the release log. */
616 uint32_t uMaxAsidForLog;
617 /** World switcher flags (HM_WSF_XXX) for the release log. */
618 uint32_t fWorldSwitcherForLog;
619
620 STAMCOUNTER StatTprPatchSuccess;
621 STAMCOUNTER StatTprPatchFailure;
622 STAMCOUNTER StatTprReplaceSuccessCr8;
623 STAMCOUNTER StatTprReplaceSuccessVmc;
624 STAMCOUNTER StatTprReplaceFailure;
625} HM;
626/** Pointer to HM VM instance data. */
627typedef HM *PHM;
628AssertCompileMemberAlignment(HM, StatTprPatchSuccess, 8);
629AssertCompileMemberAlignment(HM, vmx, 8);
630AssertCompileMemberAlignment(HM, svm, 8);
631
632
633/**
634 * Per-VM ring-0 instance data for HM.
635 */
636typedef struct HMR0PERVM
637{
638 /** Set if nested paging is enabled. */
639 bool fNestedPaging;
640 /** Set if we can support 64-bit guests or not. */
641 bool fAllow64BitGuests;
642 bool afAlignment0[2];
643
644 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
645 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
646 uint32_t cMaxResumeLoops;
647
648 /** VT-x specific data. */
649 struct HMR0VMXVM
650 {
651 /** Set if unrestricted guest execution is in use (real and protected mode
652 * without paging). */
653 bool fUnrestrictedGuest;
654 /** Set if the preemption timer is in use. */
655 bool fUsePreemptTimer;
656 /** Whether to use VMCS shadowing. */
657 bool fUseVmcsShadowing;
658 /** Set if Last Branch Record (LBR) is enabled. */
659 bool fLbr;
660 /** Set if VPID is supported (copy in HM::vmx::fVpidForRing3). */
661 bool fVpid;
662 /** Tagged-TLB flush type. */
663 VMXTLBFLUSHTYPE enmTlbFlushType;
664 /** Flush type to use for INVEPT. */
665 VMXTLBFLUSHEPT enmTlbFlushEpt;
666 /** Flush type to use for INVVPID. */
667 VMXTLBFLUSHVPID enmTlbFlushVpid;
668
669 /** The first valid host LBR branch-from-IP stack range. */
670 uint32_t idLbrFromIpMsrFirst;
671 /** The last valid host LBR branch-from-IP stack range. */
672 uint32_t idLbrFromIpMsrLast;
673
674 /** The first valid host LBR branch-to-IP stack range. */
675 uint32_t idLbrToIpMsrFirst;
676 /** The last valid host LBR branch-to-IP stack range. */
677 uint32_t idLbrToIpMsrLast;
678
679 /** The host LBR TOS (top-of-stack) MSR id. */
680 uint32_t idLbrTosMsr;
681 uint32_t u32Alignment1;
682
683 /** Virtual address of the APIC-access page. */
684 R0PTRTYPE(uint8_t *) pbApicAccess;
685 /** Pointer to the VMREAD bitmap. */
686 R0PTRTYPE(void *) pvVmreadBitmap;
687 /** Pointer to the VMWRITE bitmap. */
688 R0PTRTYPE(void *) pvVmwriteBitmap;
689
690 /** Pointer to the shadow VMCS read-only fields array. */
691 R0PTRTYPE(uint32_t *) paShadowVmcsRoFields;
692 /** Pointer to the shadow VMCS read/write fields array. */
693 R0PTRTYPE(uint32_t *) paShadowVmcsFields;
694 /** Number of elements in the shadow VMCS read-only fields array. */
695 uint32_t cShadowVmcsRoFields;
696 /** Number of elements in the shadow VMCS read-write fields array. */
697 uint32_t cShadowVmcsFields;
698
699 /** Host-physical address of the APIC-access page. */
700 RTHCPHYS HCPhysApicAccess;
701 /** Host-physical address of the VMREAD bitmap. */
702 RTHCPHYS HCPhysVmreadBitmap;
703 /** Host-physical address of the VMWRITE bitmap. */
704 RTHCPHYS HCPhysVmwriteBitmap;
705
706#ifdef VBOX_WITH_CRASHDUMP_MAGIC
707 /** Host-physical address of the crash-dump scratch area. */
708 RTHCPHYS HCPhysScratch;
709 /** Pointer to the crash-dump scratch bitmap. */
710 R0PTRTYPE(uint8_t *) pbScratch;
711#endif
712
713 /** Ring-0 memory object for per-VM VMX structures. */
714 RTR0MEMOBJ hMemObj;
715 } vmx;
716
717 /** AMD-V specific data. */
718 struct HMR0SVMVM
719 {
720 /** Set if erratum 170 affects the AMD cpu. */
721 bool fAlwaysFlushTLB;
722 bool afAlignment0[3];
723 } svm;
724} HMR0PERVM;
725/** Pointer to HM's per-VM ring-0 instance data. */
726typedef HMR0PERVM *PHMR0PERVM;
727
728
729/** @addtogroup grp_hm_int_svm SVM Internal
730 * @{ */
731/** SVM VMRun function, see SVMR0VMRun(). */
732typedef DECLCALLBACKTYPE(int, FNHMSVMVMRUN,(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhysVMCB));
733/** Pointer to a SVM VMRun function. */
734typedef R0PTRTYPE(FNHMSVMVMRUN *) PFNHMSVMVMRUN;
735
736/**
737 * SVM nested-guest VMCB cache.
738 *
739 * Contains VMCB fields from the nested-guest VMCB before they're modified by
740 * SVM R0 code for hardware-assisted SVM execution of a nested-guest.
741 *
742 * A VMCB field needs to be cached when it needs to be modified for execution using
743 * hardware-assisted SVM and any of the following are true:
744 * - If the original field needs to be inspected during execution of the
745 * nested-guest or \#VMEXIT processing.
746 * - If the field is written back to memory on \#VMEXIT by the physical CPU.
747 *
748 * A VMCB field needs to be restored only when the field is written back to
749 * memory on \#VMEXIT by the physical CPU and thus would be visible to the
750 * guest.
751 *
752 * @remarks Please update hmR3InfoSvmNstGstVmcbCache() when changes are made to
753 * this structure.
754 */
755typedef struct SVMNESTEDVMCBCACHE
756{
757 /** Cache of CRX read intercepts. */
758 uint16_t u16InterceptRdCRx;
759 /** Cache of CRX write intercepts. */
760 uint16_t u16InterceptWrCRx;
761 /** Cache of DRX read intercepts. */
762 uint16_t u16InterceptRdDRx;
763 /** Cache of DRX write intercepts. */
764 uint16_t u16InterceptWrDRx;
765
766 /** Cache of the pause-filter threshold. */
767 uint16_t u16PauseFilterThreshold;
768 /** Cache of the pause-filter count. */
769 uint16_t u16PauseFilterCount;
770
771 /** Cache of exception intercepts. */
772 uint32_t u32InterceptXcpt;
773 /** Cache of control intercepts. */
774 uint64_t u64InterceptCtrl;
775
776 /** Cache of the TSC offset. */
777 uint64_t u64TSCOffset;
778
779 /** Cache of V_INTR_MASKING bit. */
780 bool fVIntrMasking;
781 /** Cache of the nested-paging bit. */
782 bool fNestedPaging;
783 /** Cache of the LBR virtualization bit. */
784 bool fLbrVirt;
785 /** Whether the VMCB is cached by HM. */
786 bool fCacheValid;
787 /** Alignment. */
788 bool afPadding0[4];
789} SVMNESTEDVMCBCACHE;
790/** Pointer to the SVMNESTEDVMCBCACHE structure. */
791typedef SVMNESTEDVMCBCACHE *PSVMNESTEDVMCBCACHE;
792/** Pointer to a const SVMNESTEDVMCBCACHE structure. */
793typedef const SVMNESTEDVMCBCACHE *PCSVMNESTEDVMCBCACHE;
794AssertCompileSizeAlignment(SVMNESTEDVMCBCACHE, 8);
795
796/** @} */
797
798
799/** @addtogroup grp_hm_int_vmx VMX Internal
800 * @{ */
801/**
802 * VMX VMCS information, shared.
803 *
804 * This structure provides information maintained for and during the executing of a
805 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
806 *
807 * Note! The members here are ordered and aligned based on estimated frequency of
808 * usage and grouped to fit within a cache line in hot code paths. Even subtle
809 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
810 * care.
811 */
812typedef struct VMXVMCSINFOSHARED
813{
814 /** @name Real-mode emulation state.
815 * @{ */
816 /** Set if guest was executing in real mode (extra checks). */
817 bool fWasInRealMode;
818 /** Padding. */
819 bool afPadding0[7];
820 struct
821 {
822 X86DESCATTR AttrCS;
823 X86DESCATTR AttrDS;
824 X86DESCATTR AttrES;
825 X86DESCATTR AttrFS;
826 X86DESCATTR AttrGS;
827 X86DESCATTR AttrSS;
828 X86EFLAGS Eflags;
829 bool fRealOnV86Active;
830 bool afPadding1[3];
831 } RealMode;
832 /** @} */
833
834 /** @name LBR MSR data.
835 * @{ */
836 /** List of LastBranch-From-IP MSRs. */
837 uint64_t au64LbrFromIpMsr[32];
838 /** List of LastBranch-To-IP MSRs. */
839 uint64_t au64LbrToIpMsr[32];
840 /** The MSR containing the index to the most recent branch record. */
841 uint64_t u64LbrTosMsr;
842 /** @} */
843} VMXVMCSINFOSHARED;
844/** Pointer to a VMXVMCSINFOSHARED struct. */
845typedef VMXVMCSINFOSHARED *PVMXVMCSINFOSHARED;
846/** Pointer to a const VMXVMCSINFOSHARED struct. */
847typedef const VMXVMCSINFOSHARED *PCVMXVMCSINFOSHARED;
848AssertCompileSizeAlignment(VMXVMCSINFOSHARED, 8);
849
850
851/**
852 * VMX VMCS information, ring-0 only.
853 *
854 * This structure provides information maintained for and during the executing of a
855 * guest (or nested-guest) VMCS (VM control structure) using hardware-assisted VMX.
856 *
857 * Note! The members here are ordered and aligned based on estimated frequency of
858 * usage and grouped to fit within a cache line in hot code paths. Even subtle
859 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
860 * care.
861 */
862typedef struct VMXVMCSINFO
863{
864 /** Pointer to the bits we share with ring-3. */
865 R0PTRTYPE(PVMXVMCSINFOSHARED) pShared;
866
867 /** @name Auxiliary information.
868 * @{ */
869 /** Host-physical address of the EPTP. */
870 RTHCPHYS HCPhysEPTP;
871 /** The VMCS launch state, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
872 uint32_t fVmcsState;
873 /** The VMCS launch state of the shadow VMCS, see VMX_V_VMCS_LAUNCH_STATE_XXX. */
874 uint32_t fShadowVmcsState;
875 /** The host CPU for which its state has been exported to this VMCS. */
876 RTCPUID idHostCpuState;
877 /** The host CPU on which we last executed this VMCS. */
878 RTCPUID idHostCpuExec;
879 /** Number of guest MSRs in the VM-entry MSR-load area. */
880 uint32_t cEntryMsrLoad;
881 /** Number of guest MSRs in the VM-exit MSR-store area. */
882 uint32_t cExitMsrStore;
883 /** Number of host MSRs in the VM-exit MSR-load area. */
884 uint32_t cExitMsrLoad;
885 /** @} */
886
887 /** @name Cache of execution related VMCS fields.
888 * @{ */
889 /** Pin-based VM-execution controls. */
890 uint32_t u32PinCtls;
891 /** Processor-based VM-execution controls. */
892 uint32_t u32ProcCtls;
893 /** Secondary processor-based VM-execution controls. */
894 uint32_t u32ProcCtls2;
895 /** VM-entry controls. */
896 uint32_t u32EntryCtls;
897 /** VM-exit controls. */
898 uint32_t u32ExitCtls;
899 /** Exception bitmap. */
900 uint32_t u32XcptBitmap;
901 /** Page-fault exception error-code mask. */
902 uint32_t u32XcptPFMask;
903 /** Page-fault exception error-code match. */
904 uint32_t u32XcptPFMatch;
905 /** Padding. */
906 uint32_t u32Alignment0;
907 /** TSC offset. */
908 uint64_t u64TscOffset;
909 /** VMCS link pointer. */
910 uint64_t u64VmcsLinkPtr;
911 /** CR0 guest/host mask. */
912 uint64_t u64Cr0Mask;
913 /** CR4 guest/host mask. */
914 uint64_t u64Cr4Mask;
915 /** Current VMX_VMCS_HOST_RIP value (only used in HMR0A.asm). */
916 uint64_t uHostRip;
917 /** Current VMX_VMCS_HOST_RSP value (only used in HMR0A.asm). */
918 uint64_t uHostRsp;
919 /** @} */
920
921 /** @name Host-virtual address of VMCS and related data structures.
922 * @{ */
923 /** The VMCS. */
924 R0PTRTYPE(void *) pvVmcs;
925 /** The shadow VMCS. */
926 R0PTRTYPE(void *) pvShadowVmcs;
927 /** The virtual-APIC page. */
928 R0PTRTYPE(uint8_t *) pbVirtApic;
929 /** The MSR bitmap. */
930 R0PTRTYPE(void *) pvMsrBitmap;
931 /** The VM-entry MSR-load area. */
932 R0PTRTYPE(void *) pvGuestMsrLoad;
933 /** The VM-exit MSR-store area. */
934 R0PTRTYPE(void *) pvGuestMsrStore;
935 /** The VM-exit MSR-load area. */
936 R0PTRTYPE(void *) pvHostMsrLoad;
937 /** @} */
938
939 /** @name Host-physical address of VMCS and related data structures.
940 * @{ */
941 /** The VMCS. */
942 RTHCPHYS HCPhysVmcs;
943 /** The shadow VMCS. */
944 RTHCPHYS HCPhysShadowVmcs;
945 /** The virtual APIC page. */
946 RTHCPHYS HCPhysVirtApic;
947 /** The MSR bitmap. */
948 RTHCPHYS HCPhysMsrBitmap;
949 /** The VM-entry MSR-load area. */
950 RTHCPHYS HCPhysGuestMsrLoad;
951 /** The VM-exit MSR-store area. */
952 RTHCPHYS HCPhysGuestMsrStore;
953 /** The VM-exit MSR-load area. */
954 RTHCPHYS HCPhysHostMsrLoad;
955 /** @} */
956
957 /** @name R0-memory objects address for VMCS and related data structures.
958 * @{ */
959 /** R0-memory object for VMCS and related data structures. */
960 RTR0MEMOBJ hMemObj;
961 /** @} */
962} VMXVMCSINFO;
963/** Pointer to a VMXVMCSINFOR0 struct. */
964typedef VMXVMCSINFO *PVMXVMCSINFO;
965/** Pointer to a const VMXVMCSINFO struct. */
966typedef const VMXVMCSINFO *PCVMXVMCSINFO;
967AssertCompileSizeAlignment(VMXVMCSINFO, 8);
968AssertCompileMemberAlignment(VMXVMCSINFO, u32PinCtls, 4);
969AssertCompileMemberAlignment(VMXVMCSINFO, u64VmcsLinkPtr, 8);
970AssertCompileMemberAlignment(VMXVMCSINFO, pvVmcs, 8);
971AssertCompileMemberAlignment(VMXVMCSINFO, pvShadowVmcs, 8);
972AssertCompileMemberAlignment(VMXVMCSINFO, pbVirtApic, 8);
973AssertCompileMemberAlignment(VMXVMCSINFO, pvMsrBitmap, 8);
974AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrLoad, 8);
975AssertCompileMemberAlignment(VMXVMCSINFO, pvGuestMsrStore, 8);
976AssertCompileMemberAlignment(VMXVMCSINFO, pvHostMsrLoad, 8);
977AssertCompileMemberAlignment(VMXVMCSINFO, HCPhysVmcs, 8);
978AssertCompileMemberAlignment(VMXVMCSINFO, hMemObj, 8);
979
980
981/** @name Host-state restoration flags.
982 * @note If you change these values don't forget to update the assembly
983 * defines as well!
984 * @{
985 */
986#define VMX_RESTORE_HOST_SEL_DS RT_BIT(0)
987#define VMX_RESTORE_HOST_SEL_ES RT_BIT(1)
988#define VMX_RESTORE_HOST_SEL_FS RT_BIT(2)
989#define VMX_RESTORE_HOST_SEL_GS RT_BIT(3)
990#define VMX_RESTORE_HOST_SEL_TR RT_BIT(4)
991#define VMX_RESTORE_HOST_GDTR RT_BIT(5)
992#define VMX_RESTORE_HOST_IDTR RT_BIT(6)
993#define VMX_RESTORE_HOST_GDT_READ_ONLY RT_BIT(7)
994#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE RT_BIT(8)
995#define VMX_RESTORE_HOST_CAN_USE_WRFSBASE_AND_WRGSBASE RT_BIT(9)
996/**
997 * This _must_ be the top most bit, so that we can easily that that it and
998 * something else is set w/o having to do two checks like this:
999 * @code
1000 * if ( (pVCpu->hm.s.vmx.fRestoreHostFlags & VMX_RESTORE_HOST_REQUIRED)
1001 * && (pVCpu->hm.s.vmx.fRestoreHostFlags & ~VMX_RESTORE_HOST_REQUIRED))
1002 * @endcode
1003 * Instead we can then do:
1004 * @code
1005 * if (pVCpu->hm.s.vmx.fRestoreHostFlags > VMX_RESTORE_HOST_REQUIRED)
1006 * @endcode
1007 */
1008#define VMX_RESTORE_HOST_REQUIRED RT_BIT(10)
1009/** @} */
1010
1011/**
1012 * Host-state restoration structure.
1013 *
1014 * This holds host-state fields that require manual restoration.
1015 * Assembly version found in HMInternal.mac (should be automatically verified).
1016 */
1017typedef struct VMXRESTOREHOST
1018{
1019 RTSEL uHostSelDS; /**< 0x00 */
1020 RTSEL uHostSelES; /**< 0x02 */
1021 RTSEL uHostSelFS; /**< 0x04 */
1022 X86XDTR64 HostGdtr; /**< 0x06 - should be aligned by its 64-bit member. */
1023 RTSEL uHostSelGS; /**< 0x10 */
1024 RTSEL uHostSelTR; /**< 0x12 */
1025 RTSEL uHostSelSS; /**< 0x14 - not restored, just for fetching */
1026 X86XDTR64 HostGdtrRw; /**< 0x16 - should be aligned by its 64-bit member. */
1027 RTSEL uHostSelCS; /**< 0x20 - not restored, just for fetching */
1028 uint8_t abPadding1[4]; /**< 0x22 */
1029 X86XDTR64 HostIdtr; /**< 0x26 - should be aligned by its 64-bit member. */
1030 uint64_t uHostFSBase; /**< 0x30 */
1031 uint64_t uHostGSBase; /**< 0x38 */
1032} VMXRESTOREHOST;
1033/** Pointer to VMXRESTOREHOST. */
1034typedef VMXRESTOREHOST *PVMXRESTOREHOST;
1035AssertCompileSize(X86XDTR64, 10);
1036AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr, 0x08);
1037AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 0x18);
1038AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr, 0x28);
1039AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase, 0x30);
1040AssertCompileSize(VMXRESTOREHOST, 64);
1041AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
1042
1043/**
1044 * VMX StartVM function.
1045 *
1046 * @returns VBox status code (no informational stuff).
1047 * @param pVmcsInfo Pointer to the VMCS info (for cached host RIP and RSP).
1048 * @param pVCpu Pointer to the cross context per-CPU structure.
1049 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1050 */
1051typedef DECLCALLBACKTYPE(int, FNHMVMXSTARTVM,(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume));
1052/** Pointer to a VMX StartVM function. */
1053typedef R0PTRTYPE(FNHMVMXSTARTVM *) PFNHMVMXSTARTVM;
1054/** @} */
1055
1056/**
1057 * HM VMCPU Instance data.
1058 *
1059 * Note! If you change members of this struct, make sure to check if the
1060 * assembly counterpart in HMInternal.mac needs to be updated as well.
1061 *
1062 * Note! The members here are ordered and aligned based on estimated frequency of
1063 * usage and grouped to fit within a cache line in hot code paths. Even subtle
1064 * changes here have a noticeable effect in the bootsector benchmarks. Modify with
1065 * care.
1066 */
1067typedef struct HMCPU
1068{
1069 /** Set when the TLB has been checked until we return from the world switch. */
1070 bool volatile fCheckedTLBFlush;
1071 /** Set when we're using VT-x or AMD-V at that moment.
1072 * @todo r=bird: Misleading description. For AMD-V this will be set the first
1073 * time HMCanExecuteGuest() is called and only cleared again by
1074 * HMR3ResetCpu(). For VT-x it will be set by HMCanExecuteGuest when we
1075 * can execute something in VT-x mode, and cleared if we cannot.
1076 *
1077 * The field is much more about recording the last HMCanExecuteGuest
1078 * return value than anything about any "moment". */
1079 bool fActive;
1080
1081 /** Whether we should use the debug loop because of single stepping or special
1082 * debug breakpoints / events are armed. */
1083 bool fUseDebugLoop;
1084
1085 /** Whether \#UD needs to be intercepted (required by certain GIM providers). */
1086 bool fGIMTrapXcptUD;
1087 /** Whether \#GP needs to be intercepted for mesa driver workaround. */
1088 bool fTrapXcptGpForLovelyMesaDrv;
1089 /** Whether we're executing a single instruction. */
1090 bool fSingleInstruction;
1091
1092 bool afAlignment0[2];
1093
1094 /** An additional error code used for some gurus. */
1095 uint32_t u32HMError;
1096 /** The last exit-to-ring-3 reason. */
1097 int32_t rcLastExitToR3;
1098 /** CPU-context changed flags (see HM_CHANGED_xxx). */
1099 uint64_t fCtxChanged;
1100
1101 /** VT-x data. */
1102 struct HMCPUVMX
1103 {
1104 /** @name Guest information.
1105 * @{ */
1106 /** Guest VMCS information shared with ring-3. */
1107 VMXVMCSINFOSHARED VmcsInfo;
1108 /** Nested-guest VMCS information shared with ring-3. */
1109 VMXVMCSINFOSHARED VmcsInfoNstGst;
1110 /** Whether the nested-guest VMCS was the last current VMCS (shadow copy for ring-3).
1111 * @see HMR0PERVCPU::vmx.fSwitchedToNstGstVmcs */
1112 bool fSwitchedToNstGstVmcsCopyForRing3;
1113 /** Whether the static guest VMCS controls has been merged with the
1114 * nested-guest VMCS controls. */
1115 bool fMergedNstGstCtls;
1116 /** Whether the nested-guest VMCS has been copied to the shadow VMCS. */
1117 bool fCopiedNstGstToShadowVmcs;
1118 /** Whether flushing the TLB is required due to switching to/from the
1119 * nested-guest. */
1120 bool fSwitchedNstGstFlushTlb;
1121 /** Alignment. */
1122 bool afAlignment0[4];
1123 /** Cached guest APIC-base MSR for identifying when to map the APIC-access page. */
1124 uint64_t u64GstMsrApicBase;
1125 /** @} */
1126
1127 /** @name Error reporting and diagnostics.
1128 * @{ */
1129 /** VT-x error-reporting (mainly for ring-3 propagation). */
1130 struct
1131 {
1132 RTCPUID idCurrentCpu;
1133 RTCPUID idEnteredCpu;
1134 RTHCPHYS HCPhysCurrentVmcs;
1135 uint32_t u32VmcsRev;
1136 uint32_t u32InstrError;
1137 uint32_t u32ExitReason;
1138 uint32_t u32GuestIntrState;
1139 } LastError;
1140 /** @} */
1141 } vmx;
1142
1143 /** SVM data. */
1144 struct HMCPUSVM
1145 {
1146 /** Whether to emulate long mode support for sysenter/sysexit like intel CPUs
1147 * does. This means intercepting \#UD to emulate the instructions in
1148 * long-mode and to intercept reads and writes to the SYSENTER MSRs in order to
1149 * preserve the upper 32 bits written to them (AMD will ignore and discard). */
1150 bool fEmulateLongModeSysEnterExit;
1151 uint8_t au8Alignment0[7];
1152
1153 /** Cache of the nested-guest's VMCB fields that we modify in order to run the
1154 * nested-guest using AMD-V. This will be restored on \#VMEXIT. */
1155 SVMNESTEDVMCBCACHE NstGstVmcbCache;
1156 } svm;
1157
1158 /** Event injection state. */
1159 HMEVENT Event;
1160
1161 /** Current shadow paging mode for updating CR4.
1162 * @todo move later (@bugref{9217}). */
1163 PGMMODE enmShadowMode;
1164 uint32_t u32TemporaryPadding;
1165
1166 /** The PAE PDPEs used with Nested Paging (only valid when
1167 * VMCPU_FF_HM_UPDATE_PAE_PDPES is set). */
1168 X86PDPE aPdpes[4];
1169
1170 /* These two comes because they are accessed from assembly and we don't
1171 want to detail all the stats in the assembly version of this structure. */
1172 STAMCOUNTER StatVmxWriteHostRip;
1173 STAMCOUNTER StatVmxWriteHostRsp;
1174 STAMCOUNTER StatVmxVmLaunch;
1175 STAMCOUNTER StatVmxVmResume;
1176
1177 STAMPROFILEADV StatEntry;
1178 STAMPROFILEADV StatPreExit;
1179 STAMPROFILEADV StatExitHandling;
1180 STAMPROFILEADV StatExitIO;
1181 STAMPROFILEADV StatExitMovCRx;
1182 STAMPROFILEADV StatExitXcptNmi;
1183 STAMPROFILEADV StatExitVmentry;
1184 STAMPROFILEADV StatImportGuestState;
1185 STAMPROFILEADV StatExportGuestState;
1186 STAMPROFILEADV StatLoadGuestFpuState;
1187 STAMPROFILEADV StatInGC;
1188 STAMPROFILEADV StatPoke;
1189 STAMPROFILEADV StatSpinPoke;
1190 STAMPROFILEADV StatSpinPokeFailed;
1191
1192 STAMCOUNTER StatInjectInterrupt;
1193 STAMCOUNTER StatInjectXcpt;
1194 STAMCOUNTER StatInjectReflect;
1195 STAMCOUNTER StatInjectConvertDF;
1196 STAMCOUNTER StatInjectInterpret;
1197 STAMCOUNTER StatInjectReflectNPF;
1198
1199 STAMCOUNTER StatExitAll;
1200 STAMCOUNTER StatNestedExitAll;
1201 STAMCOUNTER StatExitShadowNM;
1202 STAMCOUNTER StatExitGuestNM;
1203 STAMCOUNTER StatExitShadowPF; /**< Misleading, currently used for MMIO \#PFs as well. */
1204 STAMCOUNTER StatExitShadowPFEM;
1205 STAMCOUNTER StatExitGuestPF;
1206 STAMCOUNTER StatExitGuestUD;
1207 STAMCOUNTER StatExitGuestSS;
1208 STAMCOUNTER StatExitGuestNP;
1209 STAMCOUNTER StatExitGuestTS;
1210 STAMCOUNTER StatExitGuestOF;
1211 STAMCOUNTER StatExitGuestGP;
1212 STAMCOUNTER StatExitGuestDE;
1213 STAMCOUNTER StatExitGuestDF;
1214 STAMCOUNTER StatExitGuestBR;
1215 STAMCOUNTER StatExitGuestAC;
1216 STAMCOUNTER StatExitGuestDB;
1217 STAMCOUNTER StatExitGuestMF;
1218 STAMCOUNTER StatExitGuestBP;
1219 STAMCOUNTER StatExitGuestXF;
1220 STAMCOUNTER StatExitGuestXcpUnk;
1221 STAMCOUNTER StatExitDRxWrite;
1222 STAMCOUNTER StatExitDRxRead;
1223 STAMCOUNTER StatExitCR0Read;
1224 STAMCOUNTER StatExitCR2Read;
1225 STAMCOUNTER StatExitCR3Read;
1226 STAMCOUNTER StatExitCR4Read;
1227 STAMCOUNTER StatExitCR8Read;
1228 STAMCOUNTER StatExitCR0Write;
1229 STAMCOUNTER StatExitCR2Write;
1230 STAMCOUNTER StatExitCR3Write;
1231 STAMCOUNTER StatExitCR4Write;
1232 STAMCOUNTER StatExitCR8Write;
1233 STAMCOUNTER StatExitRdmsr;
1234 STAMCOUNTER StatExitWrmsr;
1235 STAMCOUNTER StatExitClts;
1236 STAMCOUNTER StatExitXdtrAccess;
1237 STAMCOUNTER StatExitLmsw;
1238 STAMCOUNTER StatExitIOWrite;
1239 STAMCOUNTER StatExitIORead;
1240 STAMCOUNTER StatExitIOStringWrite;
1241 STAMCOUNTER StatExitIOStringRead;
1242 STAMCOUNTER StatExitIntWindow;
1243 STAMCOUNTER StatExitExtInt;
1244 STAMCOUNTER StatExitHostNmiInGC;
1245 STAMCOUNTER StatExitHostNmiInGCIpi;
1246 STAMCOUNTER StatExitPreemptTimer;
1247 STAMCOUNTER StatExitTprBelowThreshold;
1248 STAMCOUNTER StatExitTaskSwitch;
1249 STAMCOUNTER StatExitApicAccess;
1250 STAMCOUNTER StatExitReasonNpf;
1251
1252 STAMCOUNTER StatNestedExitReasonNpf;
1253
1254 STAMCOUNTER StatFlushPage;
1255 STAMCOUNTER StatFlushPageManual;
1256 STAMCOUNTER StatFlushPhysPageManual;
1257 STAMCOUNTER StatFlushTlb;
1258 STAMCOUNTER StatFlushTlbNstGst;
1259 STAMCOUNTER StatFlushTlbManual;
1260 STAMCOUNTER StatFlushTlbWorldSwitch;
1261 STAMCOUNTER StatNoFlushTlbWorldSwitch;
1262 STAMCOUNTER StatFlushEntire;
1263 STAMCOUNTER StatFlushAsid;
1264 STAMCOUNTER StatFlushNestedPaging;
1265 STAMCOUNTER StatFlushTlbInvlpgVirt;
1266 STAMCOUNTER StatFlushTlbInvlpgPhys;
1267 STAMCOUNTER StatTlbShootdown;
1268 STAMCOUNTER StatTlbShootdownFlush;
1269
1270 STAMCOUNTER StatSwitchPendingHostIrq;
1271 STAMCOUNTER StatSwitchTprMaskedIrq;
1272 STAMCOUNTER StatSwitchGuestIrq;
1273 STAMCOUNTER StatSwitchHmToR3FF;
1274 STAMCOUNTER StatSwitchVmReq;
1275 STAMCOUNTER StatSwitchPgmPoolFlush;
1276 STAMCOUNTER StatSwitchDma;
1277 STAMCOUNTER StatSwitchExitToR3;
1278 STAMCOUNTER StatSwitchLongJmpToR3;
1279 STAMCOUNTER StatSwitchMaxResumeLoops;
1280 STAMCOUNTER StatSwitchHltToR3;
1281 STAMCOUNTER StatSwitchApicAccessToR3;
1282 STAMCOUNTER StatSwitchPreempt;
1283 STAMCOUNTER StatSwitchNstGstVmexit;
1284
1285 STAMCOUNTER StatTscParavirt;
1286 STAMCOUNTER StatTscOffset;
1287 STAMCOUNTER StatTscIntercept;
1288
1289 STAMCOUNTER StatDRxArmed;
1290 STAMCOUNTER StatDRxContextSwitch;
1291 STAMCOUNTER StatDRxIoCheck;
1292
1293 STAMCOUNTER StatExportMinimal;
1294 STAMCOUNTER StatExportFull;
1295 STAMCOUNTER StatLoadGuestFpu;
1296 STAMCOUNTER StatExportHostState;
1297
1298 STAMCOUNTER StatVmxCheckBadRmSelBase;
1299 STAMCOUNTER StatVmxCheckBadRmSelLimit;
1300 STAMCOUNTER StatVmxCheckBadRmSelAttr;
1301 STAMCOUNTER StatVmxCheckBadV86SelBase;
1302 STAMCOUNTER StatVmxCheckBadV86SelLimit;
1303 STAMCOUNTER StatVmxCheckBadV86SelAttr;
1304 STAMCOUNTER StatVmxCheckRmOk;
1305 STAMCOUNTER StatVmxCheckBadSel;
1306 STAMCOUNTER StatVmxCheckBadRpl;
1307 STAMCOUNTER StatVmxCheckPmOk;
1308
1309#ifdef VBOX_WITH_STATISTICS
1310 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
1311 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
1312 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
1313 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
1314 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedXcpts;
1315 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedXcptsR0;
1316 R3PTRTYPE(PSTAMCOUNTER) paStatNestedExitReason;
1317 R0PTRTYPE(PSTAMCOUNTER) paStatNestedExitReasonR0;
1318#endif
1319#ifdef HM_PROFILE_EXIT_DISPATCH
1320 STAMPROFILEADV StatExitDispatch;
1321#endif
1322} HMCPU;
1323/** Pointer to HM VMCPU instance data. */
1324typedef HMCPU *PHMCPU;
1325AssertCompileMemberAlignment(HMCPU, fCheckedTLBFlush, 4);
1326AssertCompileMemberAlignment(HMCPU, fCtxChanged, 8);
1327AssertCompileMemberAlignment(HMCPU, vmx, 8);
1328AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfo, 8);
1329AssertCompileMemberAlignment(HMCPU, vmx.VmcsInfoNstGst, 8);
1330AssertCompileMemberAlignment(HMCPU, svm, 8);
1331AssertCompileMemberAlignment(HMCPU, Event, 8);
1332
1333
1334/**
1335 * HM per-VCpu ring-0 only instance data.
1336 */
1337typedef struct HMR0PERVCPU
1338{
1339 /** World switch exit counter. */
1340 uint32_t volatile cWorldSwitchExits;
1341 /** TLB flush count. */
1342 uint32_t cTlbFlushes;
1343 /** The last CPU we were executing code on (NIL_RTCPUID for the first time). */
1344 RTCPUID idLastCpu;
1345 /** The CPU ID of the CPU currently owning the VMCS. Set in
1346 * HMR0Enter and cleared in HMR0Leave. */
1347 RTCPUID idEnteredCpu;
1348 /** Current ASID in use by the VM. */
1349 uint32_t uCurrentAsid;
1350
1351 /** Set if we need to flush the TLB during the world switch. */
1352 bool fForceTLBFlush;
1353 /** Whether we've completed the inner HM leave function. */
1354 bool fLeaveDone;
1355 /** Whether we're using the hyper DR7 or guest DR7. */
1356 bool fUsingHyperDR7;
1357 /** Whether we are currently executing in the debug loop.
1358 * Mainly for assertions. */
1359 bool fUsingDebugLoop;
1360 /** Set if we using the debug loop and wish to intercept RDTSC. */
1361 bool fDebugWantRdTscExit;
1362 /** Set if XCR0 needs to be saved/restored when entering/exiting guest code
1363 * execution. */
1364 bool fLoadSaveGuestXcr0;
1365 /** Set if we need to clear the trap flag because of single stepping. */
1366 bool fClearTrapFlag;
1367
1368 bool afPadding1[1];
1369 /** World switcher flags (HM_WSF_XXX - was CPUMCTX::fWorldSwitcher in 6.1). */
1370 uint32_t fWorldSwitcher;
1371
1372 /** VT-x data. */
1373 struct HMR0CPUVMX
1374 {
1375 /** Ring-0 pointer to the hardware-assisted VMX execution function. */
1376 PFNHMVMXSTARTVM pfnStartVm;
1377
1378 /** @name Guest information.
1379 * @{ */
1380 /** Guest VMCS information. */
1381 VMXVMCSINFO VmcsInfo;
1382 /** Nested-guest VMCS information. */
1383 VMXVMCSINFO VmcsInfoNstGst;
1384 /* Whether the nested-guest VMCS was the last current VMCS (authoritative copy).
1385 * @see HMCPU::vmx.fSwitchedToNstGstVmcsCopyForRing3 */
1386 bool fSwitchedToNstGstVmcs;
1387 bool afAlignment0[7];
1388 /** @} */
1389
1390 /** @name Host information.
1391 * @{ */
1392 /** Host LSTAR MSR to restore lazily while leaving VT-x. */
1393 uint64_t u64HostMsrLStar;
1394 /** Host STAR MSR to restore lazily while leaving VT-x. */
1395 uint64_t u64HostMsrStar;
1396 /** Host SF_MASK MSR to restore lazily while leaving VT-x. */
1397 uint64_t u64HostMsrSfMask;
1398 /** Host KernelGS-Base MSR to restore lazily while leaving VT-x. */
1399 uint64_t u64HostMsrKernelGsBase;
1400 /** The mask of lazy MSRs swap/restore state, see VMX_LAZY_MSRS_XXX. */
1401 uint32_t fLazyMsrs;
1402 /** Whether the host MSR values are up-to-date in the auto-load/store MSR area. */
1403 bool fUpdatedHostAutoMsrs;
1404 /** Alignment. */
1405 uint8_t au8Alignment0[3];
1406 /** Which host-state bits to restore before being preempted, see
1407 * VMX_RESTORE_HOST_XXX. */
1408 uint32_t fRestoreHostFlags;
1409 /** Alignment. */
1410 uint32_t u32Alignment0;
1411 /** The host-state restoration structure. */
1412 VMXRESTOREHOST RestoreHost;
1413 /** @} */
1414 } vmx;
1415
1416 /** SVM data. */
1417 struct HMR0CPUSVM
1418 {
1419 /** Ring 0 handlers for VT-x. */
1420 PFNHMSVMVMRUN pfnVMRun;
1421
1422 /** Physical address of the host VMCB which holds additional host-state. */
1423 RTHCPHYS HCPhysVmcbHost;
1424 /** R0 memory object for the host VMCB which holds additional host-state. */
1425 RTR0MEMOBJ hMemObjVmcbHost;
1426
1427 /** Physical address of the guest VMCB. */
1428 RTHCPHYS HCPhysVmcb;
1429 /** R0 memory object for the guest VMCB. */
1430 RTR0MEMOBJ hMemObjVmcb;
1431 /** Pointer to the guest VMCB. */
1432 R0PTRTYPE(PSVMVMCB) pVmcb;
1433
1434 /** Physical address of the MSR bitmap (8 KB). */
1435 RTHCPHYS HCPhysMsrBitmap;
1436 /** R0 memory object for the MSR bitmap (8 KB). */
1437 RTR0MEMOBJ hMemObjMsrBitmap;
1438 /** Pointer to the MSR bitmap. */
1439 R0PTRTYPE(void *) pvMsrBitmap;
1440
1441 /** Whether VTPR with V_INTR_MASKING set is in effect, indicating
1442 * we should check if the VTPR changed on every VM-exit. */
1443 bool fSyncVTpr;
1444 bool afAlignment[7];
1445
1446 /** Host's TSC_AUX MSR (used when RDTSCP doesn't cause VM-exits). */
1447 uint64_t u64HostTscAux;
1448
1449 /** For saving stack space, the disassembler state is allocated here
1450 * instead of on the stack. */
1451 DISCPUSTATE DisState;
1452 } svm;
1453} HMR0PERVCPU;
1454/** Pointer to HM ring-0 VMCPU instance data. */
1455typedef HMR0PERVCPU *PHMR0PERVCPU;
1456AssertCompileMemberAlignment(HMR0PERVCPU, cWorldSwitchExits, 4);
1457AssertCompileMemberAlignment(HMR0PERVCPU, fForceTLBFlush, 4);
1458AssertCompileMemberAlignment(HMR0PERVCPU, vmx.RestoreHost, 8);
1459
1460
1461/** @name HM_WSF_XXX - @bugref{9453}, @bugref{9087}
1462 * @{ */
1463/** Touch IA32_PRED_CMD.IBPB on VM exit. */
1464#define HM_WSF_IBPB_EXIT RT_BIT_32(0)
1465/** Touch IA32_PRED_CMD.IBPB on VM entry. */
1466#define HM_WSF_IBPB_ENTRY RT_BIT_32(1)
1467/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
1468#define HM_WSF_L1D_ENTRY RT_BIT_32(2)
1469/** Flush MDS buffers on VM entry. */
1470#define HM_WSF_MDS_ENTRY RT_BIT_32(3)
1471/** @} */
1472
1473
1474#ifdef IN_RING0
1475extern bool g_fHmVmxSupported;
1476extern uint32_t g_fHmHostKernelFeatures;
1477extern uint32_t g_uHmMaxAsid;
1478extern bool g_fHmVmxUsePreemptTimer;
1479extern uint8_t g_cHmVmxPreemptTimerShift;
1480extern bool g_fHmVmxSupportsVmcsEfer;
1481extern uint64_t g_uHmVmxHostCr4;
1482extern uint64_t g_uHmVmxHostMsrEfer;
1483extern uint64_t g_uHmVmxHostSmmMonitorCtl;
1484extern bool g_fHmSvmSupported;
1485extern uint32_t g_uHmSvmRev;
1486extern uint32_t g_fHmSvmFeatures;
1487
1488extern SUPHWVIRTMSRS g_HmMsrs;
1489
1490
1491VMMR0_INT_DECL(PHMPHYSCPU) hmR0GetCurrentCpu(void);
1492VMMR0_INT_DECL(int) hmR0EnterCpu(PVMCPUCC pVCpu);
1493
1494# ifdef VBOX_STRICT
1495# define HM_DUMP_REG_FLAGS_GPRS RT_BIT(0)
1496# define HM_DUMP_REG_FLAGS_FPU RT_BIT(1)
1497# define HM_DUMP_REG_FLAGS_MSRS RT_BIT(2)
1498# define HM_DUMP_REG_FLAGS_ALL (HM_DUMP_REG_FLAGS_GPRS | HM_DUMP_REG_FLAGS_FPU | HM_DUMP_REG_FLAGS_MSRS)
1499
1500VMMR0_INT_DECL(void) hmR0DumpRegs(PVMCPUCC pVCpu, uint32_t fFlags);
1501VMMR0_INT_DECL(void) hmR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
1502# endif
1503
1504DECLASM(void) hmR0MdsClear(void);
1505#endif /* IN_RING0 */
1506
1507
1508/** @addtogroup grp_hm_int_svm SVM Internal
1509 * @{ */
1510VMM_INT_DECL(int) hmEmulateSvmMovTpr(PVMCC pVM, PVMCPUCC pVCpu);
1511
1512/**
1513 * Prepares for and executes VMRUN (64-bit register context).
1514 *
1515 * @returns VBox status code (no informational stuff).
1516 * @param pVM The cross context VM structure. (Not used.)
1517 * @param pVCpu The cross context virtual CPU structure.
1518 * @param HCPhyspVMCB Physical address of the VMCB.
1519 *
1520 * @remarks With spectre mitigations and the usual need for speed (/ micro
1521 * optimizations), we have a bunch of variations of this code depending
1522 * on a few precoditions. In release builds, the code is entirely
1523 * without conditionals. Debug builds have a couple of assertions that
1524 * shouldn't ever be triggered.
1525 *
1526 * @{
1527 */
1528DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1529DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1530DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1531DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_SansIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1532DECLASM(int) hmR0SvmVmRun_SansXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1533DECLASM(int) hmR0SvmVmRun_WithXcr0_SansIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1534DECLASM(int) hmR0SvmVmRun_SansXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1535DECLASM(int) hmR0SvmVmRun_WithXcr0_WithIbpbEntry_WithIbpbExit(PVMCC pVM, PVMCPUCC pVCpu, RTHCPHYS HCPhyspVMCB);
1536/** @} */
1537
1538/** @} */
1539
1540
1541/** @addtogroup grp_hm_int_vmx VMX Internal
1542 * @{ */
1543VMM_INT_DECL(PVMXVMCSINFOSHARED) hmGetVmxActiveVmcsInfoShared(PVMCPUCC pVCpu);
1544
1545/**
1546 * Used on platforms with poor inline assembly support to retrieve all the
1547 * info from the CPU and put it in the @a pRestoreHost structure.
1548 */
1549DECLASM(void) hmR0VmxExportHostSegmentRegsAsmHlp(PVMXRESTOREHOST pRestoreHost, bool fHaveFsGsBase);
1550
1551/**
1552 * Restores some host-state fields that need not be done on every VM-exit.
1553 *
1554 * @returns VBox status code.
1555 * @param fRestoreHostFlags Flags of which host registers needs to be
1556 * restored.
1557 * @param pRestoreHost Pointer to the host-restore structure.
1558 */
1559DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
1560
1561/**
1562 * VMX StartVM functions.
1563 *
1564 * @returns VBox status code (no informational stuff).
1565 * @param pVM Pointer to the cross context VM structure.
1566 * @param pVCpu Pointer to the cross context per-CPU structure.
1567 * @param fResume Whether to use VMRESUME (true) or VMLAUNCH (false).
1568 *
1569 * @remarks With spectre mitigations and the usual need for speed (/ micro
1570 * optimizations), we have a bunch of variations of this code depending
1571 * on a few precoditions. In release builds, the code is entirely
1572 * without conditionals. Debug builds have a couple of assertions that
1573 * shouldn't ever be triggered.
1574 *
1575 * @{
1576 */
1577DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1578DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1579DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1580DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1581DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1582DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1583DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1584DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1585DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1586DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1587DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1588DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1589DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1590DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1591DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1592DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_SansIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1593DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1594DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1595DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1596DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1597DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1598DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1599DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1600DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_SansMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1601DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1602DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1603DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1604DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_SansL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1605DECLASM(int) hmR0VmxStartVm_SansXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1606DECLASM(int) hmR0VmxStartVm_WithXcr0_SansIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1607DECLASM(int) hmR0VmxStartVm_SansXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1608DECLASM(int) hmR0VmxStartVm_WithXcr0_WithIbpbEntry_WithL1dEntry_WithMdsEntry_WithIbpbExit(PVMXVMCSINFO pVmcsInfo, PVMCPUCC pVCpu, bool fResume);
1609/** @} */
1610
1611/** @} */
1612
1613/** @} */
1614
1615RT_C_DECLS_END
1616
1617#endif /* !VMM_INCLUDED_SRC_include_HMInternal_h */
1618
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