VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 95394

Last change on this file since 95394 was 94768, checked in by vboxsync, 3 years ago

VMM/IEM: Split up IEMAll.cpp into a few more compilation units. bugref:9898
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1/* $Id: IEMMc.h 94768 2022-05-01 22:02:17Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
19#define VMM_INCLUDED_SRC_include_IEMMc_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24
25/** @name "Microcode" macros.
26 *
27 * The idea is that we should be able to use the same code to interpret
28 * instructions as well as recompiler instructions. Thus this obfuscation.
29 *
30 * @{
31 */
32#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
33#define IEM_MC_END() }
34#define IEM_MC_PAUSE() do {} while (0)
35#define IEM_MC_CONTINUE() do {} while (0)
36
37/** Internal macro. */
38#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
39 do \
40 { \
41 VBOXSTRICTRC rcStrict2 = a_Expr; \
42 if (rcStrict2 != VINF_SUCCESS) \
43 return rcStrict2; \
44 } while (0)
45
46
47#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
48#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
49#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
50#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
51#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
52#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
53#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
54#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
55#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
56 do { \
57 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
58 return iemRaiseDeviceNotAvailable(pVCpu); \
59 } while (0)
60#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
61 do { \
62 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
63 return iemRaiseDeviceNotAvailable(pVCpu); \
64 } while (0)
65#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
66 do { \
67 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
68 return iemRaiseMathFault(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
71 do { \
72 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
73 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
74 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
75 return iemRaiseUndefinedOpcode(pVCpu); \
76 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
80 do { \
81 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
82 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
83 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
84 return iemRaiseUndefinedOpcode(pVCpu); \
85 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
86 return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
89 do { \
90 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
91 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
92 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
93 return iemRaiseUndefinedOpcode(pVCpu); \
94 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
95 return iemRaiseDeviceNotAvailable(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
98 do { \
99 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
100 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
101 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
102 return iemRaiseUndefinedOpcode(pVCpu); \
103 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
104 return iemRaiseDeviceNotAvailable(pVCpu); \
105 } while (0)
106#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
107 do { \
108 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
109 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
110 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
119 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
120 return iemRaiseUndefinedOpcode(pVCpu); \
121 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
122 return iemRaiseDeviceNotAvailable(pVCpu); \
123 } while (0)
124#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
125 do { \
126 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
128 return iemRaiseUndefinedOpcode(pVCpu); \
129 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
130 return iemRaiseDeviceNotAvailable(pVCpu); \
131 } while (0)
132#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
133 do { \
134 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
135 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
136 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
137 return iemRaiseUndefinedOpcode(pVCpu); \
138 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
139 return iemRaiseDeviceNotAvailable(pVCpu); \
140 } while (0)
141#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
142 do { \
143 if (pVCpu->iem.s.uCpl != 0) \
144 return iemRaiseGeneralProtectionFault0(pVCpu); \
145 } while (0)
146#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
147 do { \
148 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
149 else return iemRaiseGeneralProtectionFault0(pVCpu); \
150 } while (0)
151#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
152 do { \
153 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
154 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
155 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 } while (0)
158#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
159 do { \
160 if (!IEM_IS_CANONICAL(a_u64Addr)) \
161 return iemRaiseGeneralProtectionFault0(pVCpu); \
162 } while (0)
163
164
165#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
166#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
167#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
168#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
169#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
170#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
171#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
172 uint32_t a_Name; \
173 uint32_t *a_pName = &a_Name
174#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
175 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
176
177#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
178#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
179
180#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
181#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
182#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
183#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
184#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
185#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
186#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
187#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
188#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
189#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
190#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
191#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
192#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
193#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
194#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
195#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
196#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
197#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
198 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
199 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
200 } while (0)
201#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
202 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
203 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
204 } while (0)
205#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
206 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
207 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
208 } while (0)
209/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
210#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
211 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
212 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
213 } while (0)
214#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
215 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
216 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
217 } while (0)
218/** @note Not for IOPL or IF testing or modification. */
219#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
220#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
221#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
222#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
223
224#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
225#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
226#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
227#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
228#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
229#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
230#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
231#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
232#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
233#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
234/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
235#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
236 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
237 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
238 } while (0)
239#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
240 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
241 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
242 } while (0)
243#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
244 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
245
246
247#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
248#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
249/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
250 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
251#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
252#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
253/** @note Not for IOPL or IF testing or modification. */
254#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
255
256#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
257#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
258#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
259 do { \
260 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
261 *pu32Reg += (a_u32Value); \
262 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
263 } while (0)
264#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
265
266#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
267#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
268#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
269 do { \
270 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
271 *pu32Reg -= (a_u32Value); \
272 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
273 } while (0)
274#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
275#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
276
277#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
278#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
279#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
280#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
281#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
282#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
283#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
284
285#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
286#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
287#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
288#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
289
290#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
291#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
292#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
293
294#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
295#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
296#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
297
298#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
299#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
300#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
301
302#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
303#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
304#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
305
306#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
307
308#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
309
310#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
311#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
312#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
313 do { \
314 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
315 *pu32Reg &= (a_u32Value); \
316 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
317 } while (0)
318#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
319
320#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
321#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
322#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
323 do { \
324 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
325 *pu32Reg |= (a_u32Value); \
326 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
327 } while (0)
328#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
329
330
331/** @note Not for IOPL or IF modification. */
332#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
333/** @note Not for IOPL or IF modification. */
334#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
335/** @note Not for IOPL or IF modification. */
336#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
337
338#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
339
340/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
341#define IEM_MC_FPU_TO_MMX_MODE() do { \
342 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
343 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
344 } while (0)
345
346/** Switches the FPU state from MMX mode (FTW=0xffff). */
347#define IEM_MC_FPU_FROM_MMX_MODE() do { \
348 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
349 } while (0)
350
351#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
352 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
353#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
354 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
355#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
356 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
357 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
358 } while (0)
359#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
360 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
361 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
362 } while (0)
363#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
364 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
365#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
366 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
367#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
368 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
369
370#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
371 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
372 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
373 } while (0)
374#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
375 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
376#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
377 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
378#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
379 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
380#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
381 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
382 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
383 } while (0)
384#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
385 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
386#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
387 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
388 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
389 } while (0)
390#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
391 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
392#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
393 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
394 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
395 } while (0)
396#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
397 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
398#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
399 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
400#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
401 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
402#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
403 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
404#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
405 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
406 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
407 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
408 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
409 } while (0)
410
411#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
412 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
413 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
414 } while (0)
415#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
416 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
417 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
418 } while (0)
419#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
420 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
421 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
422 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
423 } while (0)
424#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
425 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
426 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
427 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
428 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
429 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
430 } while (0)
431
432#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
433#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
434 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
435 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
436 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
437 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
438 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
439 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
440 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
441 } while (0)
442#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
443 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
444 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
445 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
446 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
447 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
448 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
449 } while (0)
450#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
451 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
452 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
453 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
454 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
455 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
456 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
457 } while (0)
458#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
459 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
460 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
461 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
462 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
463 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
464 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
465 } while (0)
466
467#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
468 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
469#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
470 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
471#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
472 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
473#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
474 do { uintptr_t const iYRegTmp = (a_iYReg); \
475 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
476 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
477 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
478 } while (0)
479
480#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
481 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
482 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
483 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
484 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
485 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
486 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
487 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
488 } while (0)
489#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
490 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
491 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
492 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
493 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
494 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
495 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
496 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
497 } while (0)
498#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
499 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
500 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
501 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
502 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
503 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
504 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
505 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
506 } while (0)
507
508#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
509 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
510 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
511 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
512 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
514 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
515 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
516 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
517 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
518 } while (0)
519#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
520 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
521 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
522 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
523 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
524 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
525 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
526 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
527 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
528 } while (0)
529#define IEM_MC_MERGE_YREG_U64HI_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
530 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
531 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
532 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
533 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
534 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
535 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
536 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
537 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
538 } while (0)
539#define IEM_MC_MERGE_YREG_U64LOCAL_U64_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
540 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
541 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
542 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
543 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
544 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
545 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
546 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
547 } while (0)
548
549#ifndef IEM_WITH_SETJMP
550# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
551 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
552# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
553 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
554# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
555 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
556#else
557# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
558 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
559# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
560 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
561# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
562 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
563#endif
564
565#ifndef IEM_WITH_SETJMP
566# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
567 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
568# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
569 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
570# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
571 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
572#else
573# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
574 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
575# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
576 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
577# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
578 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
579#endif
580
581#ifndef IEM_WITH_SETJMP
582# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
583 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
584# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
585 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
586# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
587 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
588#else
589# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
590 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
591# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
592 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
593# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
594 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
595#endif
596
597#ifdef SOME_UNUSED_FUNCTION
598# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
599 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
600#endif
601
602#ifndef IEM_WITH_SETJMP
603# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
604 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
605# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
606 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
607# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
608 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
609# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
610 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
611#else
612# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
613 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
614# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
615 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
616# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
617 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
618# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
619 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
620#endif
621
622#ifndef IEM_WITH_SETJMP
623# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
624 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
625# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
626 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
627# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
628 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
629# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
630 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
631#else
632# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
633 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
634# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
635 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
636# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
637 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
638# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
639 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
640#endif
641
642#ifndef IEM_WITH_SETJMP
643# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
644 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
645# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
646 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
647#else
648# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
649 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
650# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
651 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
652#endif
653
654#ifndef IEM_WITH_SETJMP
655# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
656 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
657# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
658 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
659#else
660# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
661 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
662# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
663 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
664#endif
665
666
667
668#ifndef IEM_WITH_SETJMP
669# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
670 do { \
671 uint8_t u8Tmp; \
672 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
673 (a_u16Dst) = u8Tmp; \
674 } while (0)
675# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
676 do { \
677 uint8_t u8Tmp; \
678 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
679 (a_u32Dst) = u8Tmp; \
680 } while (0)
681# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
682 do { \
683 uint8_t u8Tmp; \
684 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
685 (a_u64Dst) = u8Tmp; \
686 } while (0)
687# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
688 do { \
689 uint16_t u16Tmp; \
690 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
691 (a_u32Dst) = u16Tmp; \
692 } while (0)
693# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
694 do { \
695 uint16_t u16Tmp; \
696 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
697 (a_u64Dst) = u16Tmp; \
698 } while (0)
699# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
700 do { \
701 uint32_t u32Tmp; \
702 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
703 (a_u64Dst) = u32Tmp; \
704 } while (0)
705#else /* IEM_WITH_SETJMP */
706# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
707 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
708# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
709 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
710# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
711 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
712# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
713 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
714# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
715 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
716# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
717 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
718#endif /* IEM_WITH_SETJMP */
719
720#ifndef IEM_WITH_SETJMP
721# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
722 do { \
723 uint8_t u8Tmp; \
724 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
725 (a_u16Dst) = (int8_t)u8Tmp; \
726 } while (0)
727# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
728 do { \
729 uint8_t u8Tmp; \
730 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
731 (a_u32Dst) = (int8_t)u8Tmp; \
732 } while (0)
733# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
734 do { \
735 uint8_t u8Tmp; \
736 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
737 (a_u64Dst) = (int8_t)u8Tmp; \
738 } while (0)
739# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
740 do { \
741 uint16_t u16Tmp; \
742 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
743 (a_u32Dst) = (int16_t)u16Tmp; \
744 } while (0)
745# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
746 do { \
747 uint16_t u16Tmp; \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
749 (a_u64Dst) = (int16_t)u16Tmp; \
750 } while (0)
751# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
752 do { \
753 uint32_t u32Tmp; \
754 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
755 (a_u64Dst) = (int32_t)u32Tmp; \
756 } while (0)
757#else /* IEM_WITH_SETJMP */
758# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
759 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
760# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
761 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
762# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
763 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
764# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
765 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
766# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
767 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
768# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
769 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
770#endif /* IEM_WITH_SETJMP */
771
772#ifndef IEM_WITH_SETJMP
773# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
774 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
775# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
777# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
779# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
780 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
781#else
782# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
783 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
784# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
785 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
786# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
787 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
788# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
789 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
790#endif
791
792#ifndef IEM_WITH_SETJMP
793# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
794 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
795# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
797# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
798 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
799# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
800 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
801#else
802# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
803 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
804# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
805 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
806# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
807 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
808# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
809 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
810#endif
811
812#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
813#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
814#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
815#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
816#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
817#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
818#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
819 do { \
820 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
821 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
822 } while (0)
823#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
824 do { \
825 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
826 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
827 } while (0)
828
829#ifndef IEM_WITH_SETJMP
830# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
831 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
832# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
833 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
834#else
835# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
836 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
837# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
838 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
839#endif
840
841#ifndef IEM_WITH_SETJMP
842# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
844# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
845 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
846#else
847# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
848 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
849# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
850 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
851#endif
852
853
854#define IEM_MC_PUSH_U16(a_u16Value) \
855 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
856#define IEM_MC_PUSH_U32(a_u32Value) \
857 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
858#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
859 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
860#define IEM_MC_PUSH_U64(a_u64Value) \
861 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
862
863#define IEM_MC_POP_U16(a_pu16Value) \
864 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
865#define IEM_MC_POP_U32(a_pu32Value) \
866 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
867#define IEM_MC_POP_U64(a_pu64Value) \
868 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
869
870/** Maps guest memory for direct or bounce buffered access.
871 * The purpose is to pass it to an operand implementation, thus the a_iArg.
872 * @remarks May return.
873 */
874#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
875 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), (a_GCPtrMem), (a_fAccess)))
876
877/** Maps guest memory for direct or bounce buffered access.
878 * The purpose is to pass it to an operand implementation, thus the a_iArg.
879 * @remarks May return.
880 */
881#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_iArg) \
882 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), (a_GCPtrMem), (a_fAccess)))
883
884/** Commits the memory and unmaps the guest memory.
885 * @remarks May return.
886 */
887#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
888 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
889
890/** Commits the memory and unmaps the guest memory unless the FPU status word
891 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
892 * that would cause FLD not to store.
893 *
894 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
895 * store, while \#P will not.
896 *
897 * @remarks May in theory return - for now.
898 */
899#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
900 do { \
901 if ( !(a_u16FSW & X86_FSW_ES) \
902 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
903 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
904 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
905 } while (0)
906
907/** Calculate efficient address from R/M. */
908#ifndef IEM_WITH_SETJMP
909# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
910 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
911#else
912# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
913 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
914#endif
915
916#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
917#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
918#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
919#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
920#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
921#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
922#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
923
924/**
925 * Defers the rest of the instruction emulation to a C implementation routine
926 * and returns, only taking the standard parameters.
927 *
928 * @param a_pfnCImpl The pointer to the C routine.
929 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
930 */
931#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
932
933/**
934 * Defers the rest of instruction emulation to a C implementation routine and
935 * returns, taking one argument in addition to the standard ones.
936 *
937 * @param a_pfnCImpl The pointer to the C routine.
938 * @param a0 The argument.
939 */
940#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
941
942/**
943 * Defers the rest of the instruction emulation to a C implementation routine
944 * and returns, taking two arguments in addition to the standard ones.
945 *
946 * @param a_pfnCImpl The pointer to the C routine.
947 * @param a0 The first extra argument.
948 * @param a1 The second extra argument.
949 */
950#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
951
952/**
953 * Defers the rest of the instruction emulation to a C implementation routine
954 * and returns, taking three arguments in addition to the standard ones.
955 *
956 * @param a_pfnCImpl The pointer to the C routine.
957 * @param a0 The first extra argument.
958 * @param a1 The second extra argument.
959 * @param a2 The third extra argument.
960 */
961#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
962
963/**
964 * Defers the rest of the instruction emulation to a C implementation routine
965 * and returns, taking four arguments in addition to the standard ones.
966 *
967 * @param a_pfnCImpl The pointer to the C routine.
968 * @param a0 The first extra argument.
969 * @param a1 The second extra argument.
970 * @param a2 The third extra argument.
971 * @param a3 The fourth extra argument.
972 */
973#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
974
975/**
976 * Defers the rest of the instruction emulation to a C implementation routine
977 * and returns, taking two arguments in addition to the standard ones.
978 *
979 * @param a_pfnCImpl The pointer to the C routine.
980 * @param a0 The first extra argument.
981 * @param a1 The second extra argument.
982 * @param a2 The third extra argument.
983 * @param a3 The fourth extra argument.
984 * @param a4 The fifth extra argument.
985 */
986#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
987
988/**
989 * Defers the entire instruction emulation to a C implementation routine and
990 * returns, only taking the standard parameters.
991 *
992 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
993 *
994 * @param a_pfnCImpl The pointer to the C routine.
995 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
996 */
997#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
998
999/**
1000 * Defers the entire instruction emulation to a C implementation routine and
1001 * returns, taking one argument in addition to the standard ones.
1002 *
1003 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1004 *
1005 * @param a_pfnCImpl The pointer to the C routine.
1006 * @param a0 The argument.
1007 */
1008#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1009
1010/**
1011 * Defers the entire instruction emulation to a C implementation routine and
1012 * returns, taking two arguments in addition to the standard ones.
1013 *
1014 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1015 *
1016 * @param a_pfnCImpl The pointer to the C routine.
1017 * @param a0 The first extra argument.
1018 * @param a1 The second extra argument.
1019 */
1020#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1021
1022/**
1023 * Defers the entire instruction emulation to a C implementation routine and
1024 * returns, taking three arguments in addition to the standard ones.
1025 *
1026 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1027 *
1028 * @param a_pfnCImpl The pointer to the C routine.
1029 * @param a0 The first extra argument.
1030 * @param a1 The second extra argument.
1031 * @param a2 The third extra argument.
1032 */
1033#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1034
1035/**
1036 * Calls a FPU assembly implementation taking one visible argument.
1037 *
1038 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1039 * @param a0 The first extra argument.
1040 */
1041#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1042 do { \
1043 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1044 } while (0)
1045
1046/**
1047 * Calls a FPU assembly implementation taking two visible arguments.
1048 *
1049 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1050 * @param a0 The first extra argument.
1051 * @param a1 The second extra argument.
1052 */
1053#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1054 do { \
1055 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1056 } while (0)
1057
1058/**
1059 * Calls a FPU assembly implementation taking three visible arguments.
1060 *
1061 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1062 * @param a0 The first extra argument.
1063 * @param a1 The second extra argument.
1064 * @param a2 The third extra argument.
1065 */
1066#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1067 do { \
1068 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1069 } while (0)
1070
1071#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1072 do { \
1073 (a_FpuData).FSW = (a_FSW); \
1074 (a_FpuData).r80Result = *(a_pr80Value); \
1075 } while (0)
1076
1077/** Pushes FPU result onto the stack. */
1078#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1079 iemFpuPushResult(pVCpu, &a_FpuData)
1080/** Pushes FPU result onto the stack and sets the FPUDP. */
1081#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1082 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1083
1084/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1085#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1086 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1087
1088/** Stores FPU result in a stack register. */
1089#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1090 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1091/** Stores FPU result in a stack register and pops the stack. */
1092#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1093 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1094/** Stores FPU result in a stack register and sets the FPUDP. */
1095#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1096 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1097/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1098 * stack. */
1099#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1100 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1101
1102/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1103#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1104 iemFpuUpdateOpcodeAndIp(pVCpu)
1105/** Free a stack register (for FFREE and FFREEP). */
1106#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1107 iemFpuStackFree(pVCpu, a_iStReg)
1108/** Increment the FPU stack pointer. */
1109#define IEM_MC_FPU_STACK_INC_TOP() \
1110 iemFpuStackIncTop(pVCpu)
1111/** Decrement the FPU stack pointer. */
1112#define IEM_MC_FPU_STACK_DEC_TOP() \
1113 iemFpuStackDecTop(pVCpu)
1114
1115/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1116#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1117 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1118/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1119#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1120 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1121/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1122#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1123 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1124/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1125#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1126 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1127/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1128 * stack. */
1129#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1130 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1131/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1132#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1133 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1134
1135/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1136#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1137 iemFpuStackUnderflow(pVCpu, a_iStDst)
1138/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1139 * stack. */
1140#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1141 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1142/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1143 * FPUDS. */
1144#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1145 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1146/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1147 * FPUDS. Pops stack. */
1148#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1149 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1150/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1151 * stack twice. */
1152#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1153 iemFpuStackUnderflowThenPopPop(pVCpu)
1154/** Raises a FPU stack underflow exception for an instruction pushing a result
1155 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1156#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1157 iemFpuStackPushUnderflow(pVCpu)
1158/** Raises a FPU stack underflow exception for an instruction pushing a result
1159 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1160#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1161 iemFpuStackPushUnderflowTwo(pVCpu)
1162
1163/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1164 * FPUIP, FPUCS and FOP. */
1165#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1166 iemFpuStackPushOverflow(pVCpu)
1167/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1168 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1169#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1170 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1171/** Prepares for using the FPU state.
1172 * Ensures that we can use the host FPU in the current context (RC+R0.
1173 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1174#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1175/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1176#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1177/** Actualizes the guest FPU state so it can be accessed and modified. */
1178#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1179
1180/** Prepares for using the SSE state.
1181 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1182 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1183#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1184/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1185#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1186/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1187#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1188
1189/** Prepares for using the AVX state.
1190 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1191 * Ensures the guest AVX state in the CPUMCTX is up to date.
1192 * @note This will include the AVX512 state too when support for it is added
1193 * due to the zero extending feature of VEX instruction. */
1194#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1195/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1196#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1197/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1198#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1199
1200/**
1201 * Calls a MMX assembly implementation taking two visible arguments.
1202 *
1203 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1204 * @param a0 The first extra argument.
1205 * @param a1 The second extra argument.
1206 */
1207#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1208 do { \
1209 IEM_MC_PREPARE_FPU_USAGE(); \
1210 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1211 } while (0)
1212
1213/**
1214 * Calls a MMX assembly implementation taking three visible arguments.
1215 *
1216 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1217 * @param a0 The first extra argument.
1218 * @param a1 The second extra argument.
1219 * @param a2 The third extra argument.
1220 */
1221#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1222 do { \
1223 IEM_MC_PREPARE_FPU_USAGE(); \
1224 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1225 } while (0)
1226
1227
1228/**
1229 * Calls a SSE assembly implementation taking two visible arguments.
1230 *
1231 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1232 * @param a0 The first extra argument.
1233 * @param a1 The second extra argument.
1234 */
1235#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1236 do { \
1237 IEM_MC_PREPARE_SSE_USAGE(); \
1238 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1239 } while (0)
1240
1241/**
1242 * Calls a SSE assembly implementation taking three visible arguments.
1243 *
1244 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1245 * @param a0 The first extra argument.
1246 * @param a1 The second extra argument.
1247 * @param a2 The third extra argument.
1248 */
1249#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1250 do { \
1251 IEM_MC_PREPARE_SSE_USAGE(); \
1252 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1253 } while (0)
1254
1255
1256/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1257 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1258#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1259 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1260
1261/**
1262 * Calls a AVX assembly implementation taking two visible arguments.
1263 *
1264 * There is one implicit zero'th argument, a pointer to the extended state.
1265 *
1266 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1267 * @param a1 The first extra argument.
1268 * @param a2 The second extra argument.
1269 */
1270#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1271 do { \
1272 IEM_MC_PREPARE_AVX_USAGE(); \
1273 a_pfnAImpl(pXState, (a1), (a2)); \
1274 } while (0)
1275
1276/**
1277 * Calls a AVX assembly implementation taking three visible arguments.
1278 *
1279 * There is one implicit zero'th argument, a pointer to the extended state.
1280 *
1281 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1282 * @param a1 The first extra argument.
1283 * @param a2 The second extra argument.
1284 * @param a3 The third extra argument.
1285 */
1286#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1287 do { \
1288 IEM_MC_PREPARE_AVX_USAGE(); \
1289 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1290 } while (0)
1291
1292/** @note Not for IOPL or IF testing. */
1293#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1294/** @note Not for IOPL or IF testing. */
1295#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1296/** @note Not for IOPL or IF testing. */
1297#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1298/** @note Not for IOPL or IF testing. */
1299#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1300/** @note Not for IOPL or IF testing. */
1301#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1302 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1303 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1304/** @note Not for IOPL or IF testing. */
1305#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1306 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1307 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1308/** @note Not for IOPL or IF testing. */
1309#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1310 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1311 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1312 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1313/** @note Not for IOPL or IF testing. */
1314#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1315 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1316 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1317 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1318#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1319#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1320#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1321/** @note Not for IOPL or IF testing. */
1322#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1323 if ( pVCpu->cpum.GstCtx.cx != 0 \
1324 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1325/** @note Not for IOPL or IF testing. */
1326#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1327 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1328 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1329/** @note Not for IOPL or IF testing. */
1330#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1331 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1332 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1333/** @note Not for IOPL or IF testing. */
1334#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1335 if ( pVCpu->cpum.GstCtx.cx != 0 \
1336 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1337/** @note Not for IOPL or IF testing. */
1338#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1339 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1340 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1341/** @note Not for IOPL or IF testing. */
1342#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1343 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1344 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1345#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1346#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1347
1348#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1349 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1350#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1351 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1352#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1353 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1354#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1355 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1356#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1357 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1358#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1359 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1360#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1361 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1362#define IEM_MC_IF_FCW_IM() \
1363 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1364
1365#define IEM_MC_ELSE() } else {
1366#define IEM_MC_ENDIF() } do {} while (0)
1367
1368/** @} */
1369
1370#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1371
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