VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 96286

Last change on this file since 96286 was 96247, checked in by vboxsync, 3 years ago

VMM/IEM: Start implementing floating point SSE instructions using addps, added some new infrastructure bits (mostly untested), bugref:9898
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  • Property svn:keywords set to Author Date Id Revision
File size: 78.9 KB
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1/* $Id: IEMMc.h 96247 2022-08-17 09:08:30Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
19#define VMM_INCLUDED_SRC_include_IEMMc_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24
25/** @name "Microcode" macros.
26 *
27 * The idea is that we should be able to use the same code to interpret
28 * instructions as well as recompiler instructions. Thus this obfuscation.
29 *
30 * @{
31 */
32#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
33#define IEM_MC_END() }
34#define IEM_MC_PAUSE() do {} while (0)
35#define IEM_MC_CONTINUE() do {} while (0)
36
37/** Internal macro. */
38#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
39 do \
40 { \
41 VBOXSTRICTRC rcStrict2 = a_Expr; \
42 if (rcStrict2 != VINF_SUCCESS) \
43 return rcStrict2; \
44 } while (0)
45
46
47#define IEM_MC_ADVANCE_RIP() iemRegUpdateRipAndClearRF(pVCpu)
48#define IEM_MC_REL_JMP_S8(a_i8) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
49#define IEM_MC_REL_JMP_S16(a_i16) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
50#define IEM_MC_REL_JMP_S32(a_i32) IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
51#define IEM_MC_SET_RIP_U16(a_u16NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
52#define IEM_MC_SET_RIP_U32(a_u32NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
53#define IEM_MC_SET_RIP_U64(a_u64NewIP) IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
54#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
55#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
56 do { \
57 if (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \
58 return iemRaiseDeviceNotAvailable(pVCpu); \
59 } while (0)
60#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
61 do { \
62 if ((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)) \
63 return iemRaiseDeviceNotAvailable(pVCpu); \
64 } while (0)
65#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
66 do { \
67 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
68 return iemRaiseMathFault(pVCpu); \
69 } while (0)
70#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
71 do { \
72 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
73 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
74 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx2) \
75 return iemRaiseUndefinedOpcode(pVCpu); \
76 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
77 return iemRaiseDeviceNotAvailable(pVCpu); \
78 } while (0)
79#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
80 do { \
81 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
82 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE) \
83 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx) \
84 return iemRaiseUndefinedOpcode(pVCpu); \
85 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
86 return iemRaiseDeviceNotAvailable(pVCpu); \
87 } while (0)
88#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
89 do { \
90 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
91 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
92 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse42) \
93 return iemRaiseUndefinedOpcode(pVCpu); \
94 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
95 return iemRaiseDeviceNotAvailable(pVCpu); \
96 } while (0)
97#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
98 do { \
99 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
100 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
101 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse41) \
102 return iemRaiseUndefinedOpcode(pVCpu); \
103 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
104 return iemRaiseDeviceNotAvailable(pVCpu); \
105 } while (0)
106#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
107 do { \
108 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
109 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
110 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSsse3) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
119 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse3) \
120 return iemRaiseUndefinedOpcode(pVCpu); \
121 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
122 return iemRaiseDeviceNotAvailable(pVCpu); \
123 } while (0)
124#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
125 do { \
126 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
127 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
128 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse2) \
129 return iemRaiseUndefinedOpcode(pVCpu); \
130 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
131 return iemRaiseDeviceNotAvailable(pVCpu); \
132 } while (0)
133#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
134 do { \
135 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
136 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
137 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse) \
138 return iemRaiseUndefinedOpcode(pVCpu); \
139 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
140 return iemRaiseDeviceNotAvailable(pVCpu); \
141 } while (0)
142#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
143 do { \
144 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
145 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fMmx) \
146 return iemRaiseUndefinedOpcode(pVCpu); \
147 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
148 return iemRaiseDeviceNotAvailable(pVCpu); \
149 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
150 return iemRaiseMathFault(pVCpu); \
151 } while (0)
152#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_EX(a_fSupported) \
153 do { \
154 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
155 || !(a_fSupported)) \
156 return iemRaiseUndefinedOpcode(pVCpu); \
157 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
158 return iemRaiseDeviceNotAvailable(pVCpu); \
159 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
160 return iemRaiseMathFault(pVCpu); \
161 } while (0)
162#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT_CHECK_SSE_OR_MMXEXT() \
163 do { \
164 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
165 || ( !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSse \
166 && !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAmdMmxExts) ) \
167 return iemRaiseUndefinedOpcode(pVCpu); \
168 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
169 return iemRaiseDeviceNotAvailable(pVCpu); \
170 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
171 return iemRaiseMathFault(pVCpu); \
172 } while (0)
173#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
174 do { \
175 if (pVCpu->iem.s.uCpl != 0) \
176 return iemRaiseGeneralProtectionFault0(pVCpu); \
177 } while (0)
178#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
179 do { \
180 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
181 else return iemRaiseGeneralProtectionFault0(pVCpu); \
182 } while (0)
183#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
184 do { \
185 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
186 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
187 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
188 return iemRaiseUndefinedOpcode(pVCpu); \
189 } while (0)
190#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
191 do { \
192 if (!IEM_IS_CANONICAL(a_u64Addr)) \
193 return iemRaiseGeneralProtectionFault0(pVCpu); \
194 } while (0)
195#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
196 do { \
197 if (( ((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
198 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
199 { \
200 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
201 return iemRaiseSimdFpException(pVCpu); \
202 else \
203 return iemRaiseUndefinedOpcode(pVCpu); \
204 } \
205 } while (0)
206
207
208#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
209#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
210#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
211#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
212#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
213#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
214#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
215 uint32_t a_Name; \
216 uint32_t *a_pName = &a_Name
217#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
218 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
219
220#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
221#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
222
223#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
224#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
225#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
226#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
227#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
228#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
229#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
230#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
231#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
232#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
233#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
234#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
235#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
236#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
237#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
238#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
239#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
240#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
241 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
242 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
243 } while (0)
244#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
245 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
246 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
247 } while (0)
248#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
249 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
250 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
251 } while (0)
252/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
253#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
254 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
255 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
256 } while (0)
257#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
258 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
259 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
260 } while (0)
261/** @note Not for IOPL or IF testing or modification. */
262#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
263#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
264#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
265#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
266
267#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
268#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
269#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
270#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
271#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
272#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
273#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
274#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
275#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
276#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
277/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
278#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
279 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
280 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
281 } while (0)
282#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
283 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
284 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
285 } while (0)
286#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
287 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
288
289
290#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
291#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
292/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
293 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
294#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
295#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
296/** @note Not for IOPL or IF testing or modification. */
297#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.u
298
299#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
300#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
301#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
302 do { \
303 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
304 *pu32Reg += (a_u32Value); \
305 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
306 } while (0)
307#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
308
309#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
310#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
311#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
312 do { \
313 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
314 *pu32Reg -= (a_u32Value); \
315 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
316 } while (0)
317#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
318#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
319
320#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
321#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
322#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
323#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
324#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
325#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
326#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
327
328#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
329#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
330#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
331#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
332
333#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
334#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
335#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
336
337#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
338#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
339#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
340
341#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
342#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
343#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
344
345#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
346#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
347#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
348
349#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
350
351#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
352
353#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
354#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
355#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
356 do { \
357 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
358 *pu32Reg &= (a_u32Value); \
359 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
360 } while (0)
361#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
362
363#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
364#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
365#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
366 do { \
367 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
368 *pu32Reg |= (a_u32Value); \
369 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
370 } while (0)
371#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
372
373
374/** @note Not for IOPL or IF modification. */
375#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
376/** @note Not for IOPL or IF modification. */
377#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
378/** @note Not for IOPL or IF modification. */
379#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
380
381#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
382
383/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
384#define IEM_MC_FPU_TO_MMX_MODE() do { \
385 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
386 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
387 } while (0)
388
389/** Switches the FPU state from MMX mode (FTW=0xffff). */
390#define IEM_MC_FPU_FROM_MMX_MODE() do { \
391 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
392 } while (0)
393
394#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
395 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
396#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
397 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
398#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
399 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
400 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
401 } while (0)
402#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
403 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
404 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
405 } while (0)
406#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
407 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
408#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
409 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
410#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
411 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
412#define IEM_MC_MODIFIED_MREG(a_iMReg) \
413 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
414#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
415 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
416
417#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
418 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
419 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
420 } while (0)
421#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \
422 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0)
423#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) \
424 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0]; } while (0)
425#define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) \
426 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; } while (0)
427#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
428 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
429 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
430 } while (0)
431#define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \
432 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0)
433#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
434 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
435 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
436 } while (0)
437#define IEM_MC_STORE_XREG_U32(a_iXReg, a_u32Value) \
438 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = (a_u32Value); } while (0)
439#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
440 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
441 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
442 } while (0)
443#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
444 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
445#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
446 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
447#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
448 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
449#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
450 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
451#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
452 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
453#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
454 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
455 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
456 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
457 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
458 } while (0)
459
460#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
461 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
462 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
463 } while (0)
464#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
465 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
466 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
467 } while (0)
468#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
469 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
470 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
471 } while (0)
472#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
473 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
474 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
475 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
476 } while (0)
477#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
478 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
479 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
480 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
481 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
482 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
483 } while (0)
484
485#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
486#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
487 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
488 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
489 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
490 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
491 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
492 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
493 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
494 } while (0)
495#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
496 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
497 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
498 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
499 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
500 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
501 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
502 } while (0)
503#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
504 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
505 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
506 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
507 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
508 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
509 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
510 } while (0)
511#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
512 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
513 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
514 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
515 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
516 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
517 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
518 } while (0)
519
520#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
521 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
522#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
523 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
524#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
525 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
526#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
527 do { uintptr_t const iYRegTmp = (a_iYReg); \
528 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
529 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
530 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
531 } while (0)
532
533#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
534 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
535 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
537 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
538 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
539 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
540 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
541 } while (0)
542#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
543 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
544 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
545 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
546 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
547 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
548 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
549 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
550 } while (0)
551#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
552 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
553 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
554 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
555 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
556 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
557 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
558 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
559 } while (0)
560
561#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
562 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
563 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
564 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
565 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
566 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
567 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
568 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
569 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
570 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
571 } while (0)
572#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
573 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
574 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
575 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
576 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
577 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
578 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
579 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
580 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
581 } while (0)
582#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
583 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
584 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
585 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
586 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
587 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
588 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
589 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
590 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
591 } while (0)
592#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
593 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
594 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
595 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
596 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
597 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
598 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
599 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
600 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
601 } while (0)
602#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
603 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
604 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
605 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
606 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
607 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
609 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
610 } while (0)
611#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
612 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
613 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
614 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
615 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
616 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
617 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
618 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
619 } while (0)
620
621#ifndef IEM_WITH_SETJMP
622# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
623 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
624# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
625 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
626# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
627 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
628#else
629# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
630 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
631# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
632 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
633# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
634 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
635#endif
636
637#ifndef IEM_WITH_SETJMP
638# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
639 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
640# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
641 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
642# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
643 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
644#else
645# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
646 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
647# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
648 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
649# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
650 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
651#endif
652
653#ifndef IEM_WITH_SETJMP
654# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
655 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
656# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
657 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
658# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
659 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
660#else
661# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
662 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
663# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
664 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
665# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
666 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
667#endif
668
669#ifdef SOME_UNUSED_FUNCTION
670# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
671 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
672#endif
673
674#ifndef IEM_WITH_SETJMP
675# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
676 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
677# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
678 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
679# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
680 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
681# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
682 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
683#else
684# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
685 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
686# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
687 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
688# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
689 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
690# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
691 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
692#endif
693
694#ifndef IEM_WITH_SETJMP
695# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
696 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u32, (a_iSeg), (a_GCPtrMem)))
697# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
698 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).au64[0], (a_iSeg), (a_GCPtrMem)))
699# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
700 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
701# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
702 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
703#else
704# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
705 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
706# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
707 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
708# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
709 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
710# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
711 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
712#endif
713
714#ifndef IEM_WITH_SETJMP
715# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
716 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
717# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
718 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
719# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
720 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
721
722# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
724# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
725 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
726# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
727 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
728#else
729# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
730 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
731# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
732 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
733# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
734 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
735
736# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
737 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
738# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
739 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
740# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
741 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
742#endif
743
744#ifndef IEM_WITH_SETJMP
745# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
746 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
747# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
748 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
749# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
750 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
751
752# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
753 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
754# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
755 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
756# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
757 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
758#else
759# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
760 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
761# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
762 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
763# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
764 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
765
766# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
767 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
768# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
769 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
770# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
771 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
772#endif
773
774
775
776#ifndef IEM_WITH_SETJMP
777# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
778 do { \
779 uint8_t u8Tmp; \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
781 (a_u16Dst) = u8Tmp; \
782 } while (0)
783# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
784 do { \
785 uint8_t u8Tmp; \
786 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
787 (a_u32Dst) = u8Tmp; \
788 } while (0)
789# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
790 do { \
791 uint8_t u8Tmp; \
792 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
793 (a_u64Dst) = u8Tmp; \
794 } while (0)
795# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
796 do { \
797 uint16_t u16Tmp; \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
799 (a_u32Dst) = u16Tmp; \
800 } while (0)
801# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
802 do { \
803 uint16_t u16Tmp; \
804 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
805 (a_u64Dst) = u16Tmp; \
806 } while (0)
807# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
808 do { \
809 uint32_t u32Tmp; \
810 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
811 (a_u64Dst) = u32Tmp; \
812 } while (0)
813#else /* IEM_WITH_SETJMP */
814# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
815 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
816# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
817 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
818# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
819 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
820# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
821 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
822# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
823 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
824# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
825 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
826#endif /* IEM_WITH_SETJMP */
827
828#ifndef IEM_WITH_SETJMP
829# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
830 do { \
831 uint8_t u8Tmp; \
832 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
833 (a_u16Dst) = (int8_t)u8Tmp; \
834 } while (0)
835# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
836 do { \
837 uint8_t u8Tmp; \
838 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
839 (a_u32Dst) = (int8_t)u8Tmp; \
840 } while (0)
841# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
842 do { \
843 uint8_t u8Tmp; \
844 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
845 (a_u64Dst) = (int8_t)u8Tmp; \
846 } while (0)
847# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
848 do { \
849 uint16_t u16Tmp; \
850 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
851 (a_u32Dst) = (int16_t)u16Tmp; \
852 } while (0)
853# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
854 do { \
855 uint16_t u16Tmp; \
856 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
857 (a_u64Dst) = (int16_t)u16Tmp; \
858 } while (0)
859# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
860 do { \
861 uint32_t u32Tmp; \
862 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
863 (a_u64Dst) = (int32_t)u32Tmp; \
864 } while (0)
865#else /* IEM_WITH_SETJMP */
866# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
867 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
868# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
869 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
870# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
871 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
872# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
873 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
874# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
875 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
876# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
877 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
878#endif /* IEM_WITH_SETJMP */
879
880#ifndef IEM_WITH_SETJMP
881# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
882 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
883# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
884 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
885# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
886 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
887# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
888 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
889#else
890# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
891 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
892# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
893 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
894# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
895 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
896# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
897 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
898#endif
899
900#ifndef IEM_WITH_SETJMP
901# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
902 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
903# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
904 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
905# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
906 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
907# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
908 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
909#else
910# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
911 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
912# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
913 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
914# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
915 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
916# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
917 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
918#endif
919
920#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
921#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
922#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
923#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
924#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
925#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
926#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
927 do { \
928 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
929 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
930 } while (0)
931#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
932 do { \
933 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
934 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
935 } while (0)
936
937#ifndef IEM_WITH_SETJMP
938# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
939 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
940# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
941 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
942#else
943# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
944 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
945# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
946 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
947#endif
948
949#ifndef IEM_WITH_SETJMP
950# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
951 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
952# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
953 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
954#else
955# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
956 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
957# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
958 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
959#endif
960
961
962#define IEM_MC_PUSH_U16(a_u16Value) \
963 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
964#define IEM_MC_PUSH_U32(a_u32Value) \
965 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
966#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
967 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
968#define IEM_MC_PUSH_U64(a_u64Value) \
969 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
970
971#define IEM_MC_POP_U16(a_pu16Value) \
972 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
973#define IEM_MC_POP_U32(a_pu32Value) \
974 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
975#define IEM_MC_POP_U64(a_pu64Value) \
976 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
977
978/** Maps guest memory for direct or bounce buffered access.
979 * The purpose is to pass it to an operand implementation, thus the a_iArg.
980 * @remarks May return.
981 */
982#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
983 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
984 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
985
986/** Maps guest memory for direct or bounce buffered access.
987 * The purpose is to pass it to an operand implementation, thus the a_iArg.
988 * @remarks May return.
989 */
990#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
991 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
992 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
993
994/** Commits the memory and unmaps the guest memory.
995 * @remarks May return.
996 */
997#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
998 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
999
1000/** Commits the memory and unmaps the guest memory unless the FPU status word
1001 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1002 * that would cause FLD not to store.
1003 *
1004 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1005 * store, while \#P will not.
1006 *
1007 * @remarks May in theory return - for now.
1008 */
1009#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1010 do { \
1011 if ( !(a_u16FSW & X86_FSW_ES) \
1012 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1013 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1014 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1015 } while (0)
1016
1017/** Calculate efficient address from R/M. */
1018#ifndef IEM_WITH_SETJMP
1019# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1020 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1021#else
1022# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1023 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1024#endif
1025
1026#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1027#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1028#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1029#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1030#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1031#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1032#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1033
1034/**
1035 * Defers the rest of the instruction emulation to a C implementation routine
1036 * and returns, only taking the standard parameters.
1037 *
1038 * @param a_pfnCImpl The pointer to the C routine.
1039 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1040 */
1041#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1042
1043/**
1044 * Defers the rest of instruction emulation to a C implementation routine and
1045 * returns, taking one argument in addition to the standard ones.
1046 *
1047 * @param a_pfnCImpl The pointer to the C routine.
1048 * @param a0 The argument.
1049 */
1050#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1051
1052/**
1053 * Defers the rest of the instruction emulation to a C implementation routine
1054 * and returns, taking two arguments in addition to the standard ones.
1055 *
1056 * @param a_pfnCImpl The pointer to the C routine.
1057 * @param a0 The first extra argument.
1058 * @param a1 The second extra argument.
1059 */
1060#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1061
1062/**
1063 * Defers the rest of the instruction emulation to a C implementation routine
1064 * and returns, taking three arguments in addition to the standard ones.
1065 *
1066 * @param a_pfnCImpl The pointer to the C routine.
1067 * @param a0 The first extra argument.
1068 * @param a1 The second extra argument.
1069 * @param a2 The third extra argument.
1070 */
1071#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1072
1073/**
1074 * Defers the rest of the instruction emulation to a C implementation routine
1075 * and returns, taking four arguments in addition to the standard ones.
1076 *
1077 * @param a_pfnCImpl The pointer to the C routine.
1078 * @param a0 The first extra argument.
1079 * @param a1 The second extra argument.
1080 * @param a2 The third extra argument.
1081 * @param a3 The fourth extra argument.
1082 */
1083#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1084
1085/**
1086 * Defers the rest of the instruction emulation to a C implementation routine
1087 * and returns, taking two arguments in addition to the standard ones.
1088 *
1089 * @param a_pfnCImpl The pointer to the C routine.
1090 * @param a0 The first extra argument.
1091 * @param a1 The second extra argument.
1092 * @param a2 The third extra argument.
1093 * @param a3 The fourth extra argument.
1094 * @param a4 The fifth extra argument.
1095 */
1096#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1097
1098/**
1099 * Defers the entire instruction emulation to a C implementation routine and
1100 * returns, only taking the standard parameters.
1101 *
1102 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1103 *
1104 * @param a_pfnCImpl The pointer to the C routine.
1105 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1106 */
1107#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1108
1109/**
1110 * Defers the entire instruction emulation to a C implementation routine and
1111 * returns, taking one argument in addition to the standard ones.
1112 *
1113 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1114 *
1115 * @param a_pfnCImpl The pointer to the C routine.
1116 * @param a0 The argument.
1117 */
1118#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1119
1120/**
1121 * Defers the entire instruction emulation to a C implementation routine and
1122 * returns, taking two arguments in addition to the standard ones.
1123 *
1124 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1125 *
1126 * @param a_pfnCImpl The pointer to the C routine.
1127 * @param a0 The first extra argument.
1128 * @param a1 The second extra argument.
1129 */
1130#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1131
1132/**
1133 * Defers the entire instruction emulation to a C implementation routine and
1134 * returns, taking three arguments in addition to the standard ones.
1135 *
1136 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1137 *
1138 * @param a_pfnCImpl The pointer to the C routine.
1139 * @param a0 The first extra argument.
1140 * @param a1 The second extra argument.
1141 * @param a2 The third extra argument.
1142 */
1143#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1144
1145/**
1146 * Calls a FPU assembly implementation taking one visible argument.
1147 *
1148 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1149 * @param a0 The first extra argument.
1150 */
1151#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1152 do { \
1153 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1154 } while (0)
1155
1156/**
1157 * Calls a FPU assembly implementation taking two visible arguments.
1158 *
1159 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1160 * @param a0 The first extra argument.
1161 * @param a1 The second extra argument.
1162 */
1163#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1164 do { \
1165 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1166 } while (0)
1167
1168/**
1169 * Calls a FPU assembly implementation taking three visible arguments.
1170 *
1171 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1172 * @param a0 The first extra argument.
1173 * @param a1 The second extra argument.
1174 * @param a2 The third extra argument.
1175 */
1176#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1177 do { \
1178 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1179 } while (0)
1180
1181#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1182 do { \
1183 (a_FpuData).FSW = (a_FSW); \
1184 (a_FpuData).r80Result = *(a_pr80Value); \
1185 } while (0)
1186
1187/** Pushes FPU result onto the stack. */
1188#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1189 iemFpuPushResult(pVCpu, &a_FpuData)
1190/** Pushes FPU result onto the stack and sets the FPUDP. */
1191#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1192 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1193
1194/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1195#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1196 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1197
1198/** Stores FPU result in a stack register. */
1199#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1200 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1201/** Stores FPU result in a stack register and pops the stack. */
1202#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1203 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1204/** Stores FPU result in a stack register and sets the FPUDP. */
1205#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1206 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1207/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1208 * stack. */
1209#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1210 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1211
1212/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1213#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1214 iemFpuUpdateOpcodeAndIp(pVCpu)
1215/** Free a stack register (for FFREE and FFREEP). */
1216#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1217 iemFpuStackFree(pVCpu, a_iStReg)
1218/** Increment the FPU stack pointer. */
1219#define IEM_MC_FPU_STACK_INC_TOP() \
1220 iemFpuStackIncTop(pVCpu)
1221/** Decrement the FPU stack pointer. */
1222#define IEM_MC_FPU_STACK_DEC_TOP() \
1223 iemFpuStackDecTop(pVCpu)
1224
1225/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1226#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1227 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1228/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1229#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1230 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1231/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1232#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1233 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1234/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1235#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1236 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1237/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1238 * stack. */
1239#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1240 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1241/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1242#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1243 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1244
1245/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1246#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1247 iemFpuStackUnderflow(pVCpu, a_iStDst)
1248/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1249 * stack. */
1250#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1251 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1252/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1253 * FPUDS. */
1254#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1255 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1256/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1257 * FPUDS. Pops stack. */
1258#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1259 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1260/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1261 * stack twice. */
1262#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1263 iemFpuStackUnderflowThenPopPop(pVCpu)
1264/** Raises a FPU stack underflow exception for an instruction pushing a result
1265 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1266#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1267 iemFpuStackPushUnderflow(pVCpu)
1268/** Raises a FPU stack underflow exception for an instruction pushing a result
1269 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1270#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1271 iemFpuStackPushUnderflowTwo(pVCpu)
1272
1273/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1274 * FPUIP, FPUCS and FOP. */
1275#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1276 iemFpuStackPushOverflow(pVCpu)
1277/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1278 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1279#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1280 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1281/** Prepares for using the FPU state.
1282 * Ensures that we can use the host FPU in the current context (RC+R0.
1283 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1284#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1285/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1286#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1287/** Actualizes the guest FPU state so it can be accessed and modified. */
1288#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1289
1290/** Stores SSE SIMD result in a stack register. */
1291#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1292 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1293/** Prepares for using the SSE state.
1294 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1295 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1296#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1297/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1298#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1299/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1300#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1301
1302/** Prepares for using the AVX state.
1303 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1304 * Ensures the guest AVX state in the CPUMCTX is up to date.
1305 * @note This will include the AVX512 state too when support for it is added
1306 * due to the zero extending feature of VEX instruction. */
1307#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1308/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1309#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1310/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1311#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1312
1313/**
1314 * Calls a MMX assembly implementation taking two visible arguments.
1315 *
1316 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1317 * @param a0 The first extra argument.
1318 * @param a1 The second extra argument.
1319 */
1320#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1321 do { \
1322 IEM_MC_PREPARE_FPU_USAGE(); \
1323 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1324 } while (0)
1325
1326/**
1327 * Calls a MMX assembly implementation taking three visible arguments.
1328 *
1329 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1330 * @param a0 The first extra argument.
1331 * @param a1 The second extra argument.
1332 * @param a2 The third extra argument.
1333 */
1334#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1335 do { \
1336 IEM_MC_PREPARE_FPU_USAGE(); \
1337 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1338 } while (0)
1339
1340
1341/**
1342 * Calls a SSE assembly implementation taking two visible arguments.
1343 *
1344 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1345 * @param a0 The first extra argument.
1346 * @param a1 The second extra argument.
1347 */
1348#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1349 do { \
1350 IEM_MC_PREPARE_SSE_USAGE(); \
1351 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1352 } while (0)
1353
1354/**
1355 * Calls a SSE assembly implementation taking three visible arguments.
1356 *
1357 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1358 * @param a0 The first extra argument.
1359 * @param a1 The second extra argument.
1360 * @param a2 The third extra argument.
1361 */
1362#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1363 do { \
1364 IEM_MC_PREPARE_SSE_USAGE(); \
1365 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1366 } while (0)
1367
1368
1369/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1370 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1371#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1372 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1373
1374/**
1375 * Calls a AVX assembly implementation taking two visible arguments.
1376 *
1377 * There is one implicit zero'th argument, a pointer to the extended state.
1378 *
1379 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1380 * @param a1 The first extra argument.
1381 * @param a2 The second extra argument.
1382 */
1383#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1384 do { \
1385 IEM_MC_PREPARE_AVX_USAGE(); \
1386 a_pfnAImpl(pXState, (a1), (a2)); \
1387 } while (0)
1388
1389/**
1390 * Calls a AVX assembly implementation taking three visible arguments.
1391 *
1392 * There is one implicit zero'th argument, a pointer to the extended state.
1393 *
1394 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1395 * @param a1 The first extra argument.
1396 * @param a2 The second extra argument.
1397 * @param a3 The third extra argument.
1398 */
1399#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1400 do { \
1401 IEM_MC_PREPARE_AVX_USAGE(); \
1402 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1403 } while (0)
1404
1405/** @note Not for IOPL or IF testing. */
1406#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1407/** @note Not for IOPL or IF testing. */
1408#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1409/** @note Not for IOPL or IF testing. */
1410#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1411/** @note Not for IOPL or IF testing. */
1412#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1413/** @note Not for IOPL or IF testing. */
1414#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1415 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1416 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1417/** @note Not for IOPL or IF testing. */
1418#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1419 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1420 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1421/** @note Not for IOPL or IF testing. */
1422#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1423 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1424 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1425 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1426/** @note Not for IOPL or IF testing. */
1427#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1428 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1429 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1430 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1431#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1432#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1433#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1434/** @note Not for IOPL or IF testing. */
1435#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1436 if ( pVCpu->cpum.GstCtx.cx != 0 \
1437 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1438/** @note Not for IOPL or IF testing. */
1439#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1440 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1441 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1442/** @note Not for IOPL or IF testing. */
1443#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1444 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1445 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1446/** @note Not for IOPL or IF testing. */
1447#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1448 if ( pVCpu->cpum.GstCtx.cx != 0 \
1449 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1450/** @note Not for IOPL or IF testing. */
1451#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1452 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1453 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1454/** @note Not for IOPL or IF testing. */
1455#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1456 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1457 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1458#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1459#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1460
1461#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1462 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1463#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1464 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1465#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1466 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1467#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1468 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1469#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1470 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1471#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1472 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1473#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1474 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1475#define IEM_MC_IF_FCW_IM() \
1476 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1477
1478#define IEM_MC_ELSE() } else {
1479#define IEM_MC_ENDIF() } do {} while (0)
1480
1481/** @} */
1482
1483#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1484
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