VirtualBox

source: vbox/trunk/src/VBox/VMM/include/IEMMc.h@ 99331

Last change on this file since 99331 was 99331, checked in by vboxsync, 21 months ago

VMM/IEM: Removed CPUID check from most of the IEM_MC_MAYBE_RAISE_*_RELATED_XCPT macros. bugref:10369
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1/* $Id: IEMMc.h 99331 2023-04-07 00:27:07Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager - IEM_MC_XXX.
4 */
5
6/*
7 * Copyright (C) 2011-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28#ifndef VMM_INCLUDED_SRC_include_IEMMc_h
29#define VMM_INCLUDED_SRC_include_IEMMc_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34
35/** @name "Microcode" macros.
36 *
37 * The idea is that we should be able to use the same code to interpret
38 * instructions as well as recompiler instructions. Thus this obfuscation.
39 *
40 * @{
41 */
42#define IEM_MC_BEGIN(a_cArgs, a_cLocals) {
43#define IEM_MC_END() }
44
45/** Internal macro. */
46#define IEM_MC_RETURN_ON_FAILURE(a_Expr) \
47 do \
48 { \
49 VBOXSTRICTRC rcStrict2 = a_Expr; \
50 if (rcStrict2 != VINF_SUCCESS) \
51 return rcStrict2; \
52 } while (0)
53
54
55/** Advances RIP, finishes the instruction and returns.
56 * This may include raising debug exceptions and such. */
57#define IEM_MC_ADVANCE_RIP_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
58/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
59#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \
60 return iemRegRipRelativeJumpS8AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i8), pVCpu->iem.s.enmEffOpSize)
61/** Sets RIP (may trigger \#GP), finishes the instruction and returns.
62 * @note only usable in 16-bit op size mode. */
63#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) \
64 return iemRegRipRelativeJumpS16AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i16))
65/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
66#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32) \
67 return iemRegRipRelativeJumpS32AndFinishClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu), (a_i32), pVCpu->iem.s.enmEffOpSize)
68/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
69#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP) return iemRegRipJumpU16AndFinishClearningRF((pVCpu), (a_u16NewIP))
70/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
71#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP) return iemRegRipJumpU32AndFinishClearningRF((pVCpu), (a_u32NewIP))
72/** Sets RIP (may trigger \#GP), finishes the instruction and returns. */
73#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP) return iemRegRipJumpU64AndFinishClearningRF((pVCpu), (a_u64NewIP))
74
75#define IEM_MC_RAISE_DIVIDE_ERROR() return iemRaiseDivideError(pVCpu)
76#define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \
77 do { \
78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \
79 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
80 } while (0)
81#define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \
82 do { \
83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) \
84 { } else return iemRaiseDeviceNotAvailable(pVCpu); \
85 } while (0)
86#define IEM_MC_MAYBE_RAISE_FPU_XCPT() \
87 do { \
88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) \
89 { } else return iemRaiseMathFault(pVCpu); \
90 } while (0)
91#define IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() \
92 do { \
93 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
94 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
95 return iemRaiseUndefinedOpcode(pVCpu); \
96 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
97 return iemRaiseDeviceNotAvailable(pVCpu); \
98 } while (0)
99#define IEM_MC_MAYBE_RAISE_AVX2_RELATED_XCPT() \
100 do { \
101 if ( (pVCpu->cpum.GstCtx.aXcr[0] & (XSAVE_C_YMM | XSAVE_C_SSE)) != (XSAVE_C_YMM | XSAVE_C_SSE) \
102 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXSAVE)) \
103 return iemRaiseUndefinedOpcode(pVCpu); \
104 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
105 return iemRaiseDeviceNotAvailable(pVCpu); \
106 } while (0)
107#define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() \
108 do { \
109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
111 return iemRaiseUndefinedOpcode(pVCpu); \
112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
113 return iemRaiseDeviceNotAvailable(pVCpu); \
114 } while (0)
115#define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \
116 do { \
117 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
118 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
119 return iemRaiseUndefinedOpcode(pVCpu); \
120 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
121 return iemRaiseDeviceNotAvailable(pVCpu); \
122 } while (0)
123#define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \
124 do { \
125 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
126 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
127 return iemRaiseUndefinedOpcode(pVCpu); \
128 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
129 return iemRaiseDeviceNotAvailable(pVCpu); \
130 } while (0)
131#define IEM_MC_MAYBE_RAISE_SSE41_RELATED_XCPT() \
132 do { \
133 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
134 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
135 return iemRaiseUndefinedOpcode(pVCpu); \
136 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
137 return iemRaiseDeviceNotAvailable(pVCpu); \
138 } while (0)
139#define IEM_MC_MAYBE_RAISE_SSSE3_RELATED_XCPT() \
140 do { \
141 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
142 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
143 return iemRaiseUndefinedOpcode(pVCpu); \
144 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
145 return iemRaiseDeviceNotAvailable(pVCpu); \
146 } while (0)
147#define IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT() \
148 do { \
149 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
150 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
151 return iemRaiseUndefinedOpcode(pVCpu); \
152 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
153 return iemRaiseDeviceNotAvailable(pVCpu); \
154 } while (0)
155#define IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT() \
156 do { \
157 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
158 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
159 return iemRaiseUndefinedOpcode(pVCpu); \
160 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
161 return iemRaiseDeviceNotAvailable(pVCpu); \
162 } while (0)
163#define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \
164 do { \
165 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
166 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \
167 return iemRaiseUndefinedOpcode(pVCpu); \
168 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
169 return iemRaiseDeviceNotAvailable(pVCpu); \
170 } while (0)
171#define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \
172 do { \
173 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
174 return iemRaiseUndefinedOpcode(pVCpu); \
175 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
176 return iemRaiseDeviceNotAvailable(pVCpu); \
177 if (pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES) \
178 return iemRaiseMathFault(pVCpu); \
179 } while (0)
180#define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \
181 do { \
182 if (pVCpu->iem.s.uCpl != 0) \
183 return iemRaiseGeneralProtectionFault0(pVCpu); \
184 } while (0)
185#define IEM_MC_RAISE_GP0_IF_EFF_ADDR_UNALIGNED(a_EffAddr, a_cbAlign) \
186 do { \
187 if (!((a_EffAddr) & ((a_cbAlign) - 1))) { /* likely */ } \
188 else return iemRaiseGeneralProtectionFault0(pVCpu); \
189 } while (0)
190#define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \
191 do { \
192 if ( pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT \
193 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fFsGsBase \
194 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) \
195 return iemRaiseUndefinedOpcode(pVCpu); \
196 } while (0)
197#define IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(a_u64Addr) \
198 do { \
199 if (!IEM_IS_CANONICAL(a_u64Addr)) \
200 return iemRaiseGeneralProtectionFault0(pVCpu); \
201 } while (0)
202#define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
203 do { \
204 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
205 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) \
206 { \
207 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
208 return iemRaiseSimdFpException(pVCpu); \
209 else \
210 return iemRaiseUndefinedOpcode(pVCpu); \
211 } \
212 } while (0)
213#define IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \
214 do { \
215 if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSXMMEEXCPT)\
216 return iemRaiseSimdFpException(pVCpu); \
217 else \
218 return iemRaiseUndefinedOpcode(pVCpu); \
219 } while (0)
220#define IEM_MC_MAYBE_RAISE_PCLMUL_RELATED_XCPT() \
221 do { \
222 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \
223 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR) \
224 || !IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fPclMul) \
225 return iemRaiseUndefinedOpcode(pVCpu); \
226 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \
227 return iemRaiseDeviceNotAvailable(pVCpu); \
228 } while (0)
229
230
231#define IEM_MC_LOCAL(a_Type, a_Name) a_Type a_Name
232#define IEM_MC_LOCAL_CONST(a_Type, a_Name, a_Value) a_Type const a_Name = (a_Value)
233#define IEM_MC_REF_LOCAL(a_pRefArg, a_Local) (a_pRefArg) = &(a_Local)
234#define IEM_MC_ARG(a_Type, a_Name, a_iArg) a_Type a_Name
235#define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg) a_Type const a_Name = (a_Value)
236#define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg) a_Type const a_Name = &(a_Local)
237#define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
238 uint32_t a_Name; \
239 uint32_t *a_pName = &a_Name
240#define IEM_MC_COMMIT_EFLAGS(a_EFlags) \
241 do { pVCpu->cpum.GstCtx.eflags.u = (a_EFlags); Assert(pVCpu->cpum.GstCtx.eflags.u & X86_EFL_1); } while (0)
242
243#define IEM_MC_ASSIGN(a_VarOrArg, a_CVariableOrConst) (a_VarOrArg) = (a_CVariableOrConst)
244#define IEM_MC_ASSIGN_TO_SMALLER IEM_MC_ASSIGN
245#define IEM_MC_ASSIGN_U8_SX_U64(a_u64VarOrArg, a_u8CVariableOrConst) \
246 (a_u64VarOrArg) = (int8_t)(a_u8CVariableOrConst)
247#define IEM_MC_ASSIGN_U32_SX_U64(a_u64VarOrArg, a_u32CVariableOrConst) \
248 (a_u64VarOrArg) = (int32_t)(a_u32CVariableOrConst)
249
250#define IEM_MC_FETCH_GREG_U8(a_u8Dst, a_iGReg) (a_u8Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
251#define IEM_MC_FETCH_GREG_U8_ZX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
252#define IEM_MC_FETCH_GREG_U8_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
253#define IEM_MC_FETCH_GREG_U8_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU8(pVCpu, (a_iGReg))
254#define IEM_MC_FETCH_GREG_U8_SX_U16(a_u16Dst, a_iGReg) (a_u16Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
255#define IEM_MC_FETCH_GREG_U8_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
256#define IEM_MC_FETCH_GREG_U8_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int8_t)iemGRegFetchU8(pVCpu, (a_iGReg))
257#define IEM_MC_FETCH_GREG_U16(a_u16Dst, a_iGReg) (a_u16Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
258#define IEM_MC_FETCH_GREG_U16_ZX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
259#define IEM_MC_FETCH_GREG_U16_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU16(pVCpu, (a_iGReg))
260#define IEM_MC_FETCH_GREG_U16_SX_U32(a_u32Dst, a_iGReg) (a_u32Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
261#define IEM_MC_FETCH_GREG_U16_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int16_t)iemGRegFetchU16(pVCpu, (a_iGReg))
262#define IEM_MC_FETCH_GREG_U32(a_u32Dst, a_iGReg) (a_u32Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
263#define IEM_MC_FETCH_GREG_U32_ZX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU32(pVCpu, (a_iGReg))
264#define IEM_MC_FETCH_GREG_U32_SX_U64(a_u64Dst, a_iGReg) (a_u64Dst) = (int32_t)iemGRegFetchU32(pVCpu, (a_iGReg))
265#define IEM_MC_FETCH_GREG_U64(a_u64Dst, a_iGReg) (a_u64Dst) = iemGRegFetchU64(pVCpu, (a_iGReg))
266#define IEM_MC_FETCH_GREG_U64_ZX_U64 IEM_MC_FETCH_GREG_U64
267#define IEM_MC_FETCH_SREG_U16(a_u16Dst, a_iSReg) do { \
268 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
269 (a_u16Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
270 } while (0)
271#define IEM_MC_FETCH_SREG_ZX_U32(a_u32Dst, a_iSReg) do { \
272 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
273 (a_u32Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
274 } while (0)
275#define IEM_MC_FETCH_SREG_ZX_U64(a_u64Dst, a_iSReg) do { \
276 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
277 (a_u64Dst) = iemSRegFetchU16(pVCpu, (a_iSReg)); \
278 } while (0)
279/** @todo IEM_MC_FETCH_SREG_BASE_U64 & IEM_MC_FETCH_SREG_BASE_U32 probably aren't worth it... */
280#define IEM_MC_FETCH_SREG_BASE_U64(a_u64Dst, a_iSReg) do { \
281 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
282 (a_u64Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
283 } while (0)
284#define IEM_MC_FETCH_SREG_BASE_U32(a_u32Dst, a_iSReg) do { \
285 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
286 (a_u32Dst) = iemSRegBaseFetchU64(pVCpu, (a_iSReg)); \
287 } while (0)
288/** @note Not for IOPL or IF testing or modification. */
289#define IEM_MC_FETCH_EFLAGS(a_EFlags) (a_EFlags) = pVCpu->cpum.GstCtx.eflags.u
290#define IEM_MC_FETCH_EFLAGS_U8(a_EFlags) (a_EFlags) = (uint8_t)pVCpu->cpum.GstCtx.eflags.u
291#define IEM_MC_FETCH_FSW(a_u16Fsw) (a_u16Fsw) = pVCpu->cpum.GstCtx.XState.x87.FSW
292#define IEM_MC_FETCH_FCW(a_u16Fcw) (a_u16Fcw) = pVCpu->cpum.GstCtx.XState.x87.FCW
293
294#define IEM_MC_STORE_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) = (a_u8Value)
295#define IEM_MC_STORE_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) = (a_u16Value)
296#define IEM_MC_STORE_GREG_U32(a_iGReg, a_u32Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (uint32_t)(a_u32Value) /* clear high bits. */
297#define IEM_MC_STORE_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) = (a_u64Value)
298#define IEM_MC_STORE_GREG_I64(a_iGReg, a_i64Value) *iemGRegRefI64(pVCpu, (a_iGReg)) = (a_i64Value)
299#define IEM_MC_STORE_GREG_U8_CONST IEM_MC_STORE_GREG_U8
300#define IEM_MC_STORE_GREG_U16_CONST IEM_MC_STORE_GREG_U16
301#define IEM_MC_STORE_GREG_U32_CONST IEM_MC_STORE_GREG_U32
302#define IEM_MC_STORE_GREG_U64_CONST IEM_MC_STORE_GREG_U64
303#define IEM_MC_CLEAR_HIGH_GREG_U64(a_iGReg) *iemGRegRefU64(pVCpu, (a_iGReg)) &= UINT32_MAX
304#define IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(a_pu32Dst) do { (a_pu32Dst)[1] = 0; } while (0)
305/** @todo IEM_MC_STORE_SREG_BASE_U64 & IEM_MC_STORE_SREG_BASE_U32 aren't worth it... */
306#define IEM_MC_STORE_SREG_BASE_U64(a_iSReg, a_u64Value) do { \
307 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
308 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (a_u64Value); \
309 } while (0)
310#define IEM_MC_STORE_SREG_BASE_U32(a_iSReg, a_u32Value) do { \
311 IEM_CTX_IMPORT_NORET(pVCpu, CPUMCTX_EXTRN_SREG_FROM_IDX(a_iSReg)); \
312 *iemSRegBaseRefU64(pVCpu, (a_iSReg)) = (uint32_t)(a_u32Value); /* clear high bits. */ \
313 } while (0)
314#define IEM_MC_STORE_FPUREG_R80_SRC_REF(a_iSt, a_pr80Src) \
315 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[a_iSt].r80 = *(a_pr80Src); } while (0)
316
317
318#define IEM_MC_REF_GREG_U8(a_pu8Dst, a_iGReg) (a_pu8Dst) = iemGRegRefU8( pVCpu, (a_iGReg))
319#define IEM_MC_REF_GREG_U16(a_pu16Dst, a_iGReg) (a_pu16Dst) = iemGRegRefU16(pVCpu, (a_iGReg))
320/** @todo User of IEM_MC_REF_GREG_U32 needs to clear the high bits on commit.
321 * Use IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF! */
322#define IEM_MC_REF_GREG_U32(a_pu32Dst, a_iGReg) (a_pu32Dst) = iemGRegRefU32(pVCpu, (a_iGReg))
323#define IEM_MC_REF_GREG_I32(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t *)iemGRegRefU32(pVCpu, (a_iGReg))
324#define IEM_MC_REF_GREG_I32_CONST(a_pi32Dst, a_iGReg) (a_pi32Dst) = (int32_t const *)iemGRegRefU32(pVCpu, (a_iGReg))
325#define IEM_MC_REF_GREG_U64(a_pu64Dst, a_iGReg) (a_pu64Dst) = iemGRegRefU64(pVCpu, (a_iGReg))
326#define IEM_MC_REF_GREG_I64(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t *)iemGRegRefU64(pVCpu, (a_iGReg))
327#define IEM_MC_REF_GREG_I64_CONST(a_pi64Dst, a_iGReg) (a_pi64Dst) = (int64_t const *)iemGRegRefU64(pVCpu, (a_iGReg))
328/** @note Not for IOPL or IF testing or modification.
329 * @note Must preserve any undefined bits, see CPUMX86EFLAGS! */
330#define IEM_MC_REF_EFLAGS(a_pEFlags) (a_pEFlags) = &pVCpu->cpum.GstCtx.eflags.uBoth
331#define IEM_MC_REF_MXCSR(a_pfMxcsr) (a_pfMxcsr) = &pVCpu->cpum.GstCtx.XState.x87.MXCSR
332
333#define IEM_MC_ADD_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) += (a_u8Value)
334#define IEM_MC_ADD_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) += (a_u16Value)
335#define IEM_MC_ADD_GREG_U32(a_iGReg, a_u32Value) \
336 do { \
337 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
338 *pu32Reg += (a_u32Value); \
339 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
340 } while (0)
341#define IEM_MC_ADD_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) += (a_u64Value)
342
343#define IEM_MC_SUB_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) -= (a_u8Value)
344#define IEM_MC_SUB_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) -= (a_u16Value)
345#define IEM_MC_SUB_GREG_U32(a_iGReg, a_u32Value) \
346 do { \
347 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
348 *pu32Reg -= (a_u32Value); \
349 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
350 } while (0)
351#define IEM_MC_SUB_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) -= (a_u64Value)
352#define IEM_MC_SUB_LOCAL_U16(a_u16Value, a_u16Const) do { (a_u16Value) -= a_u16Const; } while (0)
353
354#define IEM_MC_ADD_GREG_U8_TO_LOCAL(a_u8Value, a_iGReg) do { (a_u8Value) += iemGRegFetchU8( pVCpu, (a_iGReg)); } while (0)
355#define IEM_MC_ADD_GREG_U16_TO_LOCAL(a_u16Value, a_iGReg) do { (a_u16Value) += iemGRegFetchU16(pVCpu, (a_iGReg)); } while (0)
356#define IEM_MC_ADD_GREG_U32_TO_LOCAL(a_u32Value, a_iGReg) do { (a_u32Value) += iemGRegFetchU32(pVCpu, (a_iGReg)); } while (0)
357#define IEM_MC_ADD_GREG_U64_TO_LOCAL(a_u64Value, a_iGReg) do { (a_u64Value) += iemGRegFetchU64(pVCpu, (a_iGReg)); } while (0)
358#define IEM_MC_ADD_LOCAL_S16_TO_EFF_ADDR(a_EffAddr, a_i16) do { (a_EffAddr) += (a_i16); } while (0)
359#define IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR(a_EffAddr, a_i32) do { (a_EffAddr) += (a_i32); } while (0)
360#define IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR(a_EffAddr, a_i64) do { (a_EffAddr) += (a_i64); } while (0)
361
362#define IEM_MC_AND_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) &= (a_u8Mask); } while (0)
363#define IEM_MC_AND_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) &= (a_u16Mask); } while (0)
364#define IEM_MC_AND_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
365#define IEM_MC_AND_LOCAL_U64(a_u64Local, a_u64Mask) do { (a_u64Local) &= (a_u64Mask); } while (0)
366
367#define IEM_MC_AND_ARG_U16(a_u16Arg, a_u16Mask) do { (a_u16Arg) &= (a_u16Mask); } while (0)
368#define IEM_MC_AND_ARG_U32(a_u32Arg, a_u32Mask) do { (a_u32Arg) &= (a_u32Mask); } while (0)
369#define IEM_MC_AND_ARG_U64(a_u64Arg, a_u64Mask) do { (a_u64Arg) &= (a_u64Mask); } while (0)
370
371#define IEM_MC_OR_LOCAL_U8(a_u8Local, a_u8Mask) do { (a_u8Local) |= (a_u8Mask); } while (0)
372#define IEM_MC_OR_LOCAL_U16(a_u16Local, a_u16Mask) do { (a_u16Local) |= (a_u16Mask); } while (0)
373#define IEM_MC_OR_LOCAL_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
374
375#define IEM_MC_SAR_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) >>= (a_cShift); } while (0)
376#define IEM_MC_SAR_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) >>= (a_cShift); } while (0)
377#define IEM_MC_SAR_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) >>= (a_cShift); } while (0)
378
379#define IEM_MC_SHR_LOCAL_U8(a_u8Local, a_cShift) do { (a_u8Local) >>= (a_cShift); } while (0)
380
381#define IEM_MC_SHL_LOCAL_S16(a_i16Local, a_cShift) do { (a_i16Local) <<= (a_cShift); } while (0)
382#define IEM_MC_SHL_LOCAL_S32(a_i32Local, a_cShift) do { (a_i32Local) <<= (a_cShift); } while (0)
383#define IEM_MC_SHL_LOCAL_S64(a_i64Local, a_cShift) do { (a_i64Local) <<= (a_cShift); } while (0)
384
385#define IEM_MC_AND_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) &= (a_u32Mask); } while (0)
386
387#define IEM_MC_OR_2LOCS_U32(a_u32Local, a_u32Mask) do { (a_u32Local) |= (a_u32Mask); } while (0)
388
389#define IEM_MC_AND_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) &= (a_u8Value)
390#define IEM_MC_AND_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) &= (a_u16Value)
391#define IEM_MC_AND_GREG_U32(a_iGReg, a_u32Value) \
392 do { \
393 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
394 *pu32Reg &= (a_u32Value); \
395 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
396 } while (0)
397#define IEM_MC_AND_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) &= (a_u64Value)
398
399#define IEM_MC_OR_GREG_U8(a_iGReg, a_u8Value) *iemGRegRefU8( pVCpu, (a_iGReg)) |= (a_u8Value)
400#define IEM_MC_OR_GREG_U16(a_iGReg, a_u16Value) *iemGRegRefU16(pVCpu, (a_iGReg)) |= (a_u16Value)
401#define IEM_MC_OR_GREG_U32(a_iGReg, a_u32Value) \
402 do { \
403 uint32_t *pu32Reg = iemGRegRefU32(pVCpu, (a_iGReg)); \
404 *pu32Reg |= (a_u32Value); \
405 pu32Reg[1] = 0; /* implicitly clear the high bit. */ \
406 } while (0)
407#define IEM_MC_OR_GREG_U64(a_iGReg, a_u64Value) *iemGRegRefU64(pVCpu, (a_iGReg)) |= (a_u64Value)
408
409#define IEM_MC_BSWAP_LOCAL_U16(a_u16Local) (a_u16Local) = RT_BSWAP_U16((a_u16Local));
410#define IEM_MC_BSWAP_LOCAL_U32(a_u32Local) (a_u32Local) = RT_BSWAP_U32((a_u32Local));
411#define IEM_MC_BSWAP_LOCAL_U64(a_u64Local) (a_u64Local) = RT_BSWAP_U64((a_u64Local));
412
413/** @note Not for IOPL or IF modification. */
414#define IEM_MC_SET_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u |= (a_fBit); } while (0)
415/** @note Not for IOPL or IF modification. */
416#define IEM_MC_CLEAR_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u &= ~(a_fBit); } while (0)
417/** @note Not for IOPL or IF modification. */
418#define IEM_MC_FLIP_EFL_BIT(a_fBit) do { pVCpu->cpum.GstCtx.eflags.u ^= (a_fBit); } while (0)
419
420#define IEM_MC_CLEAR_FSW_EX() do { pVCpu->cpum.GstCtx.XState.x87.FSW &= X86_FSW_C_MASK | X86_FSW_TOP_MASK; } while (0)
421
422/** Switches the FPU state to MMX mode (FSW.TOS=0, FTW=0) if necessary. */
423#define IEM_MC_FPU_TO_MMX_MODE() do { \
424 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
425 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
426 pVCpu->cpum.GstCtx.XState.x87.FTW = 0xff; \
427 } while (0)
428
429/** Switches the FPU state from MMX mode (FSW.TOS=0, FTW=0xffff). */
430#define IEM_MC_FPU_FROM_MMX_MODE() do { \
431 iemFpuRotateStackSetTop(&pVCpu->cpum.GstCtx.XState.x87, 0); \
432 pVCpu->cpum.GstCtx.XState.x87.FSW &= ~X86_FSW_TOP_MASK; \
433 pVCpu->cpum.GstCtx.XState.x87.FTW = 0; \
434 } while (0)
435
436#define IEM_MC_FETCH_MREG_U64(a_u64Value, a_iMReg) \
437 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx; } while (0)
438#define IEM_MC_FETCH_MREG_U32(a_u32Value, a_iMReg) \
439 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[0]; } while (0)
440#define IEM_MC_STORE_MREG_U64(a_iMReg, a_u64Value) do { \
441 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (a_u64Value); \
442 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
443 } while (0)
444#define IEM_MC_STORE_MREG_U32_ZX_U64(a_iMReg, a_u32Value) do { \
445 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx = (uint32_t)(a_u32Value); \
446 pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; \
447 } while (0)
448#define IEM_MC_REF_MREG_U64(a_pu64Dst, a_iMReg) /** @todo need to set high word to 0xffff on commit (see IEM_MC_STORE_MREG_U64) */ \
449 (a_pu64Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
450#define IEM_MC_REF_MREG_U64_CONST(a_pu64Dst, a_iMReg) \
451 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
452#define IEM_MC_REF_MREG_U32_CONST(a_pu32Dst, a_iMReg) \
453 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].mmx)
454#define IEM_MC_MODIFIED_MREG(a_iMReg) \
455 do { pVCpu->cpum.GstCtx.XState.x87.aRegs[(a_iMReg)].au32[2] = 0xffff; } while (0)
456#define IEM_MC_MODIFIED_MREG_BY_REF(a_pu64Dst) \
457 do { ((uint32_t *)(a_pu64Dst))[2] = 0xffff; } while (0)
458
459#define IEM_MC_CLEAR_XREG_U32_MASK(a_iXReg, a_bMask) \
460 do { if ((a_bMask) & (1 << 0)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0] = 0; \
461 if ((a_bMask) & (1 << 1)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[1] = 0; \
462 if ((a_bMask) & (1 << 2)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[2] = 0; \
463 if ((a_bMask) & (1 << 3)) pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[3] = 0; \
464 } while (0)
465#define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) \
466 do { (a_u128Value).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
467 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
468 } while (0)
469#define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \
470 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \
471 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \
472 } while (0)
473#define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg, a_iQWord) \
474 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQWord)]; } while (0)
475#define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg, a_iDWord) \
476 do { (a_u32Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDWord)]; } while (0)
477#define IEM_MC_FETCH_XREG_U16(a_u16Value, a_iXReg, a_iWord) \
478 do { (a_u16Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iWord)]; } while (0)
479#define IEM_MC_FETCH_XREG_U8( a_u8Value, a_iXReg, a_iByte) \
480 do { (a_u8Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au16[(a_iByte)]; } while (0)
481#define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) \
482 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u128Value).au64[0]; \
483 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \
484 } while (0)
485#define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \
486 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \
487 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \
488 } while (0)
489#define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \
490 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0)
491#define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \
492 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0)
493#define IEM_MC_STORE_XREG_U64(a_iXReg, a_iQword, a_u64Value) \
494 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_u64Value); } while (0)
495#define IEM_MC_STORE_XREG_U32(a_iXReg, a_iDword, a_u32Value) \
496 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_u32Value); } while (0)
497#define IEM_MC_STORE_XREG_U16(a_iXReg, a_iWord, a_u16Value) \
498 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iWord)] = (a_u16Value); } while (0)
499#define IEM_MC_STORE_XREG_U8(a_iXReg, a_iByte, a_u8Value) \
500 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iByte)] = (a_u8Value); } while (0)
501
502#define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) \
503 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); \
504 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
505 } while (0)
506
507#define IEM_MC_STORE_XREG_U32_U128(a_iXReg, a_iDwDst, a_u128Value, a_iDwSrc) \
508 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDwDst)] = (a_u128Value).au32[(a_iDwSrc)]; } while (0)
509#define IEM_MC_STORE_XREG_R32(a_iXReg, a_r32Value) \
510 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0] = (a_r32Value); } while (0)
511#define IEM_MC_STORE_XREG_R64(a_iXReg, a_r64Value) \
512 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0] = (a_r64Value); } while (0)
513#define IEM_MC_STORE_XREG_U32_ZX_U128(a_iXReg, a_u32Value) \
514 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (uint32_t)(a_u32Value); \
515 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = 0; \
516 } while (0)
517#define IEM_MC_STORE_XREG_HI_U64(a_iXReg, a_u64Value) \
518 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u64Value); } while (0)
519#define IEM_MC_REF_XREG_U128(a_pu128Dst, a_iXReg) \
520 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
521#define IEM_MC_REF_XREG_U128_CONST(a_pu128Dst, a_iXReg) \
522 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].uXmm)
523#define IEM_MC_REF_XREG_XMM_CONST(a_pXmmDst, a_iXReg) \
524 (a_pXmmDst) = (&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)])
525#define IEM_MC_REF_XREG_U32_CONST(a_pu32Dst, a_iXReg) \
526 (a_pu32Dst) = ((uint32_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[0])
527#define IEM_MC_REF_XREG_U64_CONST(a_pu64Dst, a_iXReg) \
528 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0])
529#define IEM_MC_REF_XREG_R32_CONST(a_pr32Dst, a_iXReg) \
530 (a_pr32Dst) = ((RTFLOAT32U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar32[0])
531#define IEM_MC_REF_XREG_R64_CONST(a_pr64Dst, a_iXReg) \
532 (a_pr64Dst) = ((RTFLOAT64U const *)&pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].ar64[0])
533#define IEM_MC_COPY_XREG_U128(a_iXRegDst, a_iXRegSrc) \
534 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[0] \
535 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[0]; \
536 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegDst)].au64[1] \
537 = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXRegSrc)].au64[1]; \
538 } while (0)
539
540#define IEM_MC_FETCH_YREG_U32(a_u32Dst, a_iYRegSrc) \
541 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
542 (a_u32Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au32[0]; \
543 } while (0)
544#define IEM_MC_FETCH_YREG_U64(a_u64Dst, a_iYRegSrc) \
545 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
546 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
547 } while (0)
548#define IEM_MC_FETCH_YREG_2ND_U64(a_u64Dst, a_iYRegSrc) \
549 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
550 (a_u64Dst) = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
551 } while (0)
552#define IEM_MC_FETCH_YREG_U128(a_u128Dst, a_iYRegSrc) \
553 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
554 (a_u128Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
555 (a_u128Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
556 } while (0)
557#define IEM_MC_FETCH_YREG_U256(a_u256Dst, a_iYRegSrc) \
558 do { uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
559 (a_u256Dst).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
560 (a_u256Dst).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
561 (a_u256Dst).au64[2] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
562 (a_u256Dst).au64[3] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
563 } while (0)
564
565#define IEM_MC_INT_CLEAR_ZMM_256_UP(a_iXRegDst) do { /* For AVX512 and AVX1024 support. */ } while (0)
566#define IEM_MC_STORE_YREG_U32_ZX_VLMAX(a_iYRegDst, a_u32Src) \
567 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
568 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = (a_u32Src); \
569 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = 0; \
570 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
571 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
572 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
573 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
574 } while (0)
575#define IEM_MC_STORE_YREG_U64_ZX_VLMAX(a_iYRegDst, a_u64Src) \
576 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
577 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Src); \
578 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
579 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
580 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
581 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
582 } while (0)
583#define IEM_MC_STORE_YREG_U128_ZX_VLMAX(a_iYRegDst, a_u128Src) \
584 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
585 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u128Src).au64[0]; \
586 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u128Src).au64[1]; \
587 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
588 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
589 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
590 } while (0)
591#define IEM_MC_STORE_YREG_U256_ZX_VLMAX(a_iYRegDst, a_u256Src) \
592 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
593 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u256Src).au64[0]; \
594 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u256Src).au64[1]; \
595 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = (a_u256Src).au64[2]; \
596 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = (a_u256Src).au64[3]; \
597 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
598 } while (0)
599
600#define IEM_MC_REF_YREG_U128(a_pu128Dst, a_iYReg) \
601 (a_pu128Dst) = (&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
602#define IEM_MC_REF_YREG_U128_CONST(a_pu128Dst, a_iYReg) \
603 (a_pu128Dst) = ((PCRTUINT128U)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].uXmm)
604#define IEM_MC_REF_YREG_U64_CONST(a_pu64Dst, a_iYReg) \
605 (a_pu64Dst) = ((uint64_t const *)&pVCpu->cpum.GstCtx.XState.x87.aYMM[(a_iYReg)].au64[0])
606#define IEM_MC_CLEAR_YREG_128_UP(a_iYReg) \
607 do { uintptr_t const iYRegTmp = (a_iYReg); \
608 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[0] = 0; \
609 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegTmp].au64[1] = 0; \
610 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegTmp); \
611 } while (0)
612
613#define IEM_MC_COPY_YREG_U256_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
614 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
615 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
616 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
617 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
618 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[0]; \
619 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegSrcTmp].au64[1]; \
620 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
621 } while (0)
622#define IEM_MC_COPY_YREG_U128_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
623 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
624 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
625 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
626 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[1]; \
627 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
628 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
629 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
630 } while (0)
631#define IEM_MC_COPY_YREG_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc) \
632 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
633 uintptr_t const iYRegSrcTmp = (a_iYRegSrc); \
634 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcTmp].au64[0]; \
635 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = 0; \
636 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
637 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
638 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
639 } while (0)
640
641#define IEM_MC_MERGE_YREG_U32_U96_ZX_VLMAX(a_iYRegDst, a_iYRegSrc32, a_iYRegSrcHx) \
642 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
643 uintptr_t const iYRegSrc32Tmp = (a_iYRegSrc32); \
644 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
645 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc32Tmp].au32[0]; \
646 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au32[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au32[1]; \
647 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
648 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
649 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
650 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
651 } while (0)
652#define IEM_MC_MERGE_YREG_U64_U64_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) \
653 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
654 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
655 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
656 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
657 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
658 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
659 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
660 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
661 } while (0)
662#define IEM_MC_MERGE_YREG_U64LO_U64LO_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
663 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
664 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
665 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
666 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[0]; \
667 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
668 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
669 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
670 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
671 } while (0)
672#define IEM_MC_MERGE_YREG_U64HI_U64HI_ZX_VLMAX(a_iYRegDst, a_iYRegSrc64, a_iYRegSrcHx) /* for vmovhlps */ \
673 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
674 uintptr_t const iYRegSrc64Tmp = (a_iYRegSrc64); \
675 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
676 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrc64Tmp].au64[1]; \
677 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
678 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
679 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
680 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
681 } while (0)
682#define IEM_MC_MERGE_YREG_U64LO_U64LOCAL_ZX_VLMAX(a_iYRegDst, a_iYRegSrcHx, a_u64Local) \
683 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
684 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
685 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[0]; \
686 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = (a_u64Local); \
687 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
688 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
689 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
690 } while (0)
691#define IEM_MC_MERGE_YREG_U64LOCAL_U64HI_ZX_VLMAX(a_iYRegDst, a_u64Local, a_iYRegSrcHx) \
692 do { uintptr_t const iYRegDstTmp = (a_iYRegDst); \
693 uintptr_t const iYRegSrcHxTmp = (a_iYRegSrcHx); \
694 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[0] = (a_u64Local); \
695 pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegDstTmp].au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[iYRegSrcHxTmp].au64[1]; \
696 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[0] = 0; \
697 pVCpu->cpum.GstCtx.XState.u.YmmHi.aYmmHi[iYRegDstTmp].au64[1] = 0; \
698 IEM_MC_INT_CLEAR_ZMM_256_UP(iYRegDstTmp); \
699 } while (0)
700
701#ifndef IEM_WITH_SETJMP
702# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
703 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem)))
704# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
705 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem16)))
706# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
707 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &(a_u8Dst), (a_iSeg), (a_GCPtrMem32)))
708#else
709# define IEM_MC_FETCH_MEM_U8(a_u8Dst, a_iSeg, a_GCPtrMem) \
710 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
711# define IEM_MC_FETCH_MEM16_U8(a_u8Dst, a_iSeg, a_GCPtrMem16) \
712 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem16)))
713# define IEM_MC_FETCH_MEM32_U8(a_u8Dst, a_iSeg, a_GCPtrMem32) \
714 ((a_u8Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem32)))
715#endif
716
717#ifndef IEM_WITH_SETJMP
718# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
719 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem)))
720# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
721 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &(a_u16Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
722# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
723 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, (uint16_t *)&(a_i16Dst), (a_iSeg), (a_GCPtrMem)))
724#else
725# define IEM_MC_FETCH_MEM_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
726 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
727# define IEM_MC_FETCH_MEM_U16_DISP(a_u16Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
728 ((a_u16Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
729# define IEM_MC_FETCH_MEM_I16(a_i16Dst, a_iSeg, a_GCPtrMem) \
730 ((a_i16Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
731#endif
732
733#ifndef IEM_WITH_SETJMP
734# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
735 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem)))
736# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
737 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_u32Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
738# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
739 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, (uint32_t *)&(a_i32Dst), (a_iSeg), (a_GCPtrMem)))
740#else
741# define IEM_MC_FETCH_MEM_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
742 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
743# define IEM_MC_FETCH_MEM_U32_DISP(a_u32Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
744 ((a_u32Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
745# define IEM_MC_FETCH_MEM_I32(a_i32Dst, a_iSeg, a_GCPtrMem) \
746 ((a_i32Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
747#endif
748
749#ifdef SOME_UNUSED_FUNCTION
750# define IEM_MC_FETCH_MEM_S32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
751 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataS32SxU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
752#endif
753
754#ifndef IEM_WITH_SETJMP
755# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
756 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
757# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
758 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
759# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
760 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64AlignedU128(pVCpu, &(a_u64Dst), (a_iSeg), (a_GCPtrMem)))
761# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
762 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, (uint64_t *)&(a_i64Dst), (a_iSeg), (a_GCPtrMem)))
763#else
764# define IEM_MC_FETCH_MEM_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
765 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
766# define IEM_MC_FETCH_MEM_U64_DISP(a_u64Dst, a_iSeg, a_GCPtrMem, a_offDisp) \
767 ((a_u64Dst) = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem) + (a_offDisp)))
768# define IEM_MC_FETCH_MEM_U64_ALIGN_U128(a_u64Dst, a_iSeg, a_GCPtrMem) \
769 ((a_u64Dst) = iemMemFetchDataU64AlignedU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
770# define IEM_MC_FETCH_MEM_I64(a_i64Dst, a_iSeg, a_GCPtrMem) \
771 ((a_i64Dst) = (int64_t)iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
772#endif
773
774#ifndef IEM_WITH_SETJMP
775# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
776 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_r32Dst).u, (a_iSeg), (a_GCPtrMem)))
777# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
778 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_r64Dst).u, (a_iSeg), (a_GCPtrMem)))
779# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
780 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataR80(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem)))
781# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
782 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataD80(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem)))
783#else
784# define IEM_MC_FETCH_MEM_R32(a_r32Dst, a_iSeg, a_GCPtrMem) \
785 ((a_r32Dst).u = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
786# define IEM_MC_FETCH_MEM_R64(a_r64Dst, a_iSeg, a_GCPtrMem) \
787 ((a_r64Dst).u = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
788# define IEM_MC_FETCH_MEM_R80(a_r80Dst, a_iSeg, a_GCPtrMem) \
789 iemMemFetchDataR80Jmp(pVCpu, &(a_r80Dst), (a_iSeg), (a_GCPtrMem))
790# define IEM_MC_FETCH_MEM_D80(a_d80Dst, a_iSeg, a_GCPtrMem) \
791 iemMemFetchDataD80Jmp(pVCpu, &(a_d80Dst), (a_iSeg), (a_GCPtrMem))
792#endif
793
794#ifndef IEM_WITH_SETJMP
795# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
796 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
797# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
798 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
799# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
800 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem)))
801
802# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
803 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
804# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
805 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
806# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
807 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU128AlignedSse(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem)))
808# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
809 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &(a_XmmDst).au32[(a_iDWord)], (a_iSeg), (a_GCPtrMem)))
810# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
811 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU64(pVCpu, &(a_XmmDst).au64[(a_iQWord)], (a_iSeg), (a_GCPtrMem)))
812#else
813# define IEM_MC_FETCH_MEM_U128(a_u128Dst, a_iSeg, a_GCPtrMem) \
814 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
815# define IEM_MC_FETCH_MEM_U128_NO_AC(a_u128Dst, a_iSeg, a_GCPtrMem) \
816 iemMemFetchDataU128Jmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
817# define IEM_MC_FETCH_MEM_U128_ALIGN_SSE(a_u128Dst, a_iSeg, a_GCPtrMem) \
818 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_u128Dst), (a_iSeg), (a_GCPtrMem))
819
820# define IEM_MC_FETCH_MEM_XMM(a_XmmDst, a_iSeg, a_GCPtrMem) \
821 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
822# define IEM_MC_FETCH_MEM_XMM_NO_AC(a_XmmDst, a_iSeg, a_GCPtrMem) \
823 iemMemFetchDataU128Jmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
824# define IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(a_XmmDst, a_iSeg, a_GCPtrMem) \
825 iemMemFetchDataU128AlignedSseJmp(pVCpu, &(a_XmmDst).uXmm, (a_iSeg), (a_GCPtrMem))
826# define IEM_MC_FETCH_MEM_XMM_U32(a_XmmDst, a_iDWord, a_iSeg, a_GCPtrMem) \
827 (a_XmmDst).au32[(a_iDWord)] = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
828# define IEM_MC_FETCH_MEM_XMM_U64(a_XmmDst, a_iQWord, a_iSeg, a_GCPtrMem) \
829 (a_XmmDst).au64[(a_iQWord)] = iemMemFetchDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem))
830#endif
831
832#ifndef IEM_WITH_SETJMP
833# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
834 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
835# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
836 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
837# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
838 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem)))
839
840# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
841 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
842# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
843 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
844# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
845 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU256AlignedSse(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem)))
846#else
847# define IEM_MC_FETCH_MEM_U256(a_u256Dst, a_iSeg, a_GCPtrMem) \
848 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
849# define IEM_MC_FETCH_MEM_U256_NO_AC(a_u256Dst, a_iSeg, a_GCPtrMem) \
850 iemMemFetchDataU256Jmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
851# define IEM_MC_FETCH_MEM_U256_ALIGN_AVX(a_u256Dst, a_iSeg, a_GCPtrMem) \
852 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_u256Dst), (a_iSeg), (a_GCPtrMem))
853
854# define IEM_MC_FETCH_MEM_YMM(a_YmmDst, a_iSeg, a_GCPtrMem) \
855 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
856# define IEM_MC_FETCH_MEM_YMM_NO_AC(a_YmmDst, a_iSeg, a_GCPtrMem) \
857 iemMemFetchDataU256Jmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
858# define IEM_MC_FETCH_MEM_YMM_ALIGN_AVX(a_YmmDst, a_iSeg, a_GCPtrMem) \
859 iemMemFetchDataU256AlignedSseJmp(pVCpu, &(a_YmmDst).ymm, (a_iSeg), (a_GCPtrMem))
860#endif
861
862
863
864#ifndef IEM_WITH_SETJMP
865# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
866 do { \
867 uint8_t u8Tmp; \
868 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
869 (a_u16Dst) = u8Tmp; \
870 } while (0)
871# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
872 do { \
873 uint8_t u8Tmp; \
874 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
875 (a_u32Dst) = u8Tmp; \
876 } while (0)
877# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
878 do { \
879 uint8_t u8Tmp; \
880 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
881 (a_u64Dst) = u8Tmp; \
882 } while (0)
883# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
884 do { \
885 uint16_t u16Tmp; \
886 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
887 (a_u32Dst) = u16Tmp; \
888 } while (0)
889# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
890 do { \
891 uint16_t u16Tmp; \
892 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
893 (a_u64Dst) = u16Tmp; \
894 } while (0)
895# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
896 do { \
897 uint32_t u32Tmp; \
898 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
899 (a_u64Dst) = u32Tmp; \
900 } while (0)
901#else /* IEM_WITH_SETJMP */
902# define IEM_MC_FETCH_MEM_U8_ZX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
903 ((a_u16Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
904# define IEM_MC_FETCH_MEM_U8_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
905 ((a_u32Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
906# define IEM_MC_FETCH_MEM_U8_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
907 ((a_u64Dst) = iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
908# define IEM_MC_FETCH_MEM_U16_ZX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
909 ((a_u32Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
910# define IEM_MC_FETCH_MEM_U16_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
911 ((a_u64Dst) = iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
912# define IEM_MC_FETCH_MEM_U32_ZX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
913 ((a_u64Dst) = iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
914#endif /* IEM_WITH_SETJMP */
915
916#ifndef IEM_WITH_SETJMP
917# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
918 do { \
919 uint8_t u8Tmp; \
920 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
921 (a_u16Dst) = (int8_t)u8Tmp; \
922 } while (0)
923# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
924 do { \
925 uint8_t u8Tmp; \
926 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
927 (a_u32Dst) = (int8_t)u8Tmp; \
928 } while (0)
929# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
930 do { \
931 uint8_t u8Tmp; \
932 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU8(pVCpu, &u8Tmp, (a_iSeg), (a_GCPtrMem))); \
933 (a_u64Dst) = (int8_t)u8Tmp; \
934 } while (0)
935# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
936 do { \
937 uint16_t u16Tmp; \
938 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
939 (a_u32Dst) = (int16_t)u16Tmp; \
940 } while (0)
941# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
942 do { \
943 uint16_t u16Tmp; \
944 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU16(pVCpu, &u16Tmp, (a_iSeg), (a_GCPtrMem))); \
945 (a_u64Dst) = (int16_t)u16Tmp; \
946 } while (0)
947# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
948 do { \
949 uint32_t u32Tmp; \
950 IEM_MC_RETURN_ON_FAILURE(iemMemFetchDataU32(pVCpu, &u32Tmp, (a_iSeg), (a_GCPtrMem))); \
951 (a_u64Dst) = (int32_t)u32Tmp; \
952 } while (0)
953#else /* IEM_WITH_SETJMP */
954# define IEM_MC_FETCH_MEM_U8_SX_U16(a_u16Dst, a_iSeg, a_GCPtrMem) \
955 ((a_u16Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
956# define IEM_MC_FETCH_MEM_U8_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
957 ((a_u32Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
958# define IEM_MC_FETCH_MEM_U8_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
959 ((a_u64Dst) = (int8_t)iemMemFetchDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
960# define IEM_MC_FETCH_MEM_U16_SX_U32(a_u32Dst, a_iSeg, a_GCPtrMem) \
961 ((a_u32Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
962# define IEM_MC_FETCH_MEM_U16_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
963 ((a_u64Dst) = (int16_t)iemMemFetchDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
964# define IEM_MC_FETCH_MEM_U32_SX_U64(a_u64Dst, a_iSeg, a_GCPtrMem) \
965 ((a_u64Dst) = (int32_t)iemMemFetchDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem)))
966#endif /* IEM_WITH_SETJMP */
967
968#ifndef IEM_WITH_SETJMP
969# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
970 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value)))
971# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
972 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value)))
973# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
974 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value)))
975# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
976 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value)))
977#else
978# define IEM_MC_STORE_MEM_U8(a_iSeg, a_GCPtrMem, a_u8Value) \
979 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8Value))
980# define IEM_MC_STORE_MEM_U16(a_iSeg, a_GCPtrMem, a_u16Value) \
981 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16Value))
982# define IEM_MC_STORE_MEM_U32(a_iSeg, a_GCPtrMem, a_u32Value) \
983 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32Value))
984# define IEM_MC_STORE_MEM_U64(a_iSeg, a_GCPtrMem, a_u64Value) \
985 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64Value))
986#endif
987
988#ifndef IEM_WITH_SETJMP
989# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
990 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU8(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C)))
991# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
992 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU16(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C)))
993# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
994 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU32(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C)))
995# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
996 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU64(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C)))
997#else
998# define IEM_MC_STORE_MEM_U8_CONST(a_iSeg, a_GCPtrMem, a_u8C) \
999 iemMemStoreDataU8Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u8C))
1000# define IEM_MC_STORE_MEM_U16_CONST(a_iSeg, a_GCPtrMem, a_u16C) \
1001 iemMemStoreDataU16Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u16C))
1002# define IEM_MC_STORE_MEM_U32_CONST(a_iSeg, a_GCPtrMem, a_u32C) \
1003 iemMemStoreDataU32Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u32C))
1004# define IEM_MC_STORE_MEM_U64_CONST(a_iSeg, a_GCPtrMem, a_u64C) \
1005 iemMemStoreDataU64Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u64C))
1006#endif
1007
1008#define IEM_MC_STORE_MEM_I8_CONST_BY_REF( a_pi8Dst, a_i8C) *(a_pi8Dst) = (a_i8C)
1009#define IEM_MC_STORE_MEM_I16_CONST_BY_REF(a_pi16Dst, a_i16C) *(a_pi16Dst) = (a_i16C)
1010#define IEM_MC_STORE_MEM_I32_CONST_BY_REF(a_pi32Dst, a_i32C) *(a_pi32Dst) = (a_i32C)
1011#define IEM_MC_STORE_MEM_I64_CONST_BY_REF(a_pi64Dst, a_i64C) *(a_pi64Dst) = (a_i64C)
1012#define IEM_MC_STORE_MEM_NEG_QNAN_R32_BY_REF(a_pr32Dst) (a_pr32Dst)->u = UINT32_C(0xffc00000)
1013#define IEM_MC_STORE_MEM_NEG_QNAN_R64_BY_REF(a_pr64Dst) (a_pr64Dst)->u = UINT64_C(0xfff8000000000000)
1014#define IEM_MC_STORE_MEM_NEG_QNAN_R80_BY_REF(a_pr80Dst) \
1015 do { \
1016 (a_pr80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1017 (a_pr80Dst)->au16[4] = UINT16_C(0xffff); \
1018 } while (0)
1019#define IEM_MC_STORE_MEM_INDEF_D80_BY_REF(a_pd80Dst) \
1020 do { \
1021 (a_pd80Dst)->au64[0] = UINT64_C(0xc000000000000000); \
1022 (a_pd80Dst)->au16[4] = UINT16_C(0xffff); \
1023 } while (0)
1024
1025#ifndef IEM_WITH_SETJMP
1026# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1027 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1028# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1029 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU128AlignedSse(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value)))
1030#else
1031# define IEM_MC_STORE_MEM_U128(a_iSeg, a_GCPtrMem, a_u128Value) \
1032 iemMemStoreDataU128Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1033# define IEM_MC_STORE_MEM_U128_ALIGN_SSE(a_iSeg, a_GCPtrMem, a_u128Value) \
1034 iemMemStoreDataU128AlignedSseJmp(pVCpu, (a_iSeg), (a_GCPtrMem), (a_u128Value))
1035#endif
1036
1037#ifndef IEM_WITH_SETJMP
1038# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1039 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1040# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1041 IEM_MC_RETURN_ON_FAILURE(iemMemStoreDataU256AlignedAvx(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value)))
1042#else
1043# define IEM_MC_STORE_MEM_U256(a_iSeg, a_GCPtrMem, a_u256Value) \
1044 iemMemStoreDataU256Jmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1045# define IEM_MC_STORE_MEM_U256_ALIGN_AVX(a_iSeg, a_GCPtrMem, a_u256Value) \
1046 iemMemStoreDataU256AlignedAvxJmp(pVCpu, (a_iSeg), (a_GCPtrMem), &(a_u256Value))
1047#endif
1048
1049
1050#define IEM_MC_PUSH_U16(a_u16Value) \
1051 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU16(pVCpu, (a_u16Value)))
1052#define IEM_MC_PUSH_U32(a_u32Value) \
1053 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32(pVCpu, (a_u32Value)))
1054#define IEM_MC_PUSH_U32_SREG(a_u32Value) \
1055 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU32SReg(pVCpu, (a_u32Value)))
1056#define IEM_MC_PUSH_U64(a_u64Value) \
1057 IEM_MC_RETURN_ON_FAILURE(iemMemStackPushU64(pVCpu, (a_u64Value)))
1058
1059#define IEM_MC_POP_U16(a_pu16Value) \
1060 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU16(pVCpu, (a_pu16Value)))
1061#define IEM_MC_POP_U32(a_pu32Value) \
1062 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU32(pVCpu, (a_pu32Value)))
1063#define IEM_MC_POP_U64(a_pu64Value) \
1064 IEM_MC_RETURN_ON_FAILURE(iemMemStackPopU64(pVCpu, (a_pu64Value)))
1065
1066/** Maps guest memory for direct or bounce buffered access.
1067 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1068 * @remarks May return.
1069 */
1070#define IEM_MC_MEM_MAP(a_pMem, a_fAccess, a_iSeg, a_GCPtrMem, a_iArg) \
1071 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pMem), sizeof(*(a_pMem)), (a_iSeg), \
1072 (a_GCPtrMem), (a_fAccess), sizeof(*(a_pMem)) - 1))
1073
1074/** Maps guest memory for direct or bounce buffered access.
1075 * The purpose is to pass it to an operand implementation, thus the a_iArg.
1076 * @remarks May return.
1077 */
1078#define IEM_MC_MEM_MAP_EX(a_pvMem, a_fAccess, a_cbMem, a_iSeg, a_GCPtrMem, a_cbAlign, a_iArg) \
1079 IEM_MC_RETURN_ON_FAILURE(iemMemMap(pVCpu, (void **)&(a_pvMem), (a_cbMem), (a_iSeg), \
1080 (a_GCPtrMem), (a_fAccess), (a_cbAlign)))
1081
1082/** Commits the memory and unmaps the guest memory.
1083 * @remarks May return.
1084 */
1085#define IEM_MC_MEM_COMMIT_AND_UNMAP(a_pvMem, a_fAccess) \
1086 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess)))
1087
1088/** Commits the memory and unmaps the guest memory unless the FPU status word
1089 * indicates (@a a_u16FSW) and FPU control word indicates a pending exception
1090 * that would cause FLD not to store.
1091 *
1092 * The current understanding is that \#O, \#U, \#IA and \#IS will prevent a
1093 * store, while \#P will not.
1094 *
1095 * @remarks May in theory return - for now.
1096 */
1097#define IEM_MC_MEM_COMMIT_AND_UNMAP_FOR_FPU_STORE(a_pvMem, a_fAccess, a_u16FSW) \
1098 do { \
1099 if ( !(a_u16FSW & X86_FSW_ES) \
1100 || !( (a_u16FSW & (X86_FSW_UE | X86_FSW_OE | X86_FSW_IE)) \
1101 & ~(pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_MASK_ALL) ) ) \
1102 IEM_MC_RETURN_ON_FAILURE(iemMemCommitAndUnmap(pVCpu, (a_pvMem), (a_fAccess))); \
1103 } while (0)
1104
1105/** Calculate efficient address from R/M. */
1106#ifndef IEM_WITH_SETJMP
1107# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1108 IEM_MC_RETURN_ON_FAILURE(iemOpHlpCalcRmEffAddr(pVCpu, (bRm), (cbImm), &(a_GCPtrEff)))
1109#else
1110# define IEM_MC_CALC_RM_EFF_ADDR(a_GCPtrEff, bRm, cbImm) \
1111 ((a_GCPtrEff) = iemOpHlpCalcRmEffAddrJmp(pVCpu, (bRm), (cbImm)))
1112#endif
1113
1114#define IEM_MC_CALL_VOID_AIMPL_0(a_pfn) (a_pfn)()
1115#define IEM_MC_CALL_VOID_AIMPL_1(a_pfn, a0) (a_pfn)((a0))
1116#define IEM_MC_CALL_VOID_AIMPL_2(a_pfn, a0, a1) (a_pfn)((a0), (a1))
1117#define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2) (a_pfn)((a0), (a1), (a2))
1118#define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) (a_pfn)((a0), (a1), (a2), (a3))
1119#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) (a_rc) = (a_pfn)((a0), (a1), (a2))
1120#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
1121
1122/**
1123 * Defers the rest of the instruction emulation to a C implementation routine
1124 * and returns, only taking the standard parameters.
1125 *
1126 * @param a_pfnCImpl The pointer to the C routine.
1127 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1128 */
1129#define IEM_MC_CALL_CIMPL_0(a_pfnCImpl) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1130
1131/**
1132 * Defers the rest of instruction emulation to a C implementation routine and
1133 * returns, taking one argument in addition to the standard ones.
1134 *
1135 * @param a_pfnCImpl The pointer to the C routine.
1136 * @param a0 The argument.
1137 */
1138#define IEM_MC_CALL_CIMPL_1(a_pfnCImpl, a0) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1139
1140/**
1141 * Defers the rest of the instruction emulation to a C implementation routine
1142 * and returns, taking two arguments in addition to the standard ones.
1143 *
1144 * @param a_pfnCImpl The pointer to the C routine.
1145 * @param a0 The first extra argument.
1146 * @param a1 The second extra argument.
1147 */
1148#define IEM_MC_CALL_CIMPL_2(a_pfnCImpl, a0, a1) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1149
1150/**
1151 * Defers the rest of the instruction emulation to a C implementation routine
1152 * and returns, taking three arguments in addition to the standard ones.
1153 *
1154 * @param a_pfnCImpl The pointer to the C routine.
1155 * @param a0 The first extra argument.
1156 * @param a1 The second extra argument.
1157 * @param a2 The third extra argument.
1158 */
1159#define IEM_MC_CALL_CIMPL_3(a_pfnCImpl, a0, a1, a2) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1160
1161/**
1162 * Defers the rest of the instruction emulation to a C implementation routine
1163 * and returns, taking four arguments in addition to the standard ones.
1164 *
1165 * @param a_pfnCImpl The pointer to the C routine.
1166 * @param a0 The first extra argument.
1167 * @param a1 The second extra argument.
1168 * @param a2 The third extra argument.
1169 * @param a3 The fourth extra argument.
1170 */
1171#define IEM_MC_CALL_CIMPL_4(a_pfnCImpl, a0, a1, a2, a3) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3)
1172
1173/**
1174 * Defers the rest of the instruction emulation to a C implementation routine
1175 * and returns, taking two arguments in addition to the standard ones.
1176 *
1177 * @param a_pfnCImpl The pointer to the C routine.
1178 * @param a0 The first extra argument.
1179 * @param a1 The second extra argument.
1180 * @param a2 The third extra argument.
1181 * @param a3 The fourth extra argument.
1182 * @param a4 The fifth extra argument.
1183 */
1184#define IEM_MC_CALL_CIMPL_5(a_pfnCImpl, a0, a1, a2, a3, a4) return (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2, a3, a4)
1185
1186/**
1187 * Defers the entire instruction emulation to a C implementation routine and
1188 * returns, only taking the standard parameters.
1189 *
1190 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1191 *
1192 * @param a_pfnCImpl The pointer to the C routine.
1193 * @sa IEM_DECL_IMPL_C_TYPE_0 and IEM_CIMPL_DEF_0.
1194 */
1195#define IEM_MC_DEFER_TO_CIMPL_0(a_pfnCImpl) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu))
1196
1197/**
1198 * Defers the entire instruction emulation to a C implementation routine and
1199 * returns, taking one argument in addition to the standard ones.
1200 *
1201 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1202 *
1203 * @param a_pfnCImpl The pointer to the C routine.
1204 * @param a0 The argument.
1205 */
1206#define IEM_MC_DEFER_TO_CIMPL_1(a_pfnCImpl, a0) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0)
1207
1208/**
1209 * Defers the entire instruction emulation to a C implementation routine and
1210 * returns, taking two arguments in addition to the standard ones.
1211 *
1212 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1213 *
1214 * @param a_pfnCImpl The pointer to the C routine.
1215 * @param a0 The first extra argument.
1216 * @param a1 The second extra argument.
1217 */
1218#define IEM_MC_DEFER_TO_CIMPL_2(a_pfnCImpl, a0, a1) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1)
1219
1220/**
1221 * Defers the entire instruction emulation to a C implementation routine and
1222 * returns, taking three arguments in addition to the standard ones.
1223 *
1224 * This shall be used without any IEM_MC_BEGIN or IEM_END macro surrounding it.
1225 *
1226 * @param a_pfnCImpl The pointer to the C routine.
1227 * @param a0 The first extra argument.
1228 * @param a1 The second extra argument.
1229 * @param a2 The third extra argument.
1230 */
1231#define IEM_MC_DEFER_TO_CIMPL_3(a_pfnCImpl, a0, a1, a2) (a_pfnCImpl)(pVCpu, IEM_GET_INSTR_LEN(pVCpu), a0, a1, a2)
1232
1233/**
1234 * Calls a FPU assembly implementation taking one visible argument.
1235 *
1236 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1237 * @param a0 The first extra argument.
1238 */
1239#define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0) \
1240 do { \
1241 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0)); \
1242 } while (0)
1243
1244/**
1245 * Calls a FPU assembly implementation taking two visible arguments.
1246 *
1247 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1248 * @param a0 The first extra argument.
1249 * @param a1 The second extra argument.
1250 */
1251#define IEM_MC_CALL_FPU_AIMPL_2(a_pfnAImpl, a0, a1) \
1252 do { \
1253 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1254 } while (0)
1255
1256/**
1257 * Calls a FPU assembly implementation taking three visible arguments.
1258 *
1259 * @param a_pfnAImpl Pointer to the assembly FPU routine.
1260 * @param a0 The first extra argument.
1261 * @param a1 The second extra argument.
1262 * @param a2 The third extra argument.
1263 */
1264#define IEM_MC_CALL_FPU_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1265 do { \
1266 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1267 } while (0)
1268
1269#define IEM_MC_SET_FPU_RESULT(a_FpuData, a_FSW, a_pr80Value) \
1270 do { \
1271 (a_FpuData).FSW = (a_FSW); \
1272 (a_FpuData).r80Result = *(a_pr80Value); \
1273 } while (0)
1274
1275/** Pushes FPU result onto the stack. */
1276#define IEM_MC_PUSH_FPU_RESULT(a_FpuData) \
1277 iemFpuPushResult(pVCpu, &a_FpuData)
1278/** Pushes FPU result onto the stack and sets the FPUDP. */
1279#define IEM_MC_PUSH_FPU_RESULT_MEM_OP(a_FpuData, a_iEffSeg, a_GCPtrEff) \
1280 iemFpuPushResultWithMemOp(pVCpu, &a_FpuData, a_iEffSeg, a_GCPtrEff)
1281
1282/** Replaces ST0 with value one and pushes value 2 onto the FPU stack. */
1283#define IEM_MC_PUSH_FPU_RESULT_TWO(a_FpuDataTwo) \
1284 iemFpuPushResultTwo(pVCpu, &a_FpuDataTwo)
1285
1286/** Stores FPU result in a stack register. */
1287#define IEM_MC_STORE_FPU_RESULT(a_FpuData, a_iStReg) \
1288 iemFpuStoreResult(pVCpu, &a_FpuData, a_iStReg)
1289/** Stores FPU result in a stack register and pops the stack. */
1290#define IEM_MC_STORE_FPU_RESULT_THEN_POP(a_FpuData, a_iStReg) \
1291 iemFpuStoreResultThenPop(pVCpu, &a_FpuData, a_iStReg)
1292/** Stores FPU result in a stack register and sets the FPUDP. */
1293#define IEM_MC_STORE_FPU_RESULT_MEM_OP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1294 iemFpuStoreResultWithMemOp(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1295/** Stores FPU result in a stack register, sets the FPUDP, and pops the
1296 * stack. */
1297#define IEM_MC_STORE_FPU_RESULT_WITH_MEM_OP_THEN_POP(a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff) \
1298 iemFpuStoreResultWithMemOpThenPop(pVCpu, &a_FpuData, a_iStReg, a_iEffSeg, a_GCPtrEff)
1299
1300/** Only update the FOP, FPUIP, and FPUCS. (For FNOP.) */
1301#define IEM_MC_UPDATE_FPU_OPCODE_IP() \
1302 iemFpuUpdateOpcodeAndIp(pVCpu)
1303/** Free a stack register (for FFREE and FFREEP). */
1304#define IEM_MC_FPU_STACK_FREE(a_iStReg) \
1305 iemFpuStackFree(pVCpu, a_iStReg)
1306/** Increment the FPU stack pointer. */
1307#define IEM_MC_FPU_STACK_INC_TOP() \
1308 iemFpuStackIncTop(pVCpu)
1309/** Decrement the FPU stack pointer. */
1310#define IEM_MC_FPU_STACK_DEC_TOP() \
1311 iemFpuStackDecTop(pVCpu)
1312
1313/** Updates the FSW, FOP, FPUIP, and FPUCS. */
1314#define IEM_MC_UPDATE_FSW(a_u16FSW) \
1315 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1316/** Updates the FSW with a constant value as well as FOP, FPUIP, and FPUCS. */
1317#define IEM_MC_UPDATE_FSW_CONST(a_u16FSW) \
1318 iemFpuUpdateFSW(pVCpu, a_u16FSW)
1319/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP, and FPUDS. */
1320#define IEM_MC_UPDATE_FSW_WITH_MEM_OP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1321 iemFpuUpdateFSWWithMemOp(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1322/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack. */
1323#define IEM_MC_UPDATE_FSW_THEN_POP(a_u16FSW) \
1324 iemFpuUpdateFSWThenPop(pVCpu, a_u16FSW)
1325/** Updates the FSW, FOP, FPUIP, FPUCS, FPUDP and FPUDS, and then pops the
1326 * stack. */
1327#define IEM_MC_UPDATE_FSW_WITH_MEM_OP_THEN_POP(a_u16FSW, a_iEffSeg, a_GCPtrEff) \
1328 iemFpuUpdateFSWWithMemOpThenPop(pVCpu, a_u16FSW, a_iEffSeg, a_GCPtrEff)
1329/** Updates the FSW, FOP, FPUIP, and FPUCS, and then pops the stack twice. */
1330#define IEM_MC_UPDATE_FSW_THEN_POP_POP(a_u16FSW) \
1331 iemFpuUpdateFSWThenPopPop(pVCpu, a_u16FSW)
1332
1333/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. */
1334#define IEM_MC_FPU_STACK_UNDERFLOW(a_iStDst) \
1335 iemFpuStackUnderflow(pVCpu, a_iStDst)
1336/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1337 * stack. */
1338#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(a_iStDst) \
1339 iemFpuStackUnderflowThenPop(pVCpu, a_iStDst)
1340/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1341 * FPUDS. */
1342#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1343 iemFpuStackUnderflowWithMemOp(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1344/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS, FOP, FPUDP and
1345 * FPUDS. Pops stack. */
1346#define IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(a_iStDst, a_iEffSeg, a_GCPtrEff) \
1347 iemFpuStackUnderflowWithMemOpThenPop(pVCpu, a_iStDst, a_iEffSeg, a_GCPtrEff)
1348/** Raises a FPU stack underflow exception. Sets FPUIP, FPUCS and FOP. Pops
1349 * stack twice. */
1350#define IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP() \
1351 iemFpuStackUnderflowThenPopPop(pVCpu)
1352/** Raises a FPU stack underflow exception for an instruction pushing a result
1353 * value onto the stack. Sets FPUIP, FPUCS and FOP. */
1354#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW() \
1355 iemFpuStackPushUnderflow(pVCpu)
1356/** Raises a FPU stack underflow exception for an instruction pushing a result
1357 * value onto the stack and replacing ST0. Sets FPUIP, FPUCS and FOP. */
1358#define IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO() \
1359 iemFpuStackPushUnderflowTwo(pVCpu)
1360
1361/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1362 * FPUIP, FPUCS and FOP. */
1363#define IEM_MC_FPU_STACK_PUSH_OVERFLOW() \
1364 iemFpuStackPushOverflow(pVCpu)
1365/** Raises a FPU stack overflow exception as part of a push attempt. Sets
1366 * FPUIP, FPUCS, FOP, FPUDP and FPUDS. */
1367#define IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(a_iEffSeg, a_GCPtrEff) \
1368 iemFpuStackPushOverflowWithMemOp(pVCpu, a_iEffSeg, a_GCPtrEff)
1369/** Prepares for using the FPU state.
1370 * Ensures that we can use the host FPU in the current context (RC+R0.
1371 * Ensures the guest FPU state in the CPUMCTX is up to date. */
1372#define IEM_MC_PREPARE_FPU_USAGE() iemFpuPrepareUsage(pVCpu)
1373/** Actualizes the guest FPU state so it can be accessed read-only fashion. */
1374#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_READ() iemFpuActualizeStateForRead(pVCpu)
1375/** Actualizes the guest FPU state so it can be accessed and modified. */
1376#define IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE() iemFpuActualizeStateForChange(pVCpu)
1377
1378/** Stores SSE SIMD result updating MXCSR. */
1379#define IEM_MC_STORE_SSE_RESULT(a_SseData, a_iXmmReg) \
1380 iemSseStoreResult(pVCpu, &a_SseData, a_iXmmReg)
1381/** Updates MXCSR. */
1382#define IEM_MC_SSE_UPDATE_MXCSR(a_fMxcsr) \
1383 iemSseUpdateMxcsr(pVCpu, a_fMxcsr)
1384
1385/** Prepares for using the SSE state.
1386 * Ensures that we can use the host SSE/FPU in the current context (RC+R0.
1387 * Ensures the guest SSE state in the CPUMCTX is up to date. */
1388#define IEM_MC_PREPARE_SSE_USAGE() iemFpuPrepareUsageSse(pVCpu)
1389/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1390#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_READ() iemFpuActualizeSseStateForRead(pVCpu)
1391/** Actualizes the guest XMM0..15 and MXCSR register state for read-write access. */
1392#define IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE() iemFpuActualizeSseStateForChange(pVCpu)
1393
1394/** Prepares for using the AVX state.
1395 * Ensures that we can use the host AVX/FPU in the current context (RC+R0.
1396 * Ensures the guest AVX state in the CPUMCTX is up to date.
1397 * @note This will include the AVX512 state too when support for it is added
1398 * due to the zero extending feature of VEX instruction. */
1399#define IEM_MC_PREPARE_AVX_USAGE() iemFpuPrepareUsageAvx(pVCpu)
1400/** Actualizes the guest XMM0..15 and MXCSR register state for read-only access. */
1401#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_READ() iemFpuActualizeAvxStateForRead(pVCpu)
1402/** Actualizes the guest YMM0..15 and MXCSR register state for read-write access. */
1403#define IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE() iemFpuActualizeAvxStateForChange(pVCpu)
1404
1405/**
1406 * Calls a MMX assembly implementation taking two visible arguments.
1407 *
1408 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1409 * @param a0 The first extra argument.
1410 * @param a1 The second extra argument.
1411 */
1412#define IEM_MC_CALL_MMX_AIMPL_2(a_pfnAImpl, a0, a1) \
1413 do { \
1414 IEM_MC_PREPARE_FPU_USAGE(); \
1415 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1416 } while (0)
1417
1418/**
1419 * Calls a MMX assembly implementation taking three visible arguments.
1420 *
1421 * @param a_pfnAImpl Pointer to the assembly MMX routine.
1422 * @param a0 The first extra argument.
1423 * @param a1 The second extra argument.
1424 * @param a2 The third extra argument.
1425 */
1426#define IEM_MC_CALL_MMX_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1427 do { \
1428 IEM_MC_PREPARE_FPU_USAGE(); \
1429 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1430 } while (0)
1431
1432
1433/**
1434 * Calls a SSE assembly implementation taking two visible arguments.
1435 *
1436 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1437 * @param a0 The first extra argument.
1438 * @param a1 The second extra argument.
1439 */
1440#define IEM_MC_CALL_SSE_AIMPL_2(a_pfnAImpl, a0, a1) \
1441 do { \
1442 IEM_MC_PREPARE_SSE_USAGE(); \
1443 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1)); \
1444 } while (0)
1445
1446/**
1447 * Calls a SSE assembly implementation taking three visible arguments.
1448 *
1449 * @param a_pfnAImpl Pointer to the assembly SSE routine.
1450 * @param a0 The first extra argument.
1451 * @param a1 The second extra argument.
1452 * @param a2 The third extra argument.
1453 */
1454#define IEM_MC_CALL_SSE_AIMPL_3(a_pfnAImpl, a0, a1, a2) \
1455 do { \
1456 IEM_MC_PREPARE_SSE_USAGE(); \
1457 a_pfnAImpl(&pVCpu->cpum.GstCtx.XState.x87, (a0), (a1), (a2)); \
1458 } while (0)
1459
1460
1461/** Declares implicit arguments for IEM_MC_CALL_AVX_AIMPL_2,
1462 * IEM_MC_CALL_AVX_AIMPL_3, IEM_MC_CALL_AVX_AIMPL_4, ... */
1463#define IEM_MC_IMPLICIT_AVX_AIMPL_ARGS() \
1464 IEM_MC_ARG_CONST(PX86XSAVEAREA, pXState, &pVCpu->cpum.GstCtx.XState, 0)
1465
1466/**
1467 * Calls a AVX assembly implementation taking two visible arguments.
1468 *
1469 * There is one implicit zero'th argument, a pointer to the extended state.
1470 *
1471 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1472 * @param a1 The first extra argument.
1473 * @param a2 The second extra argument.
1474 */
1475#define IEM_MC_CALL_AVX_AIMPL_2(a_pfnAImpl, a1, a2) \
1476 do { \
1477 IEM_MC_PREPARE_AVX_USAGE(); \
1478 a_pfnAImpl(pXState, (a1), (a2)); \
1479 } while (0)
1480
1481/**
1482 * Calls a AVX assembly implementation taking three visible arguments.
1483 *
1484 * There is one implicit zero'th argument, a pointer to the extended state.
1485 *
1486 * @param a_pfnAImpl Pointer to the assembly AVX routine.
1487 * @param a1 The first extra argument.
1488 * @param a2 The second extra argument.
1489 * @param a3 The third extra argument.
1490 */
1491#define IEM_MC_CALL_AVX_AIMPL_3(a_pfnAImpl, a1, a2, a3) \
1492 do { \
1493 IEM_MC_PREPARE_AVX_USAGE(); \
1494 a_pfnAImpl(pXState, (a1), (a2), (a3)); \
1495 } while (0)
1496
1497/** @note Not for IOPL or IF testing. */
1498#define IEM_MC_IF_EFL_BIT_SET(a_fBit) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) {
1499/** @note Not for IOPL or IF testing. */
1500#define IEM_MC_IF_EFL_BIT_NOT_SET(a_fBit) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit))) {
1501/** @note Not for IOPL or IF testing. */
1502#define IEM_MC_IF_EFL_ANY_BITS_SET(a_fBits) if (pVCpu->cpum.GstCtx.eflags.u & (a_fBits)) {
1503/** @note Not for IOPL or IF testing. */
1504#define IEM_MC_IF_EFL_NO_BITS_SET(a_fBits) if (!(pVCpu->cpum.GstCtx.eflags.u & (a_fBits))) {
1505/** @note Not for IOPL or IF testing. */
1506#define IEM_MC_IF_EFL_BITS_NE(a_fBit1, a_fBit2) \
1507 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1508 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1509/** @note Not for IOPL or IF testing. */
1510#define IEM_MC_IF_EFL_BITS_EQ(a_fBit1, a_fBit2) \
1511 if ( !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1512 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1513/** @note Not for IOPL or IF testing. */
1514#define IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(a_fBit, a_fBit1, a_fBit2) \
1515 if ( (pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1516 || !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1517 != !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1518/** @note Not for IOPL or IF testing. */
1519#define IEM_MC_IF_EFL_BIT_NOT_SET_AND_BITS_EQ(a_fBit, a_fBit1, a_fBit2) \
1520 if ( !(pVCpu->cpum.GstCtx.eflags.u & (a_fBit)) \
1521 && !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit1)) \
1522 == !!(pVCpu->cpum.GstCtx.eflags.u & (a_fBit2)) ) {
1523#define IEM_MC_IF_CX_IS_NZ() if (pVCpu->cpum.GstCtx.cx != 0) {
1524#define IEM_MC_IF_ECX_IS_NZ() if (pVCpu->cpum.GstCtx.ecx != 0) {
1525#define IEM_MC_IF_RCX_IS_NZ() if (pVCpu->cpum.GstCtx.rcx != 0) {
1526/** @note Not for IOPL or IF testing. */
1527#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1528 if ( pVCpu->cpum.GstCtx.cx != 0 \
1529 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1530/** @note Not for IOPL or IF testing. */
1531#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1532 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1533 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1534/** @note Not for IOPL or IF testing. */
1535#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(a_fBit) \
1536 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1537 && (pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1538/** @note Not for IOPL or IF testing. */
1539#define IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1540 if ( pVCpu->cpum.GstCtx.cx != 0 \
1541 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1542/** @note Not for IOPL or IF testing. */
1543#define IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1544 if ( pVCpu->cpum.GstCtx.ecx != 0 \
1545 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1546/** @note Not for IOPL or IF testing. */
1547#define IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(a_fBit) \
1548 if ( pVCpu->cpum.GstCtx.rcx != 0 \
1549 && !(pVCpu->cpum.GstCtx.eflags.u & a_fBit)) {
1550#define IEM_MC_IF_LOCAL_IS_Z(a_Local) if ((a_Local) == 0) {
1551#define IEM_MC_IF_GREG_BIT_SET(a_iGReg, a_iBitNo) if (iemGRegFetchU64(pVCpu, (a_iGReg)) & RT_BIT_64(a_iBitNo)) {
1552
1553#define IEM_MC_REF_FPUREG(a_pr80Dst, a_iSt) \
1554 do { (a_pr80Dst) = &pVCpu->cpum.GstCtx.XState.x87.aRegs[X86_FSW_TOP_GET_ST(pVCpu->cpum.GstCtx.XState.x87.FSW, a_iSt)].r80; } while (0)
1555#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1556 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1557#define IEM_MC_IF_FPUREG_NOT_EMPTY(a_iSt) \
1558 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) == VINF_SUCCESS) {
1559#define IEM_MC_IF_FPUREG_IS_EMPTY(a_iSt) \
1560 if (iemFpuStRegNotEmpty(pVCpu, (a_iSt)) != VINF_SUCCESS) {
1561#define IEM_MC_IF_FPUREG_NOT_EMPTY_REF_R80(a_pr80Dst, a_iSt) \
1562 if (iemFpuStRegNotEmptyRef(pVCpu, (a_iSt), &(a_pr80Dst)) == VINF_SUCCESS) {
1563#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80(a_pr80Dst0, a_iSt0, a_pr80Dst1, a_iSt1) \
1564 if (iemFpu2StRegsNotEmptyRef(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1), &(a_pr80Dst1)) == VINF_SUCCESS) {
1565#define IEM_MC_IF_TWO_FPUREGS_NOT_EMPTY_REF_R80_FIRST(a_pr80Dst0, a_iSt0, a_iSt1) \
1566 if (iemFpu2StRegsNotEmptyRefFirst(pVCpu, (a_iSt0), &(a_pr80Dst0), (a_iSt1)) == VINF_SUCCESS) {
1567#define IEM_MC_IF_FCW_IM() \
1568 if (pVCpu->cpum.GstCtx.XState.x87.FCW & X86_FCW_IM) {
1569#define IEM_MC_IF_MXCSR_XCPT_PENDING() \
1570 if (( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \
1571 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) != 0) {
1572
1573#define IEM_MC_ELSE() } else {
1574#define IEM_MC_ENDIF() } do {} while (0)
1575
1576/** @} */
1577
1578#endif /* !VMM_INCLUDED_SRC_include_IEMMc_h */
1579
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