PGMInternal.h@ 55493

Last change on this file since 55493 was 55493, checked in by vboxsync, 10 years ago
PGM,++: Separated physical access handler callback function pointers from the access handler registrations to reduce footprint and simplify adding a couple of more callbacks.
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File size: 190.2 KB

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1	/* $Id: PGMInternal.h 55493 2015-04-28 16:51:35Z vboxsync $ */
2	/** @file
3	* PGM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___PGMInternal_h
19	#define ___PGMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/err.h>
24	#include <VBox/dbg.h>
25	#include <VBox/vmm/stam.h>
26	#include <VBox/param.h>
27	#include <VBox/vmm/vmm.h>
28	#include <VBox/vmm/mm.h>
29	#include <VBox/vmm/pdmcritsect.h>
30	#include <VBox/vmm/pdmapi.h>
31	#include <VBox/dis.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/log.h>
34	#include <VBox/vmm/gmm.h>
35	#include <VBox/vmm/hm.h>
36	#include <VBox/vmm/hm_vmx.h>
37	#include "internal/pgm.h"
38	#include <iprt/asm.h>
39	#include <iprt/assert.h>
40	#include <iprt/avl.h>
41	#include <iprt/critsect.h>
42	#include <iprt/list-off32.h>
43	#include <iprt/sha.h>
44
45
46
47	/** @defgroup grp_pgm_int Internals
48	* @ingroup grp_pgm
49	* @internal
50	* @{
51	*/
52
53
54	/** @name PGM Compile Time Config
55	* @{
56	*/
57
58	/**
59	* Indicates that there are no guest mappings in the shadow tables.
60	*
61	* Note! In ring-3 the macro is also used to exclude the managment of the
62	* intermediate context page tables. On 32-bit systems we use the intermediate
63	* context to support 64-bit guest execution. Thus, we cannot fully make it
64	* without mappings there even when VBOX_WITH_RAW_MODE is not defined.
65	*
66	* In raw-mode context there are by design always guest mappings (the code is
67	* executed from one), while in ring-0 there are none at all. Neither context
68	* manages the page tables for intermediate switcher context, that's all done in
69	* ring-3.
70	*
71	* On 32-bit darwin (hybrid kernel) we do 64-bit guest support differently, so
72	* there we can safely work without mappings if we don't compile in raw-mode.
73	*/
74	#if defined(IN_RING0) \
75	\|\| ( !defined(VBOX_WITH_RAW_MODE) \
76	&& ( HC_ARCH_BITS != 32 \
77	\|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \
78	\|\| !defined(VBOX_WITH_64_BITS_GUESTS) \
79	) \
80	)
81	# define PGM_WITHOUT_MAPPINGS
82	#endif
83
84	/**
85	* Check and skip global PDEs for non-global flushes
86	*/
87	#define PGM_SKIP_GLOBAL_PAGEDIRS_ON_NONGLOBAL_FLUSH
88
89	/**
90	* Optimization for PAE page tables that are modified often
91	*/
92	//#if 0 /* disabled again while debugging */
93	#ifndef IN_RC
94	# define PGMPOOL_WITH_OPTIMIZED_DIRTY_PT
95	#endif
96	//#endif
97
98	/**
99	* Large page support enabled only on 64 bits hosts; applies to nested paging only.
100	*/
101	#if (HC_ARCH_BITS == 64) && !defined(IN_RC)
102	# define PGM_WITH_LARGE_PAGES
103	#endif
104
105	/**
106	* Enables optimizations for MMIO handlers that exploits X86_TRAP_PF_RSVD and
107	* VMX_EXIT_EPT_MISCONFIG.
108	*/
109	#if 1 /* testing */
110	# define PGM_WITH_MMIO_OPTIMIZATIONS
111	#endif
112
113	/**
114	* Sync N pages instead of a whole page table
115	*/
116	#define PGM_SYNC_N_PAGES
117
118	/**
119	* Number of pages to sync during a page fault
120	*
121	* When PGMPOOL_WITH_GCPHYS_TRACKING is enabled using high values here
122	* causes a lot of unnecessary extents and also is slower than taking more \#PFs.
123	*
124	* Note that \#PFs are much more expensive in the VT-x/AMD-V case due to
125	* world switch overhead, so let's sync more.
126	*/
127	# ifdef IN_RING0
128	/* Chose 32 based on the compile test in @bugref{4219}; 64 shows worse stats.
129	* 32 again shows better results than 16; slightly more overhead in the \#PF handler,
130	* but ~5% fewer faults.
131	*/
132	# define PGM_SYNC_NR_PAGES 32
133	#else
134	# define PGM_SYNC_NR_PAGES 8
135	#endif
136
137	/**
138	* Number of PGMPhysRead/Write cache entries (must be <= sizeof(uint64_t))
139	*/
140	#define PGM_MAX_PHYSCACHE_ENTRIES 64
141	#define PGM_MAX_PHYSCACHE_ENTRIES_MASK (PGM_MAX_PHYSCACHE_ENTRIES-1)
142
143
144	/** @def PGMPOOL_CFG_MAX_GROW
145	* The maximum number of pages to add to the pool in one go.
146	*/
147	#define PGMPOOL_CFG_MAX_GROW (_256K >> PAGE_SHIFT)
148
149	/** @def VBOX_STRICT_PGM_HANDLER_VIRTUAL
150	* Enables some extra assertions for virtual handlers (mainly phys2virt related).
151	*/
152	#ifdef VBOX_STRICT
153	# define VBOX_STRICT_PGM_HANDLER_VIRTUAL
154	#endif
155
156	/** @def VBOX_WITH_NEW_LAZY_PAGE_ALLOC
157	* Enables the experimental lazy page allocation code. */
158	/#define VBOX_WITH_NEW_LAZY_PAGE_ALLOC /
159
160	/** @def VBOX_WITH_REAL_WRITE_MONITORED_PAGES
161	* Enables real write monitoring of pages, i.e. mapping them read-only and
162	* only making them writable when getting a write access #PF. */
163	#define VBOX_WITH_REAL_WRITE_MONITORED_PAGES
164
165	/** @} */
166
167
168	/** @name PDPT and PML4 flags.
169	* These are placed in the three bits available for system programs in
170	* the PDPT and PML4 entries.
171	* @{ */
172	/** The entry is a permanent one and it's must always be present.
173	* Never free such an entry. */
174	#define PGM_PLXFLAGS_PERMANENT RT_BIT_64(10)
175	/** Mapping (hypervisor allocated pagetable). */
176	#define PGM_PLXFLAGS_MAPPING RT_BIT_64(11)
177	/** @} */
178
179	/** @name Page directory flags.
180	* These are placed in the three bits available for system programs in
181	* the page directory entries.
182	* @{ */
183	/** Mapping (hypervisor allocated pagetable). */
184	#define PGM_PDFLAGS_MAPPING RT_BIT_64(10)
185	/** Made read-only to facilitate dirty bit tracking. */
186	#define PGM_PDFLAGS_TRACK_DIRTY RT_BIT_64(11)
187	/** @} */
188
189	/** @name Page flags.
190	* These are placed in the three bits available for system programs in
191	* the page entries.
192	* @{ */
193	/** Made read-only to facilitate dirty bit tracking. */
194	#define PGM_PTFLAGS_TRACK_DIRTY RT_BIT_64(9)
195
196	#ifndef PGM_PTFLAGS_CSAM_VALIDATED
197	/** Scanned and approved by CSAM (tm).
198	* NOTE: Must be identical to the one defined in CSAMInternal.h!!
199	* @todo Move PGM_PTFLAGS_* and PGM_PDFLAGS_* to VBox/vmm/pgm.h. */
200	#define PGM_PTFLAGS_CSAM_VALIDATED RT_BIT_64(11)
201	#endif
202
203	/** @} */
204
205	/** @name Defines used to indicate the shadow and guest paging in the templates.
206	* @{ */
207	#define PGM_TYPE_REAL 1
208	#define PGM_TYPE_PROT 2
209	#define PGM_TYPE_32BIT 3
210	#define PGM_TYPE_PAE 4
211	#define PGM_TYPE_AMD64 5
212	#define PGM_TYPE_NESTED 6
213	#define PGM_TYPE_EPT 7
214	#define PGM_TYPE_MAX PGM_TYPE_EPT
215	/** @} */
216
217	/** Macro for checking if the guest is using paging.
218	* @param uGstType PGM_TYPE_*
219	* @param uShwType PGM_TYPE_*
220	* @remark ASSUMES certain order of the PGM_TYPE_* values.
221	*/
222	#define PGM_WITH_PAGING(uGstType, uShwType) \
223	( (uGstType) >= PGM_TYPE_32BIT \
224	&& (uShwType) != PGM_TYPE_NESTED \
225	&& (uShwType) != PGM_TYPE_EPT)
226
227	/** Macro for checking if the guest supports the NX bit.
228	* @param uGstType PGM_TYPE_*
229	* @param uShwType PGM_TYPE_*
230	* @remark ASSUMES certain order of the PGM_TYPE_* values.
231	*/
232	#define PGM_WITH_NX(uGstType, uShwType) \
233	( (uGstType) >= PGM_TYPE_PAE \
234	&& (uShwType) != PGM_TYPE_NESTED \
235	&& (uShwType) != PGM_TYPE_EPT)
236
237
238	/** @def PGM_HCPHYS_2_PTR
239	* Maps a HC physical page pool address to a virtual address.
240	*
241	* @returns VBox status code.
242	* @param pVM Pointer to the VM.
243	* @param pVCpu The current CPU.
244	* @param HCPhys The HC physical address to map to a virtual one.
245	* @param ppv Where to store the virtual address. No need to cast
246	* this.
247	*
248	* @remark Use with care as we don't have so much dynamic mapping space in
249	* ring-0 on 32-bit darwin and in RC.
250	* @remark There is no need to assert on the result.
251	*/
252	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
253	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
254	pgmRZDynMapHCPageInlined(pVCpu, HCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
255	#else
256	# define PGM_HCPHYS_2_PTR(pVM, pVCpu, HCPhys, ppv) \
257	MMPagePhys2PageEx(pVM, HCPhys, (void **)(ppv))
258	#endif
259
260	/** @def PGM_GCPHYS_2_PTR_V2
261	* Maps a GC physical page address to a virtual address.
262	*
263	* @returns VBox status code.
264	* @param pVM Pointer to the VM.
265	* @param pVCpu The current CPU.
266	* @param GCPhys The GC physical address to map to a virtual one.
267	* @param ppv Where to store the virtual address. No need to cast this.
268	*
269	* @remark Use with care as we don't have so much dynamic mapping space in
270	* ring-0 on 32-bit darwin and in RC.
271	* @remark There is no need to assert on the result.
272	*/
273	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
274	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
275	pgmRZDynMapGCPageV2Inlined(pVM, pVCpu, GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
276	#else
277	# define PGM_GCPHYS_2_PTR_V2(pVM, pVCpu, GCPhys, ppv) \
278	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
279	#endif
280
281	/** @def PGM_GCPHYS_2_PTR
282	* Maps a GC physical page address to a virtual address.
283	*
284	* @returns VBox status code.
285	* @param pVM Pointer to the VM.
286	* @param GCPhys The GC physical address to map to a virtual one.
287	* @param ppv Where to store the virtual address. No need to cast this.
288	*
289	* @remark Use with care as we don't have so much dynamic mapping space in
290	* ring-0 on 32-bit darwin and in RC.
291	* @remark There is no need to assert on the result.
292	*/
293	#define PGM_GCPHYS_2_PTR(pVM, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2(pVM, VMMGetCpu(pVM), GCPhys, ppv)
294
295	/** @def PGM_GCPHYS_2_PTR_BY_VMCPU
296	* Maps a GC physical page address to a virtual address.
297	*
298	* @returns VBox status code.
299	* @param pVCpu The current CPU.
300	* @param GCPhys The GC physical address to map to a virtual one.
301	* @param ppv Where to store the virtual address. No need to cast this.
302	*
303	* @remark Use with care as we don't have so much dynamic mapping space in
304	* ring-0 on 32-bit darwin and in RC.
305	* @remark There is no need to assert on the result.
306	*/
307	#define PGM_GCPHYS_2_PTR_BY_VMCPU(pVCpu, GCPhys, ppv) PGM_GCPHYS_2_PTR_V2((pVCpu)->CTX_SUFF(pVM), pVCpu, GCPhys, ppv)
308
309	/** @def PGM_GCPHYS_2_PTR_EX
310	* Maps a unaligned GC physical page address to a virtual address.
311	*
312	* @returns VBox status code.
313	* @param pVM Pointer to the VM.
314	* @param GCPhys The GC physical address to map to a virtual one.
315	* @param ppv Where to store the virtual address. No need to cast this.
316	*
317	* @remark Use with care as we don't have so much dynamic mapping space in
318	* ring-0 on 32-bit darwin and in RC.
319	* @remark There is no need to assert on the result.
320	*/
321	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
322	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
323	pgmRZDynMapGCPageOffInlined(VMMGetCpu(pVM), GCPhys, (void **)(ppv) RTLOG_COMMA_SRC_POS)
324	#else
325	# define PGM_GCPHYS_2_PTR_EX(pVM, GCPhys, ppv) \
326	pgmPhysGCPhys2R3Ptr(pVM, GCPhys, (PRTR3PTR)(ppv)) /** @todo this isn't asserting! */
327	#endif
328
329	/** @def PGM_DYNMAP_UNUSED_HINT
330	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
331	* is no longer used.
332	*
333	* For best effect only apply this to the page that was mapped most recently.
334	*
335	* @param pVCpu The current CPU.
336	* @param pvPage The pool page.
337	*/
338	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
339	# ifdef LOG_ENABLED
340	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage, RT_SRC_POS)
341	# else
342	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) pgmRZDynMapUnusedHint(pVCpu, pvPage)
343	# endif
344	#else
345	# define PGM_DYNMAP_UNUSED_HINT(pVCpu, pvPage) do {} while (0)
346	#endif
347
348	/** @def PGM_DYNMAP_UNUSED_HINT_VM
349	* Hints to the dynamic mapping code in RC and R0/darwin that the specified page
350	* is no longer used.
351	*
352	* For best effect only apply this to the page that was mapped most recently.
353	*
354	* @param pVM Pointer to the VM.
355	* @param pvPage The pool page.
356	*/
357	#define PGM_DYNMAP_UNUSED_HINT_VM(pVM, pvPage) PGM_DYNMAP_UNUSED_HINT(VMMGetCpu(pVM), pvPage)
358
359
360	/** @def PGM_INVL_PG
361	* Invalidates a page.
362	*
363	* @param pVCpu Pointer to the VMCPU.
364	* @param GCVirt The virtual address of the page to invalidate.
365	*/
366	#ifdef IN_RC
367	# define PGM_INVL_PG(pVCpu, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
368	#elif defined(IN_RING0)
369	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
370	#else
371	# define PGM_INVL_PG(pVCpu, GCVirt) HMInvalidatePage(pVCpu, (RTGCPTR)(GCVirt))
372	#endif
373
374	/** @def PGM_INVL_PG_ALL_VCPU
375	* Invalidates a page on all VCPUs
376	*
377	* @param pVM Pointer to the VM.
378	* @param GCVirt The virtual address of the page to invalidate.
379	*/
380	#ifdef IN_RC
381	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) ASMInvalidatePage((void *)(uintptr_t)(GCVirt))
382	#elif defined(IN_RING0)
383	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
384	#else
385	# define PGM_INVL_PG_ALL_VCPU(pVM, GCVirt) HMInvalidatePageOnAllVCpus(pVM, (RTGCPTR)(GCVirt))
386	#endif
387
388	/** @def PGM_INVL_BIG_PG
389	* Invalidates a 4MB page directory entry.
390	*
391	* @param pVCpu Pointer to the VMCPU.
392	* @param GCVirt The virtual address within the page directory to invalidate.
393	*/
394	#ifdef IN_RC
395	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) ASMReloadCR3()
396	#elif defined(IN_RING0)
397	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
398	#else
399	# define PGM_INVL_BIG_PG(pVCpu, GCVirt) HMFlushTLB(pVCpu)
400	#endif
401
402	/** @def PGM_INVL_VCPU_TLBS()
403	* Invalidates the TLBs of the specified VCPU
404	*
405	* @param pVCpu Pointer to the VMCPU.
406	*/
407	#ifdef IN_RC
408	# define PGM_INVL_VCPU_TLBS(pVCpu) ASMReloadCR3()
409	#elif defined(IN_RING0)
410	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
411	#else
412	# define PGM_INVL_VCPU_TLBS(pVCpu) HMFlushTLB(pVCpu)
413	#endif
414
415	/** @def PGM_INVL_ALL_VCPU_TLBS()
416	* Invalidates the TLBs of all VCPUs
417	*
418	* @param pVM Pointer to the VM.
419	*/
420	#ifdef IN_RC
421	# define PGM_INVL_ALL_VCPU_TLBS(pVM) ASMReloadCR3()
422	#elif defined(IN_RING0)
423	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
424	#else
425	# define PGM_INVL_ALL_VCPU_TLBS(pVM) HMFlushTLBOnAllVCpus(pVM)
426	#endif
427
428
429	/** @name Safer Shadow PAE PT/PTE
430	* For helping avoid misinterpreting invalid PAE/AMD64 page table entries as
431	* present.
432	*
433	* @{
434	*/
435	#if 1
436	/**
437	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
438	* invalid entries for present.
439	* @sa X86PTEPAE.
440	*/
441	typedef union PGMSHWPTEPAE
442	{
443	/** Unsigned integer view */
444	X86PGPAEUINT uCareful;
445	/* Not other views. */
446	} PGMSHWPTEPAE;
447
448	# define PGMSHWPTEPAE_IS_P(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_PAE_MBZ_MASK_NX)) == X86_PTE_P )
449	# define PGMSHWPTEPAE_IS_RW(Pte) ( !!((Pte).uCareful & X86_PTE_RW))
450	# define PGMSHWPTEPAE_IS_US(Pte) ( !!((Pte).uCareful & X86_PTE_US))
451	# define PGMSHWPTEPAE_IS_A(Pte) ( !!((Pte).uCareful & X86_PTE_A))
452	# define PGMSHWPTEPAE_IS_D(Pte) ( !!((Pte).uCareful & X86_PTE_D))
453	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).uCareful & PGM_PTFLAGS_TRACK_DIRTY) )
454	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).uCareful & (X86_PTE_P \| X86_PTE_RW \| X86_PTE_PAE_MBZ_MASK_NX)) == (X86_PTE_P \| X86_PTE_RW) )
455	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).uCareful )
456	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).uCareful & X86_PTE_PAE_PG_MASK )
457	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).uCareful ) /*< Use with care. /
458	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).uCareful = (uVal); } while (0)
459	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).uCareful = (Pte2).uCareful; } while (0)
460	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).uCareful, (uVal)); } while (0)
461	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).uCareful, (Pte2).uCareful); } while (0)
462	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).uCareful &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
463	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).uCareful \|= X86_PTE_RW; } while (0)
464
465	/**
466	* For making sure that u1Present and X86_PTE_P checks doesn't mistake
467	* invalid entries for present.
468	* @sa X86PTPAE.
469	*/
470	typedef struct PGMSHWPTPAE
471	{
472	PGMSHWPTEPAE a[X86_PG_PAE_ENTRIES];
473	} PGMSHWPTPAE;
474
475	#else
476	typedef X86PTEPAE PGMSHWPTEPAE;
477	typedef X86PTPAE PGMSHWPTPAE;
478	# define PGMSHWPTEPAE_IS_P(Pte) ( (Pte).n.u1Present )
479	# define PGMSHWPTEPAE_IS_RW(Pte) ( (Pte).n.u1Write )
480	# define PGMSHWPTEPAE_IS_US(Pte) ( (Pte).n.u1User )
481	# define PGMSHWPTEPAE_IS_A(Pte) ( (Pte).n.u1Accessed )
482	# define PGMSHWPTEPAE_IS_D(Pte) ( (Pte).n.u1Dirty )
483	# define PGMSHWPTEPAE_IS_TRACK_DIRTY(Pte) ( !!((Pte).u & PGM_PTFLAGS_TRACK_DIRTY) )
484	# define PGMSHWPTEPAE_IS_P_RW(Pte) ( ((Pte).u & (X86_PTE_P \| X86_PTE_RW)) == (X86_PTE_P \| X86_PTE_RW) )
485	# define PGMSHWPTEPAE_GET_LOG(Pte) ( (Pte).u )
486	# define PGMSHWPTEPAE_GET_HCPHYS(Pte) ( (Pte).u & X86_PTE_PAE_PG_MASK )
487	# define PGMSHWPTEPAE_GET_U(Pte) ( (Pte).u ) /*< Use with care. /
488	# define PGMSHWPTEPAE_SET(Pte, uVal) do { (Pte).u = (uVal); } while (0)
489	# define PGMSHWPTEPAE_SET2(Pte, Pte2) do { (Pte).u = (Pte2).u; } while (0)
490	# define PGMSHWPTEPAE_ATOMIC_SET(Pte, uVal) do { ASMAtomicWriteU64(&(Pte).u, (uVal)); } while (0)
491	# define PGMSHWPTEPAE_ATOMIC_SET2(Pte, Pte2) do { ASMAtomicWriteU64(&(Pte).u, (Pte2).u); } while (0)
492	# define PGMSHWPTEPAE_SET_RO(Pte) do { (Pte).u &= ~(X86PGPAEUINT)X86_PTE_RW; } while (0)
493	# define PGMSHWPTEPAE_SET_RW(Pte) do { (Pte).u \|= X86_PTE_RW; } while (0)
494
495	#endif
496
497	/** Pointer to a shadow PAE PTE. */
498	typedef PGMSHWPTEPAE *PPGMSHWPTEPAE;
499	/** Pointer to a const shadow PAE PTE. */
500	typedef PGMSHWPTEPAE const *PCPGMSHWPTEPAE;
501
502	/** Pointer to a shadow PAE page table. */
503	typedef PGMSHWPTPAE *PPGMSHWPTPAE;
504	/** Pointer to a const shadow PAE page table. */
505	typedef PGMSHWPTPAE const *PCPGMSHWPTPAE;
506	/** @} */
507
508
509	/** Size of the GCPtrConflict array in PGMMAPPING.
510	* @remarks Must be a power of two. */
511	#define PGMMAPPING_CONFLICT_MAX 8
512
513	/**
514	* Structure for tracking GC Mappings.
515	*
516	* This structure is used by linked list in both GC and HC.
517	*/
518	typedef struct PGMMAPPING
519	{
520	/** Pointer to next entry. */
521	R3PTRTYPE(struct PGMMAPPING *) pNextR3;
522	/** Pointer to next entry. */
523	R0PTRTYPE(struct PGMMAPPING *) pNextR0;
524	/** Pointer to next entry. */
525	RCPTRTYPE(struct PGMMAPPING *) pNextRC;
526	/** Indicate whether this entry is finalized. */
527	bool fFinalized;
528	/** Start Virtual address. */
529	RTGCPTR GCPtr;
530	/** Last Virtual address (inclusive). */
531	RTGCPTR GCPtrLast;
532	/** Range size (bytes). */
533	RTGCPTR cb;
534	/** Pointer to relocation callback function. */
535	R3PTRTYPE(PFNPGMRELOCATE) pfnRelocate;
536	/** User argument to the callback. */
537	R3PTRTYPE(void *) pvUser;
538	/** Mapping description / name. For easing debugging. */
539	R3PTRTYPE(const char *) pszDesc;
540	/** Last 8 addresses that caused conflicts. */
541	RTGCPTR aGCPtrConflicts[PGMMAPPING_CONFLICT_MAX];
542	/** Number of conflicts for this hypervisor mapping. */
543	uint32_t cConflicts;
544	/** Number of page tables. */
545	uint32_t cPTs;
546
547	/** Array of page table mapping data. Each entry
548	* describes one page table. The array can be longer
549	* than the declared length.
550	*/
551	struct
552	{
553	/** The HC physical address of the page table. */
554	RTHCPHYS HCPhysPT;
555	/** The HC physical address of the first PAE page table. */
556	RTHCPHYS HCPhysPaePT0;
557	/** The HC physical address of the second PAE page table. */
558	RTHCPHYS HCPhysPaePT1;
559	/** The HC virtual address of the 32-bit page table. */
560	R3PTRTYPE(PX86PT) pPTR3;
561	/** The HC virtual address of the two PAE page table. (i.e 1024 entries instead of 512) */
562	R3PTRTYPE(PPGMSHWPTPAE) paPaePTsR3;
563	/** The RC virtual address of the 32-bit page table. */
564	RCPTRTYPE(PX86PT) pPTRC;
565	/** The RC virtual address of the two PAE page table. */
566	RCPTRTYPE(PPGMSHWPTPAE) paPaePTsRC;
567	/** The R0 virtual address of the 32-bit page table. */
568	R0PTRTYPE(PX86PT) pPTR0;
569	/** The R0 virtual address of the two PAE page table. */
570	R0PTRTYPE(PPGMSHWPTPAE) paPaePTsR0;
571	} aPTs[1];
572	} PGMMAPPING;
573	/** Pointer to structure for tracking GC Mappings. */
574	typedef struct PGMMAPPING *PPGMMAPPING;
575
576
577	/**
578	* Physical page access handler type registration.
579	*/
580	typedef struct PGMPHYSHANDLERTYPEINT
581	{
582	/** Number of references. */
583	uint32_t volatile cRefs;
584	/** Magic number (PGMPHYSHANDLERTYPEINT_MAGIC). */
585	uint32_t u32Magic;
586	/** Link of handler types anchored in PGMTREES::HeadPhysHandlerTypes. */
587	RTLISTOFF32NODE ListNode;
588	/** The kind of accesses we're handling. */
589	PGMPHYSHANDLERKIND enmKind;
590	/** The PGM_PAGE_HNDL_PHYS_STATE_XXX value corresponding to enmKind. */
591	uint32_t uState;
592	/** Pointer to RC callback function. */
593	RCPTRTYPE(PFNPGMRCPHYSHANDLER) pfnHandlerRC;
594	/** Explicit alignment padding. */
595	RTRCPTR RCPtrPadding;
596	/** Pointer to R3 callback function. */
597	R3PTRTYPE(PFNPGMR3PHYSHANDLER) pfnHandlerR3;
598	/** Pointer to R0 callback function. */
599	R0PTRTYPE(PFNPGMR0PHYSHANDLER) pfnHandlerR0;
600	/** Description / Name. For easing debugging. */
601	R3PTRTYPE(const char *) pszDesc;
602	} PGMPHYSHANDLERTYPEINT;
603	/** Pointer to a physical access handler type registration. */
604	typedef PGMPHYSHANDLERTYPEINT *PPGMPHYSHANDLERTYPEINT;
605	/** Magic value for the physical handler callbacks (Robert A. Heinlein). */
606	#define PGMPHYSHANDLERTYPEINT_MAGIC UINT32_C(0x19070707)
607	/** Magic value for the physical handler callbacks. */
608	#define PGMPHYSHANDLERTYPEINT_MAGIC_DEAD UINT32_C(0x19880508)
609
610	/**
611	* Converts a handle to a pointer.
612	* @returns PPGMPHYSHANDLERTYPEINT
613	* @param a_pVM Pointer to the cross context VM structure.
614	* @param a_hType Physical access handler handle.
615	*/
616	#define PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, a_hType) ((PPGMPHYSHANDLERTYPEINT)MMHyperHeapOffsetToPtr(a_pVM, a_hType))
617
618
619	/**
620	* Physical page access handler structure.
621	*
622	* This is used to keep track of physical address ranges
623	* which are being monitored in some kind of way.
624	*/
625	typedef struct PGMPHYSHANDLER
626	{
627	AVLROGCPHYSNODECORE Core;
628	/** Number of pages to update. */
629	uint32_t cPages;
630	/** Set if we have pages that have been aliased. */
631	uint32_t cAliasedPages;
632	/** Set if we have pages that have temporarily been disabled. */
633	uint32_t cTmpOffPages;
634	/** Registered handler type handle (heap offset). */
635	PGMPHYSHANDLERTYPE hType;
636	/** User argument for RC handlers. */
637	RCPTRTYPE(void *) pvUserRC;
638	#if HC_ARCH_BITS == 64
639	RTRCPTR Padding0; /*< Explicit alignment padding. /
640	#endif
641	/** User argument for R3 handlers. */
642	R3PTRTYPE(void *) pvUserR3;
643	/** User argument for R0 handlers. */
644	R0PTRTYPE(void *) pvUserR0;
645	/** Description / Name. For easing debugging. */
646	R3PTRTYPE(const char *) pszDesc;
647	#ifdef VBOX_WITH_STATISTICS
648	/** Profiling of this handler. */
649	STAMPROFILE Stat;
650	#endif
651	} PGMPHYSHANDLER;
652	/** Pointer to a physical page access handler structure. */
653	typedef PGMPHYSHANDLER *PPGMPHYSHANDLER;
654
655	/**
656	* Gets the type record for a physical handler (no reference added).
657	* @returns PPGMPHYSHANDLERTYPEINT
658	* @param a_pVM Pointer to the cross context VM structure.
659	* @param a_pPhysHandler Pointer to the physical handler structure
660	* (PGMPHYSHANDLER).
661	*/
662	#define PGMPHYSHANDLER_GET_TYPE(a_pVM, a_pPhysHandler) PGMPHYSHANDLERTYPEINT_FROM_HANDLE(a_pVM, (a_pPhysHandler)->hType)
663
664
665	/**
666	* Cache node for the physical addresses covered by a virtual handler.
667	*/
668	typedef struct PGMPHYS2VIRTHANDLER
669	{
670	/** Core node for the tree based on physical ranges. */
671	AVLROGCPHYSNODECORE Core;
672	/** Offset from this struct to the PGMVIRTHANDLER structure. */
673	int32_t offVirtHandler;
674	/** Offset of the next alias relative to this one.
675	* Bit 0 is used for indicating whether we're in the tree.
676	* Bit 1 is used for indicating that we're the head node.
677	*/
678	int32_t offNextAlias;
679	} PGMPHYS2VIRTHANDLER;
680	/** Pointer to a phys to virtual handler structure. */
681	typedef PGMPHYS2VIRTHANDLER *PPGMPHYS2VIRTHANDLER;
682
683	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
684	* node is in the tree. */
685	#define PGMPHYS2VIRTHANDLER_IN_TREE RT_BIT(0)
686	/** The bit in PGMPHYS2VIRTHANDLER::offNextAlias used to indicate that the
687	* node is in the head of an alias chain.
688	* The PGMPHYS2VIRTHANDLER_IN_TREE is always set if this bit is set. */
689	#define PGMPHYS2VIRTHANDLER_IS_HEAD RT_BIT(1)
690	/** The mask to apply to PGMPHYS2VIRTHANDLER::offNextAlias to get the offset. */
691	#define PGMPHYS2VIRTHANDLER_OFF_MASK (~(int32_t)3)
692
693
694	/**
695	* Virtual page access handler structure.
696	*
697	* This is used to keep track of virtual address ranges
698	* which are being monitored in some kind of way.
699	*/
700	typedef struct PGMVIRTHANDLER
701	{
702	/** Core node for the tree based on virtual ranges. */
703	AVLROGCPTRNODECORE Core;
704	/** Size of the range (in bytes). */
705	RTGCPTR cb;
706	/** Number of cache pages. */
707	uint32_t cPages;
708	/** Access type. */
709	PGMVIRTHANDLERTYPE enmType;
710	/** Pointer to the RC callback function. */
711	RCPTRTYPE(PFNPGMRCVIRTHANDLER) pfnHandlerRC;
712	#if HC_ARCH_BITS == 64
713	RTRCPTR padding;
714	#endif
715	/** Pointer to the R3 callback function for invalidation. */
716	R3PTRTYPE(PFNPGMR3VIRTINVALIDATE) pfnInvalidateR3;
717	/** Pointer to the R3 callback function. */
718	R3PTRTYPE(PFNPGMR3VIRTHANDLER) pfnHandlerR3;
719	/** Description / Name. For easing debugging. */
720	R3PTRTYPE(const char *) pszDesc;
721	#ifdef VBOX_WITH_STATISTICS
722	/** Profiling of this handler. */
723	STAMPROFILE Stat;
724	#endif
725	/** Array of cached physical addresses for the monitored ranged. */
726	PGMPHYS2VIRTHANDLER aPhysToVirt[HC_ARCH_BITS == 32 ? 1 : 2];
727	} PGMVIRTHANDLER;
728	/** Pointer to a virtual page access handler structure. */
729	typedef PGMVIRTHANDLER *PPGMVIRTHANDLER;
730
731
732	/** @name Page type predicates.
733	* @{ */
734	#define PGMPAGETYPE_IS_READABLE(type) ( (type) <= PGMPAGETYPE_ROM )
735	#define PGMPAGETYPE_IS_WRITEABLE(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
736	#define PGMPAGETYPE_IS_RWX(type) ( (type) <= PGMPAGETYPE_ROM_SHADOW )
737	#define PGMPAGETYPE_IS_ROX(type) ( (type) == PGMPAGETYPE_ROM )
738	#define PGMPAGETYPE_IS_NP(type) ( (type) == PGMPAGETYPE_MMIO )
739	/** @} */
740
741
742	/**
743	* A Physical Guest Page tracking structure.
744	*
745	* The format of this structure is complicated because we have to fit a lot
746	* of information into as few bits as possible. The format is also subject
747	* to change (there is one coming up soon). Which means that for we'll be
748	* using PGM_PAGE_GET_, PGM_PAGE_IS_ and PGM_PAGE_SET_ macros for all
749	* accesses to the structure.
750	*/
751	typedef union PGMPAGE
752	{
753	/** Structured view. */
754	struct
755	{
756	/** 1:0 - The physical handler state (PGM_PAGE_HNDL_PHYS_STATE_). /
757	uint64_t u2HandlerPhysStateY : 2;
758	/** 3:2 - Paging structure needed to map the page
759	* (PGM_PAGE_PDE_TYPE_). /
760	uint64_t u2PDETypeY : 2;
761	/** 4 - Indicator of dirty page for fault tolerance tracking. */
762	uint64_t fFTDirtyY : 1;
763	/** 5 - Flag indicating that a write monitored page was written to
764	* when set. */
765	uint64_t fWrittenToY : 1;
766	/** 7:6 - Unused. */
767	uint64_t u2Unused0 : 2;
768	/** 9:8 - The physical handler state (PGM_PAGE_HNDL_VIRT_STATE_). /
769	uint64_t u2HandlerVirtStateY : 2;
770	/** 11:10 - Unused. */
771	uint64_t u2Unused1 : 2;
772	/** 12:48 - The host physical frame number (shift left to get the
773	* address). */
774	uint64_t HCPhysFN : 36;
775	/** 50:48 - The page state. */
776	uint64_t uStateY : 3;
777	/** 51:53 - The page type (PGMPAGETYPE). */
778	uint64_t uTypeY : 3;
779	/** 63:54 - PTE index for usage tracking (page pool). */
780	uint64_t u10PteIdx : 10;
781
782	/** The GMM page ID.
783	* @remarks In the current implementation, MMIO2 and pages aliased to
784	* MMIO2 pages will be exploiting this field to calculate the
785	* ring-3 mapping address corresponding to the page.
786	* Later we may consider including MMIO2 management into GMM. */
787	uint32_t idPage;
788	/** Usage tracking (page pool). */
789	uint16_t u16TrackingY;
790	/** The number of read locks on this page. */
791	uint8_t cReadLocksY;
792	/** The number of write locks on this page. */
793	uint8_t cWriteLocksY;
794	} s;
795
796	/** 64-bit integer view. */
797	uint64_t au64[2];
798	/** 16-bit view. */
799	uint32_t au32[4];
800	/** 16-bit view. */
801	uint16_t au16[8];
802	/** 8-bit view. */
803	uint8_t au8[16];
804	} PGMPAGE;
805	AssertCompileSize(PGMPAGE, 16);
806	/** Pointer to a physical guest page. */
807	typedef PGMPAGE *PPGMPAGE;
808	/** Pointer to a const physical guest page. */
809	typedef const PGMPAGE *PCPGMPAGE;
810	/** Pointer to a physical guest page pointer. */
811	typedef PPGMPAGE *PPPGMPAGE;
812
813
814	/**
815	* Clears the page structure.
816	* @param a_pPage Pointer to the physical guest page tracking structure.
817	*/
818	#define PGM_PAGE_CLEAR(a_pPage) \
819	do { \
820	(a_pPage)->au64[0] = 0; \
821	(a_pPage)->au64[1] = 0; \
822	} while (0)
823
824	/**
825	* Initializes the page structure.
826	* @param a_pPage Pointer to the physical guest page tracking structure.
827	*/
828	#define PGM_PAGE_INIT(a_pPage, a_HCPhys, a_idPage, a_uType, a_uState) \
829	do { \
830	RTHCPHYS SetHCPhysTmp = (a_HCPhys); \
831	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
832	(a_pPage)->au64[0] = SetHCPhysTmp; \
833	(a_pPage)->au64[1] = 0; \
834	(a_pPage)->s.idPage = (a_idPage); \
835	(a_pPage)->s.uStateY = (a_uState); \
836	(a_pPage)->s.uTypeY = (a_uType); \
837	} while (0)
838
839	/**
840	* Initializes the page structure of a ZERO page.
841	* @param a_pPage Pointer to the physical guest page tracking structure.
842	* @param a_pVM The VM handle (for getting the zero page address).
843	* @param a_uType The page type (PGMPAGETYPE).
844	*/
845	#define PGM_PAGE_INIT_ZERO(a_pPage, a_pVM, a_uType) \
846	PGM_PAGE_INIT((a_pPage), (a_pVM)->pgm.s.HCPhysZeroPg, NIL_GMM_PAGEID, (a_uType), PGM_PAGE_STATE_ZERO)
847
848
849	/** @name The Page state, PGMPAGE::uStateY.
850	* @{ */
851	/** The zero page.
852	* This is a per-VM page that's never ever mapped writable. */
853	#define PGM_PAGE_STATE_ZERO 0
854	/** A allocated page.
855	* This is a per-VM page allocated from the page pool (or wherever
856	* we get MMIO2 pages from if the type is MMIO2).
857	*/
858	#define PGM_PAGE_STATE_ALLOCATED 1
859	/** A allocated page that's being monitored for writes.
860	* The shadow page table mappings are read-only. When a write occurs, the
861	* fWrittenTo member is set, the page remapped as read-write and the state
862	* moved back to allocated. */
863	#define PGM_PAGE_STATE_WRITE_MONITORED 2
864	/** The page is shared, aka. copy-on-write.
865	* This is a page that's shared with other VMs. */
866	#define PGM_PAGE_STATE_SHARED 3
867	/** The page is ballooned, so no longer available for this VM. */
868	#define PGM_PAGE_STATE_BALLOONED 4
869	/** @} */
870
871
872	/** Asserts lock ownership in some of the PGM_PAGE_XXX macros. */
873	#if defined(VBOX_STRICT) && 0 /** @todo triggers in pgmRZDynMapGCPageV2Inlined */
874	# define PGM_PAGE_ASSERT_LOCK(a_pVM) PGM_LOCK_ASSERT_OWNER(a_pVM)
875	#else
876	# define PGM_PAGE_ASSERT_LOCK(a_pVM) do { } while (0)
877	#endif
878
879	/**
880	* Gets the page state.
881	* @returns page state (PGM_PAGE_STATE_*).
882	* @param a_pPage Pointer to the physical guest page tracking structure.
883	*
884	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
885	* builds.
886	*/
887	#define PGM_PAGE_GET_STATE_NA(a_pPage) ( (a_pPage)->s.uStateY )
888	#if defined(__GNUC__) && defined(VBOX_STRICT)
889	# define PGM_PAGE_GET_STATE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_STATE_NA(a_pPage); })
890	#else
891	# define PGM_PAGE_GET_STATE PGM_PAGE_GET_STATE_NA
892	#endif
893
894	/**
895	* Sets the page state.
896	* @param a_pVM The VM handle, only used for lock ownership assertions.
897	* @param a_pPage Pointer to the physical guest page tracking structure.
898	* @param a_uState The new page state.
899	*/
900	#define PGM_PAGE_SET_STATE(a_pVM, a_pPage, a_uState) \
901	do { (a_pPage)->s.uStateY = (a_uState); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
902
903
904	/**
905	* Gets the host physical address of the guest page.
906	* @returns host physical address (RTHCPHYS).
907	* @param a_pPage Pointer to the physical guest page tracking structure.
908	*
909	* @remarks In strict builds on gcc platforms, this macro will make some ugly
910	* assumption about a valid pVM variable/parameter being in the
911	* current context. It will use this pVM variable to assert that the
912	* PGM lock is held. Use the PGM_PAGE_GET_HCPHYS_NA in contexts where
913	* pVM is not around.
914	*/
915	#if 0
916	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->s.HCPhysFN << 12 )
917	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
918	#else
919	# define PGM_PAGE_GET_HCPHYS_NA(a_pPage) ( (a_pPage)->au64[0] & UINT64_C(0x0000fffffffff000) )
920	# if defined(__GNUC__) && defined(VBOX_STRICT)
921	# define PGM_PAGE_GET_HCPHYS(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_HCPHYS_NA(a_pPage); })
922	# else
923	# define PGM_PAGE_GET_HCPHYS PGM_PAGE_GET_HCPHYS_NA
924	# endif
925	#endif
926
927	/**
928	* Sets the host physical address of the guest page.
929	*
930	* @param a_pVM The VM handle, only used for lock ownership assertions.
931	* @param a_pPage Pointer to the physical guest page tracking structure.
932	* @param a_HCPhys The new host physical address.
933	*/
934	#define PGM_PAGE_SET_HCPHYS(a_pVM, a_pPage, a_HCPhys) \
935	do { \
936	RTHCPHYS const SetHCPhysTmp = (a_HCPhys); \
937	AssertFatal(!(SetHCPhysTmp & ~UINT64_C(0x0000fffffffff000))); \
938	(a_pPage)->s.HCPhysFN = SetHCPhysTmp >> 12; \
939	PGM_PAGE_ASSERT_LOCK(a_pVM); \
940	} while (0)
941
942	/**
943	* Get the Page ID.
944	* @returns The Page ID; NIL_GMM_PAGEID if it's a ZERO page.
945	* @param a_pPage Pointer to the physical guest page tracking structure.
946	*/
947	#define PGM_PAGE_GET_PAGEID(a_pPage) ( (uint32_t)(a_pPage)->s.idPage )
948
949	/**
950	* Sets the Page ID.
951	* @param a_pVM The VM handle, only used for lock ownership assertions.
952	* @param a_pPage Pointer to the physical guest page tracking structure.
953	* @param a_idPage The new page ID.
954	*/
955	#define PGM_PAGE_SET_PAGEID(a_pVM, a_pPage, a_idPage) \
956	do { \
957	(a_pPage)->s.idPage = (a_idPage); \
958	PGM_PAGE_ASSERT_LOCK(a_pVM); \
959	} while (0)
960
961	/**
962	* Get the Chunk ID.
963	* @returns The Chunk ID; NIL_GMM_CHUNKID if it's a ZERO page.
964	* @param a_pPage Pointer to the physical guest page tracking structure.
965	*/
966	#define PGM_PAGE_GET_CHUNKID(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) >> GMM_CHUNKID_SHIFT )
967
968	/**
969	* Get the index of the page within the allocation chunk.
970	* @returns The page index.
971	* @param a_pPage Pointer to the physical guest page tracking structure.
972	*/
973	#define PGM_PAGE_GET_PAGE_IN_CHUNK(a_pPage) ( PGM_PAGE_GET_PAGEID(a_pPage) & GMM_PAGEID_IDX_MASK )
974
975	/**
976	* Gets the page type.
977	* @returns The page type.
978	* @param a_pPage Pointer to the physical guest page tracking structure.
979	*
980	* @remarks See PGM_PAGE_GET_HCPHYS_NA for remarks about GCC and strict
981	* builds.
982	*/
983	#define PGM_PAGE_GET_TYPE_NA(a_pPage) ( (a_pPage)->s.uTypeY )
984	#if defined(__GNUC__) && defined(VBOX_STRICT)
985	# define PGM_PAGE_GET_TYPE(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TYPE_NA(a_pPage); })
986	#else
987	# define PGM_PAGE_GET_TYPE PGM_PAGE_GET_TYPE_NA
988	#endif
989
990	/**
991	* Sets the page type.
992	*
993	* @param a_pVM The VM handle, only used for lock ownership assertions.
994	* @param a_pPage Pointer to the physical guest page tracking structure.
995	* @param a_enmType The new page type (PGMPAGETYPE).
996	*/
997	#define PGM_PAGE_SET_TYPE(a_pVM, a_pPage, a_enmType) \
998	do { (a_pPage)->s.uTypeY = (a_enmType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
999
1000	/**
1001	* Gets the page table index
1002	* @returns The page table index.
1003	* @param a_pPage Pointer to the physical guest page tracking structure.
1004	*/
1005	#define PGM_PAGE_GET_PTE_INDEX(a_pPage) ( (a_pPage)->s.u10PteIdx )
1006
1007	/**
1008	* Sets the page table index.
1009	* @param a_pVM The VM handle, only used for lock ownership assertions.
1010	* @param a_pPage Pointer to the physical guest page tracking structure.
1011	* @param a_iPte New page table index.
1012	*/
1013	#define PGM_PAGE_SET_PTE_INDEX(a_pVM, a_pPage, a_iPte) \
1014	do { (a_pPage)->s.u10PteIdx = (a_iPte); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1015
1016	/**
1017	* Checks if the page is marked for MMIO, no MMIO2 aliasing.
1018	* @returns true/false.
1019	* @param a_pPage Pointer to the physical guest page tracking structure.
1020	*/
1021	#define PGM_PAGE_IS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO )
1022
1023	/**
1024	* Checks if the page is marked for MMIO, including both aliases.
1025	* @returns true/false.
1026	* @param a_pPage Pointer to the physical guest page tracking structure.
1027	*/
1028	#define PGM_PAGE_IS_MMIO_OR_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1029	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO2_ALIAS_MMIO \
1030	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO \
1031	)
1032
1033	/**
1034	* Checks if the page is marked for MMIO, including special aliases.
1035	* @returns true/false.
1036	* @param a_pPage Pointer to the physical guest page tracking structure.
1037	*/
1038	#define PGM_PAGE_IS_MMIO_OR_SPECIAL_ALIAS(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_MMIO \
1039	\|\| (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1040
1041	/**
1042	* Checks if the page is a special aliased MMIO page.
1043	* @returns true/false.
1044	* @param a_pPage Pointer to the physical guest page tracking structure.
1045	*/
1046	#define PGM_PAGE_IS_SPECIAL_ALIAS_MMIO(a_pPage) ( (a_pPage)->s.uTypeY == PGMPAGETYPE_SPECIAL_ALIAS_MMIO )
1047
1048	/**
1049	* Checks if the page is backed by the ZERO page.
1050	* @returns true/false.
1051	* @param a_pPage Pointer to the physical guest page tracking structure.
1052	*/
1053	#define PGM_PAGE_IS_ZERO(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ZERO )
1054
1055	/**
1056	* Checks if the page is backed by a SHARED page.
1057	* @returns true/false.
1058	* @param a_pPage Pointer to the physical guest page tracking structure.
1059	*/
1060	#define PGM_PAGE_IS_SHARED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_SHARED )
1061
1062	/**
1063	* Checks if the page is ballooned.
1064	* @returns true/false.
1065	* @param a_pPage Pointer to the physical guest page tracking structure.
1066	*/
1067	#define PGM_PAGE_IS_BALLOONED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_BALLOONED )
1068
1069	/**
1070	* Checks if the page is allocated.
1071	* @returns true/false.
1072	* @param a_pPage Pointer to the physical guest page tracking structure.
1073	*/
1074	#define PGM_PAGE_IS_ALLOCATED(a_pPage) ( (a_pPage)->s.uStateY == PGM_PAGE_STATE_ALLOCATED )
1075
1076	/**
1077	* Marks the page as written to (for GMM change monitoring).
1078	* @param a_pVM The VM handle, only used for lock ownership assertions.
1079	* @param a_pPage Pointer to the physical guest page tracking structure.
1080	*/
1081	#define PGM_PAGE_SET_WRITTEN_TO(a_pVM, a_pPage) \
1082	do { (a_pPage)->s.fWrittenToY = 1; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1083
1084	/**
1085	* Clears the written-to indicator.
1086	* @param a_pVM The VM handle, only used for lock ownership assertions.
1087	* @param a_pPage Pointer to the physical guest page tracking structure.
1088	*/
1089	#define PGM_PAGE_CLEAR_WRITTEN_TO(a_pVM, a_pPage) \
1090	do { (a_pPage)->s.fWrittenToY = 0; PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1091
1092	/**
1093	* Checks if the page was marked as written-to.
1094	* @returns true/false.
1095	* @param a_pPage Pointer to the physical guest page tracking structure.
1096	*/
1097	#define PGM_PAGE_IS_WRITTEN_TO(a_pPage) ( (a_pPage)->s.fWrittenToY )
1098
1099	/**
1100	* Marks the page as dirty for FTM
1101	* @param a_pPage Pointer to the physical guest page tracking structure.
1102	*/
1103	#define PGM_PAGE_SET_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 1; } while (0)
1104
1105	/**
1106	* Clears the FTM dirty indicator
1107	* @param a_pPage Pointer to the physical guest page tracking structure.
1108	*/
1109	#define PGM_PAGE_CLEAR_FT_DIRTY(a_pPage) do { (a_pPage)->s.fFTDirtyY = 0; } while (0)
1110
1111	/**
1112	* Checks if the page was marked as dirty for FTM
1113	* @returns true/false.
1114	* @param a_pPage Pointer to the physical guest page tracking structure.
1115	*/
1116	#define PGM_PAGE_IS_FT_DIRTY(a_pPage) ( (a_pPage)->s.fFTDirtyY )
1117
1118
1119	/** @name PT usage values (PGMPAGE::u2PDEType).
1120	*
1121	* @{ */
1122	/** Either as a PT or PDE. */
1123	#define PGM_PAGE_PDE_TYPE_DONTCARE 0
1124	/** Must use a page table to map the range. */
1125	#define PGM_PAGE_PDE_TYPE_PT 1
1126	/** Can use a page directory entry to map the continuous range. */
1127	#define PGM_PAGE_PDE_TYPE_PDE 2
1128	/** Can use a page directory entry to map the continuous range - temporarily disabled (by page monitoring). */
1129	#define PGM_PAGE_PDE_TYPE_PDE_DISABLED 3
1130	/** @} */
1131
1132	/**
1133	* Set the PDE type of the page
1134	* @param a_pVM The VM handle, only used for lock ownership assertions.
1135	* @param a_pPage Pointer to the physical guest page tracking structure.
1136	* @param a_uType PGM_PAGE_PDE_TYPE_*.
1137	*/
1138	#define PGM_PAGE_SET_PDE_TYPE(a_pVM, a_pPage, a_uType) \
1139	do { (a_pPage)->s.u2PDETypeY = (a_uType); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1140
1141	/**
1142	* Checks if the page was marked being part of a large page
1143	* @returns true/false.
1144	* @param a_pPage Pointer to the physical guest page tracking structure.
1145	*/
1146	#define PGM_PAGE_GET_PDE_TYPE(a_pPage) ( (a_pPage)->s.u2PDETypeY )
1147
1148	/** Enabled optimized access handler tests.
1149	* These optimizations makes ASSUMPTIONS about the state values and the s1
1150	* layout. When enabled, the compiler should normally generate more compact
1151	* code.
1152	*/
1153	#define PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS 1
1154
1155	/** @name Physical Access Handler State values (PGMPAGE::u2HandlerPhysStateY).
1156	*
1157	* @remarks The values are assigned in order of priority, so we can calculate
1158	* the correct state for a page with different handlers installed.
1159	* @{ */
1160	/** No handler installed. */
1161	#define PGM_PAGE_HNDL_PHYS_STATE_NONE 0
1162	/** Monitoring is temporarily disabled. */
1163	#define PGM_PAGE_HNDL_PHYS_STATE_DISABLED 1
1164	/** Write access is monitored. */
1165	#define PGM_PAGE_HNDL_PHYS_STATE_WRITE 2
1166	/** All access is monitored. */
1167	#define PGM_PAGE_HNDL_PHYS_STATE_ALL 3
1168	/** @} */
1169
1170	/**
1171	* Gets the physical access handler state of a page.
1172	* @returns PGM_PAGE_HNDL_PHYS_STATE_* value.
1173	* @param a_pPage Pointer to the physical guest page tracking structure.
1174	*/
1175	#define PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) ( (a_pPage)->s.u2HandlerPhysStateY )
1176
1177	/**
1178	* Sets the physical access handler state of a page.
1179	* @param a_pPage Pointer to the physical guest page tracking structure.
1180	* @param a_uState The new state value.
1181	*/
1182	#define PGM_PAGE_SET_HNDL_PHYS_STATE(a_pPage, a_uState) \
1183	do { (a_pPage)->s.u2HandlerPhysStateY = (a_uState); } while (0)
1184
1185	/**
1186	* Checks if the page has any physical access handlers, including temporarily disabled ones.
1187	* @returns true/false
1188	* @param a_pPage Pointer to the physical guest page tracking structure.
1189	*/
1190	#define PGM_PAGE_HAS_ANY_PHYSICAL_HANDLERS(a_pPage) \
1191	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE )
1192
1193	/**
1194	* Checks if the page has any active physical access handlers.
1195	* @returns true/false
1196	* @param a_pPage Pointer to the physical guest page tracking structure.
1197	*/
1198	#define PGM_PAGE_HAS_ACTIVE_PHYSICAL_HANDLERS(a_pPage) \
1199	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE )
1200
1201
1202	/** @name Virtual Access Handler State values (PGMPAGE::u2HandlerVirtStateY).
1203	*
1204	* @remarks The values are assigned in order of priority, so we can calculate
1205	* the correct state for a page with different handlers installed.
1206	* @{ */
1207	/** No handler installed. */
1208	#define PGM_PAGE_HNDL_VIRT_STATE_NONE 0
1209	/* 1 is reserved so the lineup is identical with the physical ones. */
1210	/** Write access is monitored. */
1211	#define PGM_PAGE_HNDL_VIRT_STATE_WRITE 2
1212	/** All access is monitored. */
1213	#define PGM_PAGE_HNDL_VIRT_STATE_ALL 3
1214	/** @} */
1215
1216	/**
1217	* Gets the virtual access handler state of a page.
1218	* @returns PGM_PAGE_HNDL_VIRT_STATE_* value.
1219	* @param a_pPage Pointer to the physical guest page tracking structure.
1220	*/
1221	#define PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) ( (a_pPage)->s.u2HandlerVirtStateY )
1222
1223	/**
1224	* Sets the virtual access handler state of a page.
1225	* @param a_pPage Pointer to the physical guest page tracking structure.
1226	* @param a_uState The new state value.
1227	*/
1228	#define PGM_PAGE_SET_HNDL_VIRT_STATE(a_pPage, a_uState) \
1229	do { (a_pPage)->s.u2HandlerVirtStateY = (a_uState); } while (0)
1230
1231	/**
1232	* Checks if the page has any virtual access handlers.
1233	* @returns true/false
1234	* @param a_pPage Pointer to the physical guest page tracking structure.
1235	*/
1236	#define PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage) \
1237	( PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1238
1239	/**
1240	* Same as PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS - can't disable pages in
1241	* virtual handlers.
1242	* @returns true/false
1243	* @param a_pPage Pointer to the physical guest page tracking structure.
1244	*/
1245	#define PGM_PAGE_HAS_ACTIVE_VIRTUAL_HANDLERS(a_pPage) \
1246	PGM_PAGE_HAS_ANY_VIRTUAL_HANDLERS(a_pPage)
1247
1248
1249	/**
1250	* Checks if the page has any access handlers, including temporarily disabled ones.
1251	* @returns true/false
1252	* @param a_pPage Pointer to the physical guest page tracking structure.
1253	*/
1254	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1255	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1256	( ((a_pPage)->au32[0] & UINT16_C(0x0303)) != 0 )
1257	#else
1258	# define PGM_PAGE_HAS_ANY_HANDLERS(a_pPage) \
1259	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) != PGM_PAGE_HNDL_PHYS_STATE_NONE \
1260	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) != PGM_PAGE_HNDL_VIRT_STATE_NONE )
1261	#endif
1262
1263	/**
1264	* Checks if the page has any active access handlers.
1265	* @returns true/false
1266	* @param a_pPage Pointer to the physical guest page tracking structure.
1267	*/
1268	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1269	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1270	( ((a_pPage)->au32[0] & UINT16_C(0x0202)) != 0 )
1271	#else
1272	# define PGM_PAGE_HAS_ACTIVE_HANDLERS(a_pPage) \
1273	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) >= PGM_PAGE_HNDL_PHYS_STATE_WRITE \
1274	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) >= PGM_PAGE_HNDL_VIRT_STATE_WRITE )
1275	#endif
1276
1277	/**
1278	* Checks if the page has any active access handlers catching all accesses.
1279	* @returns true/false
1280	* @param a_pPage Pointer to the physical guest page tracking structure.
1281	*/
1282	#ifdef PGM_PAGE_WITH_OPTIMIZED_HANDLER_ACCESS
1283	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1284	( ( ((a_pPage)->au8[0] \| (a_pPage)->au8[1]) & UINT8_C(0x3) ) \
1285	== PGM_PAGE_HNDL_PHYS_STATE_ALL )
1286	#else
1287	# define PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(a_pPage) \
1288	( PGM_PAGE_GET_HNDL_PHYS_STATE(a_pPage) == PGM_PAGE_HNDL_PHYS_STATE_ALL \
1289	\|\| PGM_PAGE_GET_HNDL_VIRT_STATE(a_pPage) == PGM_PAGE_HNDL_VIRT_STATE_ALL )
1290	#endif
1291
1292
1293	/** @def PGM_PAGE_GET_TRACKING
1294	* Gets the packed shadow page pool tracking data associated with a guest page.
1295	* @returns uint16_t containing the data.
1296	* @param a_pPage Pointer to the physical guest page tracking structure.
1297	*/
1298	#define PGM_PAGE_GET_TRACKING_NA(a_pPage) ( (a_pPage)->s.u16TrackingY )
1299	#if defined(__GNUC__) && defined(VBOX_STRICT)
1300	# define PGM_PAGE_GET_TRACKING(a_pPage) __extension__ ({ PGM_PAGE_ASSERT_LOCK(pVM); PGM_PAGE_GET_TRACKING_NA(a_pPage); })
1301	#else
1302	# define PGM_PAGE_GET_TRACKING PGM_PAGE_GET_TRACKING_NA
1303	#endif
1304
1305	/** @def PGM_PAGE_SET_TRACKING
1306	* Sets the packed shadow page pool tracking data associated with a guest page.
1307	* @param a_pVM The VM handle, only used for lock ownership assertions.
1308	* @param a_pPage Pointer to the physical guest page tracking structure.
1309	* @param a_u16TrackingData The tracking data to store.
1310	*/
1311	#define PGM_PAGE_SET_TRACKING(a_pVM, a_pPage, a_u16TrackingData) \
1312	do { (a_pPage)->s.u16TrackingY = (a_u16TrackingData); PGM_PAGE_ASSERT_LOCK(a_pVM); } while (0)
1313
1314	/** @def PGM_PAGE_GET_TD_CREFS
1315	* Gets the @a cRefs tracking data member.
1316	* @returns cRefs.
1317	* @param a_pPage Pointer to the physical guest page tracking structure.
1318	*/
1319	#define PGM_PAGE_GET_TD_CREFS(a_pPage) \
1320	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1321	#define PGM_PAGE_GET_TD_CREFS_NA(a_pPage) \
1322	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK)
1323
1324	/** @def PGM_PAGE_GET_TD_IDX
1325	* Gets the @a idx tracking data member.
1326	* @returns idx.
1327	* @param a_pPage Pointer to the physical guest page tracking structure.
1328	*/
1329	#define PGM_PAGE_GET_TD_IDX(a_pPage) \
1330	((PGM_PAGE_GET_TRACKING(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1331	#define PGM_PAGE_GET_TD_IDX_NA(a_pPage) \
1332	((PGM_PAGE_GET_TRACKING_NA(a_pPage) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK)
1333
1334
1335	/** Max number of locks on a page. */
1336	#define PGM_PAGE_MAX_LOCKS UINT8_C(254)
1337
1338	/** Get the read lock count.
1339	* @returns count.
1340	* @param a_pPage Pointer to the physical guest page tracking structure.
1341	*/
1342	#define PGM_PAGE_GET_READ_LOCKS(a_pPage) ( (a_pPage)->s.cReadLocksY )
1343
1344	/** Get the write lock count.
1345	* @returns count.
1346	* @param a_pPage Pointer to the physical guest page tracking structure.
1347	*/
1348	#define PGM_PAGE_GET_WRITE_LOCKS(a_pPage) ( (a_pPage)->s.cWriteLocksY )
1349
1350	/** Decrement the read lock counter.
1351	* @param a_pPage Pointer to the physical guest page tracking structure.
1352	*/
1353	#define PGM_PAGE_DEC_READ_LOCKS(a_pPage) do { --(a_pPage)->s.cReadLocksY; } while (0)
1354
1355	/** Decrement the write lock counter.
1356	* @param a_pPage Pointer to the physical guest page tracking structure.
1357	*/
1358	#define PGM_PAGE_DEC_WRITE_LOCKS(a_pPage) do { --(a_pPage)->s.cWriteLocksY; } while (0)
1359
1360	/** Increment the read lock counter.
1361	* @param a_pPage Pointer to the physical guest page tracking structure.
1362	*/
1363	#define PGM_PAGE_INC_READ_LOCKS(a_pPage) do { ++(a_pPage)->s.cReadLocksY; } while (0)
1364
1365	/** Increment the write lock counter.
1366	* @param a_pPage Pointer to the physical guest page tracking structure.
1367	*/
1368	#define PGM_PAGE_INC_WRITE_LOCKS(a_pPage) do { ++(a_pPage)->s.cWriteLocksY; } while (0)
1369
1370
1371	#if 0
1372	/** Enables sanity checking of write monitoring using CRC-32. */
1373	# define PGMLIVESAVERAMPAGE_WITH_CRC32
1374	#endif
1375
1376	/**
1377	* Per page live save tracking data.
1378	*/
1379	typedef struct PGMLIVESAVERAMPAGE
1380	{
1381	/** Number of times it has been dirtied. */
1382	uint32_t cDirtied : 24;
1383	/** Whether it is currently dirty. */
1384	uint32_t fDirty : 1;
1385	/** Ignore the page.
1386	* This is used for pages that has been MMIO, MMIO2 or ROM pages once. We will
1387	* deal with these after pausing the VM and DevPCI have said it bit about
1388	* remappings. */
1389	uint32_t fIgnore : 1;
1390	/** Was a ZERO page last time around. */
1391	uint32_t fZero : 1;
1392	/** Was a SHARED page last time around. */
1393	uint32_t fShared : 1;
1394	/** Whether the page is/was write monitored in a previous pass. */
1395	uint32_t fWriteMonitored : 1;
1396	/** Whether the page is/was write monitored earlier in this pass. */
1397	uint32_t fWriteMonitoredJustNow : 1;
1398	/** Bits reserved for future use. */
1399	uint32_t u2Reserved : 2;
1400	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1401	/** CRC-32 for the page. This is for internal consistency checks. */
1402	uint32_t u32Crc;
1403	#endif
1404	} PGMLIVESAVERAMPAGE;
1405	#ifdef PGMLIVESAVERAMPAGE_WITH_CRC32
1406	AssertCompileSize(PGMLIVESAVERAMPAGE, 8);
1407	#else
1408	AssertCompileSize(PGMLIVESAVERAMPAGE, 4);
1409	#endif
1410	/** Pointer to the per page live save tracking data. */
1411	typedef PGMLIVESAVERAMPAGE *PPGMLIVESAVERAMPAGE;
1412
1413	/** The max value of PGMLIVESAVERAMPAGE::cDirtied. */
1414	#define PGMLIVSAVEPAGE_MAX_DIRTIED 0x00fffff0
1415
1416
1417	/**
1418	* RAM range for GC Phys to HC Phys conversion.
1419	*
1420	* Can be used for HC Virt to GC Phys and HC Virt to HC Phys
1421	* conversions too, but we'll let MM handle that for now.
1422	*
1423	* This structure is used by linked lists in both GC and HC.
1424	*/
1425	typedef struct PGMRAMRANGE
1426	{
1427	/** Start of the range. Page aligned. */
1428	RTGCPHYS GCPhys;
1429	/** Size of the range. (Page aligned of course). */
1430	RTGCPHYS cb;
1431	/** Pointer to the next RAM range - for R3. */
1432	R3PTRTYPE(struct PGMRAMRANGE *) pNextR3;
1433	/** Pointer to the next RAM range - for R0. */
1434	R0PTRTYPE(struct PGMRAMRANGE *) pNextR0;
1435	/** Pointer to the next RAM range - for RC. */
1436	RCPTRTYPE(struct PGMRAMRANGE *) pNextRC;
1437	/** PGM_RAM_RANGE_FLAGS_* flags. */
1438	uint32_t fFlags;
1439	/** Last address in the range (inclusive). Page aligned (-1). */
1440	RTGCPHYS GCPhysLast;
1441	/** Start of the HC mapping of the range. This is only used for MMIO2. */
1442	R3PTRTYPE(void *) pvR3;
1443	/** Live save per page tracking data. */
1444	R3PTRTYPE(PPGMLIVESAVERAMPAGE) paLSPages;
1445	/** The range description. */
1446	R3PTRTYPE(const char *) pszDesc;
1447	/** Pointer to self - R0 pointer. */
1448	R0PTRTYPE(struct PGMRAMRANGE *) pSelfR0;
1449	/** Pointer to self - RC pointer. */
1450	RCPTRTYPE(struct PGMRAMRANGE *) pSelfRC;
1451
1452	/** Alignment padding. */
1453	RTRCPTR Alignment0;
1454	/** Pointer to the left search three node - ring-3 context. */
1455	R3PTRTYPE(struct PGMRAMRANGE *) pLeftR3;
1456	/** Pointer to the right search three node - ring-3 context. */
1457	R3PTRTYPE(struct PGMRAMRANGE *) pRightR3;
1458	/** Pointer to the left search three node - ring-0 context. */
1459	R0PTRTYPE(struct PGMRAMRANGE *) pLeftR0;
1460	/** Pointer to the right search three node - ring-0 context. */
1461	R0PTRTYPE(struct PGMRAMRANGE *) pRightR0;
1462	/** Pointer to the left search three node - raw-mode context. */
1463	RCPTRTYPE(struct PGMRAMRANGE *) pLeftRC;
1464	/** Pointer to the right search three node - raw-mode context. */
1465	RCPTRTYPE(struct PGMRAMRANGE *) pRightRC;
1466
1467	/** Padding to make aPage aligned on sizeof(PGMPAGE). */
1468	#if HC_ARCH_BITS == 32
1469	uint32_t au32Alignment2[HC_ARCH_BITS == 32 ? 2 : 0];
1470	#endif
1471	/** Array of physical guest page tracking structures. */
1472	PGMPAGE aPages[1];
1473	} PGMRAMRANGE;
1474	/** Pointer to RAM range for GC Phys to HC Phys conversion. */
1475	typedef PGMRAMRANGE *PPGMRAMRANGE;
1476
1477	/** @name PGMRAMRANGE::fFlags
1478	* @{ */
1479	/** The RAM range is floating around as an independent guest mapping. */
1480	#define PGM_RAM_RANGE_FLAGS_FLOATING RT_BIT(20)
1481	/** Ad hoc RAM range for an ROM mapping. */
1482	#define PGM_RAM_RANGE_FLAGS_AD_HOC_ROM RT_BIT(21)
1483	/** Ad hoc RAM range for an MMIO mapping. */
1484	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO RT_BIT(22)
1485	/** Ad hoc RAM range for an MMIO2 mapping. */
1486	#define PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2 RT_BIT(23)
1487	/** @} */
1488
1489	/** Tests if a RAM range is an ad hoc one or not.
1490	* @returns true/false.
1491	* @param pRam The RAM range.
1492	*/
1493	#define PGM_RAM_RANGE_IS_AD_HOC(pRam) \
1494	(!!( (pRam)->fFlags & (PGM_RAM_RANGE_FLAGS_AD_HOC_ROM \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO \| PGM_RAM_RANGE_FLAGS_AD_HOC_MMIO2) ) )
1495
1496	/** The number of entries in the RAM range TLBs (there is one for each
1497	* context). Must be a power of two. */
1498	#define PGM_RAMRANGE_TLB_ENTRIES 8
1499
1500	/**
1501	* Calculates the RAM range TLB index for the physical address.
1502	*
1503	* @returns RAM range TLB index.
1504	* @param GCPhys The guest physical address.
1505	*/
1506	#define PGM_RAMRANGE_TLB_IDX(a_GCPhys) ( ((a_GCPhys) >> 20) & (PGM_RAMRANGE_TLB_ENTRIES - 1) )
1507
1508
1509
1510	/**
1511	* Per page tracking structure for ROM image.
1512	*
1513	* A ROM image may have a shadow page, in which case we may have two pages
1514	* backing it. This structure contains the PGMPAGE for both while
1515	* PGMRAMRANGE have a copy of the active one. It is important that these
1516	* aren't out of sync in any regard other than page pool tracking data.
1517	*/
1518	typedef struct PGMROMPAGE
1519	{
1520	/** The page structure for the virgin ROM page. */
1521	PGMPAGE Virgin;
1522	/** The page structure for the shadow RAM page. */
1523	PGMPAGE Shadow;
1524	/** The current protection setting. */
1525	PGMROMPROT enmProt;
1526	/** Live save status information. Makes use of unused alignment space. */
1527	struct
1528	{
1529	/** The previous protection value. */
1530	uint8_t u8Prot;
1531	/** Written to flag set by the handler. */
1532	bool fWrittenTo;
1533	/** Whether the shadow page is dirty or not. */
1534	bool fDirty;
1535	/** Whether it was dirtied in the recently. */
1536	bool fDirtiedRecently;
1537	} LiveSave;
1538	} PGMROMPAGE;
1539	AssertCompileSizeAlignment(PGMROMPAGE, 8);
1540	/** Pointer to a ROM page tracking structure. */
1541	typedef PGMROMPAGE *PPGMROMPAGE;
1542
1543
1544	/**
1545	* A registered ROM image.
1546	*
1547	* This is needed to keep track of ROM image since they generally intrude
1548	* into a PGMRAMRANGE. It also keeps track of additional info like the
1549	* two page sets (read-only virgin and read-write shadow), the current
1550	* state of each page.
1551	*
1552	* Because access handlers cannot easily be executed in a different
1553	* context, the ROM ranges needs to be accessible and in all contexts.
1554	*/
1555	typedef struct PGMROMRANGE
1556	{
1557	/** Pointer to the next range - R3. */
1558	R3PTRTYPE(struct PGMROMRANGE *) pNextR3;
1559	/** Pointer to the next range - R0. */
1560	R0PTRTYPE(struct PGMROMRANGE *) pNextR0;
1561	/** Pointer to the next range - RC. */
1562	RCPTRTYPE(struct PGMROMRANGE *) pNextRC;
1563	/** Pointer alignment */
1564	RTRCPTR RCPtrAlignment;
1565	/** Address of the range. */
1566	RTGCPHYS GCPhys;
1567	/** Address of the last byte in the range. */
1568	RTGCPHYS GCPhysLast;
1569	/** Size of the range. */
1570	RTGCPHYS cb;
1571	/** The flags (PGMPHYS_ROM_FLAGS_). /
1572	uint32_t fFlags;
1573	/** The saved state range ID. */
1574	uint8_t idSavedState;
1575	/** Alignment padding. */
1576	uint8_t au8Alignment[3];
1577	/** Alignment padding ensuring that aPages is sizeof(PGMROMPAGE) aligned. */
1578	uint32_t au32Alignemnt[HC_ARCH_BITS == 32 ? 5 : 1];
1579	/** The size bits pvOriginal points to. */
1580	uint32_t cbOriginal;
1581	/** Pointer to the original bits when PGMPHYS_ROM_FLAGS_PERMANENT_BINARY was specified.
1582	* This is used for strictness checks. */
1583	R3PTRTYPE(const void *) pvOriginal;
1584	/** The ROM description. */
1585	R3PTRTYPE(const char *) pszDesc;
1586	/** The per page tracking structures. */
1587	PGMROMPAGE aPages[1];
1588	} PGMROMRANGE;
1589	/** Pointer to a ROM range. */
1590	typedef PGMROMRANGE *PPGMROMRANGE;
1591
1592
1593	/**
1594	* Live save per page data for an MMIO2 page.
1595	*
1596	* Not using PGMLIVESAVERAMPAGE here because we cannot use normal write monitoring
1597	* of MMIO2 pages. The current approach is using some optimistic SHA-1 +
1598	* CRC-32 for detecting changes as well as special handling of zero pages. This
1599	* is a TEMPORARY measure which isn't perfect, but hopefully it is good enough
1600	* for speeding things up. (We're using SHA-1 and not SHA-256 or SHA-512
1601	* because of speed (2.5x and 6x slower).)
1602	*
1603	* @todo Implement dirty MMIO2 page reporting that can be enabled during live
1604	* save but normally is disabled. Since we can write monitor guest
1605	* accesses on our own, we only need this for host accesses. Shouldn't be
1606	* too difficult for DevVGA, VMMDev might be doable, the planned
1607	* networking fun will be fun since it involves ring-0.
1608	*/
1609	typedef struct PGMLIVESAVEMMIO2PAGE
1610	{
1611	/** Set if the page is considered dirty. */
1612	bool fDirty;
1613	/** The number of scans this page has remained unchanged for.
1614	* Only updated for dirty pages. */
1615	uint8_t cUnchangedScans;
1616	/** Whether this page was zero at the last scan. */
1617	bool fZero;
1618	/** Alignment padding. */
1619	bool fReserved;
1620	/** CRC-32 for the first half of the page.
1621	* This is used together with u32CrcH2 to quickly detect changes in the page
1622	* during the non-final passes. */
1623	uint32_t u32CrcH1;
1624	/** CRC-32 for the second half of the page. */
1625	uint32_t u32CrcH2;
1626	/** SHA-1 for the saved page.
1627	* This is used in the final pass to skip pages without changes. */
1628	uint8_t abSha1Saved[RTSHA1_HASH_SIZE];
1629	} PGMLIVESAVEMMIO2PAGE;
1630	/** Pointer to a live save status data for an MMIO2 page. */
1631	typedef PGMLIVESAVEMMIO2PAGE *PPGMLIVESAVEMMIO2PAGE;
1632
1633	/**
1634	* A registered MMIO2 (= Device RAM) range.
1635	*
1636	* There are a few reason why we need to keep track of these
1637	* registrations. One of them is the deregistration & cleanup stuff,
1638	* while another is that the PGMRAMRANGE associated with such a region may
1639	* have to be removed from the ram range list.
1640	*
1641	* Overlapping with a RAM range has to be 100% or none at all. The pages
1642	* in the existing RAM range must not be ROM nor MMIO. A guru meditation
1643	* will be raised if a partial overlap or an overlap of ROM pages is
1644	* encountered. On an overlap we will free all the existing RAM pages and
1645	* put in the ram range pages instead.
1646	*/
1647	typedef struct PGMMMIO2RANGE
1648	{
1649	/** The owner of the range. (a device) */
1650	PPDMDEVINSR3 pDevInsR3;
1651	/** Pointer to the ring-3 mapping of the allocation. */
1652	RTR3PTR pvR3;
1653	/** Pointer to the next range - R3. */
1654	R3PTRTYPE(struct PGMMMIO2RANGE *) pNextR3;
1655	/** Whether it's mapped or not. */
1656	bool fMapped;
1657	/** Whether it's overlapping or not. */
1658	bool fOverlapping;
1659	/** The PCI region number.
1660	* @remarks This ASSUMES that nobody will ever really need to have multiple
1661	* PCI devices with matching MMIO region numbers on a single device. */
1662	uint8_t iRegion;
1663	/** The saved state range ID. */
1664	uint8_t idSavedState;
1665	/** MMIO2 range identifier, for page IDs (PGMPAGE::s.idPage). */
1666	uint8_t idMmio2;
1667	/** Alignment padding for putting the ram range on a PGMPAGE alignment boundary. */
1668	uint8_t abAlignment[HC_ARCH_BITS == 32 ? 11 : 11];
1669	/** Live save per page tracking data. */
1670	R3PTRTYPE(PPGMLIVESAVEMMIO2PAGE) paLSPages;
1671	/** The associated RAM range. */
1672	PGMRAMRANGE RamRange;
1673	} PGMMMIO2RANGE;
1674	/** Pointer to a MMIO2 range. */
1675	typedef PGMMMIO2RANGE *PPGMMMIO2RANGE;
1676
1677	/** @name Intenal MMIO2 constants.
1678	* @{ */
1679	/** The maximum number of MMIO2 ranges. */
1680	#define PGM_MMIO2_MAX_RANGES 8
1681	/** The maximum number of pages in a MMIO2 range. */
1682	#define PGM_MMIO2_MAX_PAGE_COUNT UINT32_C(0x00ffffff)
1683	/** Makes a MMIO2 page ID out of a MMIO2 range ID and page index number. */
1684	#define PGM_MMIO2_PAGEID_MAKE(a_idMmio2, a_iPage) ( ((uint32_t)(a_idMmio2) << 24) \| (uint32_t)(a_iPage) )
1685	/** Gets the MMIO2 range ID from an MMIO2 page ID. */
1686	#define PGM_MMIO2_PAGEID_GET_MMIO2_ID(a_idPage) ( (uint8_t)((a_idPage) >> 24) )
1687	/** Gets the MMIO2 page index from an MMIO2 page ID. */
1688	#define PGM_MMIO2_PAGEID_GET_IDX(a_idPage) ( ((a_idPage) & UINT32_C(0x00ffffff)) )
1689	/** @} */
1690
1691
1692
1693	/**
1694	* PGMPhysRead/Write cache entry
1695	*/
1696	typedef struct PGMPHYSCACHEENTRY
1697	{
1698	/** R3 pointer to physical page. */
1699	R3PTRTYPE(uint8_t *) pbR3;
1700	/** GC Physical address for cache entry */
1701	RTGCPHYS GCPhys;
1702	#if HC_ARCH_BITS == 64 && GC_ARCH_BITS == 32
1703	RTGCPHYS u32Padding0; /*< alignment padding. /
1704	#endif
1705	} PGMPHYSCACHEENTRY;
1706
1707	/**
1708	* PGMPhysRead/Write cache to reduce REM memory access overhead
1709	*/
1710	typedef struct PGMPHYSCACHE
1711	{
1712	/** Bitmap of valid cache entries */
1713	uint64_t aEntries;
1714	/** Cache entries */
1715	PGMPHYSCACHEENTRY Entry[PGM_MAX_PHYSCACHE_ENTRIES];
1716	} PGMPHYSCACHE;
1717
1718
1719	/** Pointer to an allocation chunk ring-3 mapping. */
1720	typedef struct PGMCHUNKR3MAP *PPGMCHUNKR3MAP;
1721	/** Pointer to an allocation chunk ring-3 mapping pointer. */
1722	typedef PPGMCHUNKR3MAP *PPPGMCHUNKR3MAP;
1723
1724	/**
1725	* Ring-3 tracking structore for an allocation chunk ring-3 mapping.
1726	*
1727	* The primary tree (Core) uses the chunk id as key.
1728	*/
1729	typedef struct PGMCHUNKR3MAP
1730	{
1731	/** The key is the chunk id. */
1732	AVLU32NODECORE Core;
1733	/** The time (ChunkR3Map.iNow) this chunk was last used. Used for unmap
1734	* selection. */
1735	uint32_t iLastUsed;
1736	/** The current reference count. */
1737	uint32_t volatile cRefs;
1738	/** The current permanent reference count. */
1739	uint32_t volatile cPermRefs;
1740	/** The mapping address. */
1741	void *pv;
1742	} PGMCHUNKR3MAP;
1743
1744	/**
1745	* Allocation chunk ring-3 mapping TLB entry.
1746	*/
1747	typedef struct PGMCHUNKR3MAPTLBE
1748	{
1749	/** The chunk id. */
1750	uint32_t volatile idChunk;
1751	#if HC_ARCH_BITS == 64
1752	uint32_t u32Padding; /*< alignment padding. /
1753	#endif
1754	/** The chunk map. */
1755	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1756	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1757	#else
1758	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pChunk;
1759	#endif
1760	} PGMCHUNKR3MAPTLBE;
1761	/** Pointer to the an allocation chunk ring-3 mapping TLB entry. */
1762	typedef PGMCHUNKR3MAPTLBE *PPGMCHUNKR3MAPTLBE;
1763
1764	/** The number of TLB entries in PGMCHUNKR3MAPTLB.
1765	* @remark Must be a power of two value. */
1766	#define PGM_CHUNKR3MAPTLB_ENTRIES 64
1767
1768	/**
1769	* Allocation chunk ring-3 mapping TLB.
1770	*
1771	* @remarks We use a TLB to speed up lookups by avoiding walking the AVL.
1772	* At first glance this might look kinda odd since AVL trees are
1773	* supposed to give the most optimal lookup times of all trees
1774	* due to their balancing. However, take a tree with 1023 nodes
1775	* in it, that's 10 levels, meaning that most searches has to go
1776	* down 9 levels before they find what they want. This isn't fast
1777	* compared to a TLB hit. There is the factor of cache misses,
1778	* and of course the problem with trees and branch prediction.
1779	* This is why we use TLBs in front of most of the trees.
1780	*
1781	* @todo Generalize this TLB + AVL stuff, shouldn't be all that
1782	* difficult when we switch to the new inlined AVL trees (from kStuff).
1783	*/
1784	typedef struct PGMCHUNKR3MAPTLB
1785	{
1786	/** The TLB entries. */
1787	PGMCHUNKR3MAPTLBE aEntries[PGM_CHUNKR3MAPTLB_ENTRIES];
1788	} PGMCHUNKR3MAPTLB;
1789
1790	/**
1791	* Calculates the index of a guest page in the Ring-3 Chunk TLB.
1792	* @returns Chunk TLB index.
1793	* @param idChunk The Chunk ID.
1794	*/
1795	#define PGM_CHUNKR3MAPTLB_IDX(idChunk) ( (idChunk) & (PGM_CHUNKR3MAPTLB_ENTRIES - 1) )
1796
1797
1798	/**
1799	* Ring-3 guest page mapping TLB entry.
1800	* @remarks used in ring-0 as well at the moment.
1801	*/
1802	typedef struct PGMPAGER3MAPTLBE
1803	{
1804	/** Address of the page. */
1805	RTGCPHYS volatile GCPhys;
1806	/** The guest page. */
1807	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1808	R3PTRTYPE(PPGMPAGE) volatile pPage;
1809	#else
1810	R3R0PTRTYPE(PPGMPAGE) volatile pPage;
1811	#endif
1812	/** Pointer to the page mapping tracking structure, PGMCHUNKR3MAP. */
1813	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1814	R3PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1815	#else
1816	R3R0PTRTYPE(PPGMCHUNKR3MAP) volatile pMap;
1817	#endif
1818	/** The address */
1819	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1820	R3PTRTYPE(void *) volatile pv;
1821	#else
1822	R3R0PTRTYPE(void *) volatile pv;
1823	#endif
1824	#if HC_ARCH_BITS == 32
1825	uint32_t u32Padding; /*< alignment padding. /
1826	#endif
1827	} PGMPAGER3MAPTLBE;
1828	/** Pointer to an entry in the HC physical TLB. */
1829	typedef PGMPAGER3MAPTLBE *PPGMPAGER3MAPTLBE;
1830
1831
1832	/** The number of entries in the ring-3 guest page mapping TLB.
1833	* @remarks The value must be a power of two. */
1834	#define PGM_PAGER3MAPTLB_ENTRIES 256
1835
1836	/**
1837	* Ring-3 guest page mapping TLB.
1838	* @remarks used in ring-0 as well at the moment.
1839	*/
1840	typedef struct PGMPAGER3MAPTLB
1841	{
1842	/** The TLB entries. */
1843	PGMPAGER3MAPTLBE aEntries[PGM_PAGER3MAPTLB_ENTRIES];
1844	} PGMPAGER3MAPTLB;
1845	/** Pointer to the ring-3 guest page mapping TLB. */
1846	typedef PGMPAGER3MAPTLB *PPGMPAGER3MAPTLB;
1847
1848	/**
1849	* Calculates the index of the TLB entry for the specified guest page.
1850	* @returns Physical TLB index.
1851	* @param GCPhys The guest physical address.
1852	*/
1853	#define PGM_PAGER3MAPTLB_IDX(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGM_PAGER3MAPTLB_ENTRIES - 1) )
1854
1855
1856	/**
1857	* Raw-mode context dynamic mapping cache entry.
1858	*
1859	* Because of raw-mode context being reloctable and all relocations are applied
1860	* in ring-3, this has to be defined here and be RC specific.
1861	*
1862	* @sa PGMRZDYNMAPENTRY, PGMR0DYNMAPENTRY.
1863	*/
1864	typedef struct PGMRCDYNMAPENTRY
1865	{
1866	/** The physical address of the currently mapped page.
1867	* This is duplicate for three reasons: cache locality, cache policy of the PT
1868	* mappings and sanity checks. */
1869	RTHCPHYS HCPhys;
1870	/** Pointer to the page. */
1871	RTRCPTR pvPage;
1872	/** The number of references. */
1873	int32_t volatile cRefs;
1874	/** PTE pointer union. */
1875	struct PGMRCDYNMAPENTRY_PPTE
1876	{
1877	/** PTE pointer, 32-bit legacy version. */
1878	RCPTRTYPE(PX86PTE) pLegacy;
1879	/** PTE pointer, PAE version. */
1880	RCPTRTYPE(PX86PTEPAE) pPae;
1881	} uPte;
1882	} PGMRCDYNMAPENTRY;
1883	/** Pointer to a dynamic mapping cache entry for the raw-mode context. */
1884	typedef PGMRCDYNMAPENTRY *PPGMRCDYNMAPENTRY;
1885
1886
1887	/**
1888	* Dynamic mapping cache for the raw-mode context.
1889	*
1890	* This is initialized during VMMRC init based upon the pbDynPageMapBaseGC and
1891	* paDynPageMap* PGM members. However, it has to be defined in PGMInternal.h
1892	* so that we can perform relocations from PGMR3Relocate. This has the
1893	* consequence that we must have separate ring-0 and raw-mode context versions
1894	* of this struct even if they share the basic elements.
1895	*
1896	* @sa PPGMRZDYNMAP, PGMR0DYNMAP.
1897	*/
1898	typedef struct PGMRCDYNMAP
1899	{
1900	/** The usual magic number / eye catcher (PGMRZDYNMAP_MAGIC). */
1901	uint32_t u32Magic;
1902	/** Array for tracking and managing the pages. */
1903	RCPTRTYPE(PPGMRCDYNMAPENTRY) paPages;
1904	/** The cache size given as a number of pages. */
1905	uint32_t cPages;
1906	/** The current load.
1907	* This does not include guard pages. */
1908	uint32_t cLoad;
1909	/** The max load ever.
1910	* This is maintained to get trigger adding of more mapping space. */
1911	uint32_t cMaxLoad;
1912	/** The number of guard pages. */
1913	uint32_t cGuardPages;
1914	/** The number of users (protected by hInitLock). */
1915	uint32_t cUsers;
1916	} PGMRCDYNMAP;
1917	/** Pointer to the dynamic cache for the raw-mode context. */
1918	typedef PGMRCDYNMAP *PPGMRCDYNMAP;
1919
1920
1921	/**
1922	* Mapping cache usage set entry.
1923	*
1924	* @remarks 16-bit ints was chosen as the set is not expected to be used beyond
1925	* the dynamic ring-0 and (to some extent) raw-mode context mapping
1926	* cache. If it's extended to include ring-3, well, then something
1927	* will have be changed here...
1928	*/
1929	typedef struct PGMMAPSETENTRY
1930	{
1931	/** Pointer to the page. */
1932	#ifndef IN_RC
1933	RTR0PTR pvPage;
1934	#else
1935	RTRCPTR pvPage;
1936	# if HC_ARCH_BITS == 64
1937	uint32_t u32Alignment2;
1938	# endif
1939	#endif
1940	/** The mapping cache index. */
1941	uint16_t iPage;
1942	/** The number of references.
1943	* The max is UINT16_MAX - 1. */
1944	uint16_t cRefs;
1945	/** The number inlined references.
1946	* The max is UINT16_MAX - 1. */
1947	uint16_t cInlinedRefs;
1948	/** Unreferences. */
1949	uint16_t cUnrefs;
1950
1951	#if HC_ARCH_BITS == 32
1952	uint32_t u32Alignment1;
1953	#endif
1954	/** The physical address for this entry. */
1955	RTHCPHYS HCPhys;
1956	} PGMMAPSETENTRY;
1957	AssertCompileMemberOffset(PGMMAPSETENTRY, iPage, RT_MAX(sizeof(RTR0PTR), sizeof(RTRCPTR)));
1958	AssertCompileMemberAlignment(PGMMAPSETENTRY, HCPhys, sizeof(RTHCPHYS));
1959	/** Pointer to a mapping cache usage set entry. */
1960	typedef PGMMAPSETENTRY *PPGMMAPSETENTRY;
1961
1962	/**
1963	* Mapping cache usage set.
1964	*
1965	* This is used in ring-0 and the raw-mode context to track dynamic mappings
1966	* done during exits / traps. The set is
1967	*/
1968	typedef struct PGMMAPSET
1969	{
1970	/** The number of occupied entries.
1971	* This is PGMMAPSET_CLOSED if the set is closed and we're not supposed to do
1972	* dynamic mappings. */
1973	uint32_t cEntries;
1974	/** The start of the current subset.
1975	* This is UINT32_MAX if no subset is currently open. */
1976	uint32_t iSubset;
1977	/** The index of the current CPU, only valid if the set is open. */
1978	int32_t iCpu;
1979	uint32_t alignment;
1980	/** The entries. */
1981	PGMMAPSETENTRY aEntries[64];
1982	/** HCPhys -> iEntry fast lookup table.
1983	* Use PGMMAPSET_HASH for hashing.
1984	* The entries may or may not be valid, check against cEntries. */
1985	uint8_t aiHashTable[128];
1986	} PGMMAPSET;
1987	AssertCompileSizeAlignment(PGMMAPSET, 8);
1988	/** Pointer to the mapping cache set. */
1989	typedef PGMMAPSET *PPGMMAPSET;
1990
1991	/** PGMMAPSET::cEntries value for a closed set. */
1992	#define PGMMAPSET_CLOSED UINT32_C(0xdeadc0fe)
1993
1994	/** Hash function for aiHashTable. */
1995	#define PGMMAPSET_HASH(HCPhys) (((HCPhys) >> PAGE_SHIFT) & 127)
1996
1997
1998	/** @name Context neutral page mapper TLB.
1999	*
2000	* Hoping to avoid some code and bug duplication parts of the GCxxx->CCPtr
2001	* code is writting in a kind of context neutral way. Time will show whether
2002	* this actually makes sense or not...
2003	*
2004	* @todo this needs to be reconsidered and dropped/redone since the ring-0
2005	* context ends up using a global mapping cache on some platforms
2006	* (darwin).
2007	*
2008	* @{ */
2009	/** @typedef PPGMPAGEMAPTLB
2010	* The page mapper TLB pointer type for the current context. */
2011	/** @typedef PPGMPAGEMAPTLB
2012	* The page mapper TLB entry pointer type for the current context. */
2013	/** @typedef PPGMPAGEMAPTLB
2014	* The page mapper TLB entry pointer pointer type for the current context. */
2015	/** @def PGM_PAGEMAPTLB_ENTRIES
2016	* The number of TLB entries in the page mapper TLB for the current context. */
2017	/** @def PGM_PAGEMAPTLB_IDX
2018	* Calculate the TLB index for a guest physical address.
2019	* @returns The TLB index.
2020	* @param GCPhys The guest physical address. */
2021	/** @typedef PPGMPAGEMAP
2022	* Pointer to a page mapper unit for current context. */
2023	/** @typedef PPPGMPAGEMAP
2024	* Pointer to a page mapper unit pointer for current context. */
2025	#ifdef IN_RC
2026	// typedef PPGMPAGEGCMAPTLB PPGMPAGEMAPTLB;
2027	// typedef PPGMPAGEGCMAPTLBE PPGMPAGEMAPTLBE;
2028	// typedef PPGMPAGEGCMAPTLBE *PPPGMPAGEMAPTLBE;
2029	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGEGCMAPTLB_ENTRIES
2030	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGEGCMAPTLB_IDX(GCPhys)
2031	typedef void * PPGMPAGEMAP;
2032	typedef void ** PPPGMPAGEMAP;
2033	//#elif IN_RING0
2034	// typedef PPGMPAGER0MAPTLB PPGMPAGEMAPTLB;
2035	// typedef PPGMPAGER0MAPTLBE PPGMPAGEMAPTLBE;
2036	// typedef PPGMPAGER0MAPTLBE *PPPGMPAGEMAPTLBE;
2037	//# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER0MAPTLB_ENTRIES
2038	//# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER0MAPTLB_IDX(GCPhys)
2039	// typedef PPGMCHUNKR0MAP PPGMPAGEMAP;
2040	// typedef PPPGMCHUNKR0MAP PPPGMPAGEMAP;
2041	#else
2042	typedef PPGMPAGER3MAPTLB PPGMPAGEMAPTLB;
2043	typedef PPGMPAGER3MAPTLBE PPGMPAGEMAPTLBE;
2044	typedef PPGMPAGER3MAPTLBE *PPPGMPAGEMAPTLBE;
2045	# define PGM_PAGEMAPTLB_ENTRIES PGM_PAGER3MAPTLB_ENTRIES
2046	# define PGM_PAGEMAPTLB_IDX(GCPhys) PGM_PAGER3MAPTLB_IDX(GCPhys)
2047	typedef PPGMCHUNKR3MAP PPGMPAGEMAP;
2048	typedef PPPGMCHUNKR3MAP PPPGMPAGEMAP;
2049	#endif
2050	/** @} */
2051
2052
2053	/** @name PGM Pool Indexes.
2054	* Aka. the unique shadow page identifier.
2055	* @{ */
2056	/** NIL page pool IDX. */
2057	#define NIL_PGMPOOL_IDX 0
2058	/** The first normal index. There used to be 5 fictive pages up front, now
2059	* there is only the NIL page. */
2060	#define PGMPOOL_IDX_FIRST 1
2061	/** The last valid index. (inclusive, 14 bits) */
2062	#define PGMPOOL_IDX_LAST 0x3fff
2063	/** @} */
2064
2065	/** The NIL index for the parent chain. */
2066	#define NIL_PGMPOOL_USER_INDEX ((uint16_t)0xffff)
2067	#define NIL_PGMPOOL_PRESENT_INDEX ((uint16_t)0xffff)
2068
2069	/**
2070	* Node in the chain linking a shadowed page to it's parent (user).
2071	*/
2072	#pragma pack(1)
2073	typedef struct PGMPOOLUSER
2074	{
2075	/** The index to the next item in the chain. NIL_PGMPOOL_USER_INDEX is no next. */
2076	uint16_t iNext;
2077	/** The user page index. */
2078	uint16_t iUser;
2079	/** Index into the user table. */
2080	uint32_t iUserTable;
2081	} PGMPOOLUSER, *PPGMPOOLUSER;
2082	typedef const PGMPOOLUSER *PCPGMPOOLUSER;
2083	#pragma pack()
2084
2085
2086	/** The NIL index for the phys ext chain. */
2087	#define NIL_PGMPOOL_PHYSEXT_INDEX ((uint16_t)0xffff)
2088	/** The NIL pte index for a phys ext chain slot. */
2089	#define NIL_PGMPOOL_PHYSEXT_IDX_PTE ((uint16_t)0xffff)
2090
2091	/**
2092	* Node in the chain of physical cross reference extents.
2093	* @todo Calling this an 'extent' is not quite right, find a better name.
2094	* @todo find out the optimal size of the aidx array
2095	*/
2096	#pragma pack(1)
2097	typedef struct PGMPOOLPHYSEXT
2098	{
2099	/** The index to the next item in the chain. NIL_PGMPOOL_PHYSEXT_INDEX is no next. */
2100	uint16_t iNext;
2101	/** Alignment. */
2102	uint16_t u16Align;
2103	/** The user page index. */
2104	uint16_t aidx[3];
2105	/** The page table index or NIL_PGMPOOL_PHYSEXT_IDX_PTE if unknown. */
2106	uint16_t apte[3];
2107	} PGMPOOLPHYSEXT, *PPGMPOOLPHYSEXT;
2108	typedef const PGMPOOLPHYSEXT *PCPGMPOOLPHYSEXT;
2109	#pragma pack()
2110
2111
2112	/**
2113	* The kind of page that's being shadowed.
2114	*/
2115	typedef enum PGMPOOLKIND
2116	{
2117	/** The virtual invalid 0 entry. */
2118	PGMPOOLKIND_INVALID = 0,
2119	/** The entry is free (=unused). */
2120	PGMPOOLKIND_FREE,
2121
2122	/** Shw: 32-bit page table; Gst: no paging. */
2123	PGMPOOLKIND_32BIT_PT_FOR_PHYS,
2124	/** Shw: 32-bit page table; Gst: 32-bit page table. */
2125	PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT,
2126	/** Shw: 32-bit page table; Gst: 4MB page. */
2127	PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB,
2128	/** Shw: PAE page table; Gst: no paging. */
2129	PGMPOOLKIND_PAE_PT_FOR_PHYS,
2130	/** Shw: PAE page table; Gst: 32-bit page table. */
2131	PGMPOOLKIND_PAE_PT_FOR_32BIT_PT,
2132	/** Shw: PAE page table; Gst: Half of a 4MB page. */
2133	PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB,
2134	/** Shw: PAE page table; Gst: PAE page table. */
2135	PGMPOOLKIND_PAE_PT_FOR_PAE_PT,
2136	/** Shw: PAE page table; Gst: 2MB page. */
2137	PGMPOOLKIND_PAE_PT_FOR_PAE_2MB,
2138
2139	/** Shw: 32-bit page directory. Gst: 32-bit page directory. */
2140	PGMPOOLKIND_32BIT_PD,
2141	/** Shw: 32-bit page directory. Gst: no paging. */
2142	PGMPOOLKIND_32BIT_PD_PHYS,
2143	/** Shw: PAE page directory 0; Gst: 32-bit page directory. */
2144	PGMPOOLKIND_PAE_PD0_FOR_32BIT_PD,
2145	/** Shw: PAE page directory 1; Gst: 32-bit page directory. */
2146	PGMPOOLKIND_PAE_PD1_FOR_32BIT_PD,
2147	/** Shw: PAE page directory 2; Gst: 32-bit page directory. */
2148	PGMPOOLKIND_PAE_PD2_FOR_32BIT_PD,
2149	/** Shw: PAE page directory 3; Gst: 32-bit page directory. */
2150	PGMPOOLKIND_PAE_PD3_FOR_32BIT_PD,
2151	/** Shw: PAE page directory; Gst: PAE page directory. */
2152	PGMPOOLKIND_PAE_PD_FOR_PAE_PD,
2153	/** Shw: PAE page directory; Gst: no paging. Note: +NP. */
2154	PGMPOOLKIND_PAE_PD_PHYS,
2155
2156	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst 32 bits paging. */
2157	PGMPOOLKIND_PAE_PDPT_FOR_32BIT,
2158	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst PAE PDPT. */
2159	PGMPOOLKIND_PAE_PDPT,
2160	/** Shw: PAE page directory pointer table (legacy, 4 entries); Gst: no paging. */
2161	PGMPOOLKIND_PAE_PDPT_PHYS,
2162
2163	/** Shw: 64-bit page directory pointer table; Gst: 64-bit page directory pointer table. */
2164	PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT,
2165	/** Shw: 64-bit page directory pointer table; Gst: no paging. */
2166	PGMPOOLKIND_64BIT_PDPT_FOR_PHYS,
2167	/** Shw: 64-bit page directory table; Gst: 64-bit page directory table. */
2168	PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
2169	/** Shw: 64-bit page directory table; Gst: no paging. */
2170	PGMPOOLKIND_64BIT_PD_FOR_PHYS, /* 24 */
2171
2172	/** Shw: 64-bit PML4; Gst: 64-bit PML4. */
2173	PGMPOOLKIND_64BIT_PML4,
2174
2175	/** Shw: EPT page directory pointer table; Gst: no paging. */
2176	PGMPOOLKIND_EPT_PDPT_FOR_PHYS,
2177	/** Shw: EPT page directory table; Gst: no paging. */
2178	PGMPOOLKIND_EPT_PD_FOR_PHYS,
2179	/** Shw: EPT page table; Gst: no paging. */
2180	PGMPOOLKIND_EPT_PT_FOR_PHYS,
2181
2182	/** Shw: Root Nested paging table. */
2183	PGMPOOLKIND_ROOT_NESTED,
2184
2185	/** The last valid entry. */
2186	PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_NESTED
2187	} PGMPOOLKIND;
2188
2189	/**
2190	* The access attributes of the page; only applies to big pages.
2191	*/
2192	typedef enum
2193	{
2194	PGMPOOLACCESS_DONTCARE = 0,
2195	PGMPOOLACCESS_USER_RW,
2196	PGMPOOLACCESS_USER_R,
2197	PGMPOOLACCESS_USER_RW_NX,
2198	PGMPOOLACCESS_USER_R_NX,
2199	PGMPOOLACCESS_SUPERVISOR_RW,
2200	PGMPOOLACCESS_SUPERVISOR_R,
2201	PGMPOOLACCESS_SUPERVISOR_RW_NX,
2202	PGMPOOLACCESS_SUPERVISOR_R_NX
2203	} PGMPOOLACCESS;
2204
2205	/**
2206	* The tracking data for a page in the pool.
2207	*/
2208	typedef struct PGMPOOLPAGE
2209	{
2210	/** AVL node code with the (HC) physical address of this page. */
2211	AVLOHCPHYSNODECORE Core;
2212	/** Pointer to the R3 mapping of the page. */
2213	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2214	R3PTRTYPE(void *) pvPageR3;
2215	#else
2216	R3R0PTRTYPE(void *) pvPageR3;
2217	#endif
2218	#if HC_ARCH_BITS == 32 && GC_ARCH_BITS == 64
2219	uint32_t Alignment0;
2220	#endif
2221	/** The guest physical address. */
2222	RTGCPHYS GCPhys;
2223	/** The kind of page we're shadowing. (This is really a PGMPOOLKIND enum.) */
2224	uint8_t enmKind;
2225	/** The subkind of page we're shadowing. (This is really a PGMPOOLACCESS enum.) */
2226	uint8_t enmAccess;
2227	/** This supplements enmKind and enmAccess */
2228	bool fA20Enabled : 1;
2229
2230	/** Used to indicate that the page is zeroed. */
2231	bool fZeroed : 1;
2232	/** Used to indicate that a PT has non-global entries. */
2233	bool fSeenNonGlobal : 1;
2234	/** Used to indicate that we're monitoring writes to the guest page. */
2235	bool fMonitored : 1;
2236	/** Used to indicate that the page is in the cache (e.g. in the GCPhys hash).
2237	* (All pages are in the age list.) */
2238	bool fCached : 1;
2239	/** This is used by the R3 access handlers when invoked by an async thread.
2240	* It's a hack required because of REMR3NotifyHandlerPhysicalDeregister. */
2241	bool volatile fReusedFlushPending : 1;
2242	/** Used to mark the page as dirty (write monitoring is temporarily
2243	* off). */
2244	bool fDirty : 1;
2245	bool fPadding1 : 1;
2246	bool fPadding2;
2247
2248	/** The index of this page. */
2249	uint16_t idx;
2250	/** The next entry in the list this page currently resides in.
2251	* It's either in the free list or in the GCPhys hash. */
2252	uint16_t iNext;
2253	/** Head of the user chain. NIL_PGMPOOL_USER_INDEX if not currently in use. */
2254	uint16_t iUserHead;
2255	/** The number of present entries. */
2256	uint16_t cPresent;
2257	/** The first entry in the table which is present. */
2258	uint16_t iFirstPresent;
2259	/** The number of modifications to the monitored page. */
2260	uint16_t cModifications;
2261	/** The next modified page. NIL_PGMPOOL_IDX if tail. */
2262	uint16_t iModifiedNext;
2263	/** The previous modified page. NIL_PGMPOOL_IDX if head. */
2264	uint16_t iModifiedPrev;
2265	/** The next page sharing access handler. NIL_PGMPOOL_IDX if tail. */
2266	uint16_t iMonitoredNext;
2267	/** The previous page sharing access handler. NIL_PGMPOOL_IDX if head. */
2268	uint16_t iMonitoredPrev;
2269	/** The next page in the age list. */
2270	uint16_t iAgeNext;
2271	/** The previous page in the age list. */
2272	uint16_t iAgePrev;
2273	/** Index into PGMPOOL::aDirtyPages if fDirty is set. */
2274	uint8_t idxDirtyEntry;
2275
2276	/** @name Access handler statistics to determine whether the guest is
2277	* (re)initializing a page table.
2278	* @{ */
2279	RTGCPTR GCPtrLastAccessHandlerRip;
2280	RTGCPTR GCPtrLastAccessHandlerFault;
2281	uint64_t cLastAccessHandler;
2282	/** @} */
2283	/** Used to indicate that this page can't be flushed. Important for cr3 root pages or shadow pae pd pages. */
2284	uint32_t volatile cLocked;
2285	#if GC_ARCH_BITS == 64
2286	uint32_t u32Alignment3;
2287	#endif
2288	# ifdef VBOX_STRICT
2289	RTGCPTR GCPtrDirtyFault;
2290	# endif
2291	} PGMPOOLPAGE;
2292	/** Pointer to a pool page. */
2293	typedef PGMPOOLPAGE *PPGMPOOLPAGE;
2294	/** Pointer to a const pool page. */
2295	typedef PGMPOOLPAGE const *PCPGMPOOLPAGE;
2296	/** Pointer to a pool page pointer. */
2297	typedef PGMPOOLPAGE **PPPGMPOOLPAGE;
2298
2299
2300	/** The hash table size. */
2301	# define PGMPOOL_HASH_SIZE 0x40
2302	/** The hash function. */
2303	# define PGMPOOL_HASH(GCPhys) ( ((GCPhys) >> PAGE_SHIFT) & (PGMPOOL_HASH_SIZE - 1) )
2304
2305
2306	/**
2307	* The shadow page pool instance data.
2308	*
2309	* It's all one big allocation made at init time, except for the
2310	* pages that is. The user nodes follows immediately after the
2311	* page structures.
2312	*/
2313	typedef struct PGMPOOL
2314	{
2315	/** The VM handle - R3 Ptr. */
2316	PVMR3 pVMR3;
2317	/** The VM handle - R0 Ptr. */
2318	PVMR0 pVMR0;
2319	/** The VM handle - RC Ptr. */
2320	PVMRC pVMRC;
2321	/** The max pool size. This includes the special IDs. */
2322	uint16_t cMaxPages;
2323	/** The current pool size. */
2324	uint16_t cCurPages;
2325	/** The head of the free page list. */
2326	uint16_t iFreeHead;
2327	/* Padding. */
2328	uint16_t u16Padding;
2329	/** Head of the chain of free user nodes. */
2330	uint16_t iUserFreeHead;
2331	/** The number of user nodes we've allocated. */
2332	uint16_t cMaxUsers;
2333	/** The number of present page table entries in the entire pool. */
2334	uint32_t cPresent;
2335	/** Pointer to the array of user nodes - RC pointer. */
2336	RCPTRTYPE(PPGMPOOLUSER) paUsersRC;
2337	/** Pointer to the array of user nodes - R3 pointer. */
2338	R3PTRTYPE(PPGMPOOLUSER) paUsersR3;
2339	/** Pointer to the array of user nodes - R0 pointer. */
2340	R0PTRTYPE(PPGMPOOLUSER) paUsersR0;
2341	/** Head of the chain of free phys ext nodes. */
2342	uint16_t iPhysExtFreeHead;
2343	/** The number of user nodes we've allocated. */
2344	uint16_t cMaxPhysExts;
2345	/** Pointer to the array of physical xref extent - RC pointer. */
2346	RCPTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsRC;
2347	/** Pointer to the array of physical xref extent nodes - R3 pointer. */
2348	R3PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR3;
2349	/** Pointer to the array of physical xref extent nodes - R0 pointer. */
2350	R0PTRTYPE(PPGMPOOLPHYSEXT) paPhysExtsR0;
2351	/** Hash table for GCPhys addresses. */
2352	uint16_t aiHash[PGMPOOL_HASH_SIZE];
2353	/** The head of the age list. */
2354	uint16_t iAgeHead;
2355	/** The tail of the age list. */
2356	uint16_t iAgeTail;
2357	/** Set if the cache is enabled. */
2358	bool fCacheEnabled;
2359	/** Alignment padding. */
2360	bool afPadding1[3];
2361	/** Head of the list of modified pages. */
2362	uint16_t iModifiedHead;
2363	/** The current number of modified pages. */
2364	uint16_t cModifiedPages;
2365	/** Physical access handler type registration handle. */
2366	PGMPHYSHANDLERTYPE hAccessHandlerType;
2367	/** Next available slot (in aDirtyPages). */
2368	uint32_t idxFreeDirtyPage;
2369	/** Number of active dirty pages. */
2370	uint32_t cDirtyPages;
2371	/** Array of current dirty pgm pool page indices. */
2372	struct
2373	{
2374	uint16_t uIdx;
2375	uint16_t Alignment[3];
2376	uint64_t aPage[512];
2377	} aDirtyPages[16];
2378	/** The number of pages currently in use. */
2379	uint16_t cUsedPages;
2380	#ifdef VBOX_WITH_STATISTICS
2381	/** The high water mark for cUsedPages. */
2382	uint16_t cUsedPagesHigh;
2383	uint32_t Alignment1; /*< Align the next member on a 64-bit boundary. /
2384	/** Profiling pgmPoolAlloc(). */
2385	STAMPROFILEADV StatAlloc;
2386	/** Profiling pgmR3PoolClearDoIt(). */
2387	STAMPROFILE StatClearAll;
2388	/** Profiling pgmR3PoolReset(). */
2389	STAMPROFILE StatR3Reset;
2390	/** Profiling pgmPoolFlushPage(). */
2391	STAMPROFILE StatFlushPage;
2392	/** Profiling pgmPoolFree(). */
2393	STAMPROFILE StatFree;
2394	/** Counting explicit flushes by PGMPoolFlushPage(). */
2395	STAMCOUNTER StatForceFlushPage;
2396	/** Counting explicit flushes of dirty pages by PGMPoolFlushPage(). */
2397	STAMCOUNTER StatForceFlushDirtyPage;
2398	/** Counting flushes for reused pages. */
2399	STAMCOUNTER StatForceFlushReused;
2400	/** Profiling time spent zeroing pages. */
2401	STAMPROFILE StatZeroPage;
2402	/** Profiling of pgmPoolTrackDeref. */
2403	STAMPROFILE StatTrackDeref;
2404	/** Profiling pgmTrackFlushGCPhysPT. */
2405	STAMPROFILE StatTrackFlushGCPhysPT;
2406	/** Profiling pgmTrackFlushGCPhysPTs. */
2407	STAMPROFILE StatTrackFlushGCPhysPTs;
2408	/** Profiling pgmTrackFlushGCPhysPTsSlow. */
2409	STAMPROFILE StatTrackFlushGCPhysPTsSlow;
2410	/** Number of times we've been out of user records. */
2411	STAMCOUNTER StatTrackFreeUpOneUser;
2412	/** Nr of flushed entries. */
2413	STAMCOUNTER StatTrackFlushEntry;
2414	/** Nr of updated entries. */
2415	STAMCOUNTER StatTrackFlushEntryKeep;
2416	/** Profiling deref activity related tracking GC physical pages. */
2417	STAMPROFILE StatTrackDerefGCPhys;
2418	/** Number of linear searches for a HCPhys in the ram ranges. */
2419	STAMCOUNTER StatTrackLinearRamSearches;
2420	/** The number of failing pgmPoolTrackPhysExtAlloc calls. */
2421	STAMCOUNTER StamTrackPhysExtAllocFailures;
2422	/** Profiling the RC/R0 access handler. */
2423	STAMPROFILE StatMonitorRZ;
2424	/** Times we've failed interpreting the instruction. */
2425	STAMCOUNTER StatMonitorRZEmulateInstr;
2426	/** Profiling the pgmPoolFlushPage calls made from the RC/R0 access handler. */
2427	STAMPROFILE StatMonitorRZFlushPage;
2428	/* Times we've detected a page table reinit. */
2429	STAMCOUNTER StatMonitorRZFlushReinit;
2430	/** Counting flushes for pages that are modified too often. */
2431	STAMCOUNTER StatMonitorRZFlushModOverflow;
2432	/** Times we've detected fork(). */
2433	STAMCOUNTER StatMonitorRZFork;
2434	/** Profiling the RC/R0 access we've handled (except REP STOSD). */
2435	STAMPROFILE StatMonitorRZHandled;
2436	/** Times we've failed interpreting a patch code instruction. */
2437	STAMCOUNTER StatMonitorRZIntrFailPatch1;
2438	/** Times we've failed interpreting a patch code instruction during flushing. */
2439	STAMCOUNTER StatMonitorRZIntrFailPatch2;
2440	/** The number of times we've seen rep prefixes we can't handle. */
2441	STAMCOUNTER StatMonitorRZRepPrefix;
2442	/** Profiling the REP STOSD cases we've handled. */
2443	STAMPROFILE StatMonitorRZRepStosd;
2444	/** Nr of handled PT faults. */
2445	STAMCOUNTER StatMonitorRZFaultPT;
2446	/** Nr of handled PD faults. */
2447	STAMCOUNTER StatMonitorRZFaultPD;
2448	/** Nr of handled PDPT faults. */
2449	STAMCOUNTER StatMonitorRZFaultPDPT;
2450	/** Nr of handled PML4 faults. */
2451	STAMCOUNTER StatMonitorRZFaultPML4;
2452
2453	/** Profiling the R3 access handler. */
2454	STAMPROFILE StatMonitorR3;
2455	/** Times we've failed interpreting the instruction. */
2456	STAMCOUNTER StatMonitorR3EmulateInstr;
2457	/** Profiling the pgmPoolFlushPage calls made from the R3 access handler. */
2458	STAMPROFILE StatMonitorR3FlushPage;
2459	/* Times we've detected a page table reinit. */
2460	STAMCOUNTER StatMonitorR3FlushReinit;
2461	/** Counting flushes for pages that are modified too often. */
2462	STAMCOUNTER StatMonitorR3FlushModOverflow;
2463	/** Times we've detected fork(). */
2464	STAMCOUNTER StatMonitorR3Fork;
2465	/** Profiling the R3 access we've handled (except REP STOSD). */
2466	STAMPROFILE StatMonitorR3Handled;
2467	/** The number of times we've seen rep prefixes we can't handle. */
2468	STAMCOUNTER StatMonitorR3RepPrefix;
2469	/** Profiling the REP STOSD cases we've handled. */
2470	STAMPROFILE StatMonitorR3RepStosd;
2471	/** Nr of handled PT faults. */
2472	STAMCOUNTER StatMonitorR3FaultPT;
2473	/** Nr of handled PD faults. */
2474	STAMCOUNTER StatMonitorR3FaultPD;
2475	/** Nr of handled PDPT faults. */
2476	STAMCOUNTER StatMonitorR3FaultPDPT;
2477	/** Nr of handled PML4 faults. */
2478	STAMCOUNTER StatMonitorR3FaultPML4;
2479	/** The number of times we're called in an async thread an need to flush. */
2480	STAMCOUNTER StatMonitorR3Async;
2481	/** Times we've called pgmPoolResetDirtyPages (and there were dirty page). */
2482	STAMCOUNTER StatResetDirtyPages;
2483	/** Times we've called pgmPoolAddDirtyPage. */
2484	STAMCOUNTER StatDirtyPage;
2485	/** Times we've had to flush duplicates for dirty page management. */
2486	STAMCOUNTER StatDirtyPageDupFlush;
2487	/** Times we've had to flush because of overflow. */
2488	STAMCOUNTER StatDirtyPageOverFlowFlush;
2489
2490	/** The high water mark for cModifiedPages. */
2491	uint16_t cModifiedPagesHigh;
2492	uint16_t Alignment2[3]; /*< Align the next member on a 64-bit boundary. /
2493
2494	/** The number of cache hits. */
2495	STAMCOUNTER StatCacheHits;
2496	/** The number of cache misses. */
2497	STAMCOUNTER StatCacheMisses;
2498	/** The number of times we've got a conflict of 'kind' in the cache. */
2499	STAMCOUNTER StatCacheKindMismatches;
2500	/** Number of times we've been out of pages. */
2501	STAMCOUNTER StatCacheFreeUpOne;
2502	/** The number of cacheable allocations. */
2503	STAMCOUNTER StatCacheCacheable;
2504	/** The number of uncacheable allocations. */
2505	STAMCOUNTER StatCacheUncacheable;
2506	#else
2507	uint32_t Alignment3; /*< Align the next member on a 64-bit boundary. /
2508	#endif
2509	/** The AVL tree for looking up a page by its HC physical address. */
2510	AVLOHCPHYSTREE HCPhysTree;
2511	uint32_t Alignment4; /*< Align the next member on a 64-bit boundary. /
2512	/** Array of pages. (cMaxPages in length)
2513	* The Id is the index into thist array.
2514	*/
2515	PGMPOOLPAGE aPages[PGMPOOL_IDX_FIRST];
2516	} PGMPOOL, PPGMPOOL, *PPPGMPOOL;
2517	AssertCompileMemberAlignment(PGMPOOL, iModifiedHead, 8);
2518	AssertCompileMemberAlignment(PGMPOOL, aDirtyPages, 8);
2519	AssertCompileMemberAlignment(PGMPOOL, cUsedPages, 8);
2520	#ifdef VBOX_WITH_STATISTICS
2521	AssertCompileMemberAlignment(PGMPOOL, StatAlloc, 8);
2522	#endif
2523	AssertCompileMemberAlignment(PGMPOOL, aPages, 8);
2524
2525
2526	/** @def PGMPOOL_PAGE_2_PTR
2527	* Maps a pool page pool into the current context.
2528	*
2529	* @returns VBox status code.
2530	* @param a_pVM Pointer to the VM.
2531	* @param a_pPage The pool page.
2532	*
2533	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2534	* small page window employeed by that function. Be careful.
2535	* @remark There is no need to assert on the result.
2536	*/
2537	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2538	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageInlined((a_pVM), (a_pPage) RTLOG_COMMA_SRC_POS)
2539	#elif defined(VBOX_STRICT) \|\| 1 /* temporarily going strict here */
2540	# define PGMPOOL_PAGE_2_PTR(a_pVM, a_pPage) pgmPoolMapPageStrict(a_pPage, __FUNCTION__)
2541	DECLINLINE(void ) pgmPoolMapPageStrict(PPGMPOOLPAGE a_pPage, const char pszCaller)
2542	{
2543	AssertPtr(a_pPage);
2544	AssertReleaseMsg(RT_VALID_PTR(a_pPage->pvPageR3), ("enmKind=%d idx=%#x HCPhys=%RHp GCPhys=%RGp caller=%s\n", a_pPage->enmKind, a_pPage->idx, a_pPage->Core.Key, a_pPage->GCPhys, pszCaller));
2545	return a_pPage->pvPageR3;
2546	}
2547	#else
2548	# define PGMPOOL_PAGE_2_PTR(pVM, a_pPage) ((a_pPage)->pvPageR3)
2549	#endif
2550
2551
2552	/** @def PGMPOOL_PAGE_2_PTR_V2
2553	* Maps a pool page pool into the current context, taking both VM and VMCPU.
2554	*
2555	* @returns VBox status code.
2556	* @param a_pVM Pointer to the VM.
2557	* @param a_pVCpu The current CPU.
2558	* @param a_pPage The pool page.
2559	*
2560	* @remark In RC this uses PGMGCDynMapHCPage(), so it will consume of the
2561	* small page window employeed by that function. Be careful.
2562	* @remark There is no need to assert on the result.
2563	*/
2564	#if defined(IN_RC) \|\| defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0)
2565	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) pgmPoolMapPageV2Inlined((a_pVM), (a_pVCpu), (a_pPage) RTLOG_COMMA_SRC_POS)
2566	#else
2567	# define PGMPOOL_PAGE_2_PTR_V2(a_pVM, a_pVCpu, a_pPage) PGMPOOL_PAGE_2_PTR((a_pVM), (a_pPage))
2568	#endif
2569
2570
2571	/** @name Per guest page tracking data.
2572	* This is currently as a 16-bit word in the PGMPAGE structure, the idea though
2573	* is to use more bits for it and split it up later on. But for now we'll play
2574	* safe and change as little as possible.
2575	*
2576	* The 16-bit word has two parts:
2577	*
2578	* The first 14-bit forms the @a idx field. It is either the index of a page in
2579	* the shadow page pool, or and index into the extent list.
2580	*
2581	* The 2 topmost bits makes up the @a cRefs field, which counts the number of
2582	* shadow page pool references to the page. If cRefs equals
2583	* PGMPOOL_CREFS_PHYSEXT, then the @a idx field is an indext into the extent
2584	* (misnomer) table and not the shadow page pool.
2585	*
2586	* See PGM_PAGE_GET_TRACKING and PGM_PAGE_SET_TRACKING for how to get and set
2587	* the 16-bit word.
2588	*
2589	* @{ */
2590	/** The shift count for getting to the cRefs part. */
2591	#define PGMPOOL_TD_CREFS_SHIFT 14
2592	/** The mask applied after shifting the tracking data down by
2593	* PGMPOOL_TD_CREFS_SHIFT. */
2594	#define PGMPOOL_TD_CREFS_MASK 0x3
2595	/** The cRefs value used to indicate that the idx is the head of a
2596	* physical cross reference list. */
2597	#define PGMPOOL_TD_CREFS_PHYSEXT PGMPOOL_TD_CREFS_MASK
2598	/** The shift used to get idx. */
2599	#define PGMPOOL_TD_IDX_SHIFT 0
2600	/** The mask applied to the idx after shifting down by PGMPOOL_TD_IDX_SHIFT. */
2601	#define PGMPOOL_TD_IDX_MASK 0x3fff
2602	/** The idx value when we're out of of PGMPOOLPHYSEXT entries or/and there are
2603	* simply too many mappings of this page. */
2604	#define PGMPOOL_TD_IDX_OVERFLOWED PGMPOOL_TD_IDX_MASK
2605
2606	/** @def PGMPOOL_TD_MAKE
2607	* Makes a 16-bit tracking data word.
2608	*
2609	* @returns tracking data.
2610	* @param cRefs The @a cRefs field. Must be within bounds!
2611	* @param idx The @a idx field. Must also be within bounds! */
2612	#define PGMPOOL_TD_MAKE(cRefs, idx) ( ((cRefs) << PGMPOOL_TD_CREFS_SHIFT) \| (idx) )
2613
2614	/** @def PGMPOOL_TD_GET_CREFS
2615	* Get the @a cRefs field from a tracking data word.
2616	*
2617	* @returns The @a cRefs field
2618	* @param u16 The tracking data word.
2619	* @remarks This will only return 1 or PGMPOOL_TD_CREFS_PHYSEXT for a
2620	* non-zero @a u16. */
2621	#define PGMPOOL_TD_GET_CREFS(u16) ( ((u16) >> PGMPOOL_TD_CREFS_SHIFT) & PGMPOOL_TD_CREFS_MASK )
2622
2623	/** @def PGMPOOL_TD_GET_IDX
2624	* Get the @a idx field from a tracking data word.
2625	*
2626	* @returns The @a idx field
2627	* @param u16 The tracking data word. */
2628	#define PGMPOOL_TD_GET_IDX(u16) ( ((u16) >> PGMPOOL_TD_IDX_SHIFT) & PGMPOOL_TD_IDX_MASK )
2629	/** @} */
2630
2631
2632
2633	/** @name A20 gate macros
2634	* @{ */
2635	#define PGM_WITH_A20
2636	#ifdef PGM_WITH_A20
2637	# define PGM_A20_IS_ENABLED(a_pVCpu) ((a_pVCpu)->pgm.s.fA20Enabled)
2638	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) ((a_GCPhys) & (a_pVCpu)->pgm.s.GCPhysA20Mask)
2639	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) \
2640	do { a_GCPhysVar &= (a_pVCpu)->pgm.s.GCPhysA20Mask; } while (0)
2641	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) Assert(PGM_A20_APPLY(pVCpu, a_GCPhys) == (a_GCPhys))
2642	#else
2643	# define PGM_A20_IS_ENABLED(a_pVCpu) (true)
2644	# define PGM_A20_APPLY(a_pVCpu, a_GCPhys) (a_GCPhys)
2645	# define PGM_A20_APPLY_TO_VAR(a_pVCpu, a_GCPhysVar) do { } while (0)
2646	# define PGM_A20_ASSERT_MASKED(pVCpu, a_GCPhys) do { } while (0)
2647	#endif
2648	/** @} */
2649
2650
2651	/**
2652	* Roots and anchors for trees and list employing self relative offsets as
2653	* pointers.
2654	*
2655	* When using self-relative offsets instead of pointers, the offsets needs to be
2656	* the same in all offsets. Thus the roots and anchors needs to live on the
2657	* hyper heap just like the nodes.
2658	*/
2659	typedef struct PGMTREES
2660	{
2661	/** Physical access handlers (AVL range+offsetptr tree). */
2662	AVLROGCPHYSTREE PhysHandlers;
2663	/** Virtual access handlers (AVL range + GC ptr tree). */
2664	AVLROGCPTRTREE VirtHandlers;
2665	/** Virtual access handlers (Phys range AVL range + offsetptr tree). */
2666	AVLROGCPHYSTREE PhysToVirtHandlers;
2667	/** Virtual access handlers for the hypervisor (AVL range + GC ptr tree). */
2668	AVLROGCPTRTREE HyperVirtHandlers;
2669	/** List of physical access handler types (offset pointers) of type
2670	* PGMPHYSHANDLERTYPEINT. This is needed for relocations. */
2671	RTLISTOFF32ANCHOR HeadPhysHandlerTypes;
2672	} PGMTREES;
2673	/** Pointer to PGM trees. */
2674	typedef PGMTREES *PPGMTREES;
2675
2676
2677	/**
2678	* Page fault guest state for the AMD64 paging mode.
2679	*/
2680	typedef struct PGMPTWALKCORE
2681	{
2682	/** The guest virtual address that is being resolved by the walk
2683	* (input). */
2684	RTGCPTR GCPtr;
2685
2686	/** The guest physical address that is the result of the walk.
2687	* @remarks only valid if fSucceeded is set. */
2688	RTGCPHYS GCPhys;
2689
2690	/** Set if the walk succeeded, i.d. GCPhys is valid. */
2691	bool fSucceeded;
2692	/** The level problem arrised at.
2693	* PTE is level 1, PDE is level 2, PDPE is level 3, PML4 is level 4, CR3 is
2694	* level 8. This is 0 on success. */
2695	uint8_t uLevel;
2696	/** Set if the page isn't present. */
2697	bool fNotPresent;
2698	/** Encountered a bad physical address. */
2699	bool fBadPhysAddr;
2700	/** Set if there was reserved bit violations. */
2701	bool fRsvdError;
2702	/** Set if it involves a big page (2/4 MB). */
2703	bool fBigPage;
2704	/** Set if it involves a gigantic page (1 GB). */
2705	bool fGigantPage;
2706	/** The effect X86_PTE_US flag for the address. */
2707	bool fEffectiveUS;
2708	/** The effect X86_PTE_RW flag for the address. */
2709	bool fEffectiveRW;
2710	/** The effect X86_PTE_NX flag for the address. */
2711	bool fEffectiveNX;
2712	} PGMPTWALKCORE;
2713
2714
2715	/**
2716	* Guest page table walk for the AMD64 mode.
2717	*/
2718	typedef struct PGMPTWALKGSTAMD64
2719	{
2720	/** The common core. */
2721	PGMPTWALKCORE Core;
2722
2723	PX86PML4 pPml4;
2724	PX86PML4E pPml4e;
2725	X86PML4E Pml4e;
2726
2727	PX86PDPT pPdpt;
2728	PX86PDPE pPdpe;
2729	X86PDPE Pdpe;
2730
2731	PX86PDPAE pPd;
2732	PX86PDEPAE pPde;
2733	X86PDEPAE Pde;
2734
2735	PX86PTPAE pPt;
2736	PX86PTEPAE pPte;
2737	X86PTEPAE Pte;
2738	} PGMPTWALKGSTAMD64;
2739	/** Pointer to a AMD64 guest page table walk. */
2740	typedef PGMPTWALKGSTAMD64 *PPGMPTWALKGSTAMD64;
2741	/** Pointer to a const AMD64 guest page table walk. */
2742	typedef PGMPTWALKGSTAMD64 const *PCPGMPTWALKGSTAMD64;
2743
2744	/**
2745	* Guest page table walk for the PAE mode.
2746	*/
2747	typedef struct PGMPTWALKGSTPAE
2748	{
2749	/** The common core. */
2750	PGMPTWALKCORE Core;
2751
2752	PX86PDPT pPdpt;
2753	PX86PDPE pPdpe;
2754	X86PDPE Pdpe;
2755
2756	PX86PDPAE pPd;
2757	PX86PDEPAE pPde;
2758	X86PDEPAE Pde;
2759
2760	PX86PTPAE pPt;
2761	PX86PTEPAE pPte;
2762	X86PTEPAE Pte;
2763	} PGMPTWALKGSTPAE;
2764	/** Pointer to a PAE guest page table walk. */
2765	typedef PGMPTWALKGSTPAE *PPGMPTWALKGSTPAE;
2766	/** Pointer to a const AMD64 guest page table walk. */
2767	typedef PGMPTWALKGSTPAE const *PCPGMPTWALKGSTPAE;
2768
2769	/**
2770	* Guest page table walk for the 32-bit mode.
2771	*/
2772	typedef struct PGMPTWALKGST32BIT
2773	{
2774	/** The common core. */
2775	PGMPTWALKCORE Core;
2776
2777	PX86PD pPd;
2778	PX86PDE pPde;
2779	X86PDE Pde;
2780
2781	PX86PT pPt;
2782	PX86PTE pPte;
2783	X86PTE Pte;
2784	} PGMPTWALKGST32BIT;
2785	/** Pointer to a 32-bit guest page table walk. */
2786	typedef PGMPTWALKGST32BIT *PPGMPTWALKGST32BIT;
2787	/** Pointer to a const 32-bit guest page table walk. */
2788	typedef PGMPTWALKGST32BIT const *PCPGMPTWALKGST32BIT;
2789
2790	/**
2791	* Which part of PGMPTWALKGST that is valid.
2792	*/
2793	typedef enum PGMPTWALKGSTTYPE
2794	{
2795	/** Customary invalid 0 value. */
2796	PGMPTWALKGSTTYPE_INVALID = 0,
2797	/** PGMPTWALKGST::u.Amd64 is valid. */
2798	PGMPTWALKGSTTYPE_AMD64,
2799	/** PGMPTWALKGST::u.Pae is valid. */
2800	PGMPTWALKGSTTYPE_PAE,
2801	/** PGMPTWALKGST::u.Legacy is valid. */
2802	PGMPTWALKGSTTYPE_32BIT,
2803	/** Customary 32-bit type hack. */
2804	PGMPTWALKGSTTYPE_32BIT_HACK = 0x7fff0000
2805	} PGMPTWALKGSTTYPE;
2806
2807	/**
2808	* Combined guest page table walk result.
2809	*/
2810	typedef struct PGMPTWALKGST
2811	{
2812	union
2813	{
2814	/** The page walker core - always valid. */
2815	PGMPTWALKCORE Core;
2816	/** The page walker for AMD64. */
2817	PGMPTWALKGSTAMD64 Amd64;
2818	/** The page walker for PAE (32-bit). */
2819	PGMPTWALKGSTPAE Pae;
2820	/** The page walker for 32-bit paging (called legacy due to C naming
2821	* convension). */
2822	PGMPTWALKGST32BIT Legacy;
2823	} u;
2824	/** Indicates which part of the union is valid. */
2825	PGMPTWALKGSTTYPE enmType;
2826	} PGMPTWALKGST;
2827	/** Pointer to a combined guest page table walk result. */
2828	typedef PGMPTWALKGST *PPGMPTWALKGST;
2829	/** Pointer to a read-only combined guest page table walk result. */
2830	typedef PGMPTWALKGST const *PCPGMPTWALKGST;
2831
2832
2833	/** @name Paging mode macros
2834	* @{
2835	*/
2836	#ifdef IN_RC
2837	# define PGM_CTX(a,b) a##RC##b
2838	# define PGM_CTX_STR(a,b) a "GC" b
2839	# define PGM_CTX_DECL(type) VMMRCDECL(type)
2840	#else
2841	# ifdef IN_RING3
2842	# define PGM_CTX(a,b) a##R3##b
2843	# define PGM_CTX_STR(a,b) a "R3" b
2844	# define PGM_CTX_DECL(type) DECLCALLBACK(type)
2845	# else
2846	# define PGM_CTX(a,b) a##R0##b
2847	# define PGM_CTX_STR(a,b) a "R0" b
2848	# define PGM_CTX_DECL(type) VMMDECL(type)
2849	# endif
2850	#endif
2851
2852	#define PGM_GST_NAME_REAL(name) PGM_CTX(pgm,GstReal##name)
2853	#define PGM_GST_NAME_RC_REAL_STR(name) "pgmRCGstReal" #name
2854	#define PGM_GST_NAME_R0_REAL_STR(name) "pgmR0GstReal" #name
2855	#define PGM_GST_NAME_PROT(name) PGM_CTX(pgm,GstProt##name)
2856	#define PGM_GST_NAME_RC_PROT_STR(name) "pgmRCGstProt" #name
2857	#define PGM_GST_NAME_R0_PROT_STR(name) "pgmR0GstProt" #name
2858	#define PGM_GST_NAME_32BIT(name) PGM_CTX(pgm,Gst32Bit##name)
2859	#define PGM_GST_NAME_RC_32BIT_STR(name) "pgmRCGst32Bit" #name
2860	#define PGM_GST_NAME_R0_32BIT_STR(name) "pgmR0Gst32Bit" #name
2861	#define PGM_GST_NAME_PAE(name) PGM_CTX(pgm,GstPAE##name)
2862	#define PGM_GST_NAME_RC_PAE_STR(name) "pgmRCGstPAE" #name
2863	#define PGM_GST_NAME_R0_PAE_STR(name) "pgmR0GstPAE" #name
2864	#define PGM_GST_NAME_AMD64(name) PGM_CTX(pgm,GstAMD64##name)
2865	#define PGM_GST_NAME_RC_AMD64_STR(name) "pgmRCGstAMD64" #name
2866	#define PGM_GST_NAME_R0_AMD64_STR(name) "pgmR0GstAMD64" #name
2867	#define PGM_GST_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Gst##name))
2868	#define PGM_GST_DECL(type, name) PGM_CTX_DECL(type) PGM_GST_NAME(name)
2869
2870	#define PGM_SHW_NAME_32BIT(name) PGM_CTX(pgm,Shw32Bit##name)
2871	#define PGM_SHW_NAME_RC_32BIT_STR(name) "pgmRCShw32Bit" #name
2872	#define PGM_SHW_NAME_R0_32BIT_STR(name) "pgmR0Shw32Bit" #name
2873	#define PGM_SHW_NAME_PAE(name) PGM_CTX(pgm,ShwPAE##name)
2874	#define PGM_SHW_NAME_RC_PAE_STR(name) "pgmRCShwPAE" #name
2875	#define PGM_SHW_NAME_R0_PAE_STR(name) "pgmR0ShwPAE" #name
2876	#define PGM_SHW_NAME_AMD64(name) PGM_CTX(pgm,ShwAMD64##name)
2877	#define PGM_SHW_NAME_RC_AMD64_STR(name) "pgmRCShwAMD64" #name
2878	#define PGM_SHW_NAME_R0_AMD64_STR(name) "pgmR0ShwAMD64" #name
2879	#define PGM_SHW_NAME_NESTED(name) PGM_CTX(pgm,ShwNested##name)
2880	#define PGM_SHW_NAME_RC_NESTED_STR(name) "pgmRCShwNested" #name
2881	#define PGM_SHW_NAME_R0_NESTED_STR(name) "pgmR0ShwNested" #name
2882	#define PGM_SHW_NAME_EPT(name) PGM_CTX(pgm,ShwEPT##name)
2883	#define PGM_SHW_NAME_RC_EPT_STR(name) "pgmRCShwEPT" #name
2884	#define PGM_SHW_NAME_R0_EPT_STR(name) "pgmR0ShwEPT" #name
2885	#define PGM_SHW_DECL(type, name) PGM_CTX_DECL(type) PGM_SHW_NAME(name)
2886	#define PGM_SHW_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Shw##name))
2887
2888	/* Shw_Gst */
2889	#define PGM_BTH_NAME_32BIT_REAL(name) PGM_CTX(pgm,Bth32BitReal##name)
2890	#define PGM_BTH_NAME_32BIT_PROT(name) PGM_CTX(pgm,Bth32BitProt##name)
2891	#define PGM_BTH_NAME_32BIT_32BIT(name) PGM_CTX(pgm,Bth32Bit32Bit##name)
2892	#define PGM_BTH_NAME_PAE_REAL(name) PGM_CTX(pgm,BthPAEReal##name)
2893	#define PGM_BTH_NAME_PAE_PROT(name) PGM_CTX(pgm,BthPAEProt##name)
2894	#define PGM_BTH_NAME_PAE_32BIT(name) PGM_CTX(pgm,BthPAE32Bit##name)
2895	#define PGM_BTH_NAME_PAE_PAE(name) PGM_CTX(pgm,BthPAEPAE##name)
2896	#define PGM_BTH_NAME_AMD64_PROT(name) PGM_CTX(pgm,BthAMD64Prot##name)
2897	#define PGM_BTH_NAME_AMD64_AMD64(name) PGM_CTX(pgm,BthAMD64AMD64##name)
2898	#define PGM_BTH_NAME_NESTED_REAL(name) PGM_CTX(pgm,BthNestedReal##name)
2899	#define PGM_BTH_NAME_NESTED_PROT(name) PGM_CTX(pgm,BthNestedProt##name)
2900	#define PGM_BTH_NAME_NESTED_32BIT(name) PGM_CTX(pgm,BthNested32Bit##name)
2901	#define PGM_BTH_NAME_NESTED_PAE(name) PGM_CTX(pgm,BthNestedPAE##name)
2902	#define PGM_BTH_NAME_NESTED_AMD64(name) PGM_CTX(pgm,BthNestedAMD64##name)
2903	#define PGM_BTH_NAME_EPT_REAL(name) PGM_CTX(pgm,BthEPTReal##name)
2904	#define PGM_BTH_NAME_EPT_PROT(name) PGM_CTX(pgm,BthEPTProt##name)
2905	#define PGM_BTH_NAME_EPT_32BIT(name) PGM_CTX(pgm,BthEPT32Bit##name)
2906	#define PGM_BTH_NAME_EPT_PAE(name) PGM_CTX(pgm,BthEPTPAE##name)
2907	#define PGM_BTH_NAME_EPT_AMD64(name) PGM_CTX(pgm,BthEPTAMD64##name)
2908
2909	#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name) "pgmRCBth32BitReal" #name
2910	#define PGM_BTH_NAME_RC_32BIT_PROT_STR(name) "pgmRCBth32BitProt" #name
2911	#define PGM_BTH_NAME_RC_32BIT_32BIT_STR(name) "pgmRCBth32Bit32Bit" #name
2912	#define PGM_BTH_NAME_RC_PAE_REAL_STR(name) "pgmRCBthPAEReal" #name
2913	#define PGM_BTH_NAME_RC_PAE_PROT_STR(name) "pgmRCBthPAEProt" #name
2914	#define PGM_BTH_NAME_RC_PAE_32BIT_STR(name) "pgmRCBthPAE32Bit" #name
2915	#define PGM_BTH_NAME_RC_PAE_PAE_STR(name) "pgmRCBthPAEPAE" #name
2916	#define PGM_BTH_NAME_RC_AMD64_AMD64_STR(name) "pgmRCBthAMD64AMD64" #name
2917	#define PGM_BTH_NAME_RC_NESTED_REAL_STR(name) "pgmRCBthNestedReal" #name
2918	#define PGM_BTH_NAME_RC_NESTED_PROT_STR(name) "pgmRCBthNestedProt" #name
2919	#define PGM_BTH_NAME_RC_NESTED_32BIT_STR(name) "pgmRCBthNested32Bit" #name
2920	#define PGM_BTH_NAME_RC_NESTED_PAE_STR(name) "pgmRCBthNestedPAE" #name
2921	#define PGM_BTH_NAME_RC_NESTED_AMD64_STR(name) "pgmRCBthNestedAMD64" #name
2922	#define PGM_BTH_NAME_RC_EPT_REAL_STR(name) "pgmRCBthEPTReal" #name
2923	#define PGM_BTH_NAME_RC_EPT_PROT_STR(name) "pgmRCBthEPTProt" #name
2924	#define PGM_BTH_NAME_RC_EPT_32BIT_STR(name) "pgmRCBthEPT32Bit" #name
2925	#define PGM_BTH_NAME_RC_EPT_PAE_STR(name) "pgmRCBthEPTPAE" #name
2926	#define PGM_BTH_NAME_RC_EPT_AMD64_STR(name) "pgmRCBthEPTAMD64" #name
2927	#define PGM_BTH_NAME_R0_32BIT_REAL_STR(name) "pgmR0Bth32BitReal" #name
2928	#define PGM_BTH_NAME_R0_32BIT_PROT_STR(name) "pgmR0Bth32BitProt" #name
2929	#define PGM_BTH_NAME_R0_32BIT_32BIT_STR(name) "pgmR0Bth32Bit32Bit" #name
2930	#define PGM_BTH_NAME_R0_PAE_REAL_STR(name) "pgmR0BthPAEReal" #name
2931	#define PGM_BTH_NAME_R0_PAE_PROT_STR(name) "pgmR0BthPAEProt" #name
2932	#define PGM_BTH_NAME_R0_PAE_32BIT_STR(name) "pgmR0BthPAE32Bit" #name
2933	#define PGM_BTH_NAME_R0_PAE_PAE_STR(name) "pgmR0BthPAEPAE" #name
2934	#define PGM_BTH_NAME_R0_AMD64_PROT_STR(name) "pgmR0BthAMD64Prot" #name
2935	#define PGM_BTH_NAME_R0_AMD64_AMD64_STR(name) "pgmR0BthAMD64AMD64" #name
2936	#define PGM_BTH_NAME_R0_NESTED_REAL_STR(name) "pgmR0BthNestedReal" #name
2937	#define PGM_BTH_NAME_R0_NESTED_PROT_STR(name) "pgmR0BthNestedProt" #name
2938	#define PGM_BTH_NAME_R0_NESTED_32BIT_STR(name) "pgmR0BthNested32Bit" #name
2939	#define PGM_BTH_NAME_R0_NESTED_PAE_STR(name) "pgmR0BthNestedPAE" #name
2940	#define PGM_BTH_NAME_R0_NESTED_AMD64_STR(name) "pgmR0BthNestedAMD64" #name
2941	#define PGM_BTH_NAME_R0_EPT_REAL_STR(name) "pgmR0BthEPTReal" #name
2942	#define PGM_BTH_NAME_R0_EPT_PROT_STR(name) "pgmR0BthEPTProt" #name
2943	#define PGM_BTH_NAME_R0_EPT_32BIT_STR(name) "pgmR0BthEPT32Bit" #name
2944	#define PGM_BTH_NAME_R0_EPT_PAE_STR(name) "pgmR0BthEPTPAE" #name
2945	#define PGM_BTH_NAME_R0_EPT_AMD64_STR(name) "pgmR0BthEPTAMD64" #name
2946
2947	#define PGM_BTH_DECL(type, name) PGM_CTX_DECL(type) PGM_BTH_NAME(name)
2948	#define PGM_BTH_PFN(name, pVCpu) ((pVCpu)->pgm.s.PGM_CTX(pfn,Bth##name))
2949	/** @} */
2950
2951	/**
2952	* Data for each paging mode.
2953	*/
2954	typedef struct PGMMODEDATA
2955	{
2956	/** The guest mode type. */
2957	uint32_t uGstType;
2958	/** The shadow mode type. */
2959	uint32_t uShwType;
2960
2961	/** @name Function pointers for Shadow paging.
2962	* @{
2963	*/
2964	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2965	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
2966	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2967	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2968
2969	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2970	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2971
2972	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
2973	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
2974	/** @} */
2975
2976	/** @name Function pointers for Guest paging.
2977	* @{
2978	*/
2979	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2980	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
2981	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2982	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2983	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2984	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2985	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2986	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2987	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
2988	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
2989	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
2990	/** @} */
2991
2992	/** @name Function pointers for Both Shadow and Guest paging.
2993	* @{
2994	*/
2995	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
2996	/* no pfnR3BthTrap0eHandler */
2997	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
2998	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
2999	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3000	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3001	#ifdef VBOX_STRICT
3002	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3003	#endif
3004	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3005	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3006
3007	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3008	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3009	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3010	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3011	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3012	#ifdef VBOX_STRICT
3013	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3014	#endif
3015	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3016	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3017
3018	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3019	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3020	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3021	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3022	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3023	#ifdef VBOX_STRICT
3024	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3025	#endif
3026	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3027	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3028	/** @} */
3029	} PGMMODEDATA, *PPGMMODEDATA;
3030
3031
3032	#ifdef VBOX_WITH_STATISTICS
3033	/**
3034	* PGM statistics.
3035	*
3036	* These lives on the heap when compiled in as they would otherwise waste
3037	* unnecessary space in release builds.
3038	*/
3039	typedef struct PGMSTATS
3040	{
3041	/* R3 only: */
3042	STAMCOUNTER StatR3DetectedConflicts; /*< R3: Number of times PGMR3MapHasConflicts() detected a conflict. /
3043	STAMPROFILE StatR3ResolveConflict; /*< R3: pgmR3SyncPTResolveConflict() profiling (includes the entire relocation). /
3044
3045	/* R3+RZ */
3046	STAMCOUNTER StatRZChunkR3MapTlbHits; /*< RC/R0: Ring-3/0 chunk mapper TLB hits. /
3047	STAMCOUNTER StatRZChunkR3MapTlbMisses; /*< RC/R0: Ring-3/0 chunk mapper TLB misses. /
3048	STAMCOUNTER StatRZPageMapTlbHits; /*< RC/R0: Ring-3/0 page mapper TLB hits. /
3049	STAMCOUNTER StatRZPageMapTlbMisses; /*< RC/R0: Ring-3/0 page mapper TLB misses. /
3050	STAMCOUNTER StatPageMapTlbFlushes; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3051	STAMCOUNTER StatPageMapTlbFlushEntry; /*< ALL: Ring-3/0 page mapper TLB flushes. /
3052	STAMCOUNTER StatR3ChunkR3MapTlbHits; /*< R3: Ring-3/0 chunk mapper TLB hits. /
3053	STAMCOUNTER StatR3ChunkR3MapTlbMisses; /*< R3: Ring-3/0 chunk mapper TLB misses. /
3054	STAMCOUNTER StatR3PageMapTlbHits; /*< R3: Ring-3/0 page mapper TLB hits. /
3055	STAMCOUNTER StatR3PageMapTlbMisses; /*< R3: Ring-3/0 page mapper TLB misses. /
3056	STAMCOUNTER StatRZRamRangeTlbHits; /*< RC/R0: RAM range TLB hits. /
3057	STAMCOUNTER StatRZRamRangeTlbMisses; /*< RC/R0: RAM range TLB misses. /
3058	STAMCOUNTER StatR3RamRangeTlbHits; /*< R3: RAM range TLB hits. /
3059	STAMCOUNTER StatR3RamRangeTlbMisses; /*< R3: RAM range TLB misses. /
3060	STAMPROFILE StatRZSyncCR3HandlerVirtualReset; /*< RC/R0: Profiling of the virtual handler resets. /
3061	STAMPROFILE StatRZSyncCR3HandlerVirtualUpdate; /*< RC/R0: Profiling of the virtual handler updates. /
3062	STAMPROFILE StatR3SyncCR3HandlerVirtualReset; /*< R3: Profiling of the virtual handler resets. /
3063	STAMPROFILE StatR3SyncCR3HandlerVirtualUpdate; /*< R3: Profiling of the virtual handler updates. /
3064	STAMCOUNTER StatR3PhysHandlerReset; /*< R3: The number of times PGMHandlerPhysicalReset is called. /
3065	STAMCOUNTER StatRZPhysHandlerReset; /*< RC/R0: The number of times PGMHandlerPhysicalReset is called. /
3066	STAMCOUNTER StatR3PhysHandlerLookupHits; /*< R3: Number of cache hits when looking up physical handlers. /
3067	STAMCOUNTER StatR3PhysHandlerLookupMisses; /*< R3: Number of cache misses when looking up physical handlers. /
3068	STAMCOUNTER StatRZPhysHandlerLookupHits; /*< RC/R0: Number of cache hits when lookup up physical handlers. /
3069	STAMCOUNTER StatRZPhysHandlerLookupMisses; /*< RC/R0: Number of cache misses when looking up physical handlers /
3070	STAMPROFILE StatRZVirtHandlerSearchByPhys; /*< RC/R0: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3071	STAMPROFILE StatR3VirtHandlerSearchByPhys; /*< R3: Profiling of pgmHandlerVirtualFindByPhysAddr. /
3072	STAMCOUNTER StatRZPageReplaceShared; /*< RC/R0: Times a shared page has been replaced by a private one. /
3073	STAMCOUNTER StatRZPageReplaceZero; /*< RC/R0: Times the zero page has been replaced by a private one. /
3074	/// @todo STAMCOUNTER StatRZPageHandyAllocs; /*< RC/R0: The number of times we've executed GMMR3AllocateHandyPages. /
3075	STAMCOUNTER StatR3PageReplaceShared; /*< R3: Times a shared page has been replaced by a private one. /
3076	STAMCOUNTER StatR3PageReplaceZero; /*< R3: Times the zero page has been replaced by a private one. /
3077	/// @todo STAMCOUNTER StatR3PageHandyAllocs; /*< R3: The number of times we've executed GMMR3AllocateHandyPages. /
3078
3079	/* RC only: */
3080	STAMCOUNTER StatRCInvlPgConflict; /*< RC: Number of times PGMInvalidatePage() detected a mapping conflict. /
3081	STAMCOUNTER StatRCInvlPgSyncMonCR3; /*< RC: Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3. /
3082
3083	STAMCOUNTER StatRZPhysRead;
3084	STAMCOUNTER StatRZPhysReadBytes;
3085	STAMCOUNTER StatRZPhysWrite;
3086	STAMCOUNTER StatRZPhysWriteBytes;
3087	STAMCOUNTER StatR3PhysRead;
3088	STAMCOUNTER StatR3PhysReadBytes;
3089	STAMCOUNTER StatR3PhysWrite;
3090	STAMCOUNTER StatR3PhysWriteBytes;
3091	STAMCOUNTER StatRCPhysRead;
3092	STAMCOUNTER StatRCPhysReadBytes;
3093	STAMCOUNTER StatRCPhysWrite;
3094	STAMCOUNTER StatRCPhysWriteBytes;
3095
3096	STAMCOUNTER StatRZPhysSimpleRead;
3097	STAMCOUNTER StatRZPhysSimpleReadBytes;
3098	STAMCOUNTER StatRZPhysSimpleWrite;
3099	STAMCOUNTER StatRZPhysSimpleWriteBytes;
3100	STAMCOUNTER StatR3PhysSimpleRead;
3101	STAMCOUNTER StatR3PhysSimpleReadBytes;
3102	STAMCOUNTER StatR3PhysSimpleWrite;
3103	STAMCOUNTER StatR3PhysSimpleWriteBytes;
3104	STAMCOUNTER StatRCPhysSimpleRead;
3105	STAMCOUNTER StatRCPhysSimpleReadBytes;
3106	STAMCOUNTER StatRCPhysSimpleWrite;
3107	STAMCOUNTER StatRCPhysSimpleWriteBytes;
3108
3109	STAMCOUNTER StatTrackVirgin; /*< The number of first time shadowings. /
3110	STAMCOUNTER StatTrackAliased; /*< The number of times switching to cRef2, i.e. the page is being shadowed by two PTs. /
3111	STAMCOUNTER StatTrackAliasedMany; /*< The number of times we're tracking using cRef2. /
3112	STAMCOUNTER StatTrackAliasedLots; /*< The number of times we're hitting pages which has overflowed cRef2. /
3113	STAMCOUNTER StatTrackNoExtentsLeft; /*< The number of times the extent list was exhausted. /
3114	STAMCOUNTER StatTrackOverflows; /*< The number of times the extent list grows to long. /
3115	STAMPROFILE StatTrackDeref; /*< Profiling of SyncPageWorkerTrackDeref (expensive). /
3116
3117	/** Time spent by the host OS for large page allocation. */
3118	STAMPROFILE StatAllocLargePage;
3119	/** Time spent clearing the newly allocated large pages. */
3120	STAMPROFILE StatClearLargePage;
3121	/** The number of times allocating a large pages takes more than the allowed period. */
3122	STAMCOUNTER StatLargePageOverflow;
3123	/** pgmPhysIsValidLargePage profiling - R3 */
3124	STAMPROFILE StatR3IsValidLargePage;
3125	/** pgmPhysIsValidLargePage profiling - RZ*/
3126	STAMPROFILE StatRZIsValidLargePage;
3127
3128	STAMPROFILE StatChunkAging;
3129	STAMPROFILE StatChunkFindCandidate;
3130	STAMPROFILE StatChunkUnmap;
3131	STAMPROFILE StatChunkMap;
3132	} PGMSTATS;
3133	#endif /* VBOX_WITH_STATISTICS */
3134
3135
3136	/**
3137	* Converts a PGM pointer into a VM pointer.
3138	* @returns Pointer to the VM structure the PGM is part of.
3139	* @param pPGM Pointer to PGM instance data.
3140	*/
3141	#define PGM2VM(pPGM) ( (PVM)((char*)pPGM - pPGM->offVM) )
3142
3143	/**
3144	* PGM Data (part of VM)
3145	*/
3146	typedef struct PGM
3147	{
3148	/** Offset to the VM structure. */
3149	int32_t offVM;
3150	/** Offset of the PGMCPU structure relative to VMCPU. */
3151	int32_t offVCpuPGM;
3152
3153	/** @cfgm{/RamPreAlloc, boolean, false}
3154	* Indicates whether the base RAM should all be allocated before starting
3155	* the VM (default), or if it should be allocated when first written to.
3156	*/
3157	bool fRamPreAlloc;
3158	/** Indicates whether write monitoring is currently in use.
3159	* This is used to prevent conflicts between live saving and page sharing
3160	* detection. */
3161	bool fPhysWriteMonitoringEngaged;
3162	/** Set if the CPU has less than 52-bit physical address width.
3163	* This is used */
3164	bool fLessThan52PhysicalAddressBits;
3165	/** Set when nested paging is active.
3166	* This is meant to save calls to HMIsNestedPagingActive and let the
3167	* compilers optimize the code better. Whether we use nested paging or
3168	* not is something we find out during VMM initialization and we won't
3169	* change this later on. */
3170	bool fNestedPaging;
3171	/** The host paging mode. (This is what SUPLib reports.) */
3172	SUPPAGINGMODE enmHostMode;
3173	/** We're not in a state which permits writes to guest memory.
3174	* (Only used in strict builds.) */
3175	bool fNoMorePhysWrites;
3176	/** Set if PCI passthrough is enabled. */
3177	bool fPciPassthrough;
3178	/** The number of MMIO2 regions (serves as the next MMIO2 ID). */
3179	uint8_t cMmio2Regions;
3180	/** Alignment padding that makes the next member start on a 8 byte boundary. */
3181	bool afAlignment1[2];
3182
3183	/** Indicates that PGMR3FinalizeMappings has been called and that further
3184	* PGMR3MapIntermediate calls will be rejected. */
3185	bool fFinalizedMappings;
3186	/** If set no conflict checks are required. */
3187	bool fMappingsFixed;
3188	/** If set if restored as fixed but we were unable to re-fixate at the old
3189	* location because of room or address incompatibilities. */
3190	bool fMappingsFixedRestored;
3191	/** Size of fixed mapping.
3192	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3193	uint32_t cbMappingFixed;
3194	/** Generation ID for the RAM ranges. This member is incremented everytime
3195	* a RAM range is linked or unlinked. */
3196	uint32_t volatile idRamRangesGen;
3197
3198	/** Base address (GC) of fixed mapping.
3199	* This is valid if either fMappingsFixed or fMappingsFixedRestored is set. */
3200	RTGCPTR GCPtrMappingFixed;
3201	/** The address of the previous RAM range mapping. */
3202	RTGCPTR GCPtrPrevRamRangeMapping;
3203
3204	/** Physical access handler type for ROM protection. */
3205	PGMPHYSHANDLERTYPE hRomPhysHandlerType;
3206	/** Alignment padding. */
3207	uint32_t u32Padding;
3208
3209	/** 4 MB page mask; 32 or 36 bits depending on PSE-36 (identical for all VCPUs) */
3210	RTGCPHYS GCPhys4MBPSEMask;
3211	/** Mask containing the invalid bits of a guest physical address.
3212	* @remarks this does not stop at bit 52. */
3213	RTGCPHYS GCPhysInvAddrMask;
3214
3215
3216	/** RAM range TLB for R3. */
3217	R3PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR3[PGM_RAMRANGE_TLB_ENTRIES];
3218	/** Pointer to the list of RAM ranges (Phys GC -> Phys HC conversion) - for R3.
3219	* This is sorted by physical address and contains no overlapping ranges. */
3220	R3PTRTYPE(PPGMRAMRANGE) pRamRangesXR3;
3221	/** Root of the RAM range search tree for ring-3. */
3222	R3PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR3;
3223	/** PGM offset based trees - R3 Ptr. */
3224	R3PTRTYPE(PPGMTREES) pTreesR3;
3225	/** Caching the last physical handler we looked up in R3. */
3226	R3PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR3;
3227	/** Shadow Page Pool - R3 Ptr. */
3228	R3PTRTYPE(PPGMPOOL) pPoolR3;
3229	/** Linked list of GC mappings - for HC.
3230	* The list is sorted ascending on address. */
3231	R3PTRTYPE(PPGMMAPPING) pMappingsR3;
3232	/** Pointer to the list of ROM ranges - for R3.
3233	* This is sorted by physical address and contains no overlapping ranges. */
3234	R3PTRTYPE(PPGMROMRANGE) pRomRangesR3;
3235	/** Pointer to the list of MMIO2 ranges - for R3.
3236	* Registration order. */
3237	R3PTRTYPE(PPGMMMIO2RANGE) pMmio2RangesR3;
3238	/** Pointer to SHW+GST mode data (function pointers).
3239	* The index into this table is made up from */
3240	R3PTRTYPE(PPGMMODEDATA) paModeData;
3241	RTR3PTR R3PtrAlignment0;
3242	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3243	R3PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR3[PGM_MMIO2_MAX_RANGES];
3244
3245	/** RAM range TLB for R0. */
3246	R0PTRTYPE(PPGMRAMRANGE) apRamRangesTlbR0[PGM_RAMRANGE_TLB_ENTRIES];
3247	/** R0 pointer corresponding to PGM::pRamRangesXR3. */
3248	R0PTRTYPE(PPGMRAMRANGE) pRamRangesXR0;
3249	/** Root of the RAM range search tree for ring-0. */
3250	R0PTRTYPE(PPGMRAMRANGE) pRamRangeTreeR0;
3251	/** PGM offset based trees - R0 Ptr. */
3252	R0PTRTYPE(PPGMTREES) pTreesR0;
3253	/** Caching the last physical handler we looked up in R0. */
3254	R0PTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerR0;
3255	/** Shadow Page Pool - R0 Ptr. */
3256	R0PTRTYPE(PPGMPOOL) pPoolR0;
3257	/** Linked list of GC mappings - for R0.
3258	* The list is sorted ascending on address. */
3259	R0PTRTYPE(PPGMMAPPING) pMappingsR0;
3260	/** R0 pointer corresponding to PGM::pRomRangesR3. */
3261	R0PTRTYPE(PPGMROMRANGE) pRomRangesR0;
3262	RTR0PTR R0PtrAlignment0;
3263	/** MMIO2 lookup array for ring-3. Indexed by idMmio2 minus 1. */
3264	R0PTRTYPE(PPGMMMIO2RANGE) apMmio2RangesR0[PGM_MMIO2_MAX_RANGES];
3265
3266	/** RAM range TLB for RC. */
3267	RCPTRTYPE(PPGMRAMRANGE) apRamRangesTlbRC[PGM_RAMRANGE_TLB_ENTRIES];
3268	/** RC pointer corresponding to PGM::pRamRangesXR3. */
3269	RCPTRTYPE(PPGMRAMRANGE) pRamRangesXRC;
3270	/** Root of the RAM range search tree for raw-mode context. */
3271	RCPTRTYPE(PPGMRAMRANGE) pRamRangeTreeRC;
3272	/** PGM offset based trees - RC Ptr. */
3273	RCPTRTYPE(PPGMTREES) pTreesRC;
3274	/** Caching the last physical handler we looked up in RC. */
3275	RCPTRTYPE(PPGMPHYSHANDLER) pLastPhysHandlerRC;
3276	/** Shadow Page Pool - RC Ptr. */
3277	RCPTRTYPE(PPGMPOOL) pPoolRC;
3278	/** Linked list of GC mappings - for RC.
3279	* The list is sorted ascending on address. */
3280	RCPTRTYPE(PPGMMAPPING) pMappingsRC;
3281	/** RC pointer corresponding to PGM::pRomRangesR3. */
3282	RCPTRTYPE(PPGMROMRANGE) pRomRangesRC;
3283	RTRCPTR RCPtrAlignment0;
3284	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3285	RCPTRTYPE(PX86PTE) paDynPageMap32BitPTEsGC;
3286	/** Pointer to the page table entries for the dynamic page mapping area - GCPtr. */
3287	RCPTRTYPE(PPGMSHWPTEPAE) paDynPageMapPaePTEsGC;
3288
3289
3290	/** Pointer to the 5 page CR3 content mapping.
3291	* The first page is always the CR3 (in some form) while the 4 other pages
3292	* are used of the PDs in PAE mode. */
3293	RTGCPTR GCPtrCR3Mapping;
3294
3295	/** @name Intermediate Context
3296	* @{ */
3297	/** Pointer to the intermediate page directory - Normal. */
3298	R3PTRTYPE(PX86PD) pInterPD;
3299	/** Pointer to the intermediate page tables - Normal.
3300	* There are two page tables, one for the identity mapping and one for
3301	* the host context mapping (of the core code). */
3302	R3PTRTYPE(PX86PT) apInterPTs[2];
3303	/** Pointer to the intermediate page tables - PAE. */
3304	R3PTRTYPE(PX86PTPAE) apInterPaePTs[2];
3305	/** Pointer to the intermediate page directory - PAE. */
3306	R3PTRTYPE(PX86PDPAE) apInterPaePDs[4];
3307	/** Pointer to the intermediate page directory - PAE. */
3308	R3PTRTYPE(PX86PDPT) pInterPaePDPT;
3309	/** Pointer to the intermediate page-map level 4 - AMD64. */
3310	R3PTRTYPE(PX86PML4) pInterPaePML4;
3311	/** Pointer to the intermediate page directory - AMD64. */
3312	R3PTRTYPE(PX86PDPT) pInterPaePDPT64;
3313	/** The Physical Address (HC) of the intermediate Page Directory - Normal. */
3314	RTHCPHYS HCPhysInterPD;
3315	/** The Physical Address (HC) of the intermediate Page Directory Pointer Table - PAE. */
3316	RTHCPHYS HCPhysInterPaePDPT;
3317	/** The Physical Address (HC) of the intermediate Page Map Level 4 table - AMD64. */
3318	RTHCPHYS HCPhysInterPaePML4;
3319	/** @} */
3320
3321	/** Base address of the dynamic page mapping area.
3322	* The array is MM_HYPER_DYNAMIC_SIZE bytes big.
3323	*
3324	* @todo The plan of keeping PGMRCDYNMAP private to PGMRZDynMap.cpp didn't
3325	* work out. Some cleaning up of the initialization that would
3326	* remove this memory is yet to be done...
3327	*/
3328	RCPTRTYPE(uint8_t *) pbDynPageMapBaseGC;
3329	/** The address of the raw-mode context mapping cache. */
3330	RCPTRTYPE(PPGMRCDYNMAP) pRCDynMap;
3331	/** The address of the ring-0 mapping cache if we're making use of it. */
3332	RTR0PTR pvR0DynMapUsed;
3333
3334	/** Hack: Number of deprecated page mapping locks taken by the current lock
3335	* owner via pgmPhysGCPhys2CCPtrInternalDepr. */
3336	uint32_t cDeprecatedPageLocks;
3337	#if HC_ARCH_BITS == 64
3338	/** Alignment padding. */
3339	uint32_t u32Alignment2;
3340	#endif
3341
3342
3343	/** PGM critical section.
3344	* This protects the physical & virtual access handlers, ram ranges,
3345	* and the page flag updating (some of it anyway).
3346	*/
3347	PDMCRITSECT CritSectX;
3348
3349	/**
3350	* Data associated with managing the ring-3 mappings of the allocation chunks.
3351	*/
3352	struct
3353	{
3354	/** The chunk tree, ordered by chunk id. */
3355	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
3356	R3PTRTYPE(PAVLU32NODECORE) pTree;
3357	#else
3358	R3R0PTRTYPE(PAVLU32NODECORE) pTree;
3359	#endif
3360	#if HC_ARCH_BITS == 32
3361	uint32_t u32Alignment0;
3362	#endif
3363	/** The chunk mapping TLB. */
3364	PGMCHUNKR3MAPTLB Tlb;
3365	/** The number of mapped chunks. */
3366	uint32_t c;
3367	/** @cfgm{/PGM/MaxRing3Chunks, uint32_t, host dependent}
3368	* The maximum number of mapped chunks. On 64-bit this is unlimited by default,
3369	* on 32-bit it defaults to 1 or 3 GB depending on the host. */
3370	uint32_t cMax;
3371	/** The current time. This is incremented whenever a chunk is inserted. */
3372	uint32_t iNow;
3373	/** Alignment padding. */
3374	uint32_t u32Alignment1;
3375	} ChunkR3Map;
3376
3377	/**
3378	* The page mapping TLB for ring-3 and (for the time being) ring-0.
3379	*/
3380	PGMPAGER3MAPTLB PhysTlbHC;
3381
3382	/** @name The zero page.
3383	* @{ */
3384	/** The host physical address of the zero page. */
3385	RTHCPHYS HCPhysZeroPg;
3386	/** The ring-3 mapping of the zero page. */
3387	RTR3PTR pvZeroPgR3;
3388	/** The ring-0 mapping of the zero page. */
3389	RTR0PTR pvZeroPgR0;
3390	/** The GC mapping of the zero page. */
3391	RTRCPTR pvZeroPgRC;
3392	RTRCPTR RCPtrAlignment3;
3393	/** @}*/
3394
3395	/** @name The Invalid MMIO page.
3396	* This page is filled with 0xfeedface.
3397	* @{ */
3398	/** The host physical address of the invalid MMIO page. */
3399	RTHCPHYS HCPhysMmioPg;
3400	/** The host pysical address of the invalid MMIO page plus all invalid
3401	* physical address bits set. This is used to trigger X86_TRAP_PF_RSVD.
3402	* @remarks Check fLessThan52PhysicalAddressBits before use. */
3403	RTHCPHYS HCPhysInvMmioPg;
3404	/** The ring-3 mapping of the invalid MMIO page. */
3405	RTR3PTR pvMmioPgR3;
3406	#if HC_ARCH_BITS == 32
3407	RTR3PTR R3PtrAlignment4;
3408	#endif
3409	/** @} */
3410
3411
3412	/** The number of handy pages. */
3413	uint32_t cHandyPages;
3414
3415	/** The number of large handy pages. */
3416	uint32_t cLargeHandyPages;
3417
3418	/**
3419	* Array of handy pages.
3420	*
3421	* This array is used in a two way communication between pgmPhysAllocPage
3422	* and GMMR0AllocateHandyPages, with PGMR3PhysAllocateHandyPages serving as
3423	* an intermediary.
3424	*
3425	* The size of this array is important, see pgmPhysEnsureHandyPage for details.
3426	* (The current size of 32 pages, means 128 KB of handy memory.)
3427	*/
3428	GMMPAGEDESC aHandyPages[PGM_HANDY_PAGES];
3429
3430	/**
3431	* Array of large handy pages. (currently size 1)
3432	*
3433	* This array is used in a two way communication between pgmPhysAllocLargePage
3434	* and GMMR0AllocateLargePage, with PGMR3PhysAllocateLargePage serving as
3435	* an intermediary.
3436	*/
3437	GMMPAGEDESC aLargeHandyPage[1];
3438
3439	/**
3440	* Live save data.
3441	*/
3442	struct
3443	{
3444	/** Per type statistics. */
3445	struct
3446	{
3447	/** The number of ready pages. */
3448	uint32_t cReadyPages;
3449	/** The number of dirty pages. */
3450	uint32_t cDirtyPages;
3451	/** The number of ready zero pages. */
3452	uint32_t cZeroPages;
3453	/** The number of write monitored pages. */
3454	uint32_t cMonitoredPages;
3455	} Rom,
3456	Mmio2,
3457	Ram;
3458	/** The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM). */
3459	uint32_t cIgnoredPages;
3460	/** Indicates that a live save operation is active. */
3461	bool fActive;
3462	/** Padding. */
3463	bool afReserved[2];
3464	/** The next history index. */
3465	uint8_t iDirtyPagesHistory;
3466	/** History of the total amount of dirty pages. */
3467	uint32_t acDirtyPagesHistory[64];
3468	/** Short term dirty page average. */
3469	uint32_t cDirtyPagesShort;
3470	/** Long term dirty page average. */
3471	uint32_t cDirtyPagesLong;
3472	/** The number of saved pages. This is used to get some kind of estimate of the
3473	* link speed so we can decide when we're done. It is reset after the first
3474	* 7 passes so the speed estimate doesn't get inflated by the initial set of
3475	* zero pages. */
3476	uint64_t cSavedPages;
3477	/** The nanosecond timestamp when cSavedPages was 0. */
3478	uint64_t uSaveStartNS;
3479	/** Pages per second (for statistics). */
3480	uint32_t cPagesPerSecond;
3481	uint32_t cAlignment;
3482	} LiveSave;
3483
3484	/** @name Error injection.
3485	* @{ */
3486	/** Inject handy page allocation errors pretending we're completely out of
3487	* memory. */
3488	bool volatile fErrInjHandyPages;
3489	/** Padding. */
3490	bool afReserved[3];
3491	/** @} */
3492
3493	/** @name Release Statistics
3494	* @{ */
3495	uint32_t cAllPages; /*< The total number of pages. (Should be Private + Shared + Zero + Pure MMIO.) /
3496	uint32_t cPrivatePages; /*< The number of private pages. /
3497	uint32_t cSharedPages; /*< The number of shared pages. /
3498	uint32_t cReusedSharedPages; /*< The number of reused shared pages. /
3499	uint32_t cZeroPages; /*< The number of zero backed pages. /
3500	uint32_t cPureMmioPages; /*< The number of pure MMIO pages. /
3501	uint32_t cMonitoredPages; /*< The number of write monitored pages. /
3502	uint32_t cWrittenToPages; /*< The number of previously write monitored pages. /
3503	uint32_t cWriteLockedPages; /*< The number of write locked pages. /
3504	uint32_t cReadLockedPages; /*< The number of read locked pages. /
3505	uint32_t cBalloonedPages; /*< The number of ballooned pages. /
3506	uint32_t cMappedChunks; /*< Number of times we mapped a chunk. /
3507	uint32_t cUnmappedChunks; /*< Number of times we unmapped a chunk. /
3508	uint32_t cLargePages; /*< The number of large pages. /
3509	uint32_t cLargePagesDisabled; /*< The number of disabled large pages. /
3510	/* uint32_t aAlignment4[1]; */
3511
3512	/** The number of times we were forced to change the hypervisor region location. */
3513	STAMCOUNTER cRelocations;
3514
3515	STAMCOUNTER StatLargePageReused; /*< The number of large pages we've reused./
3516	STAMCOUNTER StatLargePageRefused; /*< The number of times we couldn't use a large page./
3517	STAMCOUNTER StatLargePageRecheck; /*< The number of times we rechecked a disabled large page./
3518
3519	STAMPROFILE StatShModCheck; /*< Profiles shared module checks. /
3520	/** @} */
3521
3522	#ifdef VBOX_WITH_STATISTICS
3523	/** @name Statistics on the heap.
3524	* @{ */
3525	R3PTRTYPE(PGMSTATS *) pStatsR3;
3526	R0PTRTYPE(PGMSTATS *) pStatsR0;
3527	RCPTRTYPE(PGMSTATS *) pStatsRC;
3528	RTRCPTR RCPtrAlignment;
3529	/** @} */
3530	#endif
3531	} PGM;
3532	#ifndef IN_TSTVMSTRUCTGC /* HACK */
3533	AssertCompileMemberAlignment(PGM, paDynPageMap32BitPTEsGC, 8);
3534	AssertCompileMemberAlignment(PGM, GCPtrMappingFixed, sizeof(RTGCPTR));
3535	AssertCompileMemberAlignment(PGM, HCPhysInterPD, 8);
3536	AssertCompileMemberAlignment(PGM, CritSectX, 8);
3537	AssertCompileMemberAlignment(PGM, ChunkR3Map, 8);
3538	AssertCompileMemberAlignment(PGM, PhysTlbHC, 8);
3539	AssertCompileMemberAlignment(PGM, HCPhysZeroPg, 8);
3540	AssertCompileMemberAlignment(PGM, aHandyPages, 8);
3541	AssertCompileMemberAlignment(PGM, cRelocations, 8);
3542	#endif /* !IN_TSTVMSTRUCTGC */
3543	/** Pointer to the PGM instance data. */
3544	typedef PGM *PPGM;
3545
3546
3547
3548	typedef struct PGMCPUSTATS
3549	{
3550	/* Common */
3551	STAMCOUNTER StatSyncPtPD[X86_PG_ENTRIES]; /*< SyncPT - PD distribution. /
3552	STAMCOUNTER StatSyncPagePD[X86_PG_ENTRIES]; /*< SyncPage - PD distribution. /
3553
3554	/* R0 only: */
3555	STAMPROFILE StatR0NpMiscfg; /*< R0: PGMR0Trap0eHandlerNPMisconfig() profiling. /
3556	STAMCOUNTER StatR0NpMiscfgSyncPage; /*< R0: SyncPage calls from PGMR0Trap0eHandlerNPMisconfig(). /
3557
3558	/* RZ only: */
3559	STAMPROFILE StatRZTrap0e; /*< RC/R0: PGMTrap0eHandler() profiling. /
3560	STAMPROFILE StatRZTrap0eTime2Ballooned; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is read access to a ballooned page. /
3561	STAMPROFILE StatRZTrap0eTime2CSAM; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CSAM. /
3562	STAMPROFILE StatRZTrap0eTime2DirtyAndAccessed; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation. /
3563	STAMPROFILE StatRZTrap0eTime2GuestTrap; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a guest trap. /
3564	STAMPROFILE StatRZTrap0eTime2HndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a physical handler. /
3565	STAMPROFILE StatRZTrap0eTime2HndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a virtual handler. /
3566	STAMPROFILE StatRZTrap0eTime2HndUnhandled; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page. /
3567	STAMPROFILE StatRZTrap0eTime2InvalidPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address. /
3568	STAMPROFILE StatRZTrap0eTime2MakeWritable; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is a page that needed to be made writable. /
3569	STAMPROFILE StatRZTrap0eTime2Mapping; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is the guest mappings. /
3570	STAMPROFILE StatRZTrap0eTime2Misc; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is not known. /
3571	STAMPROFILE StatRZTrap0eTime2OutOfSync; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync page. /
3572	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndPhys; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page. /
3573	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndVirt; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page. /
3574	STAMPROFILE StatRZTrap0eTime2OutOfSyncHndObs; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is an obsolete handler page. /
3575	STAMPROFILE StatRZTrap0eTime2SyncPT; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT. /
3576	STAMPROFILE StatRZTrap0eTime2WPEmulation; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP emulation. /
3577	STAMPROFILE StatRZTrap0eTime2Wp0RoUsHack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be enabled. /
3578	STAMPROFILE StatRZTrap0eTime2Wp0RoUsUnhack; /*< RC/R0: Profiling of the Trap0eHandler body when the cause is CR0.WP and netware hack to be disabled. /
3579	STAMCOUNTER StatRZTrap0eConflicts; /*< RC/R0: The number of times \#PF was caused by an undetected conflict. /
3580	STAMCOUNTER StatRZTrap0eHandlersMapping; /*< RC/R0: Number of traps due to access handlers in mappings. /
3581	STAMCOUNTER StatRZTrap0eHandlersOutOfSync; /*< RC/R0: Number of out-of-sync handled pages. /
3582	STAMCOUNTER StatRZTrap0eHandlersPhysAll; /*< RC/R0: Number of traps due to physical all-access handlers. /
3583	STAMCOUNTER StatRZTrap0eHandlersPhysAllOpt; /*< RC/R0: Number of the physical all-access handler traps using the optimization. /
3584	STAMCOUNTER StatRZTrap0eHandlersPhysWrite; /*< RC/R0: Number of traps due to write-physical access handlers. /
3585	STAMCOUNTER StatRZTrap0eHandlersVirtual; /*< RC/R0: Number of traps due to virtual access handlers. /
3586	STAMCOUNTER StatRZTrap0eHandlersVirtualByPhys; /*< RC/R0: Number of traps due to virtual access handlers found by physical address. /
3587	STAMCOUNTER StatRZTrap0eHandlersVirtualUnmarked;/*< RC/R0: Number of traps due to virtual access handlers found by virtual address (without proper physical flags). /
3588	STAMCOUNTER StatRZTrap0eHandlersUnhandled; /*< RC/R0: Number of traps due to access outside range of monitored page(s). /
3589	STAMCOUNTER StatRZTrap0eHandlersInvalid; /*< RC/R0: Number of traps due to access to invalid physical memory. /
3590	STAMCOUNTER StatRZTrap0eUSNotPresentRead; /*< RC/R0: \#PF err kind /
3591	STAMCOUNTER StatRZTrap0eUSNotPresentWrite; /*< RC/R0: \#PF err kind /
3592	STAMCOUNTER StatRZTrap0eUSWrite; /*< RC/R0: \#PF err kind /
3593	STAMCOUNTER StatRZTrap0eUSReserved; /*< RC/R0: \#PF err kind /
3594	STAMCOUNTER StatRZTrap0eUSNXE; /*< RC/R0: \#PF err kind /
3595	STAMCOUNTER StatRZTrap0eUSRead; /*< RC/R0: \#PF err kind /
3596	STAMCOUNTER StatRZTrap0eSVNotPresentRead; /*< RC/R0: \#PF err kind /
3597	STAMCOUNTER StatRZTrap0eSVNotPresentWrite; /*< RC/R0: \#PF err kind /
3598	STAMCOUNTER StatRZTrap0eSVWrite; /*< RC/R0: \#PF err kind /
3599	STAMCOUNTER StatRZTrap0eSVReserved; /*< RC/R0: \#PF err kind /
3600	STAMCOUNTER StatRZTrap0eSNXE; /*< RC/R0: \#PF err kind /
3601	STAMCOUNTER StatRZTrap0eGuestPF; /*< RC/R0: Real guest \#PFs. /
3602	STAMCOUNTER StatRZTrap0eGuestPFMapping; /*< RC/R0: Real guest \#PF to HMA or other mapping. /
3603	STAMCOUNTER StatRZTrap0eWPEmulInRZ; /*< RC/R0: WP=0 virtualization trap, handled. /
3604	STAMCOUNTER StatRZTrap0eWPEmulToR3; /*< RC/R0: WP=0 virtualization trap, chickened out. /
3605	STAMCOUNTER StatRZTrap0ePD[X86_PG_ENTRIES]; /*< RC/R0: PD distribution of the \#PFs. /
3606	STAMCOUNTER StatRZGuestCR3WriteHandled; /*< RC/R0: The number of times WriteHandlerCR3() was successfully called. /
3607	STAMCOUNTER StatRZGuestCR3WriteUnhandled; /*< RC/R0: The number of times WriteHandlerCR3() was called and we had to fall back to the recompiler. /
3608	STAMCOUNTER StatRZGuestCR3WriteConflict; /*< RC/R0: The number of times WriteHandlerCR3() was called and a conflict was detected. /
3609	STAMCOUNTER StatRZGuestROMWriteHandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was successfully called. /
3610	STAMCOUNTER StatRZGuestROMWriteUnhandled; /*< RC/R0: The number of times pgmPhysRomWriteHandler() was called and we had to fall back to the recompiler /
3611	STAMCOUNTER StatRZDynMapMigrateInvlPg; /*< RZ: invlpg in PGMR0DynMapMigrateAutoSet. /
3612	STAMPROFILE StatRZDynMapGCPageInl; /*< RZ: Calls to pgmRZDynMapGCPageInlined. /
3613	STAMCOUNTER StatRZDynMapGCPageInlHits; /*< RZ: Hash table lookup hits. /
3614	STAMCOUNTER StatRZDynMapGCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3615	STAMCOUNTER StatRZDynMapGCPageInlRamHits; /*< RZ: 1st ram range hits. /
3616	STAMCOUNTER StatRZDynMapGCPageInlRamMisses; /*< RZ: 1st ram range misses, takes slow path. /
3617	STAMPROFILE StatRZDynMapHCPageInl; /*< RZ: Calls to pgmRZDynMapHCPageInlined. /
3618	STAMCOUNTER StatRZDynMapHCPageInlHits; /*< RZ: Hash table lookup hits. /
3619	STAMCOUNTER StatRZDynMapHCPageInlMisses; /*< RZ: Misses that falls back to the code common. /
3620	STAMPROFILE StatRZDynMapHCPage; /*< RZ: Calls to pgmRZDynMapHCPageCommon. /
3621	STAMCOUNTER StatRZDynMapSetOptimize; /*< RZ: Calls to pgmRZDynMapOptimizeAutoSet. /
3622	STAMCOUNTER StatRZDynMapSetSearchFlushes; /*< RZ: Set search restoring to subset flushes. /
3623	STAMCOUNTER StatRZDynMapSetSearchHits; /*< RZ: Set search hits. /
3624	STAMCOUNTER StatRZDynMapSetSearchMisses; /*< RZ: Set search misses. /
3625	STAMCOUNTER StatRZDynMapPage; /*< RZ: Calls to pgmR0DynMapPage. /
3626	STAMCOUNTER StatRZDynMapPageHits0; /*< RZ: Hits at iPage+0. /
3627	STAMCOUNTER StatRZDynMapPageHits1; /*< RZ: Hits at iPage+1. /
3628	STAMCOUNTER StatRZDynMapPageHits2; /*< RZ: Hits at iPage+2. /
3629	STAMCOUNTER StatRZDynMapPageInvlPg; /*< RZ: invlpg. /
3630	STAMCOUNTER StatRZDynMapPageSlow; /*< RZ: Calls to pgmR0DynMapPageSlow. /
3631	STAMCOUNTER StatRZDynMapPageSlowLoopHits; /*< RZ: Hits in the pgmR0DynMapPageSlow search loop. /
3632	STAMCOUNTER StatRZDynMapPageSlowLoopMisses; /*< RZ: Misses in the pgmR0DynMapPageSlow search loop. /
3633	//STAMCOUNTER StatRZDynMapPageSlowLostHits; /*< RZ: Lost hits. /
3634	STAMCOUNTER StatRZDynMapSubsets; /*< RZ: Times PGMDynMapPushAutoSubset was called. /
3635	STAMCOUNTER StatRZDynMapPopFlushes; /*< RZ: Times PGMDynMapPopAutoSubset flushes the subset. /
3636	STAMCOUNTER aStatRZDynMapSetFilledPct[11]; /*< RZ: Set fill distribution, percent. /
3637
3638	/* HC - R3 and (maybe) R0: */
3639
3640	/* RZ & R3: */
3641	STAMPROFILE StatRZSyncCR3; /*< RC/R0: PGMSyncCR3() profiling. /
3642	STAMPROFILE StatRZSyncCR3Handlers; /*< RC/R0: Profiling of the PGMSyncCR3() update handler section. /
3643	STAMCOUNTER StatRZSyncCR3Global; /*< RC/R0: The number of global CR3 syncs. /
3644	STAMCOUNTER StatRZSyncCR3NotGlobal; /*< RC/R0: The number of non-global CR3 syncs. /
3645	STAMCOUNTER StatRZSyncCR3DstCacheHit; /*< RC/R0: The number of times we got some kind of cache hit on a page table. /
3646	STAMCOUNTER StatRZSyncCR3DstFreed; /*< RC/R0: The number of times we've had to free a shadow entry. /
3647	STAMCOUNTER StatRZSyncCR3DstFreedSrcNP; /*< RC/R0: The number of times we've had to free a shadow entry for which the source entry was not present. /
3648	STAMCOUNTER StatRZSyncCR3DstNotPresent; /*< RC/R0: The number of times we've encountered a not present shadow entry for a present guest entry. /
3649	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPD; /*< RC/R0: The number of times a global page directory wasn't flushed. /
3650	STAMCOUNTER StatRZSyncCR3DstSkippedGlobalPT; /*< RC/R0: The number of times a page table with only global entries wasn't flushed. /
3651	STAMPROFILE StatRZSyncPT; /*< RC/R0: PGMSyncPT() profiling. /
3652	STAMCOUNTER StatRZSyncPTFailed; /*< RC/R0: The number of times PGMSyncPT() failed. /
3653	STAMCOUNTER StatRZSyncPT4K; /*< RC/R0: Number of 4KB syncs. /
3654	STAMCOUNTER StatRZSyncPT4M; /*< RC/R0: Number of 4MB syncs. /
3655	STAMCOUNTER StatRZSyncPagePDNAs; /*< RC/R0: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3656	STAMCOUNTER StatRZSyncPagePDOutOfSync; /*< RC/R0: The number of time we've encountered an out-of-sync PD in SyncPage. /
3657	STAMCOUNTER StatRZAccessedPage; /*< RC/R0: The number of pages marked not present for accessed bit emulation. /
3658	STAMPROFILE StatRZDirtyBitTracking; /*< RC/R0: Profiling the dirty bit tracking in CheckPageFault().. /
3659	STAMCOUNTER StatRZDirtyPage; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3660	STAMCOUNTER StatRZDirtyPageBig; /*< RC/R0: The number of pages marked read-only for dirty bit tracking. /
3661	STAMCOUNTER StatRZDirtyPageSkipped; /*< RC/R0: The number of pages already dirty or readonly. /
3662	STAMCOUNTER StatRZDirtyPageTrap; /*< RC/R0: The number of traps generated for dirty bit tracking. /
3663	STAMCOUNTER StatRZDirtyPageStale; /*< RC/R0: The number of traps generated for dirty bit tracking. (stale tlb entries) /
3664	STAMCOUNTER StatRZDirtyTrackRealPF; /*< RC/R0: The number of real pages faults during dirty bit tracking. /
3665	STAMCOUNTER StatRZDirtiedPage; /*< RC/R0: The number of pages marked dirty because of write accesses. /
3666	STAMCOUNTER StatRZPageAlreadyDirty; /*< RC/R0: The number of pages already marked dirty because of write accesses. /
3667	STAMPROFILE StatRZInvalidatePage; /*< RC/R0: PGMInvalidatePage() profiling. /
3668	STAMCOUNTER StatRZInvalidatePage4KBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4KB page. /
3669	STAMCOUNTER StatRZInvalidatePage4MBPages; /*< RC/R0: The number of times PGMInvalidatePage() was called for a 4MB page. /
3670	STAMCOUNTER StatRZInvalidatePage4MBPagesSkip; /*< RC/R0: The number of times PGMInvalidatePage() skipped a 4MB page. /
3671	STAMCOUNTER StatRZInvalidatePagePDMappings; /*< RC/R0: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3672	STAMCOUNTER StatRZInvalidatePagePDNAs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3673	STAMCOUNTER StatRZInvalidatePagePDNPs; /*< RC/R0: The number of times PGMInvalidatePage() was called for a not present page directory. /
3674	STAMCOUNTER StatRZInvalidatePagePDOutOfSync; /*< RC/R0: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3675	STAMCOUNTER StatRZInvalidatePageSkipped; /*< RC/R0: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3676	STAMCOUNTER StatRZPageOutOfSyncUser; /*< RC/R0: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3677	STAMCOUNTER StatRZPageOutOfSyncSupervisor; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3678	STAMCOUNTER StatRZPageOutOfSyncUserWrite; /*< RC/R0: The number of times user page is out of sync was detected in \#PF. /
3679	STAMCOUNTER StatRZPageOutOfSyncSupervisorWrite; /*< RC/R0: The number of times supervisor page is out of sync was detected in in \#PF. /
3680	STAMCOUNTER StatRZPageOutOfSyncBallloon; /*< RC/R0: The number of times a ballooned page was accessed (read). /
3681	STAMPROFILE StatRZPrefetch; /*< RC/R0: PGMPrefetchPage. /
3682	STAMPROFILE StatRZFlushTLB; /*< RC/R0: Profiling of the PGMFlushTLB() body. /
3683	STAMCOUNTER StatRZFlushTLBNewCR3; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3684	STAMCOUNTER StatRZFlushTLBNewCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3685	STAMCOUNTER StatRZFlushTLBSameCR3; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3686	STAMCOUNTER StatRZFlushTLBSameCR3Global; /*< RC/R0: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3687	STAMPROFILE StatRZGstModifyPage; /*< RC/R0: Profiling of the PGMGstModifyPage() body /
3688
3689	STAMPROFILE StatR3SyncCR3; /*< R3: PGMSyncCR3() profiling. /
3690	STAMPROFILE StatR3SyncCR3Handlers; /*< R3: Profiling of the PGMSyncCR3() update handler section. /
3691	STAMCOUNTER StatR3SyncCR3Global; /*< R3: The number of global CR3 syncs. /
3692	STAMCOUNTER StatR3SyncCR3NotGlobal; /*< R3: The number of non-global CR3 syncs. /
3693	STAMCOUNTER StatR3SyncCR3DstFreed; /*< R3: The number of times we've had to free a shadow entry. /
3694	STAMCOUNTER StatR3SyncCR3DstFreedSrcNP; /*< R3: The number of times we've had to free a shadow entry for which the source entry was not present. /
3695	STAMCOUNTER StatR3SyncCR3DstNotPresent; /*< R3: The number of times we've encountered a not present shadow entry for a present guest entry. /
3696	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPD; /*< R3: The number of times a global page directory wasn't flushed. /
3697	STAMCOUNTER StatR3SyncCR3DstSkippedGlobalPT; /*< R3: The number of times a page table with only global entries wasn't flushed. /
3698	STAMCOUNTER StatR3SyncCR3DstCacheHit; /*< R3: The number of times we got some kind of cache hit on a page table. /
3699	STAMPROFILE StatR3SyncPT; /*< R3: PGMSyncPT() profiling. /
3700	STAMCOUNTER StatR3SyncPTFailed; /*< R3: The number of times PGMSyncPT() failed. /
3701	STAMCOUNTER StatR3SyncPT4K; /*< R3: Number of 4KB syncs. /
3702	STAMCOUNTER StatR3SyncPT4M; /*< R3: Number of 4MB syncs. /
3703	STAMCOUNTER StatR3SyncPagePDNAs; /*< R3: The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit. /
3704	STAMCOUNTER StatR3SyncPagePDOutOfSync; /*< R3: The number of time we've encountered an out-of-sync PD in SyncPage. /
3705	STAMCOUNTER StatR3AccessedPage; /*< R3: The number of pages marked not present for accessed bit emulation. /
3706	STAMPROFILE StatR3DirtyBitTracking; /*< R3: Profiling the dirty bit tracking in CheckPageFault(). /
3707	STAMCOUNTER StatR3DirtyPage; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3708	STAMCOUNTER StatR3DirtyPageBig; /*< R3: The number of pages marked read-only for dirty bit tracking. /
3709	STAMCOUNTER StatR3DirtyPageSkipped; /*< R3: The number of pages already dirty or readonly. /
3710	STAMCOUNTER StatR3DirtyPageTrap; /*< R3: The number of traps generated for dirty bit tracking. /
3711	STAMCOUNTER StatR3DirtyTrackRealPF; /*< R3: The number of real pages faults during dirty bit tracking. /
3712	STAMCOUNTER StatR3DirtiedPage; /*< R3: The number of pages marked dirty because of write accesses. /
3713	STAMCOUNTER StatR3PageAlreadyDirty; /*< R3: The number of pages already marked dirty because of write accesses. /
3714	STAMPROFILE StatR3InvalidatePage; /*< R3: PGMInvalidatePage() profiling. /
3715	STAMCOUNTER StatR3InvalidatePage4KBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4KB page. /
3716	STAMCOUNTER StatR3InvalidatePage4MBPages; /*< R3: The number of times PGMInvalidatePage() was called for a 4MB page. /
3717	STAMCOUNTER StatR3InvalidatePage4MBPagesSkip; /*< R3: The number of times PGMInvalidatePage() skipped a 4MB page. /
3718	STAMCOUNTER StatR3InvalidatePagePDNAs; /*< R3: The number of times PGMInvalidatePage() was called for a not accessed page directory. /
3719	STAMCOUNTER StatR3InvalidatePagePDNPs; /*< R3: The number of times PGMInvalidatePage() was called for a not present page directory. /
3720	STAMCOUNTER StatR3InvalidatePagePDMappings; /*< R3: The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict). /
3721	STAMCOUNTER StatR3InvalidatePagePDOutOfSync; /*< R3: The number of times PGMInvalidatePage() was called for an out of sync page directory. /
3722	STAMCOUNTER StatR3InvalidatePageSkipped; /*< R3: The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3. /
3723	STAMCOUNTER StatR3PageOutOfSyncUser; /*< R3: The number of times user page is out of sync was detected in \#PF or VerifyAccessSyncPage. /
3724	STAMCOUNTER StatR3PageOutOfSyncSupervisor; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF or VerifyAccessSyncPage. /
3725	STAMCOUNTER StatR3PageOutOfSyncUserWrite; /*< R3: The number of times user page is out of sync was detected in \#PF. /
3726	STAMCOUNTER StatR3PageOutOfSyncSupervisorWrite; /*< R3: The number of times supervisor page is out of sync was detected in in \#PF. /
3727	STAMCOUNTER StatR3PageOutOfSyncBallloon; /*< R3: The number of times a ballooned page was accessed (read). /
3728	STAMPROFILE StatR3Prefetch; /*< R3: PGMPrefetchPage. /
3729	STAMPROFILE StatR3FlushTLB; /*< R3: Profiling of the PGMFlushTLB() body. /
3730	STAMCOUNTER StatR3FlushTLBNewCR3; /*< R3: The number of times PGMFlushTLB was called with a new CR3, non-global. (switch) /
3731	STAMCOUNTER StatR3FlushTLBNewCR3Global; /*< R3: The number of times PGMFlushTLB was called with a new CR3, global. (switch) /
3732	STAMCOUNTER StatR3FlushTLBSameCR3; /*< R3: The number of times PGMFlushTLB was called with the same CR3, non-global. (flush) /
3733	STAMCOUNTER StatR3FlushTLBSameCR3Global; /*< R3: The number of times PGMFlushTLB was called with the same CR3, global. (flush) /
3734	STAMPROFILE StatR3GstModifyPage; /*< R3: Profiling of the PGMGstModifyPage() body /
3735	/** @} */
3736	} PGMCPUSTATS;
3737
3738
3739	/**
3740	* Converts a PGMCPU pointer into a VM pointer.
3741	* @returns Pointer to the VM structure the PGM is part of.
3742	* @param pPGM Pointer to PGMCPU instance data.
3743	*/
3744	#define PGMCPU2VM(pPGM) ( (PVM)((char*)(pPGM) - (pPGM)->offVM) )
3745
3746	/**
3747	* Converts a PGMCPU pointer into a PGM pointer.
3748	* @returns Pointer to the VM structure the PGM is part of.
3749	* @param pPGM Pointer to PGMCPU instance data.
3750	*/
3751	#define PGMCPU2PGM(pPGMCpu) ( (PPGM)((char *)(pPGMCpu) - (pPGMCpu)->offPGM) )
3752
3753	/**
3754	* PGMCPU Data (part of VMCPU).
3755	*/
3756	typedef struct PGMCPU
3757	{
3758	/** Offset to the VM structure. */
3759	int32_t offVM;
3760	/** Offset to the VMCPU structure. */
3761	int32_t offVCpu;
3762	/** Offset of the PGM structure relative to VMCPU. */
3763	int32_t offPGM;
3764	uint32_t uPadding0; /*< structure size alignment. /
3765
3766	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE) \|\| defined(VBOX_WITH_RAW_MODE)
3767	/** Automatically tracked physical memory mapping set.
3768	* Ring-0 and strict raw-mode builds. */
3769	PGMMAPSET AutoSet;
3770	#endif
3771
3772	/** A20 gate mask.
3773	* Our current approach to A20 emulation is to let REM do it and don't bother
3774	* anywhere else. The interesting Guests will be operating with it enabled anyway.
3775	* But whould need arrise, we'll subject physical addresses to this mask. */
3776	RTGCPHYS GCPhysA20Mask;
3777	/** A20 gate state - boolean! */
3778	bool fA20Enabled;
3779	/** Mirror of the EFER.NXE bit. Managed by PGMNotifyNxeChanged. */
3780	bool fNoExecuteEnabled;
3781	/** Unused bits. */
3782	bool afUnused[2];
3783
3784	/** What needs syncing (PGM_SYNC_*).
3785	* This is used to queue operations for PGMSyncCR3, PGMInvalidatePage,
3786	* PGMFlushTLB, and PGMR3Load. */
3787	uint32_t fSyncFlags;
3788
3789	/** The shadow paging mode. */
3790	PGMMODE enmShadowMode;
3791	/** The guest paging mode. */
3792	PGMMODE enmGuestMode;
3793
3794	/** The current physical address representing in the guest CR3 register. */
3795	RTGCPHYS GCPhysCR3;
3796
3797	/** @name 32-bit Guest Paging.
3798	* @{ */
3799	/** The guest's page directory, R3 pointer. */
3800	R3PTRTYPE(PX86PD) pGst32BitPdR3;
3801	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3802	/** The guest's page directory, R0 pointer. */
3803	R0PTRTYPE(PX86PD) pGst32BitPdR0;
3804	#endif
3805	/** The guest's page directory, static RC mapping. */
3806	RCPTRTYPE(PX86PD) pGst32BitPdRC;
3807	/** Mask containing the MBZ bits of a big page PDE. */
3808	uint32_t fGst32BitMbzBigPdeMask;
3809	/** Set if the page size extension (PSE) is enabled. */
3810	bool fGst32BitPageSizeExtension;
3811	/** Alignment padding. */
3812	bool afAlignment2[3];
3813	/** @} */
3814
3815	/** @name PAE Guest Paging.
3816	* @{ */
3817	/** The guest's page directory pointer table, static RC mapping. */
3818	RCPTRTYPE(PX86PDPT) pGstPaePdptRC;
3819	/** The guest's page directory pointer table, R3 pointer. */
3820	R3PTRTYPE(PX86PDPT) pGstPaePdptR3;
3821	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3822	/** The guest's page directory pointer table, R0 pointer. */
3823	R0PTRTYPE(PX86PDPT) pGstPaePdptR0;
3824	#endif
3825
3826	/** The guest's page directories, R3 pointers.
3827	* These are individual pointers and don't have to be adjacent.
3828	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3829	R3PTRTYPE(PX86PDPAE) apGstPaePDsR3[4];
3830	/** The guest's page directories, R0 pointers.
3831	* Same restrictions as apGstPaePDsR3. */
3832	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3833	R0PTRTYPE(PX86PDPAE) apGstPaePDsR0[4];
3834	#endif
3835	/** The guest's page directories, static GC mapping.
3836	* Unlike the R3/R0 array the first entry can be accessed as a 2048 entry PD.
3837	* These don't have to be up-to-date - use pgmGstGetPaePD() to access them. */
3838	RCPTRTYPE(PX86PDPAE) apGstPaePDsRC[4];
3839	/** The physical addresses of the guest page directories (PAE) pointed to by apGstPagePDsHC/GC.
3840	* @todo Remove this and use aGstPaePdpeRegs instead? */
3841	RTGCPHYS aGCPhysGstPaePDs[4];
3842	/** The values of the 4 PDPE CPU registers (PAE). */
3843	X86PDPE aGstPaePdpeRegs[4];
3844	/** The physical addresses of the monitored guest page directories (PAE). */
3845	RTGCPHYS aGCPhysGstPaePDsMonitored[4];
3846	/** Mask containing the MBZ PTE bits. */
3847	uint64_t fGstPaeMbzPteMask;
3848	/** Mask containing the MBZ PDE bits. */
3849	uint64_t fGstPaeMbzPdeMask;
3850	/** Mask containing the MBZ big page PDE bits. */
3851	uint64_t fGstPaeMbzBigPdeMask;
3852	/** Mask containing the MBZ PDPE bits. */
3853	uint64_t fGstPaeMbzPdpeMask;
3854	/** @} */
3855
3856	/** @name AMD64 Guest Paging.
3857	* @{ */
3858	/** The guest's page directory pointer table, R3 pointer. */
3859	R3PTRTYPE(PX86PML4) pGstAmd64Pml4R3;
3860	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
3861	/** The guest's page directory pointer table, R0 pointer. */
3862	R0PTRTYPE(PX86PML4) pGstAmd64Pml4R0;
3863	#else
3864	RTR0PTR alignment6b; /*< alignment equalizer. /
3865	#endif
3866	/** Mask containing the MBZ PTE bits. */
3867	uint64_t fGstAmd64MbzPteMask;
3868	/** Mask containing the MBZ PDE bits. */
3869	uint64_t fGstAmd64MbzPdeMask;
3870	/** Mask containing the MBZ big page PDE bits. */
3871	uint64_t fGstAmd64MbzBigPdeMask;
3872	/** Mask containing the MBZ PDPE bits. */
3873	uint64_t fGstAmd64MbzPdpeMask;
3874	/** Mask containing the MBZ big page PDPE bits. */
3875	uint64_t fGstAmd64MbzBigPdpeMask;
3876	/** Mask containing the MBZ PML4E bits. */
3877	uint64_t fGstAmd64MbzPml4eMask;
3878	/** Mask containing the PDPE bits that we shadow. */
3879	uint64_t fGstAmd64ShadowedPdpeMask;
3880	/** Mask containing the PML4E bits that we shadow. */
3881	uint64_t fGstAmd64ShadowedPml4eMask;
3882	/** @} */
3883
3884	/** @name PAE and AMD64 Guest Paging.
3885	* @{ */
3886	/** Mask containing the PTE bits that we shadow. */
3887	uint64_t fGst64ShadowedPteMask;
3888	/** Mask containing the PDE bits that we shadow. */
3889	uint64_t fGst64ShadowedPdeMask;
3890	/** Mask containing the big page PDE bits that we shadow in the PDE. */
3891	uint64_t fGst64ShadowedBigPdeMask;
3892	/** Mask containing the big page PDE bits that we shadow in the PTE. */
3893	uint64_t fGst64ShadowedBigPde4PteMask;
3894	/** @} */
3895
3896	/** Pointer to the page of the current active CR3 - R3 Ptr. */
3897	R3PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R3;
3898	/** Pointer to the page of the current active CR3 - R0 Ptr. */
3899	R0PTRTYPE(PPGMPOOLPAGE) pShwPageCR3R0;
3900	/** Pointer to the page of the current active CR3 - RC Ptr. */
3901	RCPTRTYPE(PPGMPOOLPAGE) pShwPageCR3RC;
3902	# if HC_ARCH_BITS == 64
3903	RTRCPTR alignment6; /*< structure size alignment. /
3904	# endif
3905	/** @} */
3906
3907	/** @name Function pointers for Shadow paging.
3908	* @{
3909	*/
3910	DECLR3CALLBACKMEMBER(int, pfnR3ShwRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3911	DECLR3CALLBACKMEMBER(int, pfnR3ShwExit,(PVMCPU pVCpu));
3912	DECLR3CALLBACKMEMBER(int, pfnR3ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3913	DECLR3CALLBACKMEMBER(int, pfnR3ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3914
3915	DECLRCCALLBACKMEMBER(int, pfnRCShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3916	DECLRCCALLBACKMEMBER(int, pfnRCShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3917
3918	DECLR0CALLBACKMEMBER(int, pfnR0ShwGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys));
3919	DECLR0CALLBACKMEMBER(int, pfnR0ShwModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags));
3920
3921	/** @} */
3922
3923	/** @name Function pointers for Guest paging.
3924	* @{
3925	*/
3926	DECLR3CALLBACKMEMBER(int, pfnR3GstRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3927	DECLR3CALLBACKMEMBER(int, pfnR3GstExit,(PVMCPU pVCpu));
3928	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3929	DECLR3CALLBACKMEMBER(int, pfnR3GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3930	DECLR3CALLBACKMEMBER(int, pfnR3GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3931	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3932	DECLRCCALLBACKMEMBER(int, pfnRCGstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3933	DECLRCCALLBACKMEMBER(int, pfnRCGstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3934	#if HC_ARCH_BITS == 64
3935	RTRCPTR alignment3; /*< structure size alignment. /
3936	#endif
3937
3938	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPage,(PVMCPU pVCpu, RTGCPTR GCPtr, uint64_t *pfFlags, PRTGCPHYS pGCPhys));
3939	DECLR0CALLBACKMEMBER(int, pfnR0GstModifyPage,(PVMCPU pVCpu, RTGCPTR GCPtr, size_t cbPages, uint64_t fFlags, uint64_t fMask));
3940	DECLR0CALLBACKMEMBER(int, pfnR0GstGetPDE,(PVMCPU pVCpu, RTGCPTR GCPtr, PX86PDEPAE pPde));
3941	/** @} */
3942
3943	/** @name Function pointers for Both Shadow and Guest paging.
3944	* @{
3945	*/
3946	DECLR3CALLBACKMEMBER(int, pfnR3BthRelocate,(PVMCPU pVCpu, RTGCPTR offDelta));
3947	/* no pfnR3BthTrap0eHandler */
3948	DECLR3CALLBACKMEMBER(int, pfnR3BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3949	DECLR3CALLBACKMEMBER(int, pfnR3BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3950	DECLR3CALLBACKMEMBER(int, pfnR3BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3951	DECLR3CALLBACKMEMBER(int, pfnR3BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3952	DECLR3CALLBACKMEMBER(unsigned, pfnR3BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3953	DECLR3CALLBACKMEMBER(int, pfnR3BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3954	DECLR3CALLBACKMEMBER(int, pfnR3BthUnmapCR3,(PVMCPU pVCpu));
3955
3956	DECLR0CALLBACKMEMBER(int, pfnR0BthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3957	DECLR0CALLBACKMEMBER(int, pfnR0BthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3958	DECLR0CALLBACKMEMBER(int, pfnR0BthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3959	DECLR0CALLBACKMEMBER(int, pfnR0BthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3960	DECLR0CALLBACKMEMBER(int, pfnR0BthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3961	DECLR0CALLBACKMEMBER(unsigned, pfnR0BthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3962	DECLR0CALLBACKMEMBER(int, pfnR0BthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3963	DECLR0CALLBACKMEMBER(int, pfnR0BthUnmapCR3,(PVMCPU pVCpu));
3964
3965	DECLRCCALLBACKMEMBER(int, pfnRCBthTrap0eHandler,(PVMCPU pVCpu, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, bool *pfLockTaken));
3966	DECLRCCALLBACKMEMBER(int, pfnRCBthInvalidatePage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3967	DECLRCCALLBACKMEMBER(int, pfnRCBthSyncCR3,(PVMCPU pVCpu, uint64_t cr0, uint64_t cr3, uint64_t cr4, bool fGlobal));
3968	DECLRCCALLBACKMEMBER(int, pfnRCBthPrefetchPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage));
3969	DECLRCCALLBACKMEMBER(int, pfnRCBthVerifyAccessSyncPage,(PVMCPU pVCpu, RTGCPTR GCPtrPage, unsigned fFlags, unsigned uError));
3970	DECLRCCALLBACKMEMBER(unsigned, pfnRCBthAssertCR3,(PVMCPU pVCpu, uint64_t cr3, uint64_t cr4, RTGCPTR GCPtr, RTGCPTR cb));
3971	DECLRCCALLBACKMEMBER(int, pfnRCBthMapCR3,(PVMCPU pVCpu, RTGCPHYS GCPhysCR3));
3972	DECLRCCALLBACKMEMBER(int, pfnRCBthUnmapCR3,(PVMCPU pVCpu));
3973	#if 0
3974	RTRCPTR alignment2; /*< structure size alignment. /
3975	#endif
3976	/** @} */
3977
3978	/** For saving stack space, the disassembler state is allocated here instead of
3979	* on the stack. */
3980	DISCPUSTATE DisState;
3981
3982	/** Counts the number of times the netware WP0+RO+US hack has been applied. */
3983	uint64_t cNetwareWp0Hacks;
3984
3985	/** Count the number of pgm pool access handler calls. */
3986	uint64_t cPoolAccessHandler;
3987
3988	/** @name Release Statistics
3989	* @{ */
3990	/** The number of times the guest has switched mode since last reset or statistics reset. */
3991	STAMCOUNTER cGuestModeChanges;
3992	/** The number of times the guest has switched mode since last reset or statistics reset. */
3993	STAMCOUNTER cA20Changes;
3994	/** @} */
3995
3996	#ifdef VBOX_WITH_STATISTICS /** @todo move this chunk to the heap. */
3997	/** @name Statistics
3998	* @{ */
3999	/** RC: Pointer to the statistics. */
4000	RCPTRTYPE(PGMCPUSTATS *) pStatsRC;
4001	/** RC: Which statistic this \#PF should be attributed to. */
4002	RCPTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionRC;
4003	/** R0: Pointer to the statistics. */
4004	R0PTRTYPE(PGMCPUSTATS *) pStatsR0;
4005	/** R0: Which statistic this \#PF should be attributed to. */
4006	R0PTRTYPE(PSTAMPROFILE) pStatTrap0eAttributionR0;
4007	/** R3: Pointer to the statistics. */
4008	R3PTRTYPE(PGMCPUSTATS *) pStatsR3;
4009	/** Alignment padding. */
4010	RTR3PTR pPaddingR3;
4011	/** @} */
4012	#endif /* VBOX_WITH_STATISTICS */
4013	} PGMCPU;
4014	/** Pointer to the per-cpu PGM data. */
4015	typedef PGMCPU *PPGMCPU;
4016
4017
4018	/** @name PGM::fSyncFlags Flags
4019	* @{
4020	*/
4021	/** Updates the virtual access handler state bit in PGMPAGE. */
4022	#define PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL RT_BIT(0)
4023	/** Always sync CR3. */
4024	#define PGM_SYNC_ALWAYS RT_BIT(1)
4025	/** Check monitoring on next CR3 (re)load and invalidate page.
4026	* @todo This is obsolete now. Remove after 2.2.0 is branched off. */
4027	#define PGM_SYNC_MONITOR_CR3 RT_BIT(2)
4028	/** Check guest mapping in SyncCR3. */
4029	#define PGM_SYNC_MAP_CR3 RT_BIT(3)
4030	/** Clear the page pool (a light weight flush). */
4031	#define PGM_SYNC_CLEAR_PGM_POOL_BIT 8
4032	#define PGM_SYNC_CLEAR_PGM_POOL RT_BIT(PGM_SYNC_CLEAR_PGM_POOL_BIT)
4033	/** @} */
4034
4035
4036	RT_C_DECLS_BEGIN
4037
4038	#if defined(VBOX_STRICT) && defined(IN_RING3)
4039	int pgmLockDebug(PVM pVM, RT_SRC_POS_DECL);
4040	# define pgmLock(a_pVM) pgmLockDebug(a_pVM, RT_SRC_POS)
4041	#else
4042	int pgmLock(PVM pVM);
4043	#endif
4044	void pgmUnlock(PVM pVM);
4045	/**
4046	* Asserts that the caller owns the PDM lock.
4047	* This is the internal variant of PGMIsLockOwner.
4048	* @param a_pVM Pointer to the VM.
4049	*/
4050	#define PGM_LOCK_ASSERT_OWNER(a_pVM) Assert(PDMCritSectIsOwner(&(a_pVM)->pgm.s.CritSectX))
4051	/**
4052	* Asserts that the caller owns the PDM lock.
4053	* This is the internal variant of PGMIsLockOwner.
4054	* @param a_pVM Pointer to the VM.
4055	* @param a_pVCpu The current CPU handle.
4056	*/
4057	#define PGM_LOCK_ASSERT_OWNER_EX(a_pVM, a_pVCpu) Assert(PDMCritSectIsOwnerEx(&(a_pVM)->pgm.s.CritSectX, pVCpu))
4058
4059	#ifndef PGM_WITHOUT_MAPPINGS
4060	int pgmR3MappingsFixInternal(PVM pVM, RTGCPTR GCPtrBase, uint32_t cb);
4061	int pgmR3SyncPTResolveConflict(PVM pVM, PPGMMAPPING pMapping, PX86PD pPDSrc, RTGCPTR GCPtrOldMapping);
4062	int pgmR3SyncPTResolveConflictPAE(PVM pVM, PPGMMAPPING pMapping, RTGCPTR GCPtrOldMapping);
4063	int pgmMapResolveConflicts(PVM pVM);
4064	#endif /* !PGM_WITHOUT_MAPPINGS */
4065	PPGMMAPPING pgmGetMapping(PVM pVM, RTGCPTR GCPtr);
4066	DECLCALLBACK(void) pgmR3MapInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4067
4068	void pgmR3HandlerPhysicalUpdateAll(PVM pVM);
4069	bool pgmHandlerPhysicalIsAll(PVM pVM, RTGCPHYS GCPhys);
4070	void pgmHandlerPhysicalResetAliasedPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhysPage, bool fDoAccounting);
4071	int pgmHandlerVirtualFindByPhysAddr(PVM pVM, RTGCPHYS GCPhys, PPGMVIRTHANDLER ppVirt, unsigned piPage);
4072	DECLCALLBACK(int) pgmHandlerVirtualResetOne(PAVLROGCPTRNODECORE pNode, void *pvUser);
4073	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
4074	void pgmHandlerVirtualDumpPhysPages(PVM pVM);
4075	#else
4076	# define pgmHandlerVirtualDumpPhysPages(a) do { } while (0)
4077	#endif
4078	DECLCALLBACK(void) pgmR3InfoHandlers(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
4079	int pgmR3InitSavedState(PVM pVM, uint64_t cbRam);
4080
4081	int pgmPhysAllocPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4082	int pgmPhysAllocLargePage(PVM pVM, RTGCPHYS GCPhys);
4083	int pgmPhysRecheckLargePage(PVM pVM, RTGCPHYS GCPhys, PPGMPAGE pLargePage);
4084	int pgmPhysPageLoadIntoTlb(PVM pVM, RTGCPHYS GCPhys);
4085	int pgmPhysPageLoadIntoTlbWithPage(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4086	void pgmPhysPageMakeWriteMonitoredWritable(PVM pVM, PPGMPAGE pPage);
4087	int pgmPhysPageMakeWritable(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys);
4088	int pgmPhysPageMakeWritableAndMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4089	int pgmPhysPageMap(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4090	int pgmPhysPageMapReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void const **ppv);
4091	int pgmPhysPageMapByPageID(PVM pVM, uint32_t idPage, RTHCPHYS HCPhys, void **ppv);
4092	int pgmPhysGCPhys2R3Ptr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4093	int pgmPhysCr3ToHCPtr(PVM pVM, RTGCPHYS GCPhys, PRTR3PTR pR3Ptr);
4094	int pgmPhysGCPhys2CCPtrInternalDepr(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv);
4095	int pgmPhysGCPhys2CCPtrInternal(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, void **ppv, PPGMPAGEMAPLOCK pLock);
4096	int pgmPhysGCPhys2CCPtrInternalReadOnly(PVM pVM, PPGMPAGE pPage, RTGCPHYS GCPhys, const void **ppv, PPGMPAGEMAPLOCK pLock);
4097	void pgmPhysReleaseInternalPageMappingLock(PVM pVM, PPGMPAGEMAPLOCK pLock);
4098	VMMDECL(int) pgmPhysHandlerRedirectToHC(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
4099	VMMDECL(int) pgmPhysRomWriteHandler(PVM pVM, RTGCUINT uErrorCode, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, RTGCPHYS GCPhysFault, void *pvUser);
4100	int pgmPhysFreePage(PVM pVM, PGMMFREEPAGESREQ pReq, uint32_t *pcPendingPages, PPGMPAGE pPage, RTGCPHYS GCPhys);
4101	void pgmPhysInvalidRamRangeTlbs(PVM pVM);
4102	void pgmPhysInvalidatePageMapTLB(PVM pVM);
4103	void pgmPhysInvalidatePageMapTLBEntry(PVM pVM, RTGCPHYS GCPhys);
4104	PPGMRAMRANGE pgmPhysGetRangeSlow(PVM pVM, RTGCPHYS GCPhys);
4105	PPGMRAMRANGE pgmPhysGetRangeAtOrAboveSlow(PVM pVM, RTGCPHYS GCPhys);
4106	PPGMPAGE pgmPhysGetPageSlow(PVM pVM, RTGCPHYS GCPhys);
4107	int pgmPhysGetPageExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage);
4108	int pgmPhysGetPageAndRangeExSlow(PVM pVM, RTGCPHYS GCPhys, PPPGMPAGE ppPage, PPGMRAMRANGE *ppRam);
4109
4110	#ifdef IN_RING3
4111	DECLCALLBACK(int) pgmR3PhysRomWriteHandler(PVM pVM, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf,
4112	PGMACCESSTYPE enmAccessType, void *pvUser);
4113	void pgmR3PhysRelinkRamRanges(PVM pVM);
4114	int pgmR3PhysRamPreAllocate(PVM pVM);
4115	int pgmR3PhysRamReset(PVM pVM);
4116	int pgmR3PhysRomReset(PVM pVM);
4117	int pgmR3PhysRamZeroAll(PVM pVM);
4118	int pgmR3PhysChunkMap(PVM pVM, uint32_t idChunk, PPPGMCHUNKR3MAP ppChunk);
4119	int pgmR3PhysRamTerm(PVM pVM);
4120	void pgmR3PhysRomTerm(PVM pVM);
4121	void pgmR3PhysAssertSharedPageChecksums(PVM pVM);
4122
4123	int pgmR3PoolInit(PVM pVM);
4124	void pgmR3PoolRelocate(PVM pVM);
4125	void pgmR3PoolResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu);
4126	void pgmR3PoolReset(PVM pVM);
4127	void pgmR3PoolClearAll(PVM pVM, bool fFlushRemTlb);
4128	DECLCALLBACK(VBOXSTRICTRC) pgmR3PoolClearAllRendezvous(PVM pVM, PVMCPU pVCpu, void *fpvFlushRemTbl);
4129	void pgmR3PoolWriteProtectPages(PVM pVM);
4130
4131	#endif /* IN_RING3 */
4132	#if defined(VBOX_WITH_2X_4GB_ADDR_SPACE_IN_R0) \|\| defined(IN_RC)
4133	int pgmRZDynMapHCPageCommon(PPGMMAPSET pSet, RTHCPHYS HCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4134	int pgmRZDynMapGCPageCommon(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void **ppv RTLOG_COMMA_SRC_POS_DECL);
4135	# ifdef LOG_ENABLED
4136	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint, RT_SRC_POS_DECL);
4137	# else
4138	void pgmRZDynMapUnusedHint(PVMCPU pVCpu, void *pvHint);
4139	# endif
4140	#endif
4141	int pgmPoolAlloc(PVM pVM, RTGCPHYS GCPhys, PGMPOOLKIND enmKind, PGMPOOLACCESS enmAccess, bool fA20Enabled,
4142	uint16_t iUser, uint32_t iUserTable, bool fLockPage, PPPGMPOOLPAGE ppPage);
4143	void pgmPoolFree(PVM pVM, RTHCPHYS HCPhys, uint16_t iUser, uint32_t iUserTable);
4144	void pgmPoolFreeByPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, uint16_t iUser, uint32_t iUserTable);
4145	int pgmPoolFlushPage(PPGMPOOL pPool, PPGMPOOLPAGE pPage, bool fFlush = true /* DO NOT USE false UNLESS YOU KNOWN WHAT YOU'RE DOING!! */);
4146	void pgmPoolFlushPageByGCPhys(PVM pVM, RTGCPHYS GCPhys);
4147	PPGMPOOLPAGE pgmPoolGetPage(PPGMPOOL pPool, RTHCPHYS HCPhys);
4148	PPGMPOOLPAGE pgmPoolQueryPageForDbg(PPGMPOOL pPool, RTHCPHYS HCPhys);
4149	int pgmPoolSyncCR3(PVMCPU pVCpu);
4150	bool pgmPoolIsDirtyPage(PVM pVM, RTGCPHYS GCPhys);
4151	void pgmPoolInvalidateDirtyPage(PVM pVM, RTGCPHYS GCPhysPT);
4152	int pgmPoolTrackUpdateGCPhys(PVM pVM, RTGCPHYS GCPhysPage, PPGMPAGE pPhysPage, bool fFlushPTEs, bool *pfFlushTLBs);
4153	void pgmPoolTracDerefGCPhysHint(PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTHCPHYS HCPhys, RTGCPHYS GCPhysHint, uint16_t iPte);
4154	uint16_t pgmPoolTrackPhysExtAddref(PVM pVM, PPGMPAGE pPhysPage, uint16_t u16, uint16_t iShwPT, uint16_t iPte);
4155	void pgmPoolTrackPhysExtDerefGCPhys(PPGMPOOL pPool, PPGMPOOLPAGE pPoolPage, PPGMPAGE pPhysPage, uint16_t iPte);
4156	void pgmPoolMonitorChainChanging(PVMCPU pVCpu, PPGMPOOL pPool, PPGMPOOLPAGE pPage, RTGCPHYS GCPhysFault, CTXTYPE(RTGCPTR, RTHCPTR, RTGCPTR) pvAddress, unsigned cbWrite);
4157	int pgmPoolMonitorChainFlush(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4158	void pgmPoolMonitorModifiedInsert(PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4159
4160	void pgmPoolAddDirtyPage(PVM pVM, PPGMPOOL pPool, PPGMPOOLPAGE pPage);
4161	void pgmPoolResetDirtyPages(PVM pVM);
4162	void pgmPoolResetDirtyPage(PVM pVM, RTGCPTR GCPtrPage);
4163
4164	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu);
4165	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu);
4166	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu);
4167
4168	void pgmMapSetShadowPDEs(PVM pVM, PPGMMAPPING pMap, unsigned iNewPDE);
4169	void pgmMapClearShadowPDEs(PVM pVM, PPGMPOOLPAGE pShwPageCR3, PPGMMAPPING pMap, unsigned iOldPDE, bool fDeactivateCR3);
4170	int pgmMapActivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4171	int pgmMapDeactivateCR3(PVM pVM, PPGMPOOLPAGE pShwPageCR3);
4172
4173	int pgmShwMakePageSupervisorAndWritable(PVMCPU pVCpu, RTGCPTR GCPtr, bool fBigPage, uint32_t fOpFlags);
4174	int pgmShwSyncPaePDPtr(PVMCPU pVCpu, RTGCPTR GCPtr, X86PGPAEUINT uGstPdpe, PX86PDPAE *ppPD);
4175	int pgmShwSyncNestedPageLocked(PVMCPU pVCpu, RTGCPHYS GCPhysFault, uint32_t cPages, PGMMODE enmShwPagingMode);
4176
4177	int pgmGstLazyMap32BitPD(PVMCPU pVCpu, PX86PD *ppPd);
4178	int pgmGstLazyMapPaePDPT(PVMCPU pVCpu, PX86PDPT *ppPdpt);
4179	int pgmGstLazyMapPaePD(PVMCPU pVCpu, uint32_t iPdpt, PX86PDPAE *ppPd);
4180	int pgmGstLazyMapPml4(PVMCPU pVCpu, PX86PML4 *ppPml4);
4181	int pgmGstPtWalk(PVMCPU pVCpu, RTGCPTR GCPtr, PPGMPTWALKGST pWalk);
4182
4183	# if defined(VBOX_STRICT) && HC_ARCH_BITS == 64 && defined(IN_RING3)
4184	FNDBGCCMD pgmR3CmdCheckDuplicatePages;
4185	FNDBGCCMD pgmR3CmdShowSharedModules;
4186	# endif
4187
4188	RT_C_DECLS_END
4189
4190	/** @} */
4191
4192	#endif
4193

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source: vbox/trunk/src/VBox/VMM/include/PGMInternal.h@ 55493

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