VirtualBox

source: vbox/trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py@ 46744

Last change on this file since 46744 was 46744, checked in by vboxsync, 11 years ago

32-bit memory accesses in 64-bit mode.
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1#!/usr/bin/env python
2# -*- coding: utf-8 -*-
3# $Id: InstructionTestGen.py 46744 2013-06-23 17:54:29Z vboxsync $
4
5"""
6Instruction Test Generator.
7"""
8
9from __future__ import print_function;
10
11__copyright__ = \
12"""
13Copyright (C) 2012-2013 Oracle Corporation
14
15Oracle Corporation confidential
16All rights reserved
17"""
18__version__ = "$Revision: 46744 $";
19
20
21# Standard python imports.
22import io;
23import os;
24from optparse import OptionParser
25import random;
26import sys;
27
28
29## @name Exit codes
30## @{
31RTEXITCODE_SUCCESS = 0;
32RTEXITCODE_SYNTAX = 2;
33## @}
34
35## @name Various C macros we're used to.
36## @{
37UINT8_MAX = 0xff
38UINT16_MAX = 0xffff
39UINT32_MAX = 0xffffffff
40UINT64_MAX = 0xffffffffffffffff
41def RT_BIT_32(iBit): # pylint: disable=C0103
42 """ 32-bit one bit mask. """
43 return 1 << iBit;
44def RT_BIT_64(iBit): # pylint: disable=C0103
45 """ 64-bit one bit mask. """
46 return 1 << iBit;
47## @}
48
49
50## @name ModR/M
51## @{
52X86_MODRM_RM_MASK = 0x07;
53X86_MODRM_REG_MASK = 0x38;
54X86_MODRM_REG_SMASK = 0x07;
55X86_MODRM_REG_SHIFT = 3;
56X86_MODRM_MOD_MASK = 0xc0;
57X86_MODRM_MOD_SMASK = 0x03;
58X86_MODRM_MOD_SHIFT = 6;
59## @}
60
61## @name SIB
62## @{
63X86_SIB_BASE_MASK = 0x07;
64X86_SIB_INDEX_MASK = 0x38;
65X86_SIB_INDEX_SMASK = 0x07;
66X86_SIB_INDEX_SHIFT = 3;
67X86_SIB_SCALE_MASK = 0xc0;
68X86_SIB_SCALE_SMASK = 0x03;
69X86_SIB_SCALE_SHIFT = 6;
70## @}
71
72## @name PRefixes
73## @
74X86_OP_PRF_CS = 0x2e;
75X86_OP_PRF_SS = 0x36;
76X86_OP_PRF_DS = 0x3e;
77X86_OP_PRF_ES = 0x26;
78X86_OP_PRF_FS = 0x64;
79X86_OP_PRF_GS = 0x65;
80X86_OP_PRF_SIZE_OP = 0x66;
81X86_OP_PRF_SIZE_ADDR = 0x67;
82X86_OP_PRF_LOCK = 0xf0;
83X86_OP_PRF_REPZ = 0xf2;
84X86_OP_PRF_REPNZ = 0xf3;
85X86_OP_REX_B = 0x41;
86X86_OP_REX_X = 0x42;
87X86_OP_REX_R = 0x44;
88X86_OP_REX_W = 0x48;
89## @}
90
91
92## @name Register names.
93## @{
94g_asGRegs64NoSp = ('rax', 'rcx', 'rdx', 'rbx', None, 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
95g_asGRegs64 = ('rax', 'rcx', 'rdx', 'rbx', 'rsp', 'rbp', 'rsi', 'rdi', 'r8', 'r9', 'r10', 'r11', 'r12', 'r13', 'r14', 'r15');
96g_asGRegs32NoSp = ('eax', 'ecx', 'edx', 'ebx', None, 'ebp', 'esi', 'edi',
97 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
98g_asGRegs32 = ('eax', 'ecx', 'edx', 'ebx', 'esp', 'ebp', 'esi', 'edi',
99 'r8d', 'r9d', 'r10d', 'r11d', 'r12d', 'r13d', 'r14d', 'r15d');
100g_asGRegs16NoSp = ('ax', 'cx', 'dx', 'bx', None, 'bp', 'si', 'di',
101 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
102g_asGRegs16 = ('ax', 'cx', 'dx', 'bx', 'sp', 'bp', 'si', 'di',
103 'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
104g_asGRegs8 = ('al', 'cl', 'dl', 'bl', 'ah', 'ah', 'dh', 'bh');
105g_asGRegs8Rex = ('al', 'cl', 'dl', 'bl', 'spl', 'bpl', 'sil', 'dil',
106 'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b');
107## @}
108
109
110## @name Random
111## @{
112g_oMyRand = random.SystemRandom()
113def randU16():
114 """ Unsigned 16-bit random number. """
115 return g_oMyRand.getrandbits(16);
116
117def randU32():
118 """ Unsigned 32-bit random number. """
119 return g_oMyRand.getrandbits(32);
120
121def randU64():
122 """ Unsigned 64-bit random number. """
123 return g_oMyRand.getrandbits(64);
124
125def randUxx(cBits):
126 """ Unsigned 8-, 16-, 32-, or 64-bit random number. """
127 return g_oMyRand.getrandbits(cBits);
128
129def randUxxList(cBits, cElements):
130 """ List of nsigned 8-, 16-, 32-, or 64-bit random numbers. """
131 return [randUxx(cBits) for _ in range(cElements)];
132## @}
133
134
135
136
137## @name Instruction Emitter Helpers
138## @{
139
140def calcRexPrefixForTwoModRmRegs(iReg, iRm, bOtherRexPrefixes = 0):
141 """
142 Calculates a rex prefix if neccessary given the two registers
143 and optional rex size prefixes.
144 Returns an empty array if not necessary.
145 """
146 bRex = bOtherRexPrefixes;
147 if iReg >= 8:
148 bRex = bRex | X86_OP_REX_R;
149 if iRm >= 8:
150 bRex = bRex | X86_OP_REX_B;
151 if bRex == 0:
152 return [];
153 return [bRex,];
154
155def calcModRmForTwoRegs(iReg, iRm):
156 """
157 Calculate the RM byte for two registers.
158 Returns an array with one byte in it.
159 """
160 bRm = (0x3 << X86_MODRM_MOD_SHIFT) \
161 | ((iReg << X86_MODRM_REG_SHIFT) & X86_MODRM_REG_MASK) \
162 | (iRm & X86_MODRM_RM_MASK);
163 return [bRm,];
164
165## @}
166
167
168## @name Misc
169## @{
170
171def convU32ToSigned(u32):
172 """ Converts a 32-bit unsigned value to 32-bit signed. """
173 if u32 < 0x80000000:
174 return u32;
175 return u32 - UINT32_MAX - 1;
176
177def gregName(iReg, cBits, fRexByteRegs = True):
178 """ Gets the name of a general register by index and width. """
179 if cBits == 64:
180 return g_asGRegs64[iReg];
181 if cBits == 32:
182 return g_asGRegs32[iReg];
183 if cBits == 16:
184 return g_asGRegs16[iReg];
185 assert cBits == 8;
186 if fRexByteRegs:
187 return g_asGRegs8Rex[iReg];
188 return g_asGRegs8[iReg];
189
190## @}
191
192
193class TargetEnv(object):
194 """
195 Target Runtime Environment.
196 """
197
198 ## @name CPU Modes
199 ## @{
200 ksCpuMode_Real = 'real';
201 ksCpuMode_Protect = 'prot';
202 ksCpuMode_Paged = 'paged';
203 ksCpuMode_Long = 'long';
204 ksCpuMode_V86 = 'v86';
205 ## @}
206
207 ## @name Instruction set.
208 ## @{
209 ksInstrSet_16 = '16';
210 ksInstrSet_32 = '32';
211 ksInstrSet_64 = '64';
212 ## @}
213
214 def __init__(self, sName,
215 sInstrSet = ksInstrSet_32,
216 sCpuMode = ksCpuMode_Paged,
217 iRing = 3,
218 ):
219 self.sName = sName;
220 self.sInstrSet = sInstrSet;
221 self.sCpuMode = sCpuMode;
222 self.iRing = iRing;
223 self.asGRegs = g_asGRegs64 if self.is64Bit() else g_asGRegs32;
224 self.asGRegsNoSp = g_asGRegs64NoSp if self.is64Bit() else g_asGRegs32NoSp;
225
226 def isUsingIprt(self):
227 """ Whether it's an IPRT environment or not. """
228 return self.sName.startswith('iprt');
229
230 def is64Bit(self):
231 """ Whether it's a 64-bit environment or not. """
232 return self.sInstrSet == self.ksInstrSet_64;
233
234 def getDefOpBits(self):
235 """ Get the default operand size as a bit count. """
236 if self.sInstrSet == self.ksInstrSet_16:
237 return 16;
238 return 32;
239
240 def getDefOpBytes(self):
241 """ Get the default operand size as a byte count. """
242 return self.getDefOpBits() / 8;
243
244 def getMaxOpBits(self):
245 """ Get the max operand size as a bit count. """
246 if self.sInstrSet == self.ksInstrSet_64:
247 return 64;
248 return 32;
249
250 def getMaxOpBytes(self):
251 """ Get the max operand size as a byte count. """
252 return self.getMaxOpBits() / 8;
253
254 def getDefAddrBits(self):
255 """ Get the default address size as a bit count. """
256 if self.sInstrSet == self.ksInstrSet_16:
257 return 16;
258 if self.sInstrSet == self.ksInstrSet_32:
259 return 32;
260 return 64;
261
262 def getDefAddrBytes(self):
263 """ Get the default address size as a byte count. """
264 return self.getDefAddrBits() / 8;
265
266 def getGRegCount(self):
267 """ Get the number of general registers. """
268 if self.sInstrSet == self.ksInstrSet_64:
269 return 16;
270 return 8;
271
272 def randGRegNoSp(self):
273 """ Returns a random general register number, excluding the SP register. """
274 iReg = randU16();
275 return iReg % (16 if self.is64Bit() else 8);
276
277 def getAddrModes(self):
278 """ Gets a list of addressing mode (16, 32, or/and 64). """
279 if self.sInstrSet == self.ksInstrSet_16:
280 return [16, 32];
281 if self.sInstrSet == self.ksInstrSet_32:
282 return [32, 16];
283 return [64, 32];
284
285
286## Target environments.
287g_dTargetEnvs = {
288 'iprt-r3-32': TargetEnv('iprt-r3-32', TargetEnv.ksInstrSet_32, TargetEnv.ksCpuMode_Protect, 3),
289 'iprt-r3-64': TargetEnv('iprt-r3-64', TargetEnv.ksInstrSet_64, TargetEnv.ksCpuMode_Long, 3),
290};
291
292
293class InstrTestBase(object):
294 """
295 Base class for testing one instruction.
296 """
297
298 def __init__(self, sName, sInstr = None):
299 self.sName = sName;
300 self.sInstr = sInstr if sInstr else sName.split()[0];
301
302 def isApplicable(self, oGen):
303 """
304 Tests if the instruction test is applicable to the selected environment.
305 """
306 _ = oGen;
307 return True;
308
309 def generateTest(self, oGen, sTestFnName):
310 """
311 Emits the test assembly code.
312 """
313 oGen.write(';; @todo not implemented. This is for the linter: %s, %s\n' % (oGen, sTestFnName));
314 return True;
315
316 def generateInputs(self, cbEffOp, cbMaxOp, oGen, fLong = False):
317 """ Generate a list of inputs. """
318 if fLong:
319 #
320 # Try do extremes as well as different ranges of random numbers.
321 #
322 auRet = [0, 1, ];
323 if cbMaxOp >= 1:
324 auRet += [ UINT8_MAX / 2, UINT8_MAX / 2 + 1, UINT8_MAX ];
325 if cbMaxOp >= 2:
326 auRet += [ UINT16_MAX / 2, UINT16_MAX / 2 + 1, UINT16_MAX ];
327 if cbMaxOp >= 4:
328 auRet += [ UINT32_MAX / 2, UINT32_MAX / 2 + 1, UINT32_MAX ];
329 if cbMaxOp >= 8:
330 auRet += [ UINT64_MAX / 2, UINT64_MAX / 2 + 1, UINT64_MAX ];
331
332 if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
333 for cBits, cValues in ( (8, 4), (16, 4), (32, 8), (64, 8) ):
334 if cBits < cbMaxOp * 8:
335 auRet += randUxxList(cBits, cValues);
336 cWanted = 16;
337 elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
338 for cBits, cValues in ( (8, 8), (16, 8), (24, 2), (32, 16), (40, 1), (48, 1), (56, 1), (64, 16) ):
339 if cBits < cbMaxOp * 8:
340 auRet += randUxxList(cBits, cValues);
341 cWanted = 64;
342 else:
343 for cBits, cValues in ( (8, 16), (16, 16), (24, 4), (32, 64), (40, 4), (48, 4), (56, 4), (64, 64) ):
344 if cBits < cbMaxOp * 8:
345 auRet += randUxxList(cBits, cValues);
346 cWanted = 168;
347 if len(auRet) < cWanted:
348 auRet += randUxxList(cbEffOp * 8, cWanted - len(auRet));
349 else:
350 #
351 # Short list, just do some random numbers.
352 #
353 auRet = [];
354 if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
355 auRet += randUxxList(cbMaxOp, 1);
356 elif oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Medium:
357 auRet += randUxxList(cbMaxOp, 2);
358 else:
359 auRet = [];
360 for cBits in (8, 16, 32, 64):
361 if cBits < cbMaxOp * 8:
362 auRet += randUxxList(cBits, 1);
363 return auRet;
364
365
366
367class InstrTest_MemOrGreg_2_Greg(InstrTestBase):
368 """
369 Instruction reading memory or general register and writing the result to a
370 general register.
371 """
372
373 def __init__(self, sName, fnCalcResult, sInstr = None, acbOpVars = None):
374 InstrTestBase.__init__(self, sName, sInstr);
375 self.fnCalcResult = fnCalcResult;
376 self.acbOpVars = [ 1, 2, 4, 8 ] if not acbOpVars else list(acbOpVars);
377
378 def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
379 """ Writes the instruction with two general registers as operands. """
380 if cbEffOp == 8:
381 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs64[iOp2]));
382 elif cbEffOp == 4:
383 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs32[iOp1], g_asGRegs32[iOp2]));
384 elif cbEffOp == 2:
385 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs16[iOp1], g_asGRegs16[iOp2]));
386 elif cbEffOp == 1:
387 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs8Rex[iOp1], g_asGRegs8Rex[iOp2]));
388 else:
389 assert False;
390 return True;
391
392 def writeInstrGregPureRM(self, cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen):
393 """ Writes the instruction with two general registers as operands. """
394 if cbEffOp == 8:
395 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs64[iOp1],));
396 elif cbEffOp == 4:
397 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs32[iOp1],));
398 elif cbEffOp == 2:
399 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
400 elif cbEffOp == 1:
401 oGen.write(' %s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));
402 else:
403 assert False;
404
405 if (iOp2 == 5 or iOp2 == 13) and iMod == 0:
406 oGen.write('VBINSTST_NAME(g_u%sData)' % (cbEffOp * 8,))
407 if oGen.oTarget.is64Bit():
408 oGen.write(' wrt rip');
409 else:
410 if iMod == 1:
411 oGen.write('byte %d + ' % (offDisp,));
412 elif iMod == 2:
413 oGen.write('dword %d + ' % (offDisp,));
414 else:
415 assert iMod == 0;
416
417 if cAddrBits == 64:
418 oGen.write(g_asGRegs64[iOp2]);
419 elif cAddrBits == 32:
420 oGen.write(g_asGRegs32[iOp2]);
421 elif cAddrBits == 16:
422 assert False; ## @todo implement 16-bit addressing.
423 else:
424 assert False, str(cAddrBits);
425
426 oGen.write(']\n');
427 return True;
428
429 def generateOneStdTestGregGreg(self, oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
430 """ Generate one standard test. """
431 oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
432 oGen.write(' mov %s, 0x%x\n' % (oGen.oTarget.asGRegs[iOp2], uInput,));
433 oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
434 self.writeInstrGregGreg(cbEffOp, iOp1, iOp2, oGen);
435 oGen.pushConst(uResult);
436 oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
437 _ = cbMaxOp;
438 return True;
439
440 def generateMemSetupPureRM(self, oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp = None):
441 """ Sets up memory for a pure R/M addressed read, iOp2 being the R/M value. """
442 oGen.pushConst(uInput);
443 assert offDisp is None or iMod != 0;
444 if (iOp2 != 5 and iOp2 != 13) or iMod != 0:
445 oGen.write(' call VBINSTST_NAME(%s)\n'
446 % (oGen.needGRegMemSetup(cAddrBits, cbEffOp, iOp2, offDisp),));
447 else:
448 ## @todo generate REX.B=1 variant.
449 oGen.write(' call VBINSTST_NAME(Common_SetupMemReadU%u)\n' % (cbEffOp*8,));
450 oGen.write(' push %s\n' % (oGen.oTarget.asGRegs[iOp2],));
451 return True;
452
453
454 def generateOneStdTestGregMemNoSib(self, oGen, cAddrBits, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult):
455 """ Generate mode 0, 1 and 2 test for the R/M=iOp2. """
456 if cAddrBits == 16:
457 _ = cbMaxOp;
458 else:
459 iMod = 0; # No disp, except for i=5.
460 oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
461 self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput);
462 self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, None, oGen);
463 oGen.pushConst(uResult);
464 oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
465
466 if iOp2 != 5 and iOp2 != 13:
467 iMod = 1;
468 for offDisp in (127, -128):
469 oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
470 self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
471 self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
472 oGen.pushConst(uResult);
473 oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
474
475 iMod = 2;
476 for offDisp in (2147483647, -2147483648):
477 oGen.write(' call VBINSTST_NAME(Common_LoadKnownValues)\n');
478 self.generateMemSetupPureRM(oGen, cAddrBits, cbEffOp, iOp2, iMod, uInput, offDisp);
479 self.writeInstrGregPureRM(cbEffOp, iOp1, cAddrBits, iOp2, iMod, offDisp, oGen);
480 oGen.pushConst(uResult);
481 oGen.write(' call VBINSTST_NAME(%s)\n' % (oGen.needGRegChecker(iOp1, iOp2),));
482
483 return True;
484
485
486 def generateStandardTests(self, oGen):
487 """ Generate standard tests. """
488
489 # Parameters.
490 cbDefOp = oGen.oTarget.getDefOpBytes();
491 cbMaxOp = oGen.oTarget.getMaxOpBytes();
492 auShortInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen);
493 auLongInputs = self.generateInputs(cbDefOp, cbMaxOp, oGen, fLong = True);
494 iLongOp1 = oGen.oTarget.randGRegNoSp();
495 iLongOp2 = oGen.oTarget.randGRegNoSp();
496 oOp2Range = range(oGen.oTarget.getGRegCount());
497 oOp1MemRange = range(oGen.oTarget.getGRegCount());
498 if oGen.oOptions.sTestSize == InstructionTestGen.ksTestSize_Tiny:
499 oOp2Range = [iLongOp2,];
500 oOp1MemRange = [iLongOp1,];
501
502 # Register tests
503 if False:
504 for cbEffOp in self.acbOpVars:
505 if cbEffOp > cbMaxOp:
506 continue;
507 for iOp1 in range(oGen.oTarget.getGRegCount()):
508 if oGen.oTarget.asGRegsNoSp[iOp1] is None:
509 continue;
510 for iOp2 in oOp2Range:
511 if oGen.oTarget.asGRegsNoSp[iOp2] is None:
512 continue;
513 for uInput in (auLongInputs if iOp1 == iLongOp1 and iOp2 == iLongOp2 else auShortInputs):
514 uResult = self.fnCalcResult(cbEffOp, uInput,
515 oGen.auRegValues[iOp1] if iOp1 != iOp2 else uInput, oGen);
516 oGen.newSubTest();
517 self.generateOneStdTestGregGreg(oGen, cbEffOp, cbMaxOp, iOp1, iOp2, uInput, uResult);
518
519 # Memory test.
520 for cbEffOp in self.acbOpVars:
521 if cbEffOp > cbMaxOp:
522 continue;
523 for iOp1 in oOp1MemRange:
524 if oGen.oTarget.asGRegsNoSp[iOp1] is None:
525 continue;
526 for cAddrBits in oGen.oTarget.getAddrModes():
527 for iOp2 in range(len(oGen.oTarget.asGRegs)):
528 if iOp2 != 4:
529
530 for uInput in (auLongInputs if iOp1 == iLongOp1 and False else auShortInputs):
531 oGen.newSubTest();
532 if iOp1 == iOp2 and iOp2 != 5 and iOp2 != 13 and cbEffOp != cbMaxOp:
533 continue; # Don't know the high bit of the address ending up the result - skip it.
534 uResult = self.fnCalcResult(cbEffOp, uInput, oGen.auRegValues[iOp1], oGen);
535 self.generateOneStdTestGregMemNoSib(oGen, cAddrBits, cbEffOp, cbMaxOp,
536 iOp1, iOp2, uInput, uResult);
537 else:
538 pass; # SIB
539
540 return True;
541
542 def generateTest(self, oGen, sTestFnName):
543 oGen.write('VBINSTST_BEGINPROC %s\n' % (sTestFnName,));
544 #oGen.write(' int3\n');
545
546 self.generateStandardTests(oGen);
547
548 #oGen.write(' int3\n');
549 oGen.write(' ret\n');
550 oGen.write('VBINSTST_ENDPROC %s\n' % (sTestFnName,));
551 return True;
552
553
554
555class InstrTest_Mov_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
556 """
557 Tests MOV Gv,Ev.
558 """
559 def __init__(self):
560 InstrTest_MemOrGreg_2_Greg.__init__(self, 'mov Gv,Ev', self.calc_mov);
561
562 @staticmethod
563 def calc_mov(cbEffOp, uInput, uCur, oGen):
564 """ Calculates the result of a mov instruction."""
565 if cbEffOp == 8:
566 return uInput & UINT64_MAX;
567 if cbEffOp == 4:
568 return uInput & UINT32_MAX;
569 if cbEffOp == 2:
570 return (uCur & 0xffffffffffff0000) | (uInput & UINT16_MAX);
571 assert cbEffOp == 1; _ = oGen;
572 return (uCur & 0xffffffffffffff00) | (uInput & UINT8_MAX);
573
574
575class InstrTest_MovSxD_Gv_Ev(InstrTest_MemOrGreg_2_Greg):
576 """
577 Tests MOVSXD Gv,Ev.
578 """
579 def __init__(self):
580 InstrTest_MemOrGreg_2_Greg.__init__(self, 'movsxd Gv,Ev', self.calc_movsxd, acbOpVars = [ 8, 4, 2, ]);
581
582 def writeInstrGregGreg(self, cbEffOp, iOp1, iOp2, oGen):
583 if cbEffOp == 8:
584 oGen.write(' %s %s, %s\n' % (self.sInstr, g_asGRegs64[iOp1], g_asGRegs32[iOp2]));
585 elif cbEffOp == 4 or cbEffOp == 2:
586 abInstr = [];
587 if cbEffOp != oGen.oTarget.getDefOpBytes():
588 abInstr.append(X86_OP_PRF_SIZE_OP);
589 abInstr += calcRexPrefixForTwoModRmRegs(iOp1, iOp2);
590 abInstr.append(0x63);
591 abInstr += calcModRmForTwoRegs(iOp1, iOp2);
592 oGen.writeInstrBytes(abInstr);
593 else:
594 assert False;
595 assert False;
596 return True;
597
598 def isApplicable(self, oGen):
599 return oGen.oTarget.is64Bit();
600
601 @staticmethod
602 def calc_movsxd(cbEffOp, uInput, uCur, oGen):
603 """
604 Calculates the result of a movxsd instruction.
605 Returns the result value (cbMaxOp sized).
606 """
607 _ = oGen;
608 if cbEffOp == 8 and (uInput & RT_BIT_32(31)):
609 return (UINT32_MAX << 32) | (uInput & UINT32_MAX);
610 if cbEffOp == 2:
611 return (uCur & 0xffffffffffff0000) | (uInput & 0xffff);
612 return uInput & UINT32_MAX;
613
614
615## Instruction Tests.
616g_aoInstructionTests = [
617 InstrTest_Mov_Gv_Ev(),
618 #InstrTest_MovSxD_Gv_Ev(),
619];
620
621
622class InstructionTestGen(object):
623 """
624 Instruction Test Generator.
625 """
626
627 ## @name Test size
628 ## @{
629 ksTestSize_Large = 'large';
630 ksTestSize_Medium = 'medium';
631 ksTestSize_Tiny = 'tiny';
632 ## @}
633 kasTestSizes = ( ksTestSize_Large, ksTestSize_Medium, ksTestSize_Tiny );
634
635
636
637 def __init__(self, oOptions):
638 self.oOptions = oOptions;
639 self.oTarget = g_dTargetEnvs[oOptions.sTargetEnv];
640
641 # Calculate the number of output files.
642 self.cFiles = 1;
643 if len(g_aoInstructionTests) > self.oOptions.cInstrPerFile:
644 self.cFiles = len(g_aoInstructionTests) / self.oOptions.cInstrPerFile;
645 if self.cFiles * self.oOptions.cInstrPerFile < len(g_aoInstructionTests):
646 self.cFiles += 1;
647
648 # Fix the known register values.
649 self.au64Regs = randUxxList(64, 16);
650 self.au32Regs = [(self.au64Regs[i] & UINT32_MAX) for i in range(8)];
651 self.au16Regs = [(self.au64Regs[i] & UINT16_MAX) for i in range(8)];
652 self.auRegValues = self.au64Regs if self.oTarget.is64Bit() else self.au32Regs;
653
654 # Declare state variables used while generating.
655 self.oFile = sys.stderr;
656 self.iFile = -1;
657 self.sFile = '';
658 self.dCheckFns = dict();
659 self.dMemSetupFns = dict();
660 self.d64BitConsts = dict();
661
662
663 #
664 # Methods used by instruction tests.
665 #
666
667 def write(self, sText):
668 """ Writes to the current output file. """
669 return self.oFile.write(unicode(sText));
670
671 def writeln(self, sText):
672 """ Writes a line to the current output file. """
673 self.write(sText);
674 return self.write('\n');
675
676 def writeInstrBytes(self, abInstr):
677 """
678 Emits an instruction given as a sequence of bytes values.
679 """
680 self.write(' db %#04x' % (abInstr[0],));
681 for i in range(1, len(abInstr)):
682 self.write(', %#04x' % (abInstr[i],));
683 return self.write('\n');
684
685 def newSubTest(self):
686 """
687 Indicates that a new subtest has started.
688 """
689 self.write(' mov dword [VBINSTST_NAME(g_uVBInsTstSubTestIndicator) xWrtRIP], __LINE__\n');
690 return True;
691
692 def needGRegChecker(self, iReg1, iReg2):
693 """
694 Records the need for a given register checker function, returning its label.
695 """
696 assert iReg1 < 32; assert iReg2 < 32;
697 iRegs = iReg1 + iReg2 * 32;
698 if iRegs in self.dCheckFns:
699 self.dCheckFns[iRegs] += 1;
700 else:
701 self.dCheckFns[iRegs] = 1;
702 return 'Common_Check_%s_%s' % (self.oTarget.asGRegs[iReg1], self.oTarget.asGRegs[iReg2]);
703
704 def needGRegMemSetup(self, cAddrBits, cbEffOp, iReg1, offDisp = None):
705 """
706 Records the need for a given register checker function, returning its label.
707 """
708 sName = '%ubit_U%u_%s' % (cAddrBits, cbEffOp * 8, gregName(iReg1, cAddrBits),);
709 if offDisp is not None:
710 sName += '_%#010x' % (offDisp & UINT32_MAX, );
711 if sName in self.dCheckFns:
712 self.dMemSetupFns[sName] += 1;
713 else:
714 self.dMemSetupFns[sName] = 1;
715 return 'Common_MemSetup_' + sName;
716
717 def need64BitConstant(self, uVal):
718 """
719 Records the need for a 64-bit constant, returning its label.
720 These constants are pooled to attempt reduce the size of the whole thing.
721 """
722 assert uVal >= 0 and uVal <= UINT64_MAX;
723 if uVal in self.d64BitConsts:
724 self.d64BitConsts[uVal] += 1;
725 else:
726 self.d64BitConsts[uVal] = 1;
727 return 'g_u64Const_0x%016x' % (uVal, );
728
729 def pushConst(self, uResult):
730 """
731 Emits a push constant value, taking care of high values on 64-bit hosts.
732 """
733 if self.oTarget.is64Bit() and uResult >= 0x80000000:
734 self.write(' push qword [%s wrt rip]\n' % (self.need64BitConstant(uResult),));
735 else:
736 self.write(' push dword 0x%x\n' % (uResult,));
737 return True;
738
739
740 #
741 # Internal machinery.
742 #
743
744 def _calcTestFunctionName(self, oInstrTest, iInstrTest):
745 """
746 Calc a test function name for the given instruction test.
747 """
748 sName = 'TestInstr%03u_%s' % (iInstrTest, oInstrTest.sName);
749 return sName.replace(',', '_').replace(' ', '_').replace('%', '_');
750
751 def _generateFileHeader(self, ):
752 """
753 Writes the file header.
754 Raises exception on trouble.
755 """
756 self.write('; $Id: InstructionTestGen.py 46744 2013-06-23 17:54:29Z vboxsync $\n'
757 ';; @file %s\n'
758 '; Autogenerate by %s %s. DO NOT EDIT\n'
759 ';\n'
760 '\n'
761 ';\n'
762 '; Headers\n'
763 ';\n'
764 '%%include "env-%s.mac"\n'
765 % ( os.path.basename(self.sFile),
766 os.path.basename(__file__), __version__[11:-1],
767 self.oTarget.sName,
768 ) );
769 # Target environment specific init stuff.
770
771 #
772 # Global variables.
773 #
774 self.write('\n\n'
775 ';\n'
776 '; Globals\n'
777 ';\n');
778 self.write('VBINSTST_BEGINDATA\n'
779 'VBINSTST_GLOBALNAME_EX g_pvLow16Mem4K, data hidden\n'
780 ' dq 0\n'
781 'VBINSTST_GLOBALNAME_EX g_pvLow32Mem4K, data hidden\n'
782 ' dq 0\n'
783 'VBINSTST_GLOBALNAME_EX g_pvMem4K, data hidden\n'
784 ' dq 0\n'
785 'VBINSTST_GLOBALNAME_EX g_uVBInsTstSubTestIndicator, data hidden\n'
786 ' dd 0\n'
787 'VBINSTST_BEGINCODE\n'
788 );
789 self.write('%ifdef RT_ARCH_AMD64\n');
790 for i in range(len(g_asGRegs64)):
791 self.write('g_u64KnownValue_%s: dq 0x%x\n' % (g_asGRegs64[i], self.au64Regs[i]));
792 self.write('%endif\n\n')
793
794 #
795 # Common functions.
796 #
797
798 # Loading common values.
799 self.write('\n\n'
800 'VBINSTST_BEGINPROC Common_LoadKnownValues\n'
801 '%ifdef RT_ARCH_AMD64\n');
802 for i in range(len(g_asGRegs64NoSp)):
803 if g_asGRegs64NoSp[i]:
804 self.write(' mov %s, 0x%x\n' % (g_asGRegs64NoSp[i], self.au64Regs[i],));
805 self.write('%else\n');
806 for i in range(8):
807 if g_asGRegs32NoSp[i]:
808 self.write(' mov %s, 0x%x\n' % (g_asGRegs32NoSp[i], self.au32Regs[i],));
809 self.write('%endif\n'
810 ' ret\n'
811 'VBINSTST_ENDPROC Common_LoadKnownValues\n'
812 '\n');
813
814 self.write('VBINSTST_BEGINPROC Common_CheckKnownValues\n'
815 '%ifdef RT_ARCH_AMD64\n');
816 for i in range(len(g_asGRegs64NoSp)):
817 if g_asGRegs64NoSp[i]:
818 self.write(' cmp %s, [g_u64KnownValue_%s wrt rip]\n'
819 ' je .ok_%u\n'
820 ' push %u ; register number\n'
821 ' push %s ; actual\n'
822 ' push qword [g_u64KnownValue_%s wrt rip] ; expected\n'
823 ' call VBINSTST_NAME(Common_BadValue)\n'
824 '.ok_%u:\n'
825 % ( g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i, i, g_asGRegs64NoSp[i], g_asGRegs64NoSp[i], i,));
826 self.write('%else\n');
827 for i in range(8):
828 if g_asGRegs32NoSp[i]:
829 self.write(' cmp %s, 0x%x\n'
830 ' je .ok_%u\n'
831 ' push %u ; register number\n'
832 ' push %s ; actual\n'
833 ' push dword 0x%x ; expected\n'
834 ' call VBINSTST_NAME(Common_BadValue)\n'
835 '.ok_%u:\n'
836 % ( g_asGRegs32NoSp[i], self.au32Regs[i], i, i, g_asGRegs32NoSp[i], self.au32Regs[i], i,));
837 self.write('%endif\n'
838 ' ret\n'
839 'VBINSTST_ENDPROC Common_CheckKnownValues\n'
840 '\n');
841
842 return True;
843
844 def _generateMemSetupFunctions(self):
845 """
846 Generates the memory setup functions.
847 """
848 cDefAddrBits = self.oTarget.getDefAddrBits();
849 for sName in self.dMemSetupFns:
850 # Unpack it.
851 asParams = sName.split('_');
852 cAddrBits = int(asParams[0][:-3]);
853 cEffOpBits = int(asParams[1][1:]);
854 sBaseReg = asParams[2];
855
856 if cAddrBits == 64: asAddrGRegs = g_asGRegs64;
857 elif cAddrBits == 32: asAddrGRegs = g_asGRegs32;
858 else: asAddrGRegs = g_asGRegs16;
859 try:
860 iBaseReg = asAddrGRegs.index(sBaseReg);
861 except ValueError:
862 assert False, 'sBaseReg=%s' % (sBaseReg,);
863 raise;
864
865 i = 3;
866 u32Disp = None;
867 if i < len(asParams) and len(asParams[i]) == 10:
868 u32Disp = long(asParams[i], 16);
869 i += 1;
870
871 sIndexReg = None;
872 iIndexReg = None;
873 if i < len(asParams):
874 sIndexReg = asParams[i];
875 iBaseReg = asAddrGRegs.index(sBaseReg);
876 i += 1;
877
878 iScale = 1;
879 if i < len(asParams):
880 iScale = int(asParams[i]); assert iScale in [2, 4, 8];
881 i += 1;
882
883 assert i == len(asParams), 'i=%d len=%d len[i]=%d (%s)' % (i, len(asParams), len(asParams[i]), asParams[i],);
884
885 # Prologue.
886 iTmpReg1 = 0 if iBaseReg != 0 else 1;
887 self.write('\n\n'
888 'VBINSTST_BEGINPROC Common_MemSetup_%s\n'
889 ' MY_PUSH_FLAGS\n'
890 ' push %s\n'
891 % (sName, self.oTarget.asGRegs[iTmpReg1], ));
892 self.write('; cAddrBits=%s cEffOpBits=%s iBaseReg=%s u32Disp=%s iIndexReg=%s iScale=%s\n'
893 % (cAddrBits, cEffOpBits, iBaseReg, u32Disp, iIndexReg, iScale,));
894
895 # Figure out what to use.
896 if cEffOpBits == 64:
897 sTmpReg1 = g_asGRegs64[iTmpReg1];
898 sDataVar = 'VBINSTST_NAME(g_u64Data)';
899 elif cEffOpBits == 32:
900 sTmpReg1 = g_asGRegs32[iTmpReg1];
901 sDataVar = 'VBINSTST_NAME(g_u32Data)';
902 elif cEffOpBits == 16:
903 sTmpReg1 = g_asGRegs16[iTmpReg1];
904 sDataVar = 'VBINSTST_NAME(g_u16Data)';
905 else:
906 assert cEffOpBits == 8;
907 sTmpReg1 = g_asGRegs8Rex[iTmpReg1];
908 sDataVar = 'VBINSTST_NAME(g_u8Data)';
909
910 # Load the value and mem address, sorting the value there.
911 self.write(' mov %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n' % (sTmpReg1,));
912 if cAddrBits >= cDefAddrBits:
913 self.write(' mov [%s xWrtRIP], %s\n' % (sDataVar, sTmpReg1,));
914 self.write(' lea %s, [%s xWrtRIP]\n' % (sBaseReg, sDataVar,));
915 else:
916
917 if cAddrBits == 16:
918 self.write(' mov %s, [VBINSTST_NAME(g_pvLow16Mem4K) xWrtRIP]\n' % (sBaseReg,));
919 else:
920 self.write(' mov %s, [VBINSTST_NAME(g_pvLow32Mem4K) xWrtRIP]\n' % (sBaseReg,));
921 self.write(' add %s, %s\n' % (sBaseReg, (randU16() << cEffOpBits) & 0xfff, ));
922 self.write(' mov [%s], %s\n' % (sBaseReg, sTmpReg1, ));
923
924 # Adjust for disposition and scaling.
925 if u32Disp is not None:
926 self.write(' sub %s, %d\n' % ( sBaseReg, convU32ToSigned(u32Disp), ));
927 if iIndexReg is not None:
928 uIdxRegVal = randUxx(cAddrBits);
929 self.write(' mov %s, %u\n' % ( sIndexReg, uIdxRegVal,));
930 if cAddrBits == 64:
931 self.write(' sub %s, %#06x\n' % ( sBaseReg, uIdxRegVal * iScale, ));
932 elif cAddrBits == 16:
933 self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT32_MAX, ));
934 else:
935 assert cAddrBits == 16;
936 self.write(' sub %s, %#06x\n' % ( sBaseReg, (uIdxRegVal * iScale) & UINT16_MAX, ));
937
938 # Set upper bits that's supposed to be unused.
939 if cDefAddrBits > cAddrBits or cAddrBits == 16:
940 if cDefAddrBits == 64:
941 assert cAddrBits == 32;
942 self.write(' mov %s, %#018x\n'
943 ' or %s, %s\n'
944 % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
945 g_asGRegs64[iBaseReg], g_asGRegs64[iTmpReg1],));
946 if iIndexReg is not None:
947 self.write(' mov %s, %#018x\n'
948 ' or %s, %s\n'
949 % ( g_asGRegs64[iTmpReg1], randU64() & 0xffffffff00000000,
950 g_asGRegs64[iIndexReg], g_asGRegs64[iTmpReg1],));
951 else:
952 assert cDefAddrBits == 32; assert cAddrBits == 16;
953 self.write(' or %s, %#010x\n'
954 % ( g_asGRegs32[iBaseReg], randU32() & 0xffff0000, ));
955 if iIndexReg is not None:
956 self.write(' or %s, %#010x\n'
957 % ( g_asGRegs32[iIndexReg], randU32() & 0xffff0000, ));
958
959 # Epilogue.
960 self.write(' pop %s\n'
961 ' MY_POP_FLAGS\n'
962 ' ret sCB\n'
963 'VBINSTST_ENDPROC Common_MemSetup_%s\n'
964 % ( self.oTarget.asGRegs[iTmpReg1], sName,));
965
966
967 def _generateFileFooter(self):
968 """
969 Generates file footer.
970 """
971
972 # Register checking functions.
973 for iRegs in self.dCheckFns:
974 iReg1 = iRegs & 0x1f;
975 sReg1 = self.oTarget.asGRegs[iReg1];
976 iReg2 = (iRegs >> 5) & 0x1f;
977 sReg2 = self.oTarget.asGRegs[iReg2];
978 sPushSize = 'dword';
979
980 self.write('\n\n'
981 '; Checks two register values, expected values pushed on the stack.\n'
982 '; To save space, the callee cleans up the stack.'
983 '; Ref count: %u\n'
984 'VBINSTST_BEGINPROC Common_Check_%s_%s\n'
985 ' MY_PUSH_FLAGS\n'
986 % ( self.dCheckFns[iRegs], sReg1, sReg2, ) );
987
988 self.write(' cmp %s, [xSP + MY_PUSH_FLAGS_SIZE + xCB]\n'
989 ' je .equal1\n'
990 ' push %s %u ; register number\n'
991 ' push %s ; actual\n'
992 ' mov %s, [xSP + sCB*2 + MY_PUSH_FLAGS_SIZE + xCB]\n'
993 ' push %s ; expected\n'
994 ' call VBINSTST_NAME(Common_BadValue)\n'
995 ' pop %s\n'
996 ' pop %s\n'
997 ' pop %s\n'
998 '.equal1:\n'
999 % ( sReg1, sPushSize, iReg1, sReg1, sReg1, sReg1, sReg1, sReg1, sReg1, ) );
1000 if iReg1 != iReg2: # If input and result regs are the same, only check the result.
1001 self.write(' cmp %s, [xSP + sCB + MY_PUSH_FLAGS_SIZE + xCB]\n'
1002 ' je .equal2\n'
1003 ' push %s %u ; register number\n'
1004 ' push %s ; actual\n'
1005 ' mov %s, [xSP + sCB*3 + MY_PUSH_FLAGS_SIZE + xCB]\n'
1006 ' push %s ; expected\n'
1007 ' call VBINSTST_NAME(Common_BadValue)\n'
1008 ' pop %s\n'
1009 ' pop %s\n'
1010 ' pop %s\n'
1011 '.equal2:\n'
1012 % ( sReg2, sPushSize, iReg2, sReg2, sReg2, sReg2, sReg2, sReg2, sReg2, ) );
1013
1014 if self.oTarget.is64Bit():
1015 self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg1, sReg1,));
1016 if iReg1 != iReg2:
1017 self.write(' mov %s, [g_u64KnownValue_%s wrt rip]\n' % (sReg2, sReg2,));
1018 else:
1019 self.write(' mov %s, 0x%x\n' % (sReg1, self.au32Regs[iReg1],));
1020 if iReg1 != iReg2:
1021 self.write(' mov %s, 0x%x\n' % (sReg2, self.au32Regs[iReg2],));
1022 self.write(' MY_POP_FLAGS\n'
1023 ' call VBINSTST_NAME(Common_CheckKnownValues)\n'
1024 ' ret sCB*2\n'
1025 'VBINSTST_ENDPROC Common_Check_%s_%s\n'
1026 % (sReg1, sReg2,));
1027
1028 # memory setup functions
1029 self._generateMemSetupFunctions();
1030
1031 # 64-bit constants.
1032 if len(self.d64BitConsts) > 0:
1033 self.write('\n\n'
1034 ';\n'
1035 '; 64-bit constants\n'
1036 ';\n');
1037 for uVal in self.d64BitConsts:
1038 self.write('g_u64Const_0x%016x: dq 0x%016x ; Ref count: %d\n' % (uVal, uVal, self.d64BitConsts[uVal], ) );
1039
1040 return True;
1041
1042 def _generateTests(self):
1043 """
1044 Generate the test cases.
1045 """
1046 for self.iFile in range(self.cFiles):
1047 if self.cFiles == 1:
1048 self.sFile = '%s.asm' % (self.oOptions.sOutputBase,)
1049 else:
1050 self.sFile = '%s-%u.asm' % (self.oOptions.sOutputBase, self.iFile)
1051 self.oFile = sys.stdout;
1052 if self.oOptions.sOutputBase != '-':
1053 self.oFile = io.open(self.sFile, 'w', encoding = 'utf-8');
1054
1055 self._generateFileHeader();
1056
1057 # Calc the range.
1058 iInstrTestStart = self.iFile * self.oOptions.cInstrPerFile;
1059 iInstrTestEnd = iInstrTestStart + self.oOptions.cInstrPerFile;
1060 if iInstrTestEnd > len(g_aoInstructionTests):
1061 iInstrTestEnd = len(g_aoInstructionTests);
1062
1063 # Generate the instruction tests.
1064 for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1065 oInstrTest = g_aoInstructionTests[iInstrTest];
1066 self.write('\n'
1067 '\n'
1068 ';\n'
1069 '; %s\n'
1070 ';\n'
1071 % (oInstrTest.sName,));
1072 oInstrTest.generateTest(self, self._calcTestFunctionName(oInstrTest, iInstrTest));
1073
1074 # Generate the main function.
1075 self.write('\n\n'
1076 'VBINSTST_BEGINPROC TestInstrMain\n'
1077 ' MY_PUSH_ALL\n'
1078 ' sub xSP, 40h\n'
1079 '\n');
1080
1081 for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1082 oInstrTest = g_aoInstructionTests[iInstrTest];
1083 if oInstrTest.isApplicable(self):
1084 self.write('%%ifdef ASM_CALL64_GCC\n'
1085 ' lea rdi, [.szInstr%03u wrt rip]\n'
1086 '%%elifdef ASM_CALL64_MSC\n'
1087 ' lea rcx, [.szInstr%03u wrt rip]\n'
1088 '%%else\n'
1089 ' mov xAX, .szInstr%03u\n'
1090 ' mov [xSP], xAX\n'
1091 '%%endif\n'
1092 ' VBINSTST_CALL_FN_SUB_TEST\n'
1093 ' call VBINSTST_NAME(%s)\n'
1094 % ( iInstrTest, iInstrTest, iInstrTest, self._calcTestFunctionName(oInstrTest, iInstrTest)));
1095
1096 self.write('\n'
1097 ' add xSP, 40h\n'
1098 ' MY_POP_ALL\n'
1099 ' ret\n\n');
1100 for iInstrTest in range(iInstrTestStart, iInstrTestEnd):
1101 self.write('.szInstr%03u: db \'%s\', 0\n' % (iInstrTest, g_aoInstructionTests[iInstrTest].sName,));
1102 self.write('VBINSTST_ENDPROC TestInstrMain\n\n');
1103
1104 self._generateFileFooter();
1105 if self.oOptions.sOutputBase != '-':
1106 self.oFile.close();
1107 self.oFile = None;
1108 self.sFile = '';
1109
1110 return RTEXITCODE_SUCCESS;
1111
1112 def _runMakefileMode(self):
1113 """
1114 Generate a list of output files on standard output.
1115 """
1116 if self.cFiles == 1:
1117 print('%s.asm' % (self.oOptions.sOutputBase,));
1118 else:
1119 print(' '.join('%s-%s.asm' % (self.oOptions.sOutputBase, i) for i in range(self.cFiles)));
1120 return RTEXITCODE_SUCCESS;
1121
1122 def run(self):
1123 """
1124 Generates the tests or whatever is required.
1125 """
1126 if self.oOptions.fMakefileMode:
1127 return self._runMakefileMode();
1128 return self._generateTests();
1129
1130 @staticmethod
1131 def main():
1132 """
1133 Main function a la C/C++. Returns exit code.
1134 """
1135
1136 #
1137 # Parse the command line.
1138 #
1139 oParser = OptionParser(version = __version__[11:-1].strip());
1140 oParser.add_option('--makefile-mode', dest = 'fMakefileMode', action = 'store_true', default = False,
1141 help = 'Special mode for use to output a list of output files for the benefit of '
1142 'the make program (kmk).');
1143 oParser.add_option('--split', dest = 'cInstrPerFile', metavar = '<instr-per-file>', type = 'int', default = 9999999,
1144 help = 'Number of instruction to test per output file.');
1145 oParser.add_option('--output-base', dest = 'sOutputBase', metavar = '<file>', default = None,
1146 help = 'The output file base name, no suffix please. Required.');
1147 oParser.add_option('--target', dest = 'sTargetEnv', metavar = '<target>',
1148 default = 'iprt-r3-32',
1149 choices = g_dTargetEnvs.keys(),
1150 help = 'The target environment. Choices: %s'
1151 % (', '.join(sorted(g_dTargetEnvs.keys())),));
1152 oParser.add_option('--test-size', dest = 'sTestSize', default = InstructionTestGen.ksTestSize_Medium,
1153 choices = InstructionTestGen.kasTestSizes,
1154 help = 'Selects the test size.');
1155
1156 (oOptions, asArgs) = oParser.parse_args();
1157 if len(asArgs) > 0:
1158 oParser.print_help();
1159 return RTEXITCODE_SYNTAX
1160 if oOptions.sOutputBase is None:
1161 print('syntax error: Missing required option --output-base.', file = sys.stderr);
1162 return RTEXITCODE_SYNTAX
1163
1164 #
1165 # Instantiate the program class and run it.
1166 #
1167 oProgram = InstructionTestGen(oOptions);
1168 return oProgram.run();
1169
1170
1171if __name__ == '__main__':
1172 sys.exit(InstructionTestGen.main());
1173
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