Changeset 46744 in vbox for trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

Timestamp:

Jun 23, 2013 5:54:29 PM (11 years ago)

Author:

vboxsync

Message:

32-bit memory accesses in 64-bit mode.

File:

• trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py (modified) (10 diffs)

trunk/src/VBox/VMM/testcase/Instructions/InstructionTestGen.py

@@ -45 +45 @@
     """ 64-bit one bit mask. """
     return 1 << iBit;
-## @}
-
-
-## @name Misc
-## @{
-
-def convU32ToSigned(u32):
-    """ Converts a 32-bit unsigned value to 32-bit signed. """
-    if u32 < 0x80000000:
-        return u32;
-    return u32 - UINT32_MAX - 1;
-
 ## @}
 
@@ -114 +102 @@
 g_asGRegs16     = ('ax',  'cx',  'dx',  'bx',  'sp',  'bp',  'si',  'di',
                    'r8w', 'r9w', 'r10w', 'r11w', 'r12w', 'r13w', 'r14w', 'r15w');
-g_asGRegs8_86   = ('al',  'cl',  'dl',  'bl',  'ah',  'ah',  'dh',  'bh');
-g_asGRegs8_64   = ('al',  'cl',  'dl',  'bl',  'spl', 'bpl', 'sil',  'dil',        # pylint: disable=C0103
+g_asGRegs8      = ('al',  'cl',  'dl',  'bl',  'ah',  'ah',  'dh',  'bh');
+g_asGRegs8Rex   = ('al',  'cl',  'dl',  'bl',  'spl', 'bpl', 'sil',  'dil',
                    'r8b', 'r9b', 'r10b', 'r11b', 'r12b', 'r13b', 'r14b', 'r15b');
 ## @}
@@ -174 +162 @@
         | (iRm   &  X86_MODRM_RM_MASK);
     return [bRm,];
+
+## @}
+
+
+## @name Misc
+## @{
+
+def convU32ToSigned(u32):
+    """ Converts a 32-bit unsigned value to 32-bit signed. """
+    if u32 < 0x80000000:
+        return u32;
+    return u32 - UINT32_MAX - 1;
+
+def gregName(iReg, cBits, fRexByteRegs = True):
+    """ Gets the name of a general register by index and width. """
+    if cBits == 64:
+        return g_asGRegs64[iReg];
+    if cBits == 32:
+        return g_asGRegs32[iReg];
+    if cBits == 16:
+        return g_asGRegs16[iReg];
+    assert cBits == 8;
+    if fRexByteRegs:
+        return g_asGRegs8Rex[iReg];
+    return g_asGRegs8[iReg];
 
 ## @}
@@ -268 +281 @@
         if self.sInstrSet == self.ksInstrSet_32:
             return [32, 16];
-        return [64, 64];
+        return [64, 32];
 
 
@@ -372 +385 @@
             oGen.write('        %s %s, %s\n' % (self.sInstr, g_asGRegs16[iOp1], g_asGRegs16[iOp2]));
         elif cbEffOp == 1:
-            oGen.write('        %s %s, %s\n' % (self.sInstr, g_asGRegs8_64[iOp1], g_asGRegs8_64[iOp2]));
+            oGen.write('        %s %s, %s\n' % (self.sInstr, g_asGRegs8Rex[iOp1], g_asGRegs8Rex[iOp2]));
         else:
             assert False;
@@ -386 +399 @@
             oGen.write('        %s %s, [' % (self.sInstr, g_asGRegs16[iOp1],));
         elif cbEffOp == 1:
-            oGen.write('        %s %s, [' % (self.sInstr, g_asGRegs8_64[iOp1],));
+            oGen.write('        %s %s, [' % (self.sInstr, g_asGRegs8Rex[iOp1],));
         else:
             assert False;
@@ -524 +537 @@
                         else:
                             pass; # SIB
-                    break; ## remove me!
-                #break; ## remove me!
-            #break; ## remove me!
 
         return True;
@@ -696 +706 @@
         Records the need for a given register checker function, returning its label.
         """
-        sName = '%ubit_U%u_%s' % (cAddrBits, cbEffOp * 8, self.oTarget.asGRegs[iReg1]);
+        sName = '%ubit_U%u_%s' % (cAddrBits, cbEffOp * 8, gregName(iReg1, cAddrBits),);
         if offDisp is not None:
             sName += '_%#010x' % (offDisp & UINT32_MAX, );
@@ -847 +857 @@
             elif cAddrBits == 32: asAddrGRegs = g_asGRegs32;
             else:                 asAddrGRegs = g_asGRegs16;
-            iBaseReg = asAddrGRegs.index(sBaseReg);
+            try:
+                iBaseReg = asAddrGRegs.index(sBaseReg);
+            except ValueError:
+                assert False, 'sBaseReg=%s' % (sBaseReg,);
+                raise;
 
             i = 3;
@@ -891 +905 @@
             else:
                 assert cEffOpBits == 8;
-                sTmpReg1 = g_asGRegs8_64[iTmpReg1];
+                sTmpReg1 = g_asGRegs8Rex[iTmpReg1];
                 sDataVar = 'VBINSTST_NAME(g_u8Data)';