bs3-cpu-generated-1-template.c@ 66744

Last change on this file since 66744 was 66744, checked in by vboxsync, 8 years ago
IEM: Implemented movupd Vpd,Wpd (0x66 0x0f 0x10).
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File size: 157.9 KB

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1	/* $Id: bs3-cpu-generated-1-template.c 66744 2017-05-02 11:28:41Z vboxsync $ */
2	/** @file
3	* BS3Kit - bs3-cpu-generated-1, C code template.
4	*/
5
6	/*
7	* Copyright (C) 2007-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* The contents of this file may alternatively be used under the terms
18	* of the Common Development and Distribution License Version 1.0
19	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
20	* VirtualBox OSE distribution, in which case the provisions of the
21	* CDDL are applicable instead of those of the GPL.
22	*
23	* You may elect to license modified versions of this file under the
24	* terms and conditions of either the GPL or the CDDL or both.
25	*/
26
27	#ifndef BS3_INSTANTIATING_CMN
28	# error "BS3_INSTANTIATING_CMN not defined"
29	#endif
30
31
32	/*********************************************************************************************************************************
33	* Header Files *
34	*********************************************************************************************************************************/
35	#include <iprt/asm.h>
36	#include <iprt/asm-amd64-x86.h>
37
38	#include "bs3-cpu-generated-1.h"
39
40
41	/*********************************************************************************************************************************
42	* Defined Constants And Macros *
43	*********************************************************************************************************************************/
44	#define P_CS X86_OP_PRF_CS
45	#define P_SS X86_OP_PRF_SS
46	#define P_DS X86_OP_PRF_DS
47	#define P_ES X86_OP_PRF_ES
48	#define P_FS X86_OP_PRF_FS
49	#define P_GS X86_OP_PRF_GS
50	#define P_OZ X86_OP_PRF_SIZE_OP
51	#define P_AZ X86_OP_PRF_SIZE_ADDR
52	#define P_LK X86_OP_PRF_LOCK
53	#define P_RN X86_OP_PRF_REPNZ
54	#define P_RZ X86_OP_PRF_REPZ
55
56	#define REX_WRBX (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
57	#define REX_W___ (X86_OP_REX_W)
58	#define REX_WR__ (X86_OP_REX_W \| X86_OP_REX_R)
59	#define REX_W_B_ (X86_OP_REX_W \| X86_OP_REX_B)
60	#define REX_W__X (X86_OP_REX_W \| X86_OP_REX_X)
61	#define REX_WRB_ (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_B)
62	#define REX_WR_X (X86_OP_REX_W \| X86_OP_REX_R \| X86_OP_REX_X)
63	#define REX_W_BX (X86_OP_REX_W \| X86_OP_REX_B \| X86_OP_REX_X)
64	#define REX__R__ (X86_OP_REX_R)
65	#define REX__RB_ (X86_OP_REX_R \| X86_OP_REX_B)
66	#define REX__R_X (X86_OP_REX_R \| X86_OP_REX_X)
67	#define REX__RBX (X86_OP_REX_R \| X86_OP_REX_B \| X86_OP_REX_X)
68	#define REX___B_ (X86_OP_REX_B)
69	#define REX___BX (X86_OP_REX_B \| X86_OP_REX_X)
70	#define REX____X (X86_OP_REX_X)
71	#define REX_____ (0x40)
72
73
74	/** @def BS3CG1_DPRINTF
75	* Debug print macro.
76	*/
77	#if 0
78	# define BS3CG1_DPRINTF(a_ArgList) Bs3TestPrintf a_ArgList
79	# define BS3CG1_DEBUG_CTX_MOD
80	#else
81	# define BS3CG1_DPRINTF(a_ArgList) do { } while (0)
82	#endif
83
84
85
86	/*********************************************************************************************************************************
87	* Structures and Typedefs *
88	*********************************************************************************************************************************/
89	/** Operand value location. */
90	typedef enum BS3CG1OPLOC
91	{
92	BS3CG1OPLOC_INVALID = 0,
93	BS3CG1OPLOC_CTX,
94	BS3CG1OPLOC_IMM,
95	BS3CG1OPLOC_MEM,
96	BS3CG1OPLOC_MEM_RW,
97	BS3CG1OPLOC_END
98	} BS3CG1OPLOC;
99
100
101	/**
102	* The state.
103	*/
104	typedef struct BS3CG1STATE
105	{
106	/** @name Instruction details (expanded from BS3CG1INSTR).
107	* @{ */
108	/** Pointer to the mnemonic string (not terminated) (g_achBs3Cg1Mnemonics). */
109	const char BS3_FAR *pchMnemonic;
110	/** Pointer to the test header. */
111	PCBS3CG1TESTHDR pTestHdr;
112	/** Pointer to the per operand flags (g_abBs3Cg1Operands). */
113	const uint8_t BS3_FAR *pabOperands;
114	/** Opcode bytes (g_abBs3Cg1Opcodes). */
115	const uint8_t BS3_FAR *pabOpcodes;
116	/** The current instruction number in the input array (for error reporting). */
117	uint32_t iInstr;
118
119	/** The instruction flags. */
120	uint32_t fFlags;
121	/** The encoding. */
122	BS3CG1ENC enmEncoding;
123	/** The non-invalid encoding. This differs from enmEncoding when
124	* Bs3Cg1CalcNoneIntelInvalidEncoding has been called. */
125	BS3CG1ENC enmEncodingNonInvalid;
126	/** The CPU test / CPU ID. */
127	BS3CG1CPU enmCpuTest;
128	/** Prefix sensitivity and requirements. */
129	BS3CG1PFXKIND enmPrefixKind;
130	/** Exception type (SSE, AVX). */
131	BS3CG1XCPTTYPE enmXcptType;
132	/** Per operand flags. */
133	BS3CG1OP aenmOperands[4];
134	/** Opcode bytes. */
135	uint8_t abOpcodes[4];
136
137	/** The length of the mnemonic. */
138	uint8_t cchMnemonic;
139	/** Whether to advance the mnemonic pointer or not. */
140	uint8_t fAdvanceMnemonic;
141	/** The number of opcode bytes. */
142	uint8_t cbOpcodes;
143	/** Number of operands. */
144	uint8_t cOperands;
145	/** @} */
146
147	/** Operand size in bytes (0 if not applicable). */
148	uint8_t cbOperand;
149	/** Current target ring (0..3). */
150	uint8_t uCpl;
151
152	/** The current test number. */
153	uint8_t iTest;
154
155	/** Target mode (g_bBs3CurrentMode). */
156	uint8_t bMode;
157	/** The CPU vendor (BS3CPUVENDOR). */
158	uint8_t bCpuVendor;
159	/** First ring being tested. */
160	uint8_t iFirstRing;
161	/** End of rings being tested. */
162	uint8_t iEndRing;
163
164
165	/** @name Current encoded instruction.
166	* @{ */
167	/** The size of the current instruction that we're testing. */
168	uint8_t cbCurInstr;
169	/** The size the prefixes. */
170	uint8_t cbCurPrefix;
171	/** The offset into abCurInstr of the immediate. */
172	uint8_t offCurImm;
173	/** Buffer for assembling the current instruction. */
174	uint8_t abCurInstr[23];
175
176	/** Set if the encoding can't be tested in the same ring as this test code.
177	* This is used to deal with encodings modifying SP/ESP/RSP. */
178	bool fSameRingNotOkay;
179	/** Whether to work the extended context too. */
180	bool fWorkExtCtx;
181	/** The aOperands index of the modrm.reg operand (if applicable). */
182	uint8_t iRegOp;
183	/** The aOperands index of the modrm.rm operand (if applicable). */
184	uint8_t iRmOp;
185
186	/** Operands details. */
187	struct
188	{
189	uint8_t cbOp;
190	/** BS3CG1OPLOC_XXX. */
191	uint8_t enmLocation;
192	/** The BS3CG1DST value for this field.
193	* Set to BS3CG1DST_INVALID if memory or immediate. */
194	uint8_t idxField;
195	/** Depends on enmLocation.
196	* - BS3CG1OPLOC_IMM: offset relative to start of the instruction.
197	* - BS3CG1OPLOC_MEM: offset should be subtracted from &pbDataPg[_4K].
198	* - BS3CG1OPLOC_MEM_RW: offset should be subtracted from &pbDataPg[_4K].
199	* - BS3CG1OPLOC_CTX: not used (use idxField instead).
200	*/
201	uint8_t off;
202	} aOperands[4];
203	/** @} */
204
205	/** Page to put code in. When paging is enabled, the page before and after
206	* are marked not-present. */
207	uint8_t BS3_FAR *pbCodePg;
208	/** The flat address corresponding to pbCodePg. */
209	uintptr_t uCodePgFlat;
210	/** The 16-bit address corresponding to pbCodePg if relevant for bMode. */
211	RTFAR16 CodePgFar;
212	/** The IP/EIP/RIP value for pbCodePg[0] relative to CS (bMode). */
213	uintptr_t CodePgRip;
214
215	/** Page for placing data operands in. When paging is enabled, the page before
216	* and after are marked not-present. */
217	uint8_t BS3_FAR *pbDataPg;
218	/** The flat address corresponding to pbDataPg. */
219	uintptr_t uDataPgFlat;
220	/** The 16-bit address corresponding to pbDataPg. */
221	RTFAR16 DataPgFar;
222
223	/** The name corresponding to bMode. */
224	const char BS3_FAR *pszMode;
225	/** The short name corresponding to bMode. */
226	const char BS3_FAR *pszModeShort;
227
228	/** @name Expected result (modifiable by output program).
229	* @{ */
230	/** The expected exception based on operand values or result.
231	* UINT8_MAX if no special exception expected. */
232	uint8_t bValueXcpt;
233	/** @} */
234	/** Alignment exception expected by the encoder.
235	* UINT8_MAX if no special exception expected. */
236	uint8_t bAlignmentXcpt;
237	/** Set by the encoding method to indicating invalid encoding. */
238	bool fInvalidEncoding;
239
240	/** The context we're working on. */
241	BS3REGCTX Ctx;
242	/** The trap context and frame. */
243	BS3TRAPFRAME TrapFrame;
244	/** Initial contexts, one for each ring. */
245	BS3REGCTX aInitialCtxs[4];
246
247	/** The extended context we're working on (input, expected output). */
248	PBS3EXTCTX pExtCtx;
249	/** The extended result context (analoguous to TrapFrame). */
250	PBS3EXTCTX pResultExtCtx;
251	/** The initial extended context. */
252	PBS3EXTCTX pInitialExtCtx;
253
254	/** Memory operand scratch space. */
255	union
256	{
257	uint8_t ab[128];
258	uint16_t au16[128 / sizeof(uint16_t)];
259	uint32_t au32[128 / sizeof(uint32_t)];
260	uint64_t au64[128 / sizeof(uint64_t)];
261	} MemOp;
262
263	/** Array parallel to aInitialCtxs for saving segment registers. */
264	struct
265	{
266	RTSEL ds;
267	} aSavedSegRegs[4];
268
269	} BS3CG1STATE;
270	/** Pointer to the generated test state. */
271	typedef BS3CG1STATE *PBS3CG1STATE;
272
273
274	#define BS3CG1_PF_OZ UINT16_C(0x0001)
275	#define BS3CG1_PF_AZ UINT16_C(0x0002)
276	#define BS3CG1_PF_CS UINT16_C(0x0004)
277	#define BS3CG1_PF_DS UINT16_C(0x0008)
278	#define BS3CG1_PF_ES UINT16_C(0x0010)
279	#define BS3CG1_PF_FS UINT16_C(0x0020)
280	#define BS3CG1_PF_GS UINT16_C(0x0040)
281	#define BS3CG1_PF_SS UINT16_C(0x0080)
282	#define BS3CG1_PF_SEGS (BS3CG1_PF_CS \| BS3CG1_PF_DS \| BS3CG1_PF_ES \| BS3CG1_PF_FS \| BS3CG1_PF_GS \| BS3CG1_PF_SS)
283	#define BS3CG1_PF_MEM (BS3CG1_PF_SEGS \| BS3CG1_PF_AZ)
284	#define BS3CG1_PF_LK UINT16_C(0x0100)
285	#define BS3CG1_PF_RN UINT16_C(0x0200)
286	#define BS3CG1_PF_RZ UINT16_C(0x0400)
287	#define BS3CG1_PF_W UINT16_C(0x0800) /*< REX.W /
288	#define BS3CG1_PF_R UINT16_C(0x1000) /*< REX.R /
289	#define BS3CG1_PF_B UINT16_C(0x2000) /*< REX.B /
290	#define BS3CG1_PF_X UINT16_C(0x4000) /*< REX.X /
291
292
293	/** Used in g_cbBs3Cg1DstFields to indicate that it's one of the 4 operands. */
294	#define BS3CG1DSTSIZE_OPERAND UINT8_C(255)
295	/** Used in g_cbBs3Cg1DstFields to indicate that the operand size determins
296	* the field size (2, 4, or 8). */
297	#define BS3CG1DSTSIZE_OPERAND_SIZE_GRP UINT8_C(254)
298
299
300
301	/*********************************************************************************************************************************
302	* Global Variables *
303	*********************************************************************************************************************************/
304	/** Destination field sizes indexed by bBS3CG1DST.
305	* Zero means operand size sized. */
306	static const uint8_t g_acbBs3Cg1DstFields[] =
307	{
308	/* [BS3CG1DST_INVALID] = */ BS3CG1DSTSIZE_OPERAND,
309
310	/* [BS3CG1DST_OP1] = */ BS3CG1DSTSIZE_OPERAND,
311	/* [BS3CG1DST_OP2] = */ BS3CG1DSTSIZE_OPERAND,
312	/* [BS3CG1DST_OP3] = */ BS3CG1DSTSIZE_OPERAND,
313	/* [BS3CG1DST_OP4] = */ BS3CG1DSTSIZE_OPERAND,
314	/* [BS3CG1DST_EFL] = */ 4,
315	/* [BS3CG1DST_EFL_UNDEF]=*/ 4,
316
317	/* [BS3CG1DST_AL] = */ 1,
318	/* [BS3CG1DST_CL] = */ 1,
319	/* [BS3CG1DST_DL] = */ 1,
320	/* [BS3CG1DST_BL] = */ 1,
321	/* [BS3CG1DST_AH] = */ 1,
322	/* [BS3CG1DST_CH] = */ 1,
323	/* [BS3CG1DST_DH] = */ 1,
324	/* [BS3CG1DST_BH] = */ 1,
325	/* [BS3CG1DST_SPL] = */ 1,
326	/* [BS3CG1DST_BPL] = */ 1,
327	/* [BS3CG1DST_SIL] = */ 1,
328	/* [BS3CG1DST_DIL] = */ 1,
329	/* [BS3CG1DST_R8L] = */ 1,
330	/* [BS3CG1DST_R9L] = */ 1,
331	/* [BS3CG1DST_R10L] = */ 1,
332	/* [BS3CG1DST_R11L] = */ 1,
333	/* [BS3CG1DST_R12L] = */ 1,
334	/* [BS3CG1DST_R13L] = */ 1,
335	/* [BS3CG1DST_R14L] = */ 1,
336	/* [BS3CG1DST_R15L] = */ 1,
337
338	/* [BS3CG1DST_AX] = */ 2,
339	/* [BS3CG1DST_CX] = */ 2,
340	/* [BS3CG1DST_DX] = */ 2,
341	/* [BS3CG1DST_BX] = */ 2,
342	/* [BS3CG1DST_SP] = */ 2,
343	/* [BS3CG1DST_BP] = */ 2,
344	/* [BS3CG1DST_SI] = */ 2,
345	/* [BS3CG1DST_DI] = */ 2,
346	/* [BS3CG1DST_R8W] = */ 2,
347	/* [BS3CG1DST_R9W] = */ 2,
348	/* [BS3CG1DST_R10W] = */ 2,
349	/* [BS3CG1DST_R11W] = */ 2,
350	/* [BS3CG1DST_R12W] = */ 2,
351	/* [BS3CG1DST_R13W] = */ 2,
352	/* [BS3CG1DST_R14W] = */ 2,
353	/* [BS3CG1DST_R15W] = */ 2,
354
355	/* [BS3CG1DST_EAX] = */ 4,
356	/* [BS3CG1DST_ECX] = */ 4,
357	/* [BS3CG1DST_EDX] = */ 4,
358	/* [BS3CG1DST_EBX] = */ 4,
359	/* [BS3CG1DST_ESP] = */ 4,
360	/* [BS3CG1DST_EBP] = */ 4,
361	/* [BS3CG1DST_ESI] = */ 4,
362	/* [BS3CG1DST_EDI] = */ 4,
363	/* [BS3CG1DST_R8D] = */ 4,
364	/* [BS3CG1DST_R9D] = */ 4,
365	/* [BS3CG1DST_R10D] = */ 4,
366	/* [BS3CG1DST_R11D] = */ 4,
367	/* [BS3CG1DST_R12D] = */ 4,
368	/* [BS3CG1DST_R13D] = */ 4,
369	/* [BS3CG1DST_R14D] = */ 4,
370	/* [BS3CG1DST_R15D] = */ 4,
371
372	/* [BS3CG1DST_RAX] = */ 8,
373	/* [BS3CG1DST_RCX] = */ 8,
374	/* [BS3CG1DST_RDX] = */ 8,
375	/* [BS3CG1DST_RBX] = */ 8,
376	/* [BS3CG1DST_RSP] = */ 8,
377	/* [BS3CG1DST_RBP] = */ 8,
378	/* [BS3CG1DST_RSI] = */ 8,
379	/* [BS3CG1DST_RDI] = */ 8,
380	/* [BS3CG1DST_R8] = */ 8,
381	/* [BS3CG1DST_R9] = */ 8,
382	/* [BS3CG1DST_R10] = */ 8,
383	/* [BS3CG1DST_R11] = */ 8,
384	/* [BS3CG1DST_R12] = */ 8,
385	/* [BS3CG1DST_R13] = */ 8,
386	/* [BS3CG1DST_R14] = */ 8,
387	/* [BS3CG1DST_R15] = */ 8,
388
389	/* [BS3CG1DST_OZ_RAX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
390	/* [BS3CG1DST_OZ_RCX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
391	/* [BS3CG1DST_OZ_RDX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
392	/* [BS3CG1DST_OZ_RBX] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
393	/* [BS3CG1DST_OZ_RSP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
394	/* [BS3CG1DST_OZ_RBP] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
395	/* [BS3CG1DST_OZ_RSI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
396	/* [BS3CG1DST_OZ_RDI] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
397	/* [BS3CG1DST_OZ_R8] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
398	/* [BS3CG1DST_OZ_R9] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
399	/* [BS3CG1DST_OZ_R10] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
400	/* [BS3CG1DST_OZ_R11] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
401	/* [BS3CG1DST_OZ_R12] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
402	/* [BS3CG1DST_OZ_R13] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
403	/* [BS3CG1DST_OZ_R14] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
404	/* [BS3CG1DST_OZ_R15] = */ BS3CG1DSTSIZE_OPERAND_SIZE_GRP,
405
406	/* [BS3CG1DST_CR0] = */ 4,
407	/* [BS3CG1DST_CR4] = */ 4,
408	/* [BS3CG1DST_XCR0] = */ 8,
409
410	/* [BS3CG1DST_FCW] = */ 2,
411	/* [BS3CG1DST_FSW] = */ 2,
412	/* [BS3CG1DST_FTW] = */ 2,
413	/* [BS3CG1DST_FOP] = */ 2,
414	/* [BS3CG1DST_FPUIP] = */ 2,
415	/* [BS3CG1DST_FPUCS] = */ 2,
416	/* [BS3CG1DST_FPUDP] = */ 2,
417	/* [BS3CG1DST_FPUDS] = */ 2,
418	/* [BS3CG1DST_MXCSR] = */ 4,
419	/* [BS3CG1DST_ST0] = */ 12,
420	/* [BS3CG1DST_ST1] = */ 12,
421	/* [BS3CG1DST_ST2] = */ 12,
422	/* [BS3CG1DST_ST3] = */ 12,
423	/* [BS3CG1DST_ST4] = */ 12,
424	/* [BS3CG1DST_ST5] = */ 12,
425	/* [BS3CG1DST_ST6] = */ 12,
426	/* [BS3CG1DST_ST7] = */ 12,
427	/* [BS3CG1DST_MM0] = */ 8,
428	/* [BS3CG1DST_MM1] = */ 8,
429	/* [BS3CG1DST_MM2] = */ 8,
430	/* [BS3CG1DST_MM3] = */ 8,
431	/* [BS3CG1DST_MM4] = */ 8,
432	/* [BS3CG1DST_MM5] = */ 8,
433	/* [BS3CG1DST_MM6] = */ 8,
434	/* [BS3CG1DST_MM7] = */ 8,
435	/* [BS3CG1DST_XMM0] = */ 16,
436	/* [BS3CG1DST_XMM1] = */ 16,
437	/* [BS3CG1DST_XMM2] = */ 16,
438	/* [BS3CG1DST_XMM3] = */ 16,
439	/* [BS3CG1DST_XMM4] = */ 16,
440	/* [BS3CG1DST_XMM5] = */ 16,
441	/* [BS3CG1DST_XMM6] = */ 16,
442	/* [BS3CG1DST_XMM7] = */ 16,
443	/* [BS3CG1DST_XMM8] = */ 16,
444	/* [BS3CG1DST_XMM9] = */ 16,
445	/* [BS3CG1DST_XMM10] = */ 16,
446	/* [BS3CG1DST_XMM11] = */ 16,
447	/* [BS3CG1DST_XMM12] = */ 16,
448	/* [BS3CG1DST_XMM13] = */ 16,
449	/* [BS3CG1DST_XMM14] = */ 16,
450	/* [BS3CG1DST_XMM15] = */ 16,
451	/* [BS3CG1DST_XMM0_LO] = */ 8,
452	/* [BS3CG1DST_XMM1_LO] = */ 8,
453	/* [BS3CG1DST_XMM2_LO] = */ 8,
454	/* [BS3CG1DST_XMM3_LO] = */ 8,
455	/* [BS3CG1DST_XMM4_LO] = */ 8,
456	/* [BS3CG1DST_XMM5_LO] = */ 8,
457	/* [BS3CG1DST_XMM6_LO] = */ 8,
458	/* [BS3CG1DST_XMM7_LO] = */ 8,
459	/* [BS3CG1DST_XMM8_LO] = */ 8,
460	/* [BS3CG1DST_XMM9_LO] = */ 8,
461	/* [BS3CG1DST_XMM10_LO] = */ 8,
462	/* [BS3CG1DST_XMM11_LO] = */ 8,
463	/* [BS3CG1DST_XMM12_LO] = */ 8,
464	/* [BS3CG1DST_XMM13_LO] = */ 8,
465	/* [BS3CG1DST_XMM14_LO] = */ 8,
466	/* [BS3CG1DST_XMM15_LO] = */ 8,
467	/* [BS3CG1DST_XMM0_HI] = */ 8,
468	/* [BS3CG1DST_XMM1_HI] = */ 8,
469	/* [BS3CG1DST_XMM2_HI] = */ 8,
470	/* [BS3CG1DST_XMM3_HI] = */ 8,
471	/* [BS3CG1DST_XMM4_HI] = */ 8,
472	/* [BS3CG1DST_XMM5_HI] = */ 8,
473	/* [BS3CG1DST_XMM6_HI] = */ 8,
474	/* [BS3CG1DST_XMM7_HI] = */ 8,
475	/* [BS3CG1DST_XMM8_HI] = */ 8,
476	/* [BS3CG1DST_XMM9_HI] = */ 8,
477	/* [BS3CG1DST_XMM10_HI] = */ 8,
478	/* [BS3CG1DST_XMM11_HI] = */ 8,
479	/* [BS3CG1DST_XMM12_HI] = */ 8,
480	/* [BS3CG1DST_XMM13_HI] = */ 8,
481	/* [BS3CG1DST_XMM14_HI] = */ 8,
482	/* [BS3CG1DST_XMM15_HI] = */ 8,
483	/* [BS3CG1DST_XMM0_LO_ZX] = */ 8,
484	/* [BS3CG1DST_XMM1_LO_ZX] = */ 8,
485	/* [BS3CG1DST_XMM2_LO_ZX] = */ 8,
486	/* [BS3CG1DST_XMM3_LO_ZX] = */ 8,
487	/* [BS3CG1DST_XMM4_LO_ZX] = */ 8,
488	/* [BS3CG1DST_XMM5_LO_ZX] = */ 8,
489	/* [BS3CG1DST_XMM6_LO_ZX] = */ 8,
490	/* [BS3CG1DST_XMM7_LO_ZX] = */ 8,
491	/* [BS3CG1DST_XMM8_LO_ZX] = */ 8,
492	/* [BS3CG1DST_XMM9_LO_ZX] = */ 8,
493	/* [BS3CG1DST_XMM10_LO_ZX] = */ 8,
494	/* [BS3CG1DST_XMM11_LO_ZX] = */ 8,
495	/* [BS3CG1DST_XMM12_LO_ZX] = */ 8,
496	/* [BS3CG1DST_XMM13_LO_ZX] = */ 8,
497	/* [BS3CG1DST_XMM14_LO_ZX] = */ 8,
498	/* [BS3CG1DST_XMM15_LO_ZX] = */ 8,
499	/* [BS3CG1DST_XMM0_DW0] = */ 4,
500	/* [BS3CG1DST_XMM1_DW0] = */ 4,
501	/* [BS3CG1DST_XMM2_DW0] = */ 4,
502	/* [BS3CG1DST_XMM3_DW0] = */ 4,
503	/* [BS3CG1DST_XMM4_DW0] = */ 4,
504	/* [BS3CG1DST_XMM5_DW0] = */ 4,
505	/* [BS3CG1DST_XMM6_DW0] = */ 4,
506	/* [BS3CG1DST_XMM7_DW0] = */ 4,
507	/* [BS3CG1DST_XMM8_DW0] = */ 4,
508	/* [BS3CG1DST_XMM9_DW0] = */ 4,
509	/* [BS3CG1DST_XMM10_DW0] = */ 4,
510	/* [BS3CG1DST_XMM11_DW0] = */ 4,
511	/* [BS3CG1DST_XMM12_DW0] = */ 4,
512	/* [BS3CG1DST_XMM13_DW0] = */ 4,
513	/* [BS3CG1DST_XMM14_DW0] = */ 4,
514	/* [BS3CG1DST_XMM15_DW0] = */ 4,
515	/* [BS3CG1DST_XMM0_DW0_ZX] = */ 4,
516	/* [BS3CG1DST_XMM1_DW0_ZX] = */ 4,
517	/* [BS3CG1DST_XMM2_DW0_ZX] = */ 4,
518	/* [BS3CG1DST_XMM3_DW0_ZX] = */ 4,
519	/* [BS3CG1DST_XMM4_DW0_ZX] = */ 4,
520	/* [BS3CG1DST_XMM5_DW0_ZX] = */ 4,
521	/* [BS3CG1DST_XMM6_DW0_ZX] = */ 4,
522	/* [BS3CG1DST_XMM7_DW0_ZX] = */ 4,
523	/* [BS3CG1DST_XMM8_DW0_ZX] = */ 4,
524	/* [BS3CG1DST_XMM9_DW0_ZX] = */ 4,
525	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ 4,
526	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ 4,
527	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ 4,
528	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ 4,
529	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ 4,
530	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ 4,
531	/* [BS3CG1DST_YMM0] = */ 32,
532	/* [BS3CG1DST_YMM1] = */ 32,
533	/* [BS3CG1DST_YMM2] = */ 32,
534	/* [BS3CG1DST_YMM3] = */ 32,
535	/* [BS3CG1DST_YMM4] = */ 32,
536	/* [BS3CG1DST_YMM5] = */ 32,
537	/* [BS3CG1DST_YMM6] = */ 32,
538	/* [BS3CG1DST_YMM7] = */ 32,
539	/* [BS3CG1DST_YMM8] = */ 32,
540	/* [BS3CG1DST_YMM9] = */ 32,
541	/* [BS3CG1DST_YMM10] = */ 32,
542	/* [BS3CG1DST_YMM11] = */ 32,
543	/* [BS3CG1DST_YMM12] = */ 32,
544	/* [BS3CG1DST_YMM13] = */ 32,
545	/* [BS3CG1DST_YMM14] = */ 32,
546	/* [BS3CG1DST_YMM15] = */ 32,
547
548	/* [BS3CG1DST_VALUE_XCPT] = */ 1,
549	};
550	AssertCompile(RT_ELEMENTS(g_acbBs3Cg1DstFields) == BS3CG1DST_END);
551
552	/** Destination field offset indexed by bBS3CG1DST.
553	* Zero means operand size sized. */
554	static const unsigned g_aoffBs3Cg1DstFields[] =
555	{
556	/* [BS3CG1DST_INVALID] = */ ~0U,
557	/* [BS3CG1DST_OP1] = */ ~0U,
558	/* [BS3CG1DST_OP2] = */ ~0U,
559	/* [BS3CG1DST_OP3] = */ ~0U,
560	/* [BS3CG1DST_OP4] = */ ~0U,
561	/* [BS3CG1DST_EFL] = */ RT_OFFSETOF(BS3REGCTX, rflags),
562	/* [BS3CG1DST_EFL_UNDEF]=/ ~0, / special field */
563
564	/* [BS3CG1DST_AL] = */ RT_OFFSETOF(BS3REGCTX, rax.u8),
565	/* [BS3CG1DST_CL] = */ RT_OFFSETOF(BS3REGCTX, rcx.u8),
566	/* [BS3CG1DST_DL] = */ RT_OFFSETOF(BS3REGCTX, rdx.u8),
567	/* [BS3CG1DST_BL] = */ RT_OFFSETOF(BS3REGCTX, rbx.u8),
568	/* [BS3CG1DST_AH] = */ RT_OFFSETOF(BS3REGCTX, rax.b.bHi),
569	/* [BS3CG1DST_CH] = */ RT_OFFSETOF(BS3REGCTX, rcx.b.bHi),
570	/* [BS3CG1DST_DH] = */ RT_OFFSETOF(BS3REGCTX, rdx.b.bHi),
571	/* [BS3CG1DST_BH] = */ RT_OFFSETOF(BS3REGCTX, rbx.b.bHi),
572	/* [BS3CG1DST_SPL] = */ RT_OFFSETOF(BS3REGCTX, rsp.u8),
573	/* [BS3CG1DST_BPL] = */ RT_OFFSETOF(BS3REGCTX, rbp.u8),
574	/* [BS3CG1DST_SIL] = */ RT_OFFSETOF(BS3REGCTX, rsi.u8),
575	/* [BS3CG1DST_DIL] = */ RT_OFFSETOF(BS3REGCTX, rdi.u8),
576	/* [BS3CG1DST_R8L] = */ RT_OFFSETOF(BS3REGCTX, r8.u8),
577	/* [BS3CG1DST_R9L] = */ RT_OFFSETOF(BS3REGCTX, r9.u8),
578	/* [BS3CG1DST_R10L] = */ RT_OFFSETOF(BS3REGCTX, r10.u8),
579	/* [BS3CG1DST_R11L] = */ RT_OFFSETOF(BS3REGCTX, r11.u8),
580	/* [BS3CG1DST_R12L] = */ RT_OFFSETOF(BS3REGCTX, r12.u8),
581	/* [BS3CG1DST_R13L] = */ RT_OFFSETOF(BS3REGCTX, r13.u8),
582	/* [BS3CG1DST_R14L] = */ RT_OFFSETOF(BS3REGCTX, r14.u8),
583	/* [BS3CG1DST_R15L] = */ RT_OFFSETOF(BS3REGCTX, r15.u8),
584
585	/* [BS3CG1DST_AX] = */ RT_OFFSETOF(BS3REGCTX, rax.u16),
586	/* [BS3CG1DST_CX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u16),
587	/* [BS3CG1DST_DX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u16),
588	/* [BS3CG1DST_BX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u16),
589	/* [BS3CG1DST_SP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u16),
590	/* [BS3CG1DST_BP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u16),
591	/* [BS3CG1DST_SI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u16),
592	/* [BS3CG1DST_DI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u16),
593	/* [BS3CG1DST_R8W] = */ RT_OFFSETOF(BS3REGCTX, r8.u16),
594	/* [BS3CG1DST_R9W] = */ RT_OFFSETOF(BS3REGCTX, r9.u16),
595	/* [BS3CG1DST_R10W] = */ RT_OFFSETOF(BS3REGCTX, r10.u16),
596	/* [BS3CG1DST_R11W] = */ RT_OFFSETOF(BS3REGCTX, r11.u16),
597	/* [BS3CG1DST_R12W] = */ RT_OFFSETOF(BS3REGCTX, r12.u16),
598	/* [BS3CG1DST_R13W] = */ RT_OFFSETOF(BS3REGCTX, r13.u16),
599	/* [BS3CG1DST_R14W] = */ RT_OFFSETOF(BS3REGCTX, r14.u16),
600	/* [BS3CG1DST_R15W] = */ RT_OFFSETOF(BS3REGCTX, r15.u16),
601
602	/* [BS3CG1DST_EAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u32),
603	/* [BS3CG1DST_ECX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u32),
604	/* [BS3CG1DST_EDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u32),
605	/* [BS3CG1DST_EBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u32),
606	/* [BS3CG1DST_ESP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u32),
607	/* [BS3CG1DST_EBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u32),
608	/* [BS3CG1DST_ESI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u32),
609	/* [BS3CG1DST_EDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u32),
610	/* [BS3CG1DST_R8D] = */ RT_OFFSETOF(BS3REGCTX, r8.u32),
611	/* [BS3CG1DST_R9D] = */ RT_OFFSETOF(BS3REGCTX, r9.u32),
612	/* [BS3CG1DST_R10D] = */ RT_OFFSETOF(BS3REGCTX, r10.u32),
613	/* [BS3CG1DST_R11D] = */ RT_OFFSETOF(BS3REGCTX, r11.u32),
614	/* [BS3CG1DST_R12D] = */ RT_OFFSETOF(BS3REGCTX, r12.u32),
615	/* [BS3CG1DST_R13D] = */ RT_OFFSETOF(BS3REGCTX, r13.u32),
616	/* [BS3CG1DST_R14D] = */ RT_OFFSETOF(BS3REGCTX, r14.u32),
617	/* [BS3CG1DST_R15D] = */ RT_OFFSETOF(BS3REGCTX, r15.u32),
618
619	/* [BS3CG1DST_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax.u64),
620	/* [BS3CG1DST_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx.u64),
621	/* [BS3CG1DST_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx.u64),
622	/* [BS3CG1DST_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx.u64),
623	/* [BS3CG1DST_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp.u64),
624	/* [BS3CG1DST_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp.u64),
625	/* [BS3CG1DST_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi.u64),
626	/* [BS3CG1DST_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi.u64),
627	/* [BS3CG1DST_R8] = */ RT_OFFSETOF(BS3REGCTX, r8.u64),
628	/* [BS3CG1DST_R9] = */ RT_OFFSETOF(BS3REGCTX, r9.u64),
629	/* [BS3CG1DST_R10] = */ RT_OFFSETOF(BS3REGCTX, r10.u64),
630	/* [BS3CG1DST_R11] = */ RT_OFFSETOF(BS3REGCTX, r11.u64),
631	/* [BS3CG1DST_R12] = */ RT_OFFSETOF(BS3REGCTX, r12.u64),
632	/* [BS3CG1DST_R13] = */ RT_OFFSETOF(BS3REGCTX, r13.u64),
633	/* [BS3CG1DST_R14] = */ RT_OFFSETOF(BS3REGCTX, r14.u64),
634	/* [BS3CG1DST_R15] = */ RT_OFFSETOF(BS3REGCTX, r15.u64),
635
636	/* [BS3CG1DST_OZ_RAX] = */ RT_OFFSETOF(BS3REGCTX, rax),
637	/* [BS3CG1DST_OZ_RCX] = */ RT_OFFSETOF(BS3REGCTX, rcx),
638	/* [BS3CG1DST_OZ_RDX] = */ RT_OFFSETOF(BS3REGCTX, rdx),
639	/* [BS3CG1DST_OZ_RBX] = */ RT_OFFSETOF(BS3REGCTX, rbx),
640	/* [BS3CG1DST_OZ_RSP] = */ RT_OFFSETOF(BS3REGCTX, rsp),
641	/* [BS3CG1DST_OZ_RBP] = */ RT_OFFSETOF(BS3REGCTX, rbp),
642	/* [BS3CG1DST_OZ_RSI] = */ RT_OFFSETOF(BS3REGCTX, rsi),
643	/* [BS3CG1DST_OZ_RDI] = */ RT_OFFSETOF(BS3REGCTX, rdi),
644	/* [BS3CG1DST_OZ_R8] = */ RT_OFFSETOF(BS3REGCTX, r8),
645	/* [BS3CG1DST_OZ_R9] = */ RT_OFFSETOF(BS3REGCTX, r9),
646	/* [BS3CG1DST_OZ_R10] = */ RT_OFFSETOF(BS3REGCTX, r10),
647	/* [BS3CG1DST_OZ_R11] = */ RT_OFFSETOF(BS3REGCTX, r11),
648	/* [BS3CG1DST_OZ_R12] = */ RT_OFFSETOF(BS3REGCTX, r12),
649	/* [BS3CG1DST_OZ_R13] = */ RT_OFFSETOF(BS3REGCTX, r13),
650	/* [BS3CG1DST_OZ_R14] = */ RT_OFFSETOF(BS3REGCTX, r14),
651	/* [BS3CG1DST_OZ_R15] = */ RT_OFFSETOF(BS3REGCTX, r15),
652
653	/* [BS3CG1DST_CR0] = */ RT_OFFSETOF(BS3REGCTX, cr0),
654	/* [BS3CG1DST_CR4] = */ RT_OFFSETOF(BS3REGCTX, cr4),
655	/* [BS3CG1DST_XCR0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, fXcr0Saved),
656
657	/* [BS3CG1DST_FCW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FCW),
658	/* [BS3CG1DST_FSW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FSW),
659	/* [BS3CG1DST_FTW] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FTW),
660	/* [BS3CG1DST_FOP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FOP),
661	/* [BS3CG1DST_FPUIP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUIP),
662	/* [BS3CG1DST_FPUCS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.CS),
663	/* [BS3CG1DST_FPUDP] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.FPUDP),
664	/* [BS3CG1DST_FPUDS] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.DS),
665	/* [BS3CG1DST_MXCSR] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.MXCSR),
666	/* [BS3CG1DST_ST0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
667	/* [BS3CG1DST_ST1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
668	/* [BS3CG1DST_ST2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
669	/* [BS3CG1DST_ST3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
670	/* [BS3CG1DST_ST4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
671	/* [BS3CG1DST_ST5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
672	/* [BS3CG1DST_ST6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
673	/* [BS3CG1DST_ST7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
674	/* [BS3CG1DST_MM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[0]),
675	/* [BS3CG1DST_MM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[1]),
676	/* [BS3CG1DST_MM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[2]),
677	/* [BS3CG1DST_MM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[3]),
678	/* [BS3CG1DST_MM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[4]),
679	/* [BS3CG1DST_MM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[5]),
680	/* [BS3CG1DST_MM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[6]),
681	/* [BS3CG1DST_MM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aRegs[7]),
682
683	/* [BS3CG1DST_XMM0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
684	/* [BS3CG1DST_XMM1] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
685	/* [BS3CG1DST_XMM2] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
686	/* [BS3CG1DST_XMM3] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
687	/* [BS3CG1DST_XMM4] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
688	/* [BS3CG1DST_XMM5] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
689	/* [BS3CG1DST_XMM6] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
690	/* [BS3CG1DST_XMM7] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
691	/* [BS3CG1DST_XMM8] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
692	/* [BS3CG1DST_XMM9] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
693	/* [BS3CG1DST_XMM10] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
694	/* [BS3CG1DST_XMM11] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
695	/* [BS3CG1DST_XMM12] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
696	/* [BS3CG1DST_XMM13] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
697	/* [BS3CG1DST_XMM14] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
698	/* [BS3CG1DST_XMM15] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
699	/* [BS3CG1DST_XMM0_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
700	/* [BS3CG1DST_XMM1_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
701	/* [BS3CG1DST_XMM2_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
702	/* [BS3CG1DST_XMM3_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
703	/* [BS3CG1DST_XMM4_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
704	/* [BS3CG1DST_XMM5_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
705	/* [BS3CG1DST_XMM6_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
706	/* [BS3CG1DST_XMM7_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
707	/* [BS3CG1DST_XMM8_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
708	/* [BS3CG1DST_XMM9_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
709	/* [BS3CG1DST_XMM10_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
710	/* [BS3CG1DST_XMM11_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
711	/* [BS3CG1DST_XMM12_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
712	/* [BS3CG1DST_XMM13_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
713	/* [BS3CG1DST_XMM14_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
714	/* [BS3CG1DST_XMM15_LO] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
715	/* [BS3CG1DST_XMM0_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]) + sizeof(uint64_t),
716	/* [BS3CG1DST_XMM1_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]) + sizeof(uint64_t),
717	/* [BS3CG1DST_XMM2_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]) + sizeof(uint64_t),
718	/* [BS3CG1DST_XMM3_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]) + sizeof(uint64_t),
719	/* [BS3CG1DST_XMM4_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]) + sizeof(uint64_t),
720	/* [BS3CG1DST_XMM5_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]) + sizeof(uint64_t),
721	/* [BS3CG1DST_XMM6_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]) + sizeof(uint64_t),
722	/* [BS3CG1DST_XMM7_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]) + sizeof(uint64_t),
723	/* [BS3CG1DST_XMM8_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]) + sizeof(uint64_t),
724	/* [BS3CG1DST_XMM9_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]) + sizeof(uint64_t),
725	/* [BS3CG1DST_XMM10_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]) + sizeof(uint64_t),
726	/* [BS3CG1DST_XMM11_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]) + sizeof(uint64_t),
727	/* [BS3CG1DST_XMM12_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]) + sizeof(uint64_t),
728	/* [BS3CG1DST_XMM13_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]) + sizeof(uint64_t),
729	/* [BS3CG1DST_XMM14_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]) + sizeof(uint64_t),
730	/* [BS3CG1DST_XMM15_HI] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) + sizeof(uint64_t),
731	/* [BS3CG1DST_XMM0_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
732	/* [BS3CG1DST_XMM1_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
733	/* [BS3CG1DST_XMM2_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
734	/* [BS3CG1DST_XMM3_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
735	/* [BS3CG1DST_XMM4_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
736	/* [BS3CG1DST_XMM5_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
737	/* [BS3CG1DST_XMM6_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
738	/* [BS3CG1DST_XMM7_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
739	/* [BS3CG1DST_XMM8_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
740	/* [BS3CG1DST_XMM9_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
741	/* [BS3CG1DST_XMM10_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
742	/* [BS3CG1DST_XMM11_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
743	/* [BS3CG1DST_XMM12_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
744	/* [BS3CG1DST_XMM13_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
745	/* [BS3CG1DST_XMM14_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
746	/* [BS3CG1DST_XMM15_LO_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
747	/* [BS3CG1DST_XMM0_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
748	/* [BS3CG1DST_XMM1_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
749	/* [BS3CG1DST_XMM2_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
750	/* [BS3CG1DST_XMM3_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
751	/* [BS3CG1DST_XMM4_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
752	/* [BS3CG1DST_XMM5_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
753	/* [BS3CG1DST_XMM6_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
754	/* [BS3CG1DST_XMM7_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
755	/* [BS3CG1DST_XMM8_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
756	/* [BS3CG1DST_XMM9_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
757	/* [BS3CG1DST_XMM10_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
758	/* [BS3CG1DST_XMM11_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
759	/* [BS3CG1DST_XMM12_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
760	/* [BS3CG1DST_XMM13_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
761	/* [BS3CG1DST_XMM14_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
762	/* [BS3CG1DST_XMM15_DW0] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
763	/* [BS3CG1DST_XMM0_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[0]),
764	/* [BS3CG1DST_XMM1_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[1]),
765	/* [BS3CG1DST_XMM2_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[2]),
766	/* [BS3CG1DST_XMM3_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[3]),
767	/* [BS3CG1DST_XMM4_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[4]),
768	/* [BS3CG1DST_XMM5_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[5]),
769	/* [BS3CG1DST_XMM6_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[6]),
770	/* [BS3CG1DST_XMM7_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[7]),
771	/* [BS3CG1DST_XMM8_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[8]),
772	/* [BS3CG1DST_XMM9_DW0_ZX] = */ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[9]),
773	/* [BS3CG1DST_XMM10_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[10]),
774	/* [BS3CG1DST_XMM11_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[11]),
775	/* [BS3CG1DST_XMM12_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[12]),
776	/* [BS3CG1DST_XMM13_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[13]),
777	/* [BS3CG1DST_XMM14_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[14]),
778	/* [BS3CG1DST_XMM15_DW0_ZX] =*/ sizeof(BS3REGCTX) + RT_OFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]),
779
780	/* [BS3CG1DST_YMM0] = */ ~0U,
781	/* [BS3CG1DST_YMM1] = */ ~0U,
782	/* [BS3CG1DST_YMM2] = */ ~0U,
783	/* [BS3CG1DST_YMM3] = */ ~0U,
784	/* [BS3CG1DST_YMM4] = */ ~0U,
785	/* [BS3CG1DST_YMM5] = */ ~0U,
786	/* [BS3CG1DST_YMM6] = */ ~0U,
787	/* [BS3CG1DST_YMM7] = */ ~0U,
788	/* [BS3CG1DST_YMM8] = */ ~0U,
789	/* [BS3CG1DST_YMM9] = */ ~0U,
790	/* [BS3CG1DST_YMM10] = */ ~0U,
791	/* [BS3CG1DST_YMM11] = */ ~0U,
792	/* [BS3CG1DST_YMM12] = */ ~0U,
793	/* [BS3CG1DST_YMM13] = */ ~0U,
794	/* [BS3CG1DST_YMM14] = */ ~0U,
795	/* [BS3CG1DST_YMM15] = */ ~0U,
796
797	/* [BS3CG1DST_VALUE_XCPT] = */ ~0U,
798	};
799	AssertCompile(RT_ELEMENTS(g_aoffBs3Cg1DstFields) == BS3CG1DST_END);
800
801	#ifdef BS3CG1_DEBUG_CTX_MOD
802	/** Destination field names. */
803	static const struct { char sz[12]; } g_aszBs3Cg1DstFields[] =
804	{
805	{ "INVALID" },
806	{ "OP1" },
807	{ "OP2" },
808	{ "OP3" },
809	{ "OP4" },
810	{ "EFL" },
811	{ "EFL_UND" },
812
813	{ "AL" },
814	{ "CL" },
815	{ "DL" },
816	{ "BL" },
817	{ "AH" },
818	{ "CH" },
819	{ "DH" },
820	{ "BH" },
821	{ "SPL" },
822	{ "BPL" },
823	{ "SIL" },
824	{ "DIL" },
825	{ "R8L" },
826	{ "R9L" },
827	{ "R10L" },
828	{ "R11L" },
829	{ "R12L" },
830	{ "R13L" },
831	{ "R14L" },
832	{ "R15L" },
833
834	{ "AX" },
835	{ "CX" },
836	{ "DX" },
837	{ "BX" },
838	{ "SP" },
839	{ "BP" },
840	{ "SI" },
841	{ "DI" },
842	{ "R8W" },
843	{ "R9W" },
844	{ "R10W" },
845	{ "R11W" },
846	{ "R12W" },
847	{ "R13W" },
848	{ "R14W" },
849	{ "R15W" },
850
851	{ "EAX" },
852	{ "ECX" },
853	{ "EDX" },
854	{ "EBX" },
855	{ "ESP" },
856	{ "EBP" },
857	{ "ESI" },
858	{ "EDI" },
859	{ "R8D" },
860	{ "R9D" },
861	{ "R10D" },
862	{ "R11D" },
863	{ "R12D" },
864	{ "R13D" },
865	{ "R14D" },
866	{ "R15D" },
867
868	{ "RAX" },
869	{ "RCX" },
870	{ "RDX" },
871	{ "RBX" },
872	{ "RSP" },
873	{ "RBP" },
874	{ "RSI" },
875	{ "RDI" },
876	{ "R8" },
877	{ "R9" },
878	{ "R10" },
879	{ "R11" },
880	{ "R12" },
881	{ "R13" },
882	{ "R14" },
883	{ "R15" },
884
885	{ "OZ_RAX" },
886	{ "OZ_RCX" },
887	{ "OZ_RDX" },
888	{ "OZ_RBX" },
889	{ "OZ_RSP" },
890	{ "OZ_RBP" },
891	{ "OZ_RSI" },
892	{ "OZ_RDI" },
893	{ "OZ_R8" },
894	{ "OZ_R9" },
895	{ "OZ_R10" },
896	{ "OZ_R11" },
897	{ "OZ_R12" },
898	{ "OZ_R13" },
899	{ "OZ_R14" },
900	{ "OZ_R15" },
901
902	{ "CR0" },
903	{ "CR4" },
904	{ "XCR0" },
905
906	{ "FCW" },
907	{ "FSW" },
908	{ "FTW" },
909	{ "FOP" },
910	{ "FPUIP" },
911	{ "FPUCS" },
912	{ "FPUDP" },
913	{ "FPUDS" },
914	{ "MXCSR" },
915	{ "ST0" },
916	{ "ST1" },
917	{ "ST2" },
918	{ "ST3" },
919	{ "ST4" },
920	{ "ST5" },
921	{ "ST6" },
922	{ "ST7" },
923	{ "MM0" },
924	{ "MM1" },
925	{ "MM2" },
926	{ "MM3" },
927	{ "MM4" },
928	{ "MM5" },
929	{ "MM6" },
930	{ "MM7" },
931	{ "XMM0" },
932	{ "XMM1" },
933	{ "XMM2" },
934	{ "XMM3" },
935	{ "XMM4" },
936	{ "XMM5" },
937	{ "XMM6" },
938	{ "XMM7" },
939	{ "XMM8" },
940	{ "XMM9" },
941	{ "XMM10" },
942	{ "XMM11" },
943	{ "XMM12" },
944	{ "XMM13" },
945	{ "XMM14" },
946	{ "XMM15" },
947	{ "XMM0_LO" },
948	{ "XMM1_LO" },
949	{ "XMM2_LO" },
950	{ "XMM3_LO" },
951	{ "XMM4_LO" },
952	{ "XMM5_LO" },
953	{ "XMM6_LO" },
954	{ "XMM7_LO" },
955	{ "XMM8_LO" },
956	{ "XMM9_LO" },
957	{ "XMM10_LO" },
958	{ "XMM11_LO" },
959	{ "XMM12_LO" },
960	{ "XMM13_LO" },
961	{ "XMM14_LO" },
962	{ "XMM15_LO" },
963	{ "XMM0_HI" },
964	{ "XMM1_HI" },
965	{ "XMM2_HI" },
966	{ "XMM3_HI" },
967	{ "XMM4_HI" },
968	{ "XMM5_HI" },
969	{ "XMM6_HI" },
970	{ "XMM7_HI" },
971	{ "XMM8_HI" },
972	{ "XMM9_HI" },
973	{ "XMM10_HI" },
974	{ "XMM11_HI" },
975	{ "XMM12_HI" },
976	{ "XMM13_HI" },
977	{ "XMM14_HI" },
978	{ "XMM15_HI" },
979	{ "XMM0_LO_ZX" },
980	{ "XMM1_LO_ZX" },
981	{ "XMM2_LO_ZX" },
982	{ "XMM3_LO_ZX" },
983	{ "XMM4_LO_ZX" },
984	{ "XMM5_LO_ZX" },
985	{ "XMM6_LO_ZX" },
986	{ "XMM7_LO_ZX" },
987	{ "XMM8_LO_ZX" },
988	{ "XMM9_LO_ZX" },
989	{ "XMM10_LO_ZX" },
990	{ "XMM11_LO_ZX" },
991	{ "XMM12_LO_ZX" },
992	{ "XMM13_LO_ZX" },
993	{ "XMM14_LO_ZX" },
994	{ "XMM15_LO_ZX" },
995	{ "XMM0_DW0" },
996	{ "XMM1_DW0" },
997	{ "XMM2_DW0" },
998	{ "XMM3_DW0" },
999	{ "XMM4_DW0" },
1000	{ "XMM5_DW0" },
1001	{ "XMM6_DW0" },
1002	{ "XMM7_DW0" },
1003	{ "XMM8_DW0" },
1004	{ "XMM9_DW0" },
1005	{ "XMM10_DW0" },
1006	{ "XMM11_DW0" },
1007	{ "XMM12_DW0" },
1008	{ "XMM13_DW0" },
1009	{ "XMM14_DW0" },
1010	{ "XMM15_DW0" },
1011	{ "XMM0_DW0_ZX" },
1012	{ "XMM1_DW0_ZX" },
1013	{ "XMM2_DW0_ZX" },
1014	{ "XMM3_DW0_ZX" },
1015	{ "XMM4_DW0_ZX" },
1016	{ "XMM5_DW0_ZX" },
1017	{ "XMM6_DW0_ZX" },
1018	{ "XMM7_DW0_ZX" },
1019	{ "XMM8_DW0_ZX" },
1020	{ "XMM9_DW0_ZX" },
1021	{ "XMM10_DW0_ZX" },
1022	{ "XMM11_DW0_ZX" },
1023	{ "XMM12_DW0_ZX" },
1024	{ "XMM13_DW0_ZX" },
1025	{ "XMM14_DW0_ZX" },
1026	{ "XMM15_DW0_ZX" },
1027	{ "YMM0" },
1028	{ "YMM1" },
1029	{ "YMM2" },
1030	{ "YMM3" },
1031	{ "YMM4" },
1032	{ "YMM5" },
1033	{ "YMM6" },
1034	{ "YMM7" },
1035	{ "YMM8" },
1036	{ "YMM9" },
1037	{ "YMM10" },
1038	{ "YMM11" },
1039	{ "YMM12" },
1040	{ "YMM13" },
1041	{ "YMM14" },
1042	{ "YMM15" },
1043
1044	{ "VALXCPT" },
1045	};
1046	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) >= BS3CG1DST_END);
1047	AssertCompile(RT_ELEMENTS(g_aszBs3Cg1DstFields) == BS3CG1DST_END);
1048
1049	#endif
1050
1051	#if 0
1052	static const struct
1053	{
1054	uint8_t cbPrefixes;
1055	uint8_t abPrefixes[14];
1056	uint16_t fEffective;
1057	} g_aPrefixVariations[] =
1058	{
1059	{ 0, { 0x00 }, BS3CG1_PF_NONE },
1060
1061	{ 1, { P_OZ }, BS3CG1_PF_OZ },
1062	{ 1, { P_CS }, BS3CG1_PF_CS },
1063	{ 1, { P_DS }, BS3CG1_PF_DS },
1064	{ 1, { P_ES }, BS3CG1_PF_ES },
1065	{ 1, { P_FS }, BS3CG1_PF_FS },
1066	{ 1, { P_GS }, BS3CG1_PF_GS },
1067	{ 1, { P_SS }, BS3CG1_PF_SS },
1068	{ 1, { P_LK }, BS3CG1_PF_LK },
1069
1070	{ 2, { P_CS, P_OZ, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1071	{ 2, { P_DS, P_OZ, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1072	{ 2, { P_ES, P_OZ, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1073	{ 2, { P_FS, P_OZ, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1074	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1075	{ 2, { P_GS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1076	{ 2, { P_SS, P_OZ, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1077
1078	{ 2, { P_OZ, P_CS, }, BS3CG1_PF_CS \| BS3CFG1_PF_OZ },
1079	{ 2, { P_OZ, P_DS, }, BS3CG1_PF_DS \| BS3CFG1_PF_OZ },
1080	{ 2, { P_OZ, P_ES, }, BS3CG1_PF_ES \| BS3CFG1_PF_OZ },
1081	{ 2, { P_OZ, P_FS, }, BS3CG1_PF_FS \| BS3CFG1_PF_OZ },
1082	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_GS \| BS3CFG1_PF_OZ },
1083	{ 2, { P_OZ, P_GS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1084	{ 2, { P_OZ, P_SS, }, BS3CG1_PF_SS \| BS3CFG1_PF_OZ },
1085	};
1086
1087	static const uint16_t g_afPfxKindToIgnoredFlags[BS3CG1PFXKIND_END] =
1088	{
1089	/* [BS3CG1PFXKIND_INVALID] = */ UINT16_MAX,
1090	/* [BS3CG1PFXKIND_MODRM] = */ 0,
1091	/* [BS3CG1PFXKIND_MODRM_NO_OP_SIZES] = */ BS3CG1_PF_OZ \| BS3CG1_PF_W,
1092	};
1093
1094	#endif
1095
1096
1097	/**
1098	* Checks if >= 16 byte SSE/AVX alignment are exempted for the exception type.
1099	*
1100	* @returns true / false.
1101	* @param enmXcptType The type to check.
1102	*/
1103	static bool BS3_NEAR_CODE Bs3Cg1XcptTypeIsUnaligned(BS3CG1XCPTTYPE enmXcptType)
1104	{
1105	switch (enmXcptType)
1106	{
1107	case BS3CG1XCPTTYPE_4UA:
1108	case BS3CG1XCPTTYPE_5:
1109	return true;
1110	default:
1111	return false;
1112	}
1113	}
1114
1115
1116	/**
1117	* Inserts a 2-byte VEX prefix.
1118	*
1119	* @returns New offDst value.
1120	* @param pThis The state.
1121	* @param offDst The current instruction offset.
1122	* @param uVexL The VEX.L value.
1123	* @param uVexV The VEX.V value (caller inverted it already).
1124	* @param uVexR The VEX.R value (caller inverted it already).
1125	*/
1126	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex2bPrefix(PBS3CG1STATE pThis, unsigned offDst,
1127	uint8_t uVexV, uint8_t uVexL, uint8_t uVexR)
1128	{
1129	uint8_t b = uVexR << 7;
1130	b \|= uVexV << 3;
1131	b \|= uVexL << 2;
1132	switch (pThis->enmPrefixKind)
1133	{
1134	case BS3CG1PFXKIND_NO_F2_F3_66: b \|= 0; break;
1135	case BS3CG1PFXKIND_REQ_66: b \|= 1; break;
1136	case BS3CG1PFXKIND_REQ_F3: b \|= 2; break;
1137	case BS3CG1PFXKIND_REQ_F2: b \|= 3; break;
1138	default:
1139	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n");
1140	break;
1141	}
1142
1143	pThis->abCurInstr[offDst] = 0xc5; /* vex2 */
1144	pThis->abCurInstr[offDst + 1] = b;
1145	return offDst + 2;
1146	}
1147
1148
1149	/**
1150	* Inserts a 3-byte VEX prefix.
1151	*
1152	* @returns New offDst value.
1153	* @param pThis The state.
1154	* @param offDst The current instruction offset.
1155	* @param uVexL The VEX.L value.
1156	* @param uVexV The VEX.V value (caller inverted it already).
1157	* @param uVexR The VEX.R value (caller inverted it already).
1158	* @param uVexR The VEX.X value (caller inverted it already).
1159	* @param uVexR The VEX.B value (caller inverted it already).
1160	* @param uVexR The VEX.W value (straight).
1161	*/
1162	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertVex3bPrefix(PBS3CG1STATE pThis, unsigned offDst, uint8_t uVexV, uint8_t uVexL,
1163	uint8_t uVexR, uint8_t uVexX, uint8_t uVexB, uint8_t uVexW)
1164	{
1165	uint8_t b1;
1166	uint8_t b2;
1167	b1 = uVexR << 7;
1168	b1 \|= uVexX << 6;
1169	b1 \|= uVexB << 5;
1170	b1 \|= 1; /* VEX.mmmmm = 1/ /* @todo three byte opcode tables */
1171	b2 = uVexV << 3;
1172	b2 \|= uVexW << 7;
1173	b2 \|= uVexL << 2;
1174	switch (pThis->enmPrefixKind)
1175	{
1176	case BS3CG1PFXKIND_NO_F2_F3_66: b2 \|= 0; break;
1177	case BS3CG1PFXKIND_REQ_66: b2 \|= 1; break;
1178	case BS3CG1PFXKIND_REQ_F3: b2 \|= 2; break;
1179	case BS3CG1PFXKIND_REQ_F2: b2 \|= 3; break;
1180	default:
1181	Bs3TestFailedF("enmPrefixKind=%d not supported for VEX!\n", pThis->enmPrefixKind);
1182	break;
1183	}
1184
1185	pThis->abCurInstr[offDst] = 0xc4; /* vex3 */
1186	pThis->abCurInstr[offDst + 1] = b1;
1187	pThis->abCurInstr[offDst + 2] = b2;
1188	return offDst + 3;
1189	}
1190
1191
1192	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertReqPrefix(PBS3CG1STATE pThis, unsigned offDst)
1193	{
1194	switch (pThis->enmPrefixKind)
1195	{
1196	case BS3CG1PFXKIND_REQ_66:
1197	pThis->abCurInstr[offDst] = 0x66;
1198	break;
1199	case BS3CG1PFXKIND_REQ_F2:
1200	pThis->abCurInstr[offDst] = 0xf2;
1201	break;
1202	case BS3CG1PFXKIND_REQ_F3:
1203	pThis->abCurInstr[offDst] = 0xf3;
1204	break;
1205	default:
1206	return offDst;
1207	}
1208	return offDst + 1;
1209	}
1210
1211
1212	DECLINLINE(unsigned) BS3_NEAR_CODE Bs3Cg1InsertOpcodes(PBS3CG1STATE pThis, unsigned offDst)
1213	{
1214	switch (pThis->cbOpcodes)
1215	{
1216	case 4: pThis->abCurInstr[offDst + 3] = pThis->abOpcodes[3];
1217	case 3: pThis->abCurInstr[offDst + 2] = pThis->abOpcodes[2];
1218	case 2: pThis->abCurInstr[offDst + 1] = pThis->abOpcodes[1];
1219	case 1: pThis->abCurInstr[offDst] = pThis->abOpcodes[0];
1220	return offDst + pThis->cbOpcodes;
1221
1222	default:
1223	BS3_ASSERT(0);
1224	return 0;
1225	}
1226	}
1227
1228
1229	/**
1230	* Cleans up state and context changes made by the encoder.
1231	*
1232	* @param pThis The state.
1233	*/
1234	static void BS3_NEAR_CODE Bs3Cg1EncodeCleanup(PBS3CG1STATE pThis)
1235	{
1236	/* Restore the DS registers in the contexts. */
1237	unsigned iRing = 4;
1238	while (iRing-- > 0)
1239	pThis->aInitialCtxs[iRing].ds = pThis->aSavedSegRegs[iRing].ds;
1240
1241	switch (pThis->enmEncoding)
1242	{
1243	/* Most encodings currently doesn't need any special cleaning up. */
1244	default:
1245	return;
1246	}
1247	}
1248
1249
1250	static unsigned BS3_NEAR_CODE Bs3Cfg1EncodeMemMod0Disp(PBS3CG1STATE pThis, bool fAddrOverride, unsigned off, uint8_t iReg,
1251	uint8_t cbOp, uint8_t cbMissalign, BS3CG1OPLOC enmLocation)
1252	{
1253	pThis->aOperands[pThis->iRmOp].idxField = BS3CG1DST_INVALID;
1254	pThis->aOperands[pThis->iRmOp].enmLocation = enmLocation;
1255	pThis->aOperands[pThis->iRmOp].cbOp = cbOp;
1256	pThis->aOperands[pThis->iRmOp].off = cbOp + cbMissalign;
1257
1258	if ( BS3_MODE_IS_16BIT_CODE(pThis->bMode)
1259	\|\| (fAddrOverride && BS3_MODE_IS_32BIT_CODE(pThis->bMode)) )
1260	{
1261	/*
1262	* 16-bit code doing 16-bit or 32-bit addressing,
1263	* or 32-bit code doing 16-bit addressing.
1264	*/
1265	unsigned iRing = 4;
1266	if (BS3_MODE_IS_RM_OR_V86(pThis->bMode))
1267	while (iRing-- > 0)
1268	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel;
1269	else
1270	while (iRing-- > 0)
1271	pThis->aInitialCtxs[iRing].ds = pThis->DataPgFar.sel \| iRing;
1272	if (!fAddrOverride \|\| BS3_MODE_IS_32BIT_CODE(pThis->bMode))
1273	{
1274	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 6 /disp16/);
1275	(uint16_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1276	off += 2;
1277	}
1278	else
1279	{
1280	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1281	(uint32_t )&pThis->abCurInstr[off] = pThis->DataPgFar.off + X86_PAGE_SIZE - cbOp - cbMissalign;
1282	off += 4;
1283	}
1284	}
1285	else
1286	{
1287	/*
1288	* 32-bit code doing 32-bit addressing,
1289	* or 64-bit code doing either 64-bit or 32-bit addressing.
1290	*/
1291	pThis->abCurInstr[off++] = X86_MODRM_MAKE(0, iReg, 5 /disp32/);
1292	(uint32_t )&pThis->abCurInstr[off] = BS3_FP_OFF(pThis->pbDataPg) + X86_PAGE_SIZE - cbOp - cbMissalign;
1293
1294	/* In 64-bit mode we always have a rip relative encoding regardless of fAddrOverride. */
1295	if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1296	(uint32_t )&pThis->abCurInstr[off] -= BS3_FP_OFF(&pThis->pbCodePg[X86_PAGE_SIZE]);
1297	off += 4;
1298	}
1299
1300	/*
1301	* Fill the memory with 0xcc.
1302	*/
1303	switch (cbOp + cbMissalign)
1304	{
1305	case 8: pThis->pbDataPg[X86_PAGE_SIZE - 8] = 0xcc; /* fall thru */
1306	case 7: pThis->pbDataPg[X86_PAGE_SIZE - 7] = 0xcc; /* fall thru */
1307	case 6: pThis->pbDataPg[X86_PAGE_SIZE - 6] = 0xcc; /* fall thru */
1308	case 5: pThis->pbDataPg[X86_PAGE_SIZE - 5] = 0xcc; /* fall thru */
1309	case 4: pThis->pbDataPg[X86_PAGE_SIZE - 4] = 0xcc; /* fall thru */
1310	case 3: pThis->pbDataPg[X86_PAGE_SIZE - 3] = 0xcc; /* fall thru */
1311	case 2: pThis->pbDataPg[X86_PAGE_SIZE - 2] = 0xcc; /* fall thru */
1312	case 1: pThis->pbDataPg[X86_PAGE_SIZE - 1] = 0xcc; /* fall thru */
1313	case 0: break;
1314	default:
1315	{
1316	BS3CG1_DPRINTF(("Bs3MemSet(%p,%#x,%#x)\n", &pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign));
1317	Bs3MemSet(&pThis->pbDataPg[X86_PAGE_SIZE - cbOp - cbMissalign], 0xcc, cbOp - cbMissalign);
1318	break;
1319	}
1320	}
1321
1322	return off;
1323	}
1324
1325
1326	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(PBS3CG1STATE pThis, unsigned iEncoding)
1327	{
1328	unsigned off;
1329	/* Start by reg,reg encoding. */
1330	if (iEncoding == 0)
1331	{
1332	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1333	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1334	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1335	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1336	}
1337	else if (iEncoding == 1)
1338	{
1339	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1340	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1341	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM_RW);
1342	}
1343	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1344	{
1345	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1346	pThis->abCurInstr[0] = P_AZ;
1347	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1348	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM_RW);
1349	}
1350	else
1351	return 0;
1352	pThis->cbCurInstr = off;
1353	return iEncoding + 1;
1354	}
1355
1356
1357	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(PBS3CG1STATE pThis, unsigned iEncoding)
1358	{
1359	unsigned off;
1360	/* Start by reg,reg encoding. */
1361	if (iEncoding == 0)
1362	{
1363	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1364	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xAX, X86_GREG_xCX);
1365	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_AL;
1366	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_CL;
1367	}
1368	else if (iEncoding == 1)
1369	{
1370	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_CH;
1371	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1372	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, 1, 0, BS3CG1OPLOC_MEM);
1373	}
1374	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1375	{
1376	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_BH;
1377	pThis->abCurInstr[0] = P_AZ;
1378	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1379	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, 1, 0, BS3CG1OPLOC_MEM);
1380	}
1381	else
1382	return 0;
1383	pThis->cbCurInstr = off;
1384	return iEncoding + 1;
1385	}
1386
1387
1388	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(PBS3CG1STATE pThis, unsigned iEncoding)
1389	{
1390	unsigned off;
1391	unsigned cbOp;
1392	if (iEncoding == 0)
1393	{
1394	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1395	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1396	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1397	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1398	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1399	}
1400	else if (iEncoding == 1)
1401	{
1402	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1403	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1404	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1405	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp, 0,
1406	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1407	}
1408	else if (iEncoding == 2 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1409	{
1410	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1411	pThis->abCurInstr[0] = P_OZ;
1412	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1413	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1414	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBX;
1415	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_OZ_RDX;
1416	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1417	}
1418	else if (iEncoding == 3)
1419	{
1420	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1421	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1422	pThis->abCurInstr[0] = P_OZ;
1423	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1424	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xSI, cbOp, 0,
1425	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1426	}
1427	else if (iEncoding == 4)
1428	{
1429	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1430	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RDI;
1431	pThis->abCurInstr[0] = P_AZ;
1432	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1433	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xDI, cbOp, 0,
1434	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1435	}
1436	else if (iEncoding == 5)
1437	{
1438	cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 4 : 2;
1439	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RSI;
1440	pThis->abCurInstr[0] = P_OZ;
1441	pThis->abCurInstr[1] = P_AZ;
1442	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1443	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xSI, cbOp, 0,
1444	pThis->enmEncoding == BS3CG1ENC_MODRM_Gv_Ev ? BS3CG1OPLOC_MEM : BS3CG1OPLOC_MEM_RW);
1445	}
1446	else if (iEncoding == 6 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1447	{
1448	cbOp = 8;
1449	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1450	pThis->abCurInstr[off++] = REX_W___;
1451	off = Bs3Cg1InsertOpcodes(pThis, off);
1452	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, X86_GREG_xBX, X86_GREG_xDX);
1453	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_RBX;
1454	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_RDX;
1455	pThis->aOperands[pThis->iRmOp ].enmLocation = BS3CG1OPLOC_CTX;
1456	}
1457	else
1458	return 0;
1459	pThis->aOperands[0].cbOp = cbOp;
1460	pThis->aOperands[1].cbOp = cbOp;
1461	pThis->cbOperand = cbOp;
1462	pThis->cbCurInstr = off;
1463	return iEncoding + 1;
1464	}
1465
1466
1467	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_Vss(PBS3CG1STATE pThis, unsigned iEncoding)
1468	{
1469	unsigned off;
1470	if (iEncoding == 0)
1471	{
1472	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1473	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1474	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_DW0;
1475	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0;
1476	}
1477	else if (iEncoding == 1)
1478	{
1479	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0;
1480	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1481	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 4, 0, BS3CG1OPLOC_MEM_RW);
1482	}
1483	else if (iEncoding == 2)
1484	{
1485	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0;
1486	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1487	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 4, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1488	}
1489	else
1490	return 0;
1491	pThis->cbCurInstr = off;
1492	return iEncoding + 1;
1493	}
1494
1495
1496	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_Vsd(PBS3CG1STATE pThis, unsigned iEncoding)
1497	{
1498	unsigned off;
1499	if (iEncoding == 0)
1500	{
1501	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1502	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1503	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1504	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1505	}
1506	else if (iEncoding == 1)
1507	{
1508	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1509	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1510	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1511	}
1512	else if (iEncoding == 2)
1513	{
1514	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1515	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1516	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1517	}
1518	else
1519	return 0;
1520	pThis->cbCurInstr = off;
1521	return iEncoding + 1;
1522	}
1523
1524
1525	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_Vps__OR__BS3CG1ENC_MODRM_Wpd_Vpd(PBS3CG1STATE pThis, unsigned iEncoding)
1526	{
1527	unsigned off;
1528	if (iEncoding == 0)
1529	{
1530	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1531	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1532	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1533	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1534	}
1535	else if (iEncoding == 1)
1536	{
1537	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1538	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1539	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM_RW);
1540	}
1541	else if (iEncoding == 2)
1542	{
1543	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1544	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1545	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1546	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1547	pThis->bAlignmentXcpt = X86_XCPT_GP;
1548	}
1549	else
1550	return 0;
1551	pThis->cbCurInstr = off;
1552	return iEncoding + 1;
1553	}
1554
1555
1556	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_Vq(PBS3CG1STATE pThis, unsigned iEncoding)
1557	{
1558	unsigned off;
1559	if (iEncoding == 0)
1560	{
1561	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1562	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1563	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO_ZX;
1564	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1565	}
1566	else if (iEncoding == 1)
1567	{
1568	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1569	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1570	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM_RW);
1571	}
1572	else if (iEncoding == 2)
1573	{
1574	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1575	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1576	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM_RW);
1577	}
1578	else
1579	return 0;
1580	pThis->cbCurInstr = off;
1581	return iEncoding + 1;
1582	}
1583
1584
1585	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(PBS3CG1STATE pThis, unsigned iEncoding)
1586	{
1587	unsigned off;
1588	if (iEncoding == 0)
1589	{
1590	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1591	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1592	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_HI;
1593	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_LO;
1594	}
1595	else if (iEncoding == 1)
1596	{
1597	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1598	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 2, 2);
1599	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM2_HI;
1600	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1601	}
1602	else
1603	return 0;
1604	pThis->cbCurInstr = off;
1605	return iEncoding + 1;
1606	}
1607
1608
1609	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_Mq(PBS3CG1STATE pThis, unsigned iEncoding)
1610	{
1611	unsigned off;
1612	if (iEncoding == 0)
1613	{
1614	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_LO;
1615	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1616	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 8, 0, BS3CG1OPLOC_MEM);
1617	}
1618	else if (iEncoding == 1)
1619	{
1620	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_LO;
1621	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1622	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 8, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1623	}
1624	else
1625	return 0;
1626	pThis->cbCurInstr = off;
1627	return iEncoding + 1;
1628	}
1629
1630
1631	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(PBS3CG1STATE pThis, unsigned iEncoding)
1632	{
1633	unsigned off;
1634	if (iEncoding == 0)
1635	{
1636	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1637	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1638	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1639	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1640	}
1641	else if (iEncoding == 1)
1642	{
1643	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1644	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1645	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM);
1646	}
1647	else if (iEncoding == 2)
1648	{
1649	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1650	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1651	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1652	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1653	pThis->bAlignmentXcpt = X86_XCPT_GP;
1654	}
1655	else
1656	return 0;
1657	pThis->cbCurInstr = off;
1658	return iEncoding + 1;
1659	}
1660
1661
1662	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_Wps__OR__BS3CG1ENC_MODRM_Vpd_Wpd(PBS3CG1STATE pThis,
1663	unsigned iEncoding)
1664	{
1665	unsigned off;
1666	if (iEncoding == 0)
1667	{
1668	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1669	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1670	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0;
1671	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1;
1672	}
1673	else if (iEncoding == 1)
1674	{
1675	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2;
1676	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1677	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 16, 0, BS3CG1OPLOC_MEM);
1678	}
1679	else if (iEncoding == 2)
1680	{
1681	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3;
1682	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1683	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 16, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1684	if (!Bs3Cg1XcptTypeIsUnaligned(pThis->enmXcptType))
1685	pThis->bAlignmentXcpt = X86_XCPT_GP;
1686	}
1687	else
1688	return 0;
1689	pThis->cbCurInstr = off;
1690	return iEncoding + 1;
1691	}
1692
1693
1694	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(PBS3CG1STATE pThis, unsigned iEncoding)
1695	{
1696	unsigned off;
1697	if (iEncoding == 0)
1698	{
1699	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1700	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 1, 0);
1701	pThis->aOperands[pThis->iRmOp ].idxField = BS3CG1DST_XMM0_LO;
1702	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM1_DW0_ZX;
1703	}
1704	else if (iEncoding == 1)
1705	{
1706	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM2_DW0_ZX;
1707	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1708	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 2 /iReg/, 4, 0, BS3CG1OPLOC_MEM);
1709	}
1710	else if (iEncoding == 2)
1711	{
1712	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_XMM3_DW0_ZX;
1713	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1714	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, 3 /iReg/, 4, 1 /cbMissalign/, BS3CG1OPLOC_MEM);
1715	}
1716	else
1717	return 0;
1718	pThis->cbCurInstr = off;
1719	return iEncoding + 1;
1720	}
1721
1722
1723	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(PBS3CG1STATE pThis, unsigned iEncoding)
1724	{
1725	unsigned off;
1726	unsigned cbOp = BS3_MODE_IS_16BIT_CODE(pThis->bMode) ? 2 : 4;
1727	if (iEncoding == 0)
1728	{
1729	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1730	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1731	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1732	}
1733	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1734	{
1735	cbOp = cbOp == 2 ? 4 : 2;
1736	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1737	pThis->abCurInstr[0] = P_OZ;
1738	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1739	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1740	}
1741	else if (iEncoding == 2)
1742	{
1743	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1744	pThis->abCurInstr[0] = P_AZ;
1745	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1746	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1747	}
1748	else if (iEncoding == 3)
1749	{
1750	cbOp = cbOp == 2 ? 4 : 2;
1751	pThis->aOperands[pThis->iRegOp].idxField = BS3CG1DST_OZ_RBP;
1752	pThis->abCurInstr[0] = P_AZ;
1753	pThis->abCurInstr[1] = P_OZ;
1754	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 2));
1755	off = Bs3Cfg1EncodeMemMod0Disp(pThis, true, off, X86_GREG_xBP, cbOp * 2, 0, BS3CG1OPLOC_MEM);
1756	}
1757	else
1758	return 0;
1759	pThis->aOperands[pThis->iRegOp].cbOp = cbOp;
1760	pThis->cbOperand = cbOp;
1761	pThis->cbCurInstr = off;
1762	return iEncoding + 1;
1763	}
1764
1765
1766	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(PBS3CG1STATE pThis, unsigned iEncoding)
1767	{
1768	unsigned off;
1769	if (iEncoding == 0)
1770	{
1771	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1772	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1773	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1774	1, 0, BS3CG1OPLOC_MEM);
1775	}
1776	else
1777	return 0;
1778	pThis->cbCurInstr = off;
1779	return iEncoding + 1;
1780	}
1781
1782
1783	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(PBS3CG1STATE pThis, unsigned iEncoding)
1784	{
1785	unsigned off;
1786	if (iEncoding == 0)
1787	{
1788	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1789	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1790	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1791	4, 0, BS3CG1OPLOC_MEM);
1792	}
1793	else
1794	return 0;
1795	pThis->cbCurInstr = off;
1796	return iEncoding + 1;
1797	}
1798
1799
1800	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(PBS3CG1STATE pThis, unsigned iEncoding)
1801	{
1802	unsigned off;
1803	if (iEncoding == 0)
1804	{
1805	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0)) - 1;
1806	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1807	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1808	4, 0, BS3CG1OPLOC_MEM_RW);
1809	}
1810	else
1811	return 0;
1812	pThis->cbCurInstr = off;
1813	return iEncoding + 1;
1814	}
1815
1816
1817	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_MdWO(PBS3CG1STATE pThis, unsigned iEncoding)
1818	{
1819	unsigned off;
1820	if (iEncoding == 0)
1821	{
1822	/** @todo three by opcode needs some tweaking. */
1823	off = Bs3Cg1InsertVex2bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/);
1824	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1825	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1826	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1827	4, 0, BS3CG1OPLOC_MEM_RW);
1828	}
1829	else if (iEncoding == 1)
1830	{
1831	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1832	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1833	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1834	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1835	4, 0, BS3CG1OPLOC_MEM_RW);
1836	}
1837	else if (iEncoding == 2)
1838	{
1839	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0x7 /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1840	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1841	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1842	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1843	4, 0, BS3CG1OPLOC_MEM_RW);
1844	pThis->fInvalidEncoding = true;
1845	}
1846	else if (iEncoding == 3)
1847	{
1848	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 1 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1849	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1850	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1851	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1852	4, 0, BS3CG1OPLOC_MEM_RW);
1853	pThis->fInvalidEncoding = true;
1854	}
1855	else if (iEncoding == 4)
1856	{
1857	pThis->abCurInstr[0] = P_OZ;
1858	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1859	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1860	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1861	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1862	4, 0, BS3CG1OPLOC_MEM_RW);
1863	pThis->fInvalidEncoding = true;
1864	}
1865	else if (iEncoding == 5)
1866	{
1867	pThis->abCurInstr[0] = P_RZ;
1868	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1869	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1870	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1871	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1872	4, 0, BS3CG1OPLOC_MEM_RW);
1873	pThis->fInvalidEncoding = true;
1874	}
1875	else if (iEncoding == 6)
1876	{
1877	pThis->abCurInstr[0] = P_RN;
1878	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1879	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1880	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1881	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1882	4, 0, BS3CG1OPLOC_MEM_RW);
1883	pThis->fInvalidEncoding = true;
1884	}
1885	else if (iEncoding == 7)
1886	{
1887	off = Bs3Cg1InsertVex3bPrefix(pThis, 0 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 1 /W/);
1888	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1889	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1890	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1891	4, 0, BS3CG1OPLOC_MEM_RW);
1892	}
1893	#if ARCH_BITS == 64
1894	else if (BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1895	{
1896	if (iEncoding == 8)
1897	{
1898	pThis->abCurInstr[0] = REX_____;
1899	off = Bs3Cg1InsertVex3bPrefix(pThis, 1 /offDst/, 0xf /~V/, 0 /L/, 1 /~R/, 1 /~X/, 1 /~B/, 0 /W/);
1900	off = Bs3Cg1InsertOpcodes(pThis, off) - 1;
1901	off = Bs3Cfg1EncodeMemMod0Disp(pThis, false, off,
1902	(pThis->abCurInstr[off] & X86_MODRM_REG_MASK) >> X86_MODRM_REG_SHIFT,
1903	4, 0, BS3CG1OPLOC_MEM_RW);
1904	pThis->fInvalidEncoding = true;
1905	}
1906	else
1907	return 0;
1908	}
1909	#endif
1910	else
1911	return 0;
1912	pThis->cbCurInstr = off;
1913	return iEncoding + 1;
1914	}
1915
1916
1917	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(PBS3CG1STATE pThis, unsigned iEncoding)
1918	{
1919	unsigned off;
1920	if (iEncoding == 0)
1921	{
1922	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1923	pThis->cbCurInstr = off;
1924	iEncoding++;
1925	}
1926	else
1927	return 0;
1928	return iEncoding + 1;
1929	}
1930
1931
1932	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(PBS3CG1STATE pThis, unsigned iEncoding)
1933	{
1934	unsigned off;
1935	if (iEncoding == 0)
1936	{
1937	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1938	pThis->aOperands[1].off = (uint8_t)off;
1939	pThis->abCurInstr[off++] = 0xff;
1940	pThis->cbCurInstr = off;
1941	}
1942	else
1943	return 0;
1944	return iEncoding + 1;
1945	}
1946
1947
1948	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(PBS3CG1STATE pThis, unsigned iEncoding)
1949	{
1950	unsigned off;
1951	if (iEncoding == 0)
1952	{
1953	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 0));
1954	pThis->aOperands[1].off = (uint8_t)off;
1955	if (BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1956	{
1957	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
1958	off += 2;
1959	pThis->aOperands[0].cbOp = 2;
1960	pThis->aOperands[1].cbOp = 2;
1961	pThis->cbOperand = 2;
1962	}
1963	else
1964	{
1965	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
1966	off += 4;
1967	pThis->aOperands[0].cbOp = 4;
1968	pThis->aOperands[1].cbOp = 4;
1969	pThis->cbOperand = 4;
1970	}
1971	}
1972	else if (iEncoding == 1 && (g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
1973	{
1974	pThis->abCurInstr[0] = P_OZ;
1975	off = Bs3Cg1InsertOpcodes(pThis, Bs3Cg1InsertReqPrefix(pThis, 1));
1976	pThis->aOperands[1].off = (uint8_t)off;
1977	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
1978	{
1979	(uint16_t )&pThis->abCurInstr[off] = UINT16_MAX;
1980	off += 2;
1981	pThis->aOperands[0].cbOp = 2;
1982	pThis->aOperands[1].cbOp = 2;
1983	pThis->cbOperand = 2;
1984	}
1985	else
1986	{
1987	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
1988	off += 4;
1989	pThis->aOperands[0].cbOp = 4;
1990	pThis->aOperands[1].cbOp = 4;
1991	pThis->cbOperand = 4;
1992	}
1993	}
1994	else if (iEncoding == 2 && BS3_MODE_IS_64BIT_CODE(pThis->bMode))
1995	{
1996	off = Bs3Cg1InsertReqPrefix(pThis, 0);
1997	pThis->abCurInstr[off++] = REX_W___;
1998	off = Bs3Cg1InsertOpcodes(pThis, off);
1999	pThis->aOperands[1].off = (uint8_t)off;
2000	(uint32_t )&pThis->abCurInstr[off] = UINT32_MAX;
2001	off += 4;
2002	pThis->aOperands[0].cbOp = 8;
2003	pThis->aOperands[1].cbOp = 4;
2004	pThis->cbOperand = 8;
2005	}
2006	else
2007	return 0;
2008	pThis->cbCurInstr = off;
2009	return iEncoding + 1;
2010	}
2011
2012
2013	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(PBS3CG1STATE pThis, unsigned iEncoding)
2014	{
2015	unsigned off;
2016	if (iEncoding < 8)
2017	{
2018	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2019	off = Bs3Cg1InsertOpcodes(pThis, off);
2020	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, iEncoding, 1);
2021	}
2022	else if (iEncoding < 16)
2023	{
2024	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2025	off = Bs3Cg1InsertOpcodes(pThis, off);
2026	pThis->abCurInstr[off++] = X86_MODRM_MAKE(3, 0, iEncoding);
2027	}
2028	else
2029	return 0;
2030	pThis->cbCurInstr = off;
2031
2032	return iEncoding + 1;
2033	}
2034
2035
2036	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(PBS3CG1STATE pThis, unsigned iEncoding)
2037	{
2038	unsigned off;
2039	if (iEncoding < 3)
2040	{
2041	off = Bs3Cg1InsertReqPrefix(pThis, 0);
2042	off = Bs3Cg1InsertOpcodes(pThis, off);
2043	pThis->abCurInstr[off++] = X86_MODRM_MAKE(iEncoding, 0, 1);
2044	if (iEncoding >= 1)
2045	pThis->abCurInstr[off++] = 0x7f;
2046	if (iEncoding == 2)
2047	{
2048	pThis->abCurInstr[off++] = 0x5f;
2049	if (!BS3_MODE_IS_16BIT_CODE(pThis->bMode))
2050	{
2051	pThis->abCurInstr[off++] = 0x3f;
2052	pThis->abCurInstr[off++] = 0x1f;
2053	}
2054	}
2055	}
2056	else
2057	return 0;
2058	pThis->cbCurInstr = off;
2059	return iEncoding + 1;
2060	}
2061
2062
2063	/**
2064	* Encodes the next instruction.
2065	*
2066	* @returns Next iEncoding value. Returns @a iEncoding unchanged to indicate
2067	* that there are no more encodings to test.
2068	* @param pThis The state.
2069	* @param iEncoding The encoding to produce. Meaning is specific to
2070	* each BS3CG1ENC_XXX value and should be considered
2071	* internal.
2072	*/
2073	static unsigned BS3_NEAR_CODE Bs3Cg1EncodeNext(PBS3CG1STATE pThis, unsigned iEncoding)
2074	{
2075	pThis->bAlignmentXcpt = UINT8_MAX;
2076
2077	switch (pThis->enmEncoding)
2078	{
2079	case BS3CG1ENC_MODRM_Eb_Gb:
2080	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Eb_Gb(pThis, iEncoding);
2081	case BS3CG1ENC_MODRM_Gb_Eb:
2082	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gb_Eb(pThis, iEncoding);
2083	case BS3CG1ENC_MODRM_Gv_Ev:
2084	case BS3CG1ENC_MODRM_Ev_Gv:
2085	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ev__OR__BS3CG1ENC_MODRM_Ev_Gv(pThis, iEncoding);
2086
2087	case BS3CG1ENC_MODRM_Wss_Vss:
2088	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wss_Vss(pThis, iEncoding);
2089	case BS3CG1ENC_MODRM_Wsd_Vsd:
2090	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wsd_Vsd(pThis, iEncoding);
2091	case BS3CG1ENC_MODRM_Wps_Vps:
2092	case BS3CG1ENC_MODRM_Wpd_Vpd:
2093	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Wps_Vps__OR__BS3CG1ENC_MODRM_Wpd_Vpd(pThis, iEncoding);
2094	case BS3CG1ENC_MODRM_WqZxReg_Vq:
2095	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_WqZxReg_Vq(pThis, iEncoding);
2096
2097	case BS3CG1ENC_MODRM_Vq_UqHi:
2098	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_UqHi(pThis, iEncoding);
2099	case BS3CG1ENC_MODRM_Vq_Mq:
2100	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vq_Mq(pThis, iEncoding);
2101	case BS3CG1ENC_MODRM_Vdq_Wdq:
2102	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vdq_Wdq(pThis, iEncoding);
2103	case BS3CG1ENC_MODRM_Vpd_Wpd:
2104	case BS3CG1ENC_MODRM_Vps_Wps:
2105	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Vps_Wps__OR__BS3CG1ENC_MODRM_Vpd_Wpd(pThis, iEncoding);
2106	case BS3CG1ENC_MODRM_VssZxReg_Wss:
2107	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_VssZxReg_Wss(pThis, iEncoding);
2108
2109	case BS3CG1ENC_MODRM_Gv_Ma:
2110	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_Gv_Ma(pThis, iEncoding);
2111
2112	case BS3CG1ENC_MODRM_MbRO:
2113	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MbRO(pThis, iEncoding);
2114	case BS3CG1ENC_MODRM_MdRO:
2115	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdRO(pThis, iEncoding);
2116	case BS3CG1ENC_MODRM_MdWO:
2117	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MdWO(pThis, iEncoding);
2118	case BS3CG1ENC_VEX_MODRM_MdWO:
2119	return Bs3Cg1EncodeNext_BS3CG1ENC_VEX_MODRM_MdWO(pThis, iEncoding);
2120
2121	case BS3CG1ENC_FIXED:
2122	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED(pThis, iEncoding);
2123	case BS3CG1ENC_FIXED_AL_Ib:
2124	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_AL_Ib(pThis, iEncoding);
2125	case BS3CG1ENC_FIXED_rAX_Iz:
2126	return Bs3Cg1EncodeNext_BS3CG1ENC_FIXED_rAX_Iz(pThis, iEncoding);
2127
2128	case BS3CG1ENC_MODRM_MOD_EQ_3:
2129	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_EQ_3(pThis, iEncoding);
2130	case BS3CG1ENC_MODRM_MOD_NE_3:
2131	return Bs3Cg1EncodeNext_BS3CG1ENC_MODRM_MOD_NE_3(pThis, iEncoding);
2132
2133	default:
2134	Bs3TestFailedF("Internal error! BS3CG1ENC_XXX = %u not implemented", pThis->enmEncoding);
2135	break;
2136	}
2137
2138
2139	return iEncoding;
2140	}
2141
2142
2143	/**
2144	* Prepares doing instruction encodings.
2145	*
2146	* This is in part specific to how the instruction is encoded, but generally it
2147	* sets up basic operand values that doesn't change (much) when Bs3Cg1EncodeNext
2148	* is called from within the loop.
2149	*
2150	* @returns Success indicator (true/false).
2151	* @param pThis The state.
2152	*/
2153	#define Bs3Cg1EncodePrep BS3_CMN_NM(Bs3Cg1EncodePrep)
2154	bool BS3_NEAR_CODE Bs3Cg1EncodePrep(PBS3CG1STATE pThis)
2155	{
2156	unsigned iRing = 4;
2157	while (iRing-- > 0)
2158	pThis->aSavedSegRegs[iRing].ds = pThis->aInitialCtxs[iRing].ds;
2159
2160	pThis->iRmOp = RT_ELEMENTS(pThis->aOperands) - 1;
2161	pThis->iRegOp = RT_ELEMENTS(pThis->aOperands) - 1;
2162	pThis->fSameRingNotOkay = false;
2163	pThis->cbOperand = 0;
2164
2165	switch (pThis->enmEncoding)
2166	{
2167	case BS3CG1ENC_MODRM_Eb_Gb:
2168	pThis->iRmOp = 0;
2169	pThis->iRegOp = 1;
2170	pThis->aOperands[0].cbOp = 1;
2171	pThis->aOperands[1].cbOp = 1;
2172	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2173	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2174	break;
2175
2176	case BS3CG1ENC_MODRM_Ev_Gv:
2177	pThis->iRmOp = 0;
2178	pThis->iRegOp = 1;
2179	pThis->cbOperand = 2;
2180	pThis->aOperands[0].cbOp = 2;
2181	pThis->aOperands[1].cbOp = 2;
2182	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2183	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2184	break;
2185
2186	case BS3CG1ENC_MODRM_Gb_Eb:
2187	pThis->iRmOp = 1;
2188	pThis->iRegOp = 0;
2189	pThis->aOperands[0].cbOp = 1;
2190	pThis->aOperands[1].cbOp = 1;
2191	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2192	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2193	break;
2194
2195	case BS3CG1ENC_MODRM_Gv_Ev:
2196	pThis->iRmOp = 1;
2197	pThis->iRegOp = 0;
2198	pThis->cbOperand = 2;
2199	pThis->aOperands[0].cbOp = 2;
2200	pThis->aOperands[1].cbOp = 2;
2201	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2202	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2203	break;
2204
2205	case BS3CG1ENC_MODRM_Gv_Ma:
2206	pThis->iRmOp = 1;
2207	pThis->iRegOp = 0;
2208	pThis->cbOperand = 2;
2209	pThis->aOperands[0].cbOp = 2;
2210	pThis->aOperands[1].cbOp = 4;
2211	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2212	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
2213	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2214	break;
2215
2216	case BS3CG1ENC_MODRM_Wss_Vss:
2217	pThis->iRmOp = 0;
2218	pThis->iRegOp = 1;
2219	pThis->aOperands[0].cbOp = 4;
2220	pThis->aOperands[1].cbOp = 4;
2221	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2222	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2223	break;
2224
2225	case BS3CG1ENC_MODRM_Wsd_Vsd:
2226	case BS3CG1ENC_MODRM_WqZxReg_Vq:
2227	pThis->iRmOp = 0;
2228	pThis->iRegOp = 1;
2229	pThis->aOperands[0].cbOp = 8;
2230	pThis->aOperands[1].cbOp = 8;
2231	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2232	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2233	break;
2234
2235	case BS3CG1ENC_MODRM_Wps_Vps:
2236	case BS3CG1ENC_MODRM_Wpd_Vpd:
2237	pThis->iRmOp = 0;
2238	pThis->iRegOp = 1;
2239	pThis->aOperands[0].cbOp = 16;
2240	pThis->aOperands[1].cbOp = 16;
2241	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2242	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2243	break;
2244
2245	case BS3CG1ENC_MODRM_Vdq_Wdq:
2246	pThis->iRmOp = 1;
2247	pThis->iRegOp = 0;
2248	pThis->aOperands[0].cbOp = 16;
2249	pThis->aOperands[1].cbOp = 16;
2250	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2251	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2252	break;
2253
2254	case BS3CG1ENC_MODRM_Vpd_Wpd:
2255	case BS3CG1ENC_MODRM_Vps_Wps:
2256	pThis->iRmOp = 1;
2257	pThis->iRegOp = 0;
2258	pThis->aOperands[0].cbOp = 16;
2259	pThis->aOperands[1].cbOp = 16;
2260	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2261	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2262	break;
2263
2264	case BS3CG1ENC_MODRM_Vq_UqHi:
2265	pThis->iRmOp = 1;
2266	pThis->iRegOp = 0;
2267	pThis->aOperands[0].cbOp = 8;
2268	pThis->aOperands[1].cbOp = 8;
2269	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2270	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2271	break;
2272
2273	case BS3CG1ENC_MODRM_Vq_Mq:
2274	pThis->iRmOp = 1;
2275	pThis->iRegOp = 0;
2276	pThis->aOperands[0].cbOp = 8;
2277	pThis->aOperands[1].cbOp = 8;
2278	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2279	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_MEM;
2280	break;
2281
2282	case BS3CG1ENC_MODRM_VssZxReg_Wss:
2283	pThis->iRmOp = 1;
2284	pThis->iRegOp = 0;
2285	pThis->aOperands[0].cbOp = 4;
2286	pThis->aOperands[1].cbOp = 4;
2287	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2288	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_CTX;
2289	break;
2290
2291	case BS3CG1ENC_MODRM_MbRO:
2292	pThis->iRmOp = 0;
2293	pThis->aOperands[0].cbOp = 1;
2294	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
2295	break;
2296
2297	case BS3CG1ENC_MODRM_MdRO:
2298	pThis->iRmOp = 0;
2299	pThis->aOperands[0].cbOp = 4;
2300	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM;
2301	break;
2302
2303	case BS3CG1ENC_MODRM_MdWO:
2304	case BS3CG1ENC_VEX_MODRM_MdWO:
2305	pThis->iRmOp = 0;
2306	pThis->aOperands[0].cbOp = 4;
2307	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_MEM_RW;
2308	break;
2309
2310	case BS3CG1ENC_FIXED:
2311	/* nothing to do here */
2312	break;
2313
2314	case BS3CG1ENC_FIXED_AL_Ib:
2315	pThis->aOperands[0].cbOp = 1;
2316	pThis->aOperands[1].cbOp = 1;
2317	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2318	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
2319	pThis->aOperands[0].idxField = BS3CG1DST_AL;
2320	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2321	break;
2322
2323	case BS3CG1ENC_FIXED_rAX_Iz:
2324	pThis->aOperands[0].cbOp = 2;
2325	pThis->aOperands[1].cbOp = 2;
2326	pThis->aOperands[0].enmLocation = BS3CG1OPLOC_CTX;
2327	pThis->aOperands[1].enmLocation = BS3CG1OPLOC_IMM;
2328	pThis->aOperands[0].idxField = BS3CG1DST_OZ_RAX;
2329	pThis->aOperands[1].idxField = BS3CG1DST_INVALID;
2330	break;
2331
2332	case BS3CG1ENC_MODRM_MOD_EQ_3:
2333	case BS3CG1ENC_MODRM_MOD_NE_3:
2334	/* Unused or invalid instructions mostly. */
2335	break;
2336
2337	default:
2338	Bs3TestFailedF("Invalid/unimplemented enmEncoding for instruction #%RU32 (%.*s): %d",
2339	pThis->iInstr, pThis->cchMnemonic, pThis->pchMnemonic, pThis->enmEncoding);
2340	return false;
2341	}
2342	return true;
2343	}
2344
2345
2346	/**
2347	* Calculates the appropriate non-intel invalid instruction encoding.
2348	*
2349	* @returns the encoding to use instead.
2350	* @param enmEncoding The intel invalid instruction encoding.
2351	*/
2352	static BS3CG1ENC Bs3Cg1CalcNoneIntelInvalidEncoding(BS3CG1ENC enmEncoding)
2353	{
2354	switch (enmEncoding)
2355	{
2356	case BS3CG1ENC_MODRM_Gb_Eb:
2357	case BS3CG1ENC_MODRM_Gv_Ma:
2358	case BS3CG1ENC_FIXED:
2359	return BS3CG1ENC_FIXED;
2360	default:
2361	Bs3TestFailedF("Bs3Cg1CalcNoneIntelInvalidEncoding: Unsupported encoding: %d\n", enmEncoding);
2362	return BS3CG1ENC_FIXED;
2363	}
2364	}
2365
2366
2367	/**
2368	* Sets up SSE and maybe AVX.
2369	*
2370	* @returns true (if successful, false if not and the SSE instructions ends up
2371	* being invalid).
2372	* @param pThis The state.
2373	*/
2374	static bool BS3_NEAR_CODE Bs3Cg3SetupSseAndAvx(PBS3CG1STATE pThis)
2375	{
2376	if (!pThis->fWorkExtCtx)
2377	{
2378	unsigned i;
2379	uint32_t cr0 = ASMGetCR0();
2380	uint32_t cr4 = ASMGetCR4();
2381
2382	cr0 &= ~(X86_CR0_TS \| X86_CR0_MP \| X86_CR0_EM);
2383	cr0 \|= X86_CR0_NE;
2384	ASMSetCR0(cr0);
2385	if (pThis->pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
2386	{
2387	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE;
2388	ASMSetCR4(cr4);
2389	ASMSetXcr0(pThis->pExtCtx->fXcr0Nominal);
2390	}
2391	else
2392	{
2393	cr4 \|= X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT;
2394	ASMSetCR4(cr4);
2395	}
2396
2397	for (i = 0; i < RT_ELEMENTS(pThis->aInitialCtxs); i++)
2398	{
2399	pThis->aInitialCtxs[i].cr0.u32 = cr0;
2400	pThis->aInitialCtxs[i].cr4.u32 = cr4;
2401	}
2402	pThis->fWorkExtCtx = true;
2403	}
2404
2405	return true;
2406	}
2407
2408
2409	/**
2410	* Next CPU configuration to test the current instruction in.
2411	*
2412	* This is for testing FPU, SSE and AVX instructions with the various lazy state
2413	* load and enable bits in different configurations to ensure we're getting the
2414	* right response.
2415	*
2416	* This also cleans up the CPU and test driver state.
2417	*
2418	* @returns true if we're to do another round, false if we're done.
2419	* @param pThis The state.
2420	* @param iCpuSetup The current CPU setup number.
2421	* @param pfInvalidInstr Where to indicate whether the setup causes an
2422	* invalid instruction or not. This is also used as
2423	* input to avoid unnecessary CPUID work.
2424	*/
2425	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupNext(PBS3CG1STATE pThis, unsigned iCpuSetup, bool BS3_FAR *pfInvalidInstr)
2426	{
2427	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
2428	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
2429	return false;
2430
2431	switch (pThis->enmCpuTest)
2432	{
2433	case BS3CG1CPU_ANY:
2434	case BS3CG1CPU_GE_80186:
2435	case BS3CG1CPU_GE_80286:
2436	case BS3CG1CPU_GE_80386:
2437	case BS3CG1CPU_GE_80486:
2438	case BS3CG1CPU_GE_Pentium:
2439	case BS3CG1CPU_CLFSH:
2440	case BS3CG1CPU_CLFLUSHOPT:
2441	return false;
2442
2443	case BS3CG1CPU_SSE:
2444	case BS3CG1CPU_SSE2:
2445	case BS3CG1CPU_SSE3:
2446	case BS3CG1CPU_AVX:
2447	case BS3CG1CPU_AVX2:
2448	if (iCpuSetup > 0 \|\| *pfInvalidInstr)
2449	{
2450	/** @todo do more configs here. */
2451	pThis->fWorkExtCtx = false;
2452	ASMSetCR0(ASMGetCR0() \| X86_CR0_EM \| X86_CR0_MP);
2453	ASMSetCR4(ASMGetCR4() & ~(X86_CR4_OSFXSR \| X86_CR4_OSXMMEEXCPT \| X86_CR4_OSXSAVE));
2454	return false;
2455	}
2456	return false;
2457
2458	default:
2459	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2460	return false;
2461	}
2462	}
2463
2464
2465	/**
2466	* Check if the instruction is supported by the CPU, possibly making state
2467	* adjustments to enable support for it.
2468	*
2469	* @returns true if supported, false if not.
2470	* @param pThis The state.
2471	*/
2472	static bool BS3_NEAR_CODE Bs3Cg1CpuSetupFirst(PBS3CG1STATE pThis)
2473	{
2474	uint32_t fEax;
2475	uint32_t fEbx;
2476	uint32_t fEcx;
2477	uint32_t fEdx;
2478
2479	if ( (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT)
2480	&& BS3_MODE_IS_64BIT_CODE(pThis->bMode))
2481	return false;
2482
2483	switch (pThis->enmCpuTest)
2484	{
2485	case BS3CG1CPU_ANY:
2486	return true;
2487
2488	case BS3CG1CPU_GE_80186:
2489	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80186)
2490	return true;
2491	return false;
2492
2493	case BS3CG1CPU_GE_80286:
2494	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80286)
2495	return true;
2496	return false;
2497
2498	case BS3CG1CPU_GE_80386:
2499	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80386)
2500	return true;
2501	return false;
2502
2503	case BS3CG1CPU_GE_80486:
2504	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_80486)
2505	return true;
2506	return false;
2507
2508	case BS3CG1CPU_GE_Pentium:
2509	if ((g_uBs3CpuDetected & BS3CPU_TYPE_MASK) >= BS3CPU_Pentium)
2510	return true;
2511	return false;
2512
2513	case BS3CG1CPU_SSE:
2514	case BS3CG1CPU_SSE2:
2515	case BS3CG1CPU_SSE3:
2516	case BS3CG1CPU_AVX:
2517	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2518	{
2519	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx);
2520	switch (pThis->enmCpuTest)
2521	{
2522	case BS3CG1CPU_SSE:
2523	if (fEdx & X86_CPUID_FEATURE_EDX_SSE)
2524	return Bs3Cg3SetupSseAndAvx(pThis);
2525	return false;
2526	case BS3CG1CPU_SSE2:
2527	if (fEdx & X86_CPUID_FEATURE_EDX_SSE2)
2528	return Bs3Cg3SetupSseAndAvx(pThis);
2529	return false;
2530	case BS3CG1CPU_SSE3:
2531	if (fEcx & X86_CPUID_FEATURE_ECX_SSE3)
2532	return Bs3Cg3SetupSseAndAvx(pThis);
2533	return false;
2534	case BS3CG1CPU_AVX:
2535	if (fEcx & X86_CPUID_FEATURE_ECX_AVX)
2536	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
2537	return false;
2538	default: BS3_ASSERT(0); /* impossible */
2539	}
2540	}
2541	return false;
2542
2543	case BS3CG1CPU_AVX2:
2544	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2545	{
2546	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, &fEax, &fEbx, &fEcx, &fEdx);
2547	switch (pThis->enmCpuTest)
2548	{
2549	case BS3CG1CPU_AVX2:
2550	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2)
2551	return Bs3Cg3SetupSseAndAvx(pThis) && !BS3_MODE_IS_RM_OR_V86(pThis->bMode);
2552	return false;
2553	default: BS3_ASSERT(0); return false; /* impossible */
2554	}
2555	}
2556	return false;
2557
2558	case BS3CG1CPU_CLFSH:
2559	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2560	{
2561	ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, NULL, &fEdx);
2562	if (fEdx & X86_CPUID_FEATURE_EDX_CLFSH)
2563	return true;
2564	}
2565	return false;
2566
2567	case BS3CG1CPU_CLFLUSHOPT:
2568	if (g_uBs3CpuDetected & BS3CPU_F_CPUID)
2569	{
2570	ASMCpuIdExSlow(7, 0, 0/leaf/, 0, NULL, &fEbx, NULL, NULL);
2571	if (fEbx & X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT)
2572	return true;
2573	}
2574	return false;
2575
2576	default:
2577	Bs3TestFailedF("Invalid enmCpuTest value: %d", pThis->enmCpuTest);
2578	return false;
2579	}
2580	}
2581
2582
2583
2584	/**
2585	* Checks the preconditions for a test.
2586	*
2587	* @returns true if the test be executed, false if not.
2588	* @param pThis The state.
2589	* @param pHdr The test header.
2590	*/
2591	static bool BS3_NEAR_CODE Bs3Cg1RunSelector(PBS3CG1STATE pThis, PCBS3CG1TESTHDR pHdr)
2592	{
2593
2594	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1);
2595	unsigned cbLeft = pHdr->cbSelector;
2596	while (cbLeft-- > 0)
2597	{
2598	switch (*pbCode++)
2599	{
2600	#define CASE_PRED(a_Pred, a_Expr) \
2601	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_TRUE: \
2602	if (!(a_Expr)) return false; \
2603	break; \
2604	case ((a_Pred) << BS3CG1SEL_OP_KIND_MASK) \| BS3CG1SEL_OP_IS_FALSE: \
2605	if (a_Expr) return false; \
2606	break
2607	CASE_PRED(BS3CG1PRED_SIZE_O16, pThis->cbOperand == 2);
2608	CASE_PRED(BS3CG1PRED_SIZE_O32, pThis->cbOperand == 4);
2609	CASE_PRED(BS3CG1PRED_SIZE_O64, pThis->cbOperand == 8);
2610	CASE_PRED(BS3CG1PRED_RING_0, pThis->uCpl == 0);
2611	CASE_PRED(BS3CG1PRED_RING_1, pThis->uCpl == 1);
2612	CASE_PRED(BS3CG1PRED_RING_2, pThis->uCpl == 2);
2613	CASE_PRED(BS3CG1PRED_RING_3, pThis->uCpl == 3);
2614	CASE_PRED(BS3CG1PRED_RING_0_THRU_2, pThis->uCpl <= 2);
2615	CASE_PRED(BS3CG1PRED_RING_1_THRU_3, pThis->uCpl >= 1);
2616	CASE_PRED(BS3CG1PRED_CODE_64BIT, BS3_MODE_IS_64BIT_CODE(pThis->bMode));
2617	CASE_PRED(BS3CG1PRED_CODE_32BIT, BS3_MODE_IS_32BIT_CODE(pThis->bMode));
2618	CASE_PRED(BS3CG1PRED_CODE_16BIT, BS3_MODE_IS_16BIT_CODE(pThis->bMode));
2619	CASE_PRED(BS3CG1PRED_MODE_REAL, BS3_MODE_IS_RM_SYS(pThis->bMode));
2620	CASE_PRED(BS3CG1PRED_MODE_PROT, BS3_MODE_IS_PM_SYS(pThis->bMode));
2621	CASE_PRED(BS3CG1PRED_MODE_LONG, BS3_MODE_IS_64BIT_SYS(pThis->bMode));
2622	CASE_PRED(BS3CG1PRED_MODE_SMM, false);
2623	CASE_PRED(BS3CG1PRED_MODE_VMX, false);
2624	CASE_PRED(BS3CG1PRED_MODE_SVM, false);
2625	CASE_PRED(BS3CG1PRED_PAGING_ON, BS3_MODE_IS_PAGED(pThis->bMode));
2626	CASE_PRED(BS3CG1PRED_PAGING_OFF, !BS3_MODE_IS_PAGED(pThis->bMode));
2627	CASE_PRED(BS3CG1PRED_VENDOR_AMD, pThis->bCpuVendor == BS3CPUVENDOR_AMD);
2628	CASE_PRED(BS3CG1PRED_VENDOR_INTEL, pThis->bCpuVendor == BS3CPUVENDOR_INTEL);
2629	CASE_PRED(BS3CG1PRED_VENDOR_VIA, pThis->bCpuVendor == BS3CPUVENDOR_VIA);
2630
2631	#undef CASE_PRED
2632	default:
2633	return Bs3TestFailedF("Invalid selector opcode %#x!", pbCode[-1]);
2634	}
2635	}
2636
2637	return true;
2638	}
2639
2640
2641	#ifdef BS3CG1_DEBUG_CTX_MOD
2642	/**
2643	* Translates the operator into a string.
2644	*
2645	* @returns Read-only string pointer.
2646	* @param bOpcode The context modifier program opcode.
2647	*/
2648	static const char BS3_FAR * BS3_NEAR_CODE Bs3Cg1CtxOpToString(uint8_t bOpcode)
2649	{
2650	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2651	{
2652	case BS3CG1_CTXOP_ASSIGN: return "=";
2653	case BS3CG1_CTXOP_OR: return "\|=";
2654	case BS3CG1_CTXOP_AND: return "&=";
2655	case BS3CG1_CTXOP_AND_INV: return "&~=";
2656	default: return "?WTF?";
2657	}
2658	}
2659	#endif
2660
2661
2662	/**
2663	* Runs a context modifier program.
2664	*
2665	* @returns Success indicator (true/false).
2666	* @param pThis The state.
2667	* @param pCtx The context.
2668	* @param pHdr The program header.
2669	* @param off The program offset relative to the end of the header.
2670	* @param cb The program size.
2671	* @param pEflCtx The context to take undefined EFLAGS from. (This is NULL
2672	* if we're processing a input context modifier program.)
2673	* @param pbInstr Points to the first instruction byte. For storing
2674	* immediate operands during input context modification.
2675	* NULL for output contexts.
2676	*/
2677	static bool BS3_NEAR_CODE Bs3Cg1RunContextModifier(PBS3CG1STATE pThis, PBS3REGCTX pCtx, PCBS3CG1TESTHDR pHdr,
2678	unsigned off, unsigned cb,
2679	PCBS3REGCTX pEflCtx, uint8_t BS3_FAR *pbInstr)
2680	{
2681	uint8_t const BS3_FAR pbCode = (uint8_t const BS3_FAR )(pHdr + 1) + off;
2682	int cbLeft = cb;
2683	while (cbLeft-- > 0)
2684	{
2685	/*
2686	* Decode the instruction.
2687	*/
2688	uint8_t const bOpcode = *pbCode++;
2689	unsigned cbValue;
2690	unsigned cbDst;
2691	BS3CG1DST idxField;
2692	BS3PTRUNION PtrField;
2693
2694	/* Expand the destiation field (can be escaped). */
2695	switch (bOpcode & BS3CG1_CTXOP_DST_MASK)
2696	{
2697	case BS3CG1_CTXOP_OP1:
2698	idxField = pThis->aOperands[0].idxField;
2699	if (idxField == BS3CG1DST_INVALID)
2700	idxField = BS3CG1DST_OP1;
2701	break;
2702
2703	case BS3CG1_CTXOP_OP2:
2704	idxField = pThis->aOperands[1].idxField;
2705	if (idxField == BS3CG1DST_INVALID)
2706	idxField = BS3CG1DST_OP2;
2707	break;
2708
2709	case BS3CG1_CTXOP_EFL:
2710	idxField = BS3CG1DST_EFL;
2711	break;
2712
2713	case BS3CG1_CTXOP_DST_ESC:
2714	if (cbLeft-- > 0)
2715	{
2716	idxField = (BS3CG1DST)*pbCode++;
2717	if (idxField <= BS3CG1DST_OP4)
2718	{
2719	if (idxField > BS3CG1DST_INVALID)
2720	{
2721	uint8_t idxField2 = pThis->aOperands[idxField - BS3CG1DST_OP1].idxField;
2722	if (idxField2 != BS3CG1DST_INVALID)
2723	idxField = idxField2;
2724	break;
2725	}
2726	}
2727	else if (idxField < BS3CG1DST_END)
2728	break;
2729	return Bs3TestFailedF("Malformed context instruction: idxField=%d", idxField);
2730	}
2731	/* fall thru */
2732	default:
2733	return Bs3TestFailed("Malformed context instruction: Destination");
2734	}
2735
2736
2737	/* Expand value size (can be escaped). */
2738	switch (bOpcode & BS3CG1_CTXOP_SIZE_MASK)
2739	{
2740	case BS3CG1_CTXOP_1_BYTE: cbValue = 1; break;
2741	case BS3CG1_CTXOP_2_BYTES: cbValue = 2; break;
2742	case BS3CG1_CTXOP_4_BYTES: cbValue = 4; break;
2743	case BS3CG1_CTXOP_8_BYTES: cbValue = 8; break;
2744	case BS3CG1_CTXOP_16_BYTES: cbValue = 16; break;
2745	case BS3CG1_CTXOP_32_BYTES: cbValue = 32; break;
2746	case BS3CG1_CTXOP_12_BYTES: cbValue = 12; break;
2747	case BS3CG1_CTXOP_SIZE_ESC:
2748	if (cbLeft-- > 0)
2749	{
2750	cbValue = *pbCode++;
2751	if (cbValue)
2752	break;
2753	}
2754	/* fall thru */
2755	default:
2756	return Bs3TestFailed("Malformed context instruction: size");
2757	}
2758
2759	/* Make sure there is enough instruction bytes for the value. */
2760	if (cbValue <= cbLeft)
2761	{ /* likely */ }
2762	else
2763	return Bs3TestFailedF("Malformed context instruction: %u bytes value, %u bytes left", cbValue, cbLeft);
2764
2765	/*
2766	* Do value processing specific to the target field size.
2767	*/
2768	cbDst = g_acbBs3Cg1DstFields[idxField];
2769	if (cbDst == BS3CG1DSTSIZE_OPERAND)
2770	cbDst = pThis->aOperands[idxField - BS3CG1DST_OP1].cbOp;
2771	else if (cbDst == BS3CG1DSTSIZE_OPERAND_SIZE_GRP)
2772	cbDst = pThis->cbOperand;
2773	if (cbDst <= 8)
2774	{
2775	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2776
2777	/*
2778	* Deal with fields up to 8-byte wide.
2779	*/
2780	/* Get the value. */
2781	uint64_t uValue;
2782	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT))
2783	switch (cbValue)
2784	{
2785	case 1: uValue = (int8_t const BS3_FAR )pbCode; break;
2786	case 2: uValue = (int16_t const BS3_FAR )pbCode; break;
2787	case 4: uValue = (int32_t const BS3_FAR )pbCode; break;
2788	default:
2789	if (cbValue >= 8)
2790	{
2791	uValue = (uint64_t const BS3_FAR )pbCode;
2792	break;
2793	}
2794	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2795	}
2796	else
2797	switch (cbValue)
2798	{
2799	case 1: uValue = (uint8_t const BS3_FAR )pbCode; break;
2800	case 2: uValue = (uint16_t const BS3_FAR )pbCode; break;
2801	case 4: uValue = (uint32_t const BS3_FAR )pbCode; break;
2802	default:
2803	if (cbValue >= 8)
2804	{
2805	uValue = (uint64_t const BS3_FAR )pbCode;
2806	break;
2807	}
2808	return Bs3TestFailedF("Malformed context instruction: %u bytes value (%u dst)", cbValue, cbDst);
2809	}
2810
2811	/* Find the field. */
2812	if (offField < sizeof(BS3REGCTX))
2813	PtrField.pu8 = (uint8_t BS3_FAR *)pCtx + offField;
2814	/* Non-register operands: */
2815	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
2816	{
2817	unsigned const idxOp = idxField - BS3CG1DST_OP1;
2818
2819	switch (pThis->aOperands[idxOp].enmLocation)
2820	{
2821	case BS3CG1OPLOC_IMM:
2822	if (pbInstr)
2823	PtrField.pu8 = &pbInstr[pThis->aOperands[idxOp].off];
2824	else
2825	return Bs3TestFailedF("Immediate operand referenced in output context!");
2826	break;
2827
2828	case BS3CG1OPLOC_MEM:
2829	if (!pbInstr)
2830	return Bs3TestFailedF("Read only operand specified in output!");
2831	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2832	break;
2833
2834	case BS3CG1OPLOC_MEM_RW:
2835	if (pbInstr)
2836	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
2837	else
2838	PtrField.pu8 = pThis->MemOp.ab;
2839	break;
2840
2841	default:
2842	if (pThis->enmEncoding != pThis->enmEncodingNonInvalid)
2843	goto l_advance_to_next;
2844	return Bs3TestFailedF("Internal error: cbDst=%u idxField=%d (%d) offField=%#x: enmLocation=%u off=%#x idxField=%u",
2845	cbDst, idxField, idxOp, offField, pThis->aOperands[idxOp].enmLocation,
2846	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
2847	}
2848	}
2849	/* Special field: Copying in undefined EFLAGS from the result context. */
2850	else if (idxField == BS3CG1DST_EFL_UNDEF)
2851	{
2852	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN)
2853	return Bs3TestFailed("Invalid BS3CG1DST_EFL_UNDEF usage");
2854	PtrField.pu32 = &pCtx->rflags.u32;
2855	uValue = (*PtrField.pu32 & ~(uint32_t)uValue) \| (pEflCtx->rflags.u32 & (uint32_t)uValue);
2856	}
2857	/* Special field: Expected value (in/result) exception. */
2858	else if (idxField == BS3CG1DST_VALUE_XCPT)
2859	{
2860	if (!pEflCtx \|\| (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK) != BS3CG1_CTXOP_ASSIGN \|\| cbDst != 1)
2861	return Bs3TestFailed("Invalid BS3CG1DST_VALUE_XCPT usage");
2862	PtrField.pu8 = &pThis->bValueXcpt;
2863	}
2864	/* FPU and FXSAVE format. */
2865	else if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2866	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2867	{
2868	if (!pThis->fWorkExtCtx)
2869	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2870	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2871	}
2872	/** @todo other FPU fields and FPU state formats. */
2873	else
2874	return Bs3TestFailedF("Todo implement me: cbDst=%u idxField=%d offField=%#x", cbDst, idxField, offField);
2875
2876	#ifdef BS3CG1_DEBUG_CTX_MOD
2877	switch (cbDst)
2878	{
2879	case 1:
2880	BS3CG1_DPRINTF(("dbg: modify %s: %#04RX8 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2881	*PtrField.pu8, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2882	break;
2883	case 2:
2884	BS3CG1_DPRINTF(("dbg: modify %s: %#06RX16 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2885	*PtrField.pu16, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2886	break;
2887	case 4:
2888	BS3CG1_DPRINTF(("dbg: modify %s: %#010RX32 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2889	*PtrField.pu32, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2890	break;
2891	default:
2892	BS3CG1_DPRINTF(("dbg: modify %s: %#018RX64 (LB %u) %s %#RX64 (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
2893	*PtrField.pu64, cbDst, Bs3Cg1CtxOpToString(bOpcode), uValue, cbValue));
2894	break;
2895	}
2896	#endif
2897
2898	/* Modify the field. */
2899	switch (cbDst)
2900	{
2901	case 1:
2902	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2903	{
2904	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu8 = (uint8_t)uValue; break;
2905	case BS3CG1_CTXOP_OR: *PtrField.pu8 \|= (uint8_t)uValue; break;
2906	case BS3CG1_CTXOP_AND: *PtrField.pu8 &= (uint8_t)uValue; break;
2907	case BS3CG1_CTXOP_AND_INV: *PtrField.pu8 &= ~(uint8_t)uValue; break;
2908	}
2909	break;
2910
2911	case 2:
2912	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2913	{
2914	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu16 = (uint16_t)uValue; break;
2915	case BS3CG1_CTXOP_OR: *PtrField.pu16 \|= (uint16_t)uValue; break;
2916	case BS3CG1_CTXOP_AND: *PtrField.pu16 &= (uint16_t)uValue; break;
2917	case BS3CG1_CTXOP_AND_INV: *PtrField.pu16 &= ~(uint16_t)uValue; break;
2918	}
2919	break;
2920
2921	case 4:
2922	if ((unsigned)(idxField - BS3CG1DST_XMM0_DW0_ZX) <= (unsigned)(BS3CG1DST_XMM15_DW0_ZX - BS3CG1DST_XMM0_DW0_ZX))
2923	{
2924	PtrField.pu32[1] = 0;
2925	PtrField.pu64[1] = 0;
2926	}
2927	else if (offField <= RT_OFFSETOF(BS3REGCTX, r15)) /* Clear the top dword. */
2928	PtrField.pu32[1] = 0;
2929	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2930	{
2931	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu32 = (uint32_t)uValue; break;
2932	case BS3CG1_CTXOP_OR: *PtrField.pu32 \|= (uint32_t)uValue; break;
2933	case BS3CG1_CTXOP_AND: *PtrField.pu32 &= (uint32_t)uValue; break;
2934	case BS3CG1_CTXOP_AND_INV: *PtrField.pu32 &= ~(uint32_t)uValue; break;
2935	}
2936	break;
2937
2938	case 8:
2939	if ((unsigned)(idxField - BS3CG1DST_XMM0_LO_ZX) <= (unsigned)(BS3CG1DST_XMM15_LO_ZX - BS3CG1DST_XMM0_LO_ZX))
2940	PtrField.pu64[1] = 0;
2941	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
2942	{
2943	case BS3CG1_CTXOP_ASSIGN: *PtrField.pu64 = (uint64_t)uValue; break;
2944	case BS3CG1_CTXOP_OR: *PtrField.pu64 \|= (uint64_t)uValue; break;
2945	case BS3CG1_CTXOP_AND: *PtrField.pu64 &= (uint64_t)uValue; break;
2946	case BS3CG1_CTXOP_AND_INV: *PtrField.pu64 &= ~(uint64_t)uValue; break;
2947	}
2948	break;
2949
2950	default:
2951	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, expected 1, 2, 4, or 8", cbDst);
2952	}
2953
2954	#ifdef BS3CG1_DEBUG_CTX_MOD
2955	switch (cbDst)
2956	{
2957	case 1: BS3CG1_DPRINTF(("dbg: --> %s: %#04RX8\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu8)); break;
2958	case 2: BS3CG1_DPRINTF(("dbg: --> %s: %#06RX16\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu16)); break;
2959	case 4: BS3CG1_DPRINTF(("dbg: --> %s: %#010RX32\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu32)); break;
2960	default: BS3CG1_DPRINTF(("dbg: --> %s: %#018RX64\n", g_aszBs3Cg1DstFields[idxField].sz, *PtrField.pu64)); break;
2961	}
2962	#endif
2963
2964	}
2965	/*
2966	* Deal with larger field (FPU, SSE, AVX, ...).
2967	*/
2968	else
2969	{
2970	union
2971	{
2972	X86FPUREG FpuReg;
2973	X86XMMREG XmmReg;
2974	X86YMMREG YmmReg;
2975	X86ZMMREG ZmmReg;
2976	uint8_t ab[sizeof(X86ZMMREG)];
2977	uint32_t au32[sizeof(X86ZMMREG) / sizeof(uint32_t)];
2978	} Value;
2979	unsigned const offField = g_aoffBs3Cg1DstFields[idxField];
2980
2981	if (!pThis->fWorkExtCtx)
2982	return Bs3TestFailedF("Extended context disabled: Field %d @ %#x LB %u\n", idxField, offField, cbDst);
2983
2984	/* Copy the value into the union, doing the zero padding / extending. */
2985	Bs3MemCpy(&Value, pbCode, cbValue);
2986	if (cbValue < sizeof(Value))
2987	{
2988	if ((bOpcode & BS3CG1_CTXOP_SIGN_EXT) && (Value.ab[cbValue - 1] & 0x80))
2989	Bs3MemSet(&Value.ab[cbValue], 0xff, sizeof(Value) - cbValue);
2990	else
2991	Bs3MemSet(&Value.ab[cbValue], 0x00, sizeof(Value) - cbValue);
2992	}
2993
2994	/* Optimized access to XMM and STx registers. */
2995	if ( pThis->pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT
2996	&& offField - sizeof(BS3REGCTX) <= RT_UOFFSETOF(BS3EXTCTX, Ctx.x87.aXMM[15]) )
2997	PtrField.pb = (uint8_t *)pThis->pExtCtx + offField - sizeof(BS3REGCTX);
2998	/* Non-register operands: */
2999	else if ((unsigned)(idxField - BS3CG1DST_OP1) < 4U)
3000	{
3001	unsigned const idxOp = idxField - BS3CG1DST_OP1;
3002	switch (pThis->aOperands[idxOp].enmLocation)
3003	{
3004	case BS3CG1OPLOC_MEM:
3005	if (!pbInstr)
3006	return Bs3TestFailedF("Read only operand specified in output!");
3007	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
3008	break;
3009
3010	case BS3CG1OPLOC_MEM_RW:
3011	if (pbInstr)
3012	PtrField.pu8 = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[idxOp].off];
3013	else
3014	PtrField.pu8 = pThis->MemOp.ab;
3015	break;
3016
3017	default:
3018	return Bs3TestFailedF("Internal error: Field %d (%d) @ %#x LB %u: enmLocation=%u off=%#x idxField=%u",
3019	idxField, idxOp, offField, cbDst, pThis->aOperands[idxOp].enmLocation,
3020	pThis->aOperands[idxOp].off, pThis->aOperands[idxOp].idxField);
3021	}
3022	}
3023	/* The YMM (AVX) and the first 16 ZMM (AVX512) registers have split storage in
3024	the state, so they need special handling. */
3025	else
3026	{
3027	return Bs3TestFailedF("TODO: implement me: cbDst=%d idxField=%d (AVX and other weird state)", cbDst, idxField);
3028	}
3029
3030	if (PtrField.pb)
3031	{
3032	/* Modify the field / memory. */
3033	unsigned i;
3034	if (cbDst & 3)
3035	return Bs3TestFailedF("Malformed context instruction: cbDst=%u, multiple of 4", cbDst);
3036
3037	#ifdef BS3CG1_DEBUG_CTX_MOD
3038	BS3CG1_DPRINTF(("dbg: modify %s: %.Rhxs (LB %u) %s %.Rhxs (LB %u)\n", g_aszBs3Cg1DstFields[idxField].sz,
3039	cbDst, PtrField.pb, cbDst, Bs3Cg1CtxOpToString(bOpcode), cbValue, Value.ab, cbValue));
3040	#endif
3041
3042	i = cbDst / 4;
3043	while (i-- > 0)
3044	{
3045	switch (bOpcode & BS3CG1_CTXOP_OPERATOR_MASK)
3046	{
3047	case BS3CG1_CTXOP_ASSIGN: PtrField.pu32[i] = Value.au32[i]; break;
3048	case BS3CG1_CTXOP_OR: PtrField.pu32[i] \|= Value.au32[i]; break;
3049	case BS3CG1_CTXOP_AND: PtrField.pu32[i] &= Value.au32[i]; break;
3050	case BS3CG1_CTXOP_AND_INV: PtrField.pu32[i] &= ~Value.au32[i]; break;
3051	}
3052	}
3053
3054	#ifdef BS3CG1_DEBUG_CTX_MOD
3055	BS3CG1_DPRINTF(("dbg: --> %s: %.*Rhxs\n", g_aszBs3Cg1DstFields[idxField].sz, cbDst, PtrField.pb));
3056	#endif
3057	}
3058	}
3059
3060	/*
3061	* Advance to the next instruction.
3062	*/
3063	l_advance_to_next:
3064	pbCode += cbValue;
3065	cbLeft -= cbValue;
3066	}
3067
3068	return true;
3069	}
3070
3071
3072	/**
3073	* Checks the result of a run.
3074	*
3075	* @returns true if successful, false if not.
3076	* @param pThis The state.
3077	* @param bTestXcptExpected The exception causing the test code to stop
3078	* executing.
3079	* @param fInvalidEncodingPgFault Set if we've cut the instruction a byte
3080	* short and is expecting a \#PF on the page
3081	* boundrary rather than a \#UD. Only set if
3082	* fInvalidEncoding is also set.
3083	* @param iEncoding For error reporting.
3084	*/
3085	static bool BS3_NEAR_CODE Bs3Cg1CheckResult(PBS3CG1STATE pThis, uint8_t bTestXcptExpected,
3086	bool fInvalidEncodingPgFault, unsigned iEncoding)
3087	{
3088	unsigned iOperand;
3089
3090	/*
3091	* Check the exception state first.
3092	*/
3093	uint8_t bExpectedXcpt;
3094	uint8_t cbAdjustPc;
3095	if (!pThis->fInvalidEncoding)
3096	{
3097	bExpectedXcpt = pThis->bAlignmentXcpt;
3098	if (bExpectedXcpt == UINT8_MAX)
3099	bExpectedXcpt = pThis->bValueXcpt;
3100	if (bExpectedXcpt == UINT8_MAX)
3101	{
3102	cbAdjustPc = pThis->cbCurInstr;
3103	bExpectedXcpt = bTestXcptExpected;
3104	if (bTestXcptExpected == X86_XCPT_PF)
3105	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
3106	}
3107	else
3108	cbAdjustPc = 0;
3109	}
3110	else
3111	{
3112	cbAdjustPc = 0;
3113	if (!fInvalidEncodingPgFault)
3114	bExpectedXcpt = X86_XCPT_UD;
3115	else
3116	{
3117	bExpectedXcpt = X86_XCPT_PF;
3118	pThis->Ctx.cr2.u = pThis->uCodePgFlat + X86_PAGE_SIZE;
3119	}
3120	}
3121	if (RT_LIKELY( pThis->TrapFrame.bXcpt == bExpectedXcpt
3122	&& pThis->TrapFrame.Ctx.rip.u == pThis->Ctx.rip.u + cbAdjustPc))
3123	{
3124	/*
3125	* Check the register content.
3126	*/
3127	bool fOkay = Bs3TestCheckRegCtxEx(&pThis->TrapFrame.Ctx, &pThis->Ctx,
3128	cbAdjustPc, 0 /cbSpAdjust/, 0 /fExtraEfl/,
3129	pThis->pszMode, iEncoding);
3130
3131	/*
3132	* Check memory output operands.
3133	*/
3134	if (!pThis->fInvalidEncoding)
3135	{
3136	iOperand = pThis->cOperands;
3137	while (iOperand-- > 0)
3138	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
3139	{
3140	if (pThis->aOperands[iOperand].off)
3141	{
3142	BS3PTRUNION PtrUnion;
3143	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
3144	switch (pThis->aOperands[iOperand].cbOp)
3145	{
3146	case 1:
3147	if (*PtrUnion.pu8 == pThis->MemOp.ab[0])
3148	continue;
3149	Bs3TestFailedF("op%u: Wrote %#04RX8, expected %#04RX8",
3150	iOperand, *PtrUnion.pu8, pThis->MemOp.ab[0]);
3151	break;
3152	case 2:
3153	if (*PtrUnion.pu16 == pThis->MemOp.au16[0])
3154	continue;
3155	Bs3TestFailedF("op%u: Wrote %#06RX16, expected %#06RX16",
3156	iOperand, *PtrUnion.pu16, pThis->MemOp.au16[0]);
3157	break;
3158	case 4:
3159	if (*PtrUnion.pu32 == pThis->MemOp.au32[0])
3160	continue;
3161	Bs3TestFailedF("op%u: Wrote %#010RX32, expected %#010RX32",
3162	iOperand, *PtrUnion.pu32, pThis->MemOp.au32[0]);
3163	break;
3164	case 8:
3165	if (*PtrUnion.pu64 == pThis->MemOp.au64[0])
3166	continue;
3167	Bs3TestFailedF("op%u: Wrote %#018RX64, expected %#018RX64",
3168	iOperand, *PtrUnion.pu64, pThis->MemOp.au64[0]);
3169	break;
3170	default:
3171	if (Bs3MemCmp(PtrUnion.pb, pThis->MemOp.ab, pThis->aOperands[iOperand].cbOp) == 0)
3172	continue;
3173	Bs3TestFailedF("op%u: Wrote %.Rhxs, expected %.Rhxs",
3174	iOperand,
3175	pThis->aOperands[iOperand].cbOp, PtrUnion.pb,
3176	pThis->aOperands[iOperand].cbOp, pThis->MemOp.ab);
3177	break;
3178	}
3179	}
3180	else
3181	Bs3TestFailedF("op%u: off is zero\n", iOperand);
3182	fOkay = false;
3183	}
3184	}
3185
3186	/*
3187	* Check extended context if enabled.
3188	*/
3189	if (pThis->fWorkExtCtx)
3190	{
3191	PBS3EXTCTX pExpect = pThis->pExtCtx;
3192	PBS3EXTCTX pResult = pThis->pResultExtCtx;
3193	unsigned i;
3194	if ( pExpect->enmMethod == BS3EXTCTXMETHOD_XSAVE
3195	\|\| pExpect->enmMethod == BS3EXTCTXMETHOD_FXSAVE)
3196	{
3197	/* Compare the x87 state, ASSUMING XCR0 bit 1 is set. */
3198	#define CHECK_FIELD(a_Field, a_szFmt) \
3199	if (pResult->Ctx.a_Field != pExpect->Ctx.a_Field) fOkay = Bs3TestFailedF(a_szFmt, pResult->Ctx.a_Field, pExpect->Ctx.a_Field)
3200	CHECK_FIELD(x87.FCW, "FCW: %#06x, expected %#06x");
3201	CHECK_FIELD(x87.FSW, "FSW: %#06x, expected %#06x");
3202	CHECK_FIELD(x87.FTW, "FTW: %#06x, expected %#06x");
3203	//CHECK_FIELD(x87.FOP, "FOP: %#06x, expected %#06x");
3204	//CHECK_FIELD(x87.FPUIP, "FPUIP: %#010RX32, expected %#010RX32");
3205	//CHECK_FIELD(x87.CS, "FPUCS: %#06x, expected %#06x");
3206	//CHECK_FIELD(x87.Rsrvd1, "Rsrvd1: %#06x, expected %#06x");
3207	//CHECK_FIELD(x87.DP, "FPUDP: %#010RX32, expected %#010RX32");
3208	//CHECK_FIELD(x87.DS, "FPUDS: %#06x, expected %#06x");
3209	//CHECK_FIELD(x87.Rsrvd2, "Rsrvd2: %#06x, expected %#06x");
3210	CHECK_FIELD(x87.MXCSR, "MXCSR: %#010RX32, expected %#010RX32");
3211	#undef CHECK_FIELD
3212	for (i = 0; i < RT_ELEMENTS(pExpect->Ctx.x87.aRegs); i++)
3213	if ( pResult->Ctx.x87.aRegs[i].au64[0] != pExpect->Ctx.x87.aRegs[i].au64[0]
3214	\|\| pResult->Ctx.x87.aRegs[i].au16[4] != pExpect->Ctx.x87.aRegs[i].au16[4])
3215	fOkay = Bs3TestFailedF("ST[%u]: %c m=%#RX64 e=%d, expected %c m=%#RX64 e=%d", i,
3216	pResult->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
3217	pResult->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
3218	pResult->Ctx.x87.aRegs[i].r80Ex.s.uExponent,
3219	pExpect->Ctx.x87.aRegs[i].r80Ex.s.fSign ? '-' : '+',
3220	pExpect->Ctx.x87.aRegs[i].r80Ex.s.u64Mantissa,
3221	pExpect->Ctx.x87.aRegs[i].r80Ex.s.uExponent);
3222	for (i = 0; i < (ARCH_BITS == 64 ? 16 : 8); i++)
3223	if ( pResult->Ctx.x87.aXMM[i].au64[0] != pExpect->Ctx.x87.aXMM[i].au64[0]
3224	\|\| pResult->Ctx.x87.aXMM[i].au64[1] != pExpect->Ctx.x87.aXMM[i].au64[1])
3225	fOkay = Bs3TestFailedF("XMM%u: %#010RX64'%016RX64, expected %#010RX64'%08RX64", i,
3226	pResult->Ctx.x87.aXMM[i].au64[1],
3227	pResult->Ctx.x87.aXMM[i].au64[0],
3228	pExpect->Ctx.x87.aXMM[i].au64[1],
3229	pExpect->Ctx.x87.aXMM[i].au64[0]);
3230	}
3231	else
3232	fOkay = Bs3TestFailedF("Unsupported extended CPU context method: %d", pExpect->enmMethod);
3233	}
3234
3235	/*
3236	* Done.
3237	*/
3238	if (fOkay)
3239	return true;
3240
3241	/*
3242	* Report failure.
3243	*/
3244	Bs3TestFailedF("ins#%RU32/test#%u: encoding #%u: %.*Rhxs%s",
3245	pThis->iInstr, pThis->iTest, iEncoding, pThis->cbCurInstr, pThis->abCurInstr,
3246	fInvalidEncodingPgFault ? " (cut short)" : "");
3247	}
3248	else
3249	Bs3TestFailedF("ins#%RU32/test#%u: bXcpt=%#x expected %#x; rip=%RX64 expected %RX64; encoding#%u: %.*Rhxs%s",
3250	pThis->iInstr, pThis->iTest,
3251	pThis->TrapFrame.bXcpt, bExpectedXcpt,
3252	pThis->TrapFrame.Ctx.rip.u, pThis->Ctx.rip.u + cbAdjustPc,
3253	iEncoding, pThis->cbCurInstr, pThis->abCurInstr, fInvalidEncodingPgFault ? " (cut short)" : "");
3254	Bs3TestPrintf("cpl=%u cbOperands=%u\n", pThis->uCpl, pThis->cbOperand);
3255
3256	/*
3257	* Display memory operands.
3258	*/
3259	for (iOperand = 0; iOperand < pThis->cOperands; iOperand++)
3260	{
3261	BS3PTRUNION PtrUnion;
3262	switch (pThis->aOperands[iOperand].enmLocation)
3263	{
3264	case BS3CG1OPLOC_CTX:
3265	{
3266	uint8_t idxField = pThis->aOperands[iOperand].idxField;
3267	unsigned offField = g_aoffBs3Cg1DstFields[idxField];
3268	if (offField <= sizeof(BS3REGCTX))
3269	PtrUnion.pb = (uint8_t BS3_FAR *)&pThis->Ctx + offField;
3270	else
3271	{
3272	Bs3TestPrintf("op%u: ctx%u: xxxx\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
3273	break;
3274	}
3275	switch (pThis->aOperands[iOperand].cbOp)
3276	{
3277	case 1: Bs3TestPrintf("op%u: ctx08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3278	case 2: Bs3TestPrintf("op%u: ctx16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3279	case 4: Bs3TestPrintf("op%u: ctx32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3280	case 8: Bs3TestPrintf("op%u: ctx64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3281	default:
3282	Bs3TestPrintf("op%u: ctx%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3283	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3284	break;
3285	}
3286	break;
3287	}
3288
3289	case BS3CG1OPLOC_IMM:
3290	PtrUnion.pb = &pThis->pbCodePg[pThis->aOperands[iOperand].off];
3291	switch (pThis->aOperands[iOperand].cbOp)
3292	{
3293	case 1: Bs3TestPrintf("op%u: imm08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3294	case 2: Bs3TestPrintf("op%u: imm16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3295	case 4: Bs3TestPrintf("op%u: imm32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3296	case 8: Bs3TestPrintf("op%u: imm64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3297	default:
3298	Bs3TestPrintf("op%u: imm%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3299	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3300	break;
3301	}
3302	break;
3303
3304	case BS3CG1OPLOC_MEM:
3305	case BS3CG1OPLOC_MEM_RW:
3306	if (pThis->aOperands[iOperand].off)
3307	{
3308	PtrUnion.pb = &pThis->pbDataPg[X86_PAGE_SIZE - pThis->aOperands[iOperand].off];
3309	switch (pThis->aOperands[iOperand].cbOp)
3310	{
3311	case 1: Bs3TestPrintf("op%u: result mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3312	case 2: Bs3TestPrintf("op%u: result mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3313	case 4: Bs3TestPrintf("op%u: result mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3314	case 8: Bs3TestPrintf("op%u: result mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3315	default:
3316	Bs3TestPrintf("op%u: result mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3317	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3318	break;
3319	}
3320	if (pThis->aOperands[iOperand].enmLocation == BS3CG1OPLOC_MEM_RW)
3321	{
3322	PtrUnion.pb = pThis->MemOp.ab;
3323	switch (pThis->aOperands[iOperand].cbOp)
3324	{
3325	case 1: Bs3TestPrintf("op%u: expect mem08: %#04RX8\n", iOperand, *PtrUnion.pu8); break;
3326	case 2: Bs3TestPrintf("op%u: expect mem16: %#06RX16\n", iOperand, *PtrUnion.pu16); break;
3327	case 4: Bs3TestPrintf("op%u: expect mem32: %#010RX32\n", iOperand, *PtrUnion.pu32); break;
3328	case 8: Bs3TestPrintf("op%u: expect mem64: %#018RX64\n", iOperand, *PtrUnion.pu64); break;
3329	default:
3330	Bs3TestPrintf("op%u: expect mem%u: %.Rhxs\n", iOperand, pThis->aOperands[iOperand].cbOp 8,
3331	pThis->aOperands[iOperand].cbOp, PtrUnion.pb);
3332	break;
3333	}
3334	}
3335	}
3336	else
3337	Bs3TestPrintf("op%u: mem%u: zero off value!!\n", iOperand, pThis->aOperands[iOperand].cbOp * 8);
3338	break;
3339	}
3340	}
3341
3342	/*
3343	* Display contexts.
3344	*/
3345	Bs3TestPrintf("-- Expected context:\n");
3346	Bs3RegCtxPrint(&pThis->Ctx);
3347	if (pThis->fWorkExtCtx)
3348	Bs3TestPrintf("xcr0=%RX64\n", pThis->pExtCtx->fXcr0Saved);
3349	Bs3TestPrintf("-- Actual context:\n");
3350	Bs3TrapPrintFrame(&pThis->TrapFrame);
3351	if (pThis->fWorkExtCtx)
3352	Bs3TestPrintf("xcr0=%RX64\n", pThis->pResultExtCtx->fXcr0Saved);
3353	Bs3TestPrintf("\n");
3354	return false;
3355	}
3356
3357
3358	/**
3359	* Destroys the state, freeing all allocations and such.
3360	*
3361	* @param pThis The state.
3362	*/
3363	static void BS3_NEAR_CODE Bs3Cg1Destroy(PBS3CG1STATE pThis)
3364	{
3365	if (BS3_MODE_IS_PAGED(pThis->bMode))
3366	{
3367	#if ARCH_BITS != 16
3368	Bs3MemGuardedTestPageFree(pThis->pbCodePg);
3369	Bs3MemGuardedTestPageFree(pThis->pbDataPg);
3370	#endif
3371	}
3372	else
3373	{
3374	Bs3MemFree(pThis->pbCodePg, X86_PAGE_SIZE);
3375	Bs3MemFree(pThis->pbDataPg, X86_PAGE_SIZE);
3376	}
3377
3378	if (pThis->pExtCtx)
3379	Bs3MemFree(pThis->pExtCtx, pThis->pExtCtx->cb * 3);
3380
3381	pThis->pbCodePg = NULL;
3382	pThis->pbDataPg = NULL;
3383	pThis->pExtCtx = NULL;
3384	pThis->pResultExtCtx = NULL;
3385	pThis->pInitialExtCtx = NULL;
3386	}
3387
3388
3389	/**
3390	* Initializes the state.
3391	*
3392	* @returns Success indicator (true/false)
3393	* @param pThis The state.
3394	* @param bMode The mode being tested.
3395	*/
3396	bool BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1Init)(PBS3CG1STATE pThis, uint8_t bMode)
3397	{
3398	BS3MEMKIND const enmMemKind = BS3_MODE_IS_RM_OR_V86(bMode) ? BS3MEMKIND_REAL
3399	: !BS3_MODE_IS_64BIT_CODE(bMode) ? BS3MEMKIND_TILED : BS3MEMKIND_FLAT32;
3400	unsigned iRing;
3401	unsigned cb;
3402	unsigned i;
3403	uint64_t fFlags;
3404	PBS3EXTCTX pExtCtx;
3405
3406	Bs3MemSet(pThis, 0, sizeof(*pThis));
3407
3408	pThis->iFirstRing = BS3_MODE_IS_V86(bMode) ? 3 : 0;
3409	pThis->iEndRing = BS3_MODE_IS_RM_SYS(bMode) ? 1 : 4;
3410	pThis->bMode = bMode;
3411	pThis->pszMode = Bs3GetModeName(bMode);
3412	pThis->pszModeShort = Bs3GetModeNameShortLower(bMode);
3413	pThis->bCpuVendor = Bs3GetCpuVendor();
3414	pThis->pchMnemonic = g_achBs3Cg1Mnemonics;
3415	pThis->pabOperands = g_abBs3Cg1Operands;
3416	pThis->pabOpcodes = g_abBs3Cg1Opcodes;
3417	pThis->fAdvanceMnemonic = 1;
3418
3419	/* Allocate extended context structures. */
3420	cb = Bs3ExtCtxGetSize(&fFlags);
3421	pExtCtx = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 3);
3422	if (!pExtCtx)
3423	return Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 3);
3424	pThis->pExtCtx = pExtCtx;
3425	pThis->pResultExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb);
3426	pThis->pInitialExtCtx = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx + cb + cb);
3427
3428	Bs3ExtCtxInit(pThis->pExtCtx, cb, fFlags);
3429	Bs3ExtCtxInit(pThis->pResultExtCtx, cb, fFlags);
3430	Bs3ExtCtxInit(pThis->pInitialExtCtx, cb, fFlags);
3431	//Bs3TestPrintf("fCR0=%RX64 cbExtCtx=%#x method=%d\n", fFlags, cb, pExtCtx->enmMethod);
3432
3433	/* Allocate guarded exectuable and data memory. */
3434	if (BS3_MODE_IS_PAGED(bMode))
3435	{
3436	#if ARCH_BITS != 16
3437	pThis->pbCodePg = Bs3MemGuardedTestPageAlloc(enmMemKind);
3438	pThis->pbDataPg = Bs3MemGuardedTestPageAlloc(enmMemKind);
3439	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
3440	{
3441	Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
3442	Bs3MemPrintInfo();
3443	Bs3Shutdown();
3444	return Bs3TestFailedF("Bs3MemGuardedTestPageAlloc(%d) failed", enmMemKind);
3445	}
3446	if ( BS3_MODE_IS_64BIT_CODE(bMode)
3447	&& (uintptr_t)pThis->pbDataPg >= _2G)
3448	return Bs3TestFailedF("pbDataPg=%p is above 2GB and not simple to address from 64-bit code", pThis->pbDataPg);
3449	#else
3450	return Bs3TestFailed("WTF?! #1");
3451	#endif
3452	}
3453	else
3454	{
3455	pThis->pbCodePg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
3456	pThis->pbDataPg = Bs3MemAlloc(enmMemKind, X86_PAGE_SIZE);
3457	if (!pThis->pbCodePg \|\| !pThis->pbDataPg)
3458	{
3459	Bs3MemPrintInfo();
3460	return Bs3TestFailedF("Bs3MemAlloc(%d,Pg) failed", enmMemKind);
3461	}
3462	}
3463	pThis->uCodePgFlat = Bs3SelPtrToFlat(pThis->pbCodePg);
3464	pThis->uDataPgFlat = Bs3SelPtrToFlat(pThis->pbDataPg);
3465	#if ARCH_BITS == 16
3466	pThis->CodePgFar.sel = BS3_FP_SEG(pThis->pbCodePg);
3467	pThis->CodePgFar.off = BS3_FP_OFF(pThis->pbCodePg);
3468	pThis->CodePgRip = BS3_FP_OFF(pThis->pbCodePg);
3469	pThis->DataPgFar.sel = BS3_FP_SEG(pThis->pbDataPg);
3470	pThis->DataPgFar.off = BS3_FP_OFF(pThis->pbDataPg);
3471	#else
3472	if (BS3_MODE_IS_RM_OR_V86(bMode))
3473	{
3474	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToRealMode(pThis->uDataPgFlat);
3475	ASMCompilerBarrier();
3476	pThis->CodePgFar.off = 0;
3477	pThis->CodePgFar.sel = pThis->uCodePgFlat >> 4;
3478	pThis->CodePgRip = pThis->CodePgFar.off;
3479	}
3480	else if (BS3_MODE_IS_16BIT_CODE(bMode))
3481	{
3482	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
3483	ASMCompilerBarrier();
3484	pThis->CodePgFar.sel = BS3_SEL_SPARE_00;
3485	pThis->CodePgFar.off = 0;
3486	pThis->CodePgRip = 0;
3487	}
3488	else if (BS3_MODE_IS_32BIT_CODE(bMode))
3489	{
3490	(uint32_t )&pThis->DataPgFar = Bs3SelFlatDataToProtFar16(pThis->uDataPgFlat);
3491	ASMCompilerBarrier();
3492	pThis->CodePgFar.sel = 0;
3493	pThis->CodePgFar.off = 0;
3494	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
3495	}
3496	else
3497	{
3498	pThis->DataPgFar.off = 0;
3499	pThis->DataPgFar.sel = 0;
3500	pThis->CodePgFar.off = 0;
3501	pThis->CodePgFar.sel = 0;
3502	pThis->CodePgRip = (uintptr_t)pThis->pbCodePg;
3503	}
3504	#endif
3505	BS3CG1_DPRINTF(("pbDataPg=%p %04x:%04x pbCodePg=%p %04x:%04x\n",
3506	pThis->pbDataPg, pThis->DataPgFar.sel, pThis->DataPgFar.off,
3507	pThis->pbCodePg, pThis->CodePgFar.sel, pThis->CodePgFar.off));
3508
3509	/*
3510	* Create basic context for each target ring.
3511	*
3512	* In protected 16-bit code we need set up code selectors that can access
3513	* pbCodePg.
3514	*
3515	* In long mode we make sure the high 32-bits of GPRs (sans RSP) have some
3516	* bits set so we can check that the implicit clearing is tested.
3517	*/
3518	Bs3RegCtxSaveEx(&pThis->aInitialCtxs[pThis->iFirstRing], bMode, 1024 * 3);
3519	#if ARCH_BITS == 64
3520	pThis->aInitialCtxs[pThis->iFirstRing].rax.u \|= UINT64_C(0x0101010100000000);
3521	pThis->aInitialCtxs[pThis->iFirstRing].rbx.u \|= UINT64_C(0x0202020200000000);
3522	pThis->aInitialCtxs[pThis->iFirstRing].rcx.u \|= UINT64_C(0x0303030300000000);
3523	pThis->aInitialCtxs[pThis->iFirstRing].rdx.u \|= UINT64_C(0x0404040400000000);
3524	pThis->aInitialCtxs[pThis->iFirstRing].rbp.u \|= UINT64_C(0x0505050500000000);
3525	pThis->aInitialCtxs[pThis->iFirstRing].rdi.u \|= UINT64_C(0x0606060600000000);
3526	pThis->aInitialCtxs[pThis->iFirstRing].rsi.u \|= UINT64_C(0x0707070700000000);
3527	pThis->aInitialCtxs[pThis->iFirstRing].r8.u \|= UINT64_C(0x0808080800000000);
3528	pThis->aInitialCtxs[pThis->iFirstRing].r9.u \|= UINT64_C(0x0909090900000000);
3529	pThis->aInitialCtxs[pThis->iFirstRing].r10.u \|= UINT64_C(0x1010101000000000);
3530	pThis->aInitialCtxs[pThis->iFirstRing].r11.u \|= UINT64_C(0x1111111100000000);
3531	pThis->aInitialCtxs[pThis->iFirstRing].r12.u \|= UINT64_C(0x1212121200000000);
3532	pThis->aInitialCtxs[pThis->iFirstRing].r13.u \|= UINT64_C(0x1313131300000000);
3533	pThis->aInitialCtxs[pThis->iFirstRing].r14.u \|= UINT64_C(0x1414141400000000);
3534	pThis->aInitialCtxs[pThis->iFirstRing].r15.u \|= UINT64_C(0x1515151500000000);
3535	#endif
3536
3537	if (BS3_MODE_IS_RM_OR_V86(bMode))
3538	{
3539	pThis->aInitialCtxs[pThis->iFirstRing].cs = pThis->CodePgFar.sel;
3540	BS3_ASSERT(pThis->iFirstRing + 1 == pThis->iEndRing);
3541	}
3542	else if (BS3_MODE_IS_16BIT_CODE(bMode))
3543	{
3544	#if ARCH_BITS == 16
3545	uintptr_t const uFlatCodePgSeg = Bs3SelPtrToFlat(BS3_FP_MAKE(BS3_FP_SEG(pThis->pbCodePg), 0));
3546	#else
3547	uintptr_t const uFlatCodePgSeg = (uintptr_t)pThis->pbCodePg;
3548	#endif
3549	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3550	{
3551	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3552	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3553	}
3554	for (iRing = pThis->iFirstRing; iRing < pThis->iEndRing; iRing++)
3555	{
3556	pThis->aInitialCtxs[iRing].cs = BS3_SEL_SPARE_00 + iRing * 8 + iRing;
3557	Bs3SelSetup16BitCode(&Bs3GdteSpare00 + iRing, uFlatCodePgSeg, iRing);
3558	}
3559	}
3560	else
3561	{
3562	Bs3RegCtxSetRipCsFromCurPtr(&pThis->aInitialCtxs[pThis->iFirstRing], (FPFNBS3FAR)pThis->pbCodePg);
3563	for (iRing = pThis->iFirstRing + 1; iRing < pThis->iEndRing; iRing++)
3564	{
3565	Bs3MemCpy(&pThis->aInitialCtxs[iRing], &pThis->aInitialCtxs[pThis->iFirstRing], sizeof(pThis->aInitialCtxs[iRing]));
3566	Bs3RegCtxConvertToRingX(&pThis->aInitialCtxs[iRing], iRing);
3567	}
3568	}
3569
3570	/*
3571	* Create an initial extended CPU context.
3572	*/
3573	pExtCtx = pThis->pInitialExtCtx;
3574	if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE
3575	\|\| pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE)
3576	{
3577	pExtCtx->Ctx.x87.FCW = X86_FCW_MASK_ALL \| X86_FCW_PC_64 \| X86_FCW_RC_NEAREST;
3578	pExtCtx->Ctx.x87.FSW = 0;
3579	pExtCtx->Ctx.x87.MXCSR = X86_MXCSR_IM \| X86_MXCSR_DM \| X86_MXCSR_RC_NEAREST;
3580	pExtCtx->Ctx.x87.MXCSR_MASK = 0;
3581	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aRegs); i++)
3582	{
3583	pExtCtx->Ctx.x87.aRegs[i].au16[0] = i << 4;
3584	pExtCtx->Ctx.x87.aRegs[i].au16[1] = i << 4;
3585	pExtCtx->Ctx.x87.aRegs[i].au16[2] = i << 4;
3586	pExtCtx->Ctx.x87.aRegs[i].au16[3] = i << 4;
3587	}
3588	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x87.aXMM); i++)
3589	{
3590	pExtCtx->Ctx.x87.aXMM[i].au16[0] = i;
3591	pExtCtx->Ctx.x87.aXMM[i].au16[1] = i;
3592	pExtCtx->Ctx.x87.aXMM[i].au16[2] = i;
3593	pExtCtx->Ctx.x87.aXMM[i].au16[3] = i;
3594	pExtCtx->Ctx.x87.aXMM[i].au16[4] = i;
3595	pExtCtx->Ctx.x87.aXMM[i].au16[5] = i;
3596	pExtCtx->Ctx.x87.aXMM[i].au16[6] = i;
3597	pExtCtx->Ctx.x87.aXMM[i].au16[7] = i;
3598	}
3599	if (pExtCtx->fXcr0Nominal & XSAVE_C_YMM)
3600	for (i = 0; i < RT_ELEMENTS(pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi); i++)
3601	{
3602	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[0] = i << 8;
3603	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[1] = i << 8;
3604	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[2] = i << 8;
3605	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[3] = i << 8;
3606	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[4] = i << 8;
3607	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[5] = i << 8;
3608	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[6] = i << 8;
3609	pExtCtx->Ctx.x.u.Intel.YmmHi.aYmmHi[i].au16[7] = i << 8;
3610	}
3611
3612	}
3613	//else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_ANCIENT)
3614	else
3615	return Bs3TestFailedF("Unsupported extended CPU context method: %d", pExtCtx->enmMethod);
3616
3617	return true;
3618	}
3619
3620
3621	static uint8_t BS3_NEAR_CODE BS3_CMN_NM(Bs3Cg1WorkerInner)(PBS3CG1STATE pThis)
3622	{
3623	uint8_t iRing;
3624	unsigned iInstr;
3625
3626	/*
3627	* Test the instructions.
3628	*/
3629	for (iInstr = 0; iInstr < g_cBs3Cg1Instructions;
3630	iInstr++,
3631	pThis->pchMnemonic += pThis->fAdvanceMnemonic * pThis->cchMnemonic,
3632	pThis->pabOperands += pThis->cOperands,
3633	pThis->pabOpcodes += pThis->cbOpcodes)
3634	{
3635	uint8_t const bTestXcptExpected = BS3_MODE_IS_PAGED(pThis->bMode) ? X86_XCPT_PF : X86_XCPT_UD;
3636	bool fOuterInvalidInstr = false;
3637	unsigned iCpuSetup;
3638
3639	/*
3640	* Expand the instruction information into the state.
3641	* Note! 16-bit will switch to a two level test header lookup once we exceed 64KB.
3642	*/
3643	PCBS3CG1INSTR pInstr = &g_aBs3Cg1Instructions[iInstr];
3644	pThis->iInstr = iInstr;
3645	pThis->pTestHdr = (PCBS3CG1TESTHDR)&g_abBs3Cg1Tests[pInstr->offTests];
3646	pThis->fFlags = pInstr->fFlags;
3647	pThis->enmEncoding = (BS3CG1ENC)pInstr->enmEncoding;
3648	pThis->enmEncodingNonInvalid = (BS3CG1ENC)pInstr->enmEncoding;
3649	pThis->enmCpuTest = (BS3CG1CPU)pInstr->enmCpuTest;
3650	pThis->enmPrefixKind = (BS3CG1PFXKIND)pInstr->enmPrefixKind;
3651	pThis->enmXcptType = (BS3CG1XCPTTYPE)pInstr->enmXcptType;
3652	pThis->cchMnemonic = pInstr->cchMnemonic;
3653	if (pThis->fAdvanceMnemonic)
3654	Bs3TestSubF("%s / %.*s", pThis->pszModeShort, pThis->cchMnemonic, pThis->pchMnemonic);
3655	pThis->fAdvanceMnemonic = pInstr->fAdvanceMnemonic;
3656	pThis->cOperands = pInstr->cOperands;
3657	pThis->cbOpcodes = pInstr->cbOpcodes;
3658	switch (pThis->cOperands)
3659	{
3660	case 4: pThis->aenmOperands[3] = (BS3CG1OP)pThis->pabOperands[3];
3661	case 3: pThis->aenmOperands[2] = (BS3CG1OP)pThis->pabOperands[2];
3662	case 2: pThis->aenmOperands[1] = (BS3CG1OP)pThis->pabOperands[1];
3663	case 1: pThis->aenmOperands[0] = (BS3CG1OP)pThis->pabOperands[0];
3664	}
3665	switch (pThis->cbOpcodes)
3666	{
3667	case 4: pThis->abOpcodes[3] = pThis->pabOpcodes[3];
3668	case 3: pThis->abOpcodes[2] = pThis->pabOpcodes[2];
3669	case 2: pThis->abOpcodes[1] = pThis->pabOpcodes[1];
3670	case 1: pThis->abOpcodes[0] = pThis->pabOpcodes[0];
3671	}
3672
3673	/*
3674	* Check if the CPU supports the instruction.
3675	*/
3676	if ( !Bs3Cg1CpuSetupFirst(pThis)
3677	\|\| (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID)))
3678	fOuterInvalidInstr = true;
3679
3680	/* Switch the encoder for some of the invalid instructions on non-intel CPUs. */
3681	if ( (pThis->fFlags & BS3CG1INSTR_F_INTEL_DECODES_INVALID)
3682	&& pThis->bCpuVendor != BS3CPUVENDOR_INTEL
3683	&& ( (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
3684	\|\| (BS3_MODE_IS_64BIT_CODE(pThis->bMode) && (pThis->fFlags & BS3CG1INSTR_F_INVALID_64BIT))
3685	\|\| fOuterInvalidInstr ) )
3686	pThis->enmEncoding = Bs3Cg1CalcNoneIntelInvalidEncoding(pThis->enmEncoding);
3687
3688	for (iCpuSetup = 0;; iCpuSetup++)
3689	{
3690	unsigned iEncoding;
3691	unsigned iEncodingNext;
3692
3693	/*
3694	* Prep the operands and encoding handling.
3695	*/
3696	if (!Bs3Cg1EncodePrep(pThis))
3697	break;
3698
3699	/*
3700	* Encode the instruction in various ways and check out the test values.
3701	*/
3702	for (iEncoding = 0;; iEncoding = iEncodingNext)
3703	{
3704	/*
3705	* Encode the next instruction variation.
3706	*/
3707	pThis->fInvalidEncoding = fOuterInvalidInstr;
3708	iEncodingNext = Bs3Cg1EncodeNext(pThis, iEncoding);
3709	if (iEncodingNext <= iEncoding)
3710	break;
3711	BS3CG1_DPRINTF(("\ndbg: Encoding #%u: cbCurInst=%u: %.*Rhxs fInvalidEncoding=%d\n",
3712	iEncoding, pThis->cbCurInstr, pThis->cbCurInstr, pThis->abCurInstr, pThis->fInvalidEncoding));
3713
3714	/*
3715	* Do the rings.
3716	*/
3717	for (iRing = pThis->iFirstRing + pThis->fSameRingNotOkay; iRing < pThis->iEndRing; iRing++)
3718	{
3719	PCBS3CG1TESTHDR pHdr;
3720
3721	pThis->uCpl = iRing;
3722	BS3CG1_DPRINTF(("dbg: Ring %u\n", iRing));
3723
3724	/*
3725	* Do the tests one by one.
3726	*/
3727	pHdr = pThis->pTestHdr;
3728	for (pThis->iTest = 0;; pThis->iTest++)
3729	{
3730	if (Bs3Cg1RunSelector(pThis, pHdr))
3731	{
3732	/* Okay, set up the execution context. */
3733	unsigned offCode;
3734	uint8_t BS3_FAR *pbCode;
3735
3736	Bs3MemCpy(&pThis->Ctx, &pThis->aInitialCtxs[iRing], sizeof(pThis->Ctx));
3737	if (pThis->fWorkExtCtx)
3738	Bs3ExtCtxCopy(pThis->pExtCtx, pThis->pInitialExtCtx);
3739	if (BS3_MODE_IS_PAGED(pThis->bMode))
3740	{
3741	offCode = X86_PAGE_SIZE - pThis->cbCurInstr;
3742	pbCode = &pThis->pbCodePg[offCode];
3743	//if (iEncoding > 0) { pbCode[-1] = 0xf4; offCode--; }
3744	}
3745	else
3746	{
3747	pbCode = pThis->pbCodePg;
3748	pbCode[pThis->cbCurInstr] = 0x0f; /* UD2 */
3749	pbCode[pThis->cbCurInstr + 1] = 0x0b;
3750	offCode = 0;
3751	}
3752	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3753	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr);
3754
3755	if (Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr, pHdr->cbSelector, pHdr->cbInput, NULL, pbCode))
3756	{
3757	/* Run the instruction. */
3758	BS3CG1_DPRINTF(("dbg: Running test #%u\n", pThis->iTest));
3759	//Bs3RegCtxPrint(&pThis->Ctx);
3760	if (pThis->fWorkExtCtx)
3761	Bs3ExtCtxRestore(pThis->pExtCtx);
3762	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3763	if (pThis->fWorkExtCtx)
3764	Bs3ExtCtxSave(pThis->pResultExtCtx);
3765	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64\n",
3766	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3767
3768	/*
3769	* Apply the output modification program to the context.
3770	*/
3771	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3772	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3773	pThis->bValueXcpt = UINT8_MAX; //???
3774	if ( pThis->fInvalidEncoding
3775	\|\| pThis->bAlignmentXcpt != UINT8_MAX
3776	\|\| pThis->bValueXcpt != UINT8_MAX
3777	\|\| Bs3Cg1RunContextModifier(pThis, &pThis->Ctx, pHdr,
3778	pHdr->cbSelector + pHdr->cbInput, pHdr->cbOutput,
3779	&pThis->TrapFrame.Ctx, NULL /pbCode/))
3780	{
3781	Bs3Cg1CheckResult(pThis, bTestXcptExpected, false /fInvalidEncodingPgFault/, iEncoding);
3782	}
3783
3784	/*
3785	* If this is an invalid encoding or instruction, check that we
3786	* get a page fault when shortening it by one byte.
3787	* (Since we didn't execute the output context modifier, we don't
3788	* need to re-initialize the start context.)
3789	*/
3790	if ( pThis->fInvalidEncoding
3791	&& BS3_MODE_IS_PAGED(pThis->bMode)
3792	&& pThis->cbCurInstr)
3793	{
3794	pbCode += 1;
3795	offCode += 1;
3796	pThis->Ctx.rip.u = pThis->CodePgRip + offCode;
3797	Bs3MemCpy(pbCode, pThis->abCurInstr, pThis->cbCurInstr - 1);
3798
3799	/* Run the instruction. */
3800	BS3CG1_DPRINTF(("dbg: Running test #%u (cut short #PF)\n", pThis->iTest));
3801	//Bs3RegCtxPrint(&pThis->Ctx);
3802	if (pThis->fWorkExtCtx)
3803	Bs3ExtCtxRestore(pThis->pExtCtx);
3804	Bs3TrapSetJmpAndRestore(&pThis->Ctx, &pThis->TrapFrame);
3805	if (pThis->fWorkExtCtx)
3806	Bs3ExtCtxSave(pThis->pResultExtCtx);
3807	BS3CG1_DPRINTF(("dbg: bXcpt=%#x rip=%RX64 -> %RX64 (cut short #PF)\n",
3808	pThis->TrapFrame.bXcpt, pThis->Ctx.rip.u, pThis->TrapFrame.Ctx.rip.u));
3809
3810	/* Check it */
3811	pThis->Ctx.rflags.u32 &= ~X86_EFL_RF;
3812	pThis->Ctx.rflags.u32 \|= pThis->TrapFrame.Ctx.rflags.u32 & X86_EFL_RF;
3813	Bs3Cg1CheckResult(pThis, X86_XCPT_PF, true /fInvalidEncodingPgFault/, iEncoding);
3814	}
3815	}
3816	}
3817	else
3818	BS3CG1_DPRINTF(("dbg: Skipping #%u\n", pThis->iTest));
3819
3820	/* advance */
3821	if (pHdr->fLast)
3822	{
3823	BS3CG1_DPRINTF(("dbg: Last\n\n"));
3824	break;
3825	}
3826	pHdr = (PCBS3CG1TESTHDR)((uint8_t BS3_FAR *)(pHdr + 1) + pHdr->cbInput + pHdr->cbOutput + pHdr->cbSelector);
3827	}
3828	}
3829	}
3830
3831	/*
3832	* Clean up (segment registers, etc) and get the next CPU config.
3833	*/
3834	Bs3Cg1EncodeCleanup(pThis);
3835	if (!Bs3Cg1CpuSetupNext(pThis, iCpuSetup, &fOuterInvalidInstr))
3836	break;
3837	if (pThis->fFlags & (BS3CG1INSTR_F_UNUSED \| BS3CG1INSTR_F_INVALID))
3838	fOuterInvalidInstr = true;
3839	}
3840	}
3841
3842	return 0;
3843	}
3844
3845
3846	BS3_DECL_FAR(uint8_t) BS3_CMN_NM(Bs3Cg1Worker)(uint8_t bMode)
3847	{
3848	uint8_t bRet = 1;
3849	BS3CG1STATE This;
3850
3851	#if 0
3852	/* (for debugging) */
3853	if (bMode != BS3_MODE_PP32)
3854	return BS3TESTDOMODE_SKIPPED;
3855	#endif
3856
3857	if (BS3_CMN_NM(Bs3Cg1Init)(&This, bMode))
3858	{
3859	bRet = BS3_CMN_NM(Bs3Cg1WorkerInner)(&This);
3860	Bs3TestSubDone();
3861	}
3862	Bs3Cg1Destroy(&This);
3863
3864	#if 0
3865	/* (for debugging) */
3866	//if (bMode == BS3_MODE_PP32)
3867	{
3868	Bs3TestTerm();
3869	Bs3Shutdown();
3870	}
3871	#endif
3872	return bRet;
3873	}
3874

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source: vbox/trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-generated-1-template.c@ 66744

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