Changeset 102986 in vbox for trunk/include/iprt/x86.h

Timestamp:

Jan 22, 2024 10:03:37 AM (10 months ago)

Author:

vboxsync

Message:

x86.h: bugref:10318 CPUID and MSR bits for upcoming logging of split-lock disable status on host.

File:

• trunk/include/iprt/x86.h (modified) (3 diffs)

trunk/include/iprt/x86.h

@@ -709 +709 @@
 /** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
 #define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
+/** EDX Bit 30 - CORECAP - Supports the IA32_CORE_CAPABILITIES MSR. */
+#define X86_CPUID_STEXT_FEATURE_EDX_CORECAP           RT_BIT_32(30)
 /** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
 #define X86_CPUID_STEXT_FEATURE_EDX_SSBD              RT_BIT_32(31)
@@ -1312 +1314 @@
 #endif
 
+/** Memory Control (Intel-specific). */
+#define MSR_MEMORY_CTRL                     0x33
+/** Memory Control - UC-store throttle. */
+#define MSR_MEMORY_CTRL_UC_STORE_THROTTLE           RT_BIT_64(27)
+/** Memory Control - UC-lock disable. */
+#define MSR_MEMORY_CTRL_UC_LOCK_DISABLE             RT_BIT_64(28)
+/** Memory Control - Split-lock disable. */
+#define MSR_MEMORY_CTRL_SPLIT_LOCK_DISABLE          RT_BIT_64(29)
+
 /** Undocumented intel MSR for reporting thread and core counts.
  * Judging from the XNU sources, it seems to be introduced in Nehalem. The
@@ -1399 +1410 @@
 /** Nehalem power control. */
 #define MSR_IA32_PLATFORM_INFO              0xCE
+
+/** Core Capabilities (Intel-specific). */
+#define MSR_IA32_CORE_CAPABILITIES          0xCF
+/** STLB QoS feature supported. */
+#define MSR_IA32_CORE_CAP_STLB_QOS                  RT_BIT_64(0)
+/** FUSA feature supported. */
+#define MSR_IA32_CORE_CAP_FUSA                      RT_BIT_64(2)
+/** RSM instruction only allowed in CPL 0. */
+#define MSR_IA32_CORE_CAP_RSM_CPL0                  RT_BIT_64(3)
+/** UC lock disable supported. */
+#define MSR_IA32_CORE_CAP_UC_LOCK_DISABLE           RT_BIT_64(4)
+/** Split-lock disable supported. */
+#define MSR_IA32_CORE_CAP_SPLIT_LOCK_DISABLE        RT_BIT_64(5)
+/** Snoop filter QoS Mask MSRs supported. */
+#define MSR_IA32_CORE_CAP_SNOOP_FILTER_QOS          RT_BIT_64(6)
+/** UC store throttling supported. */
+#define MSR_IA32_CORE_CAP_UC_STORE_THROTTLE         RT_BIT_64(7)
 
 /** Get FSB clock status (Intel-specific). */