Changeset 104015 in vbox for trunk

Timestamp:

Mar 23, 2024 2:04:08 AM (12 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

162403

Message:

ValKit/bs3-cpu-instr-2: update docs on odd rol/ror behaviour. bugref:10376

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-2-gen.cpp (modified) (2 diffs)
• bs3-cpu-instr-2-template.c (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-gen.cpp

@@ -568 +568 @@
                                              uSrc1, uSrc2, uResult, fEflOut); \
                             else \
-                            {   /* Seems that 'rol reg,Ib' (and possibly others) produces different OF results on intel. */ \
+                            { \
+                                /* Seems that 'rol reg,Ib' & 'ror reg,Ib' produces different OF results on intel. \
+                                   Observed on 8700B, 9980HK, 10980xe, 1260p, ++. */ \
                                 a_ValueType    uResultIb = 0; \
                                 uint32_t const fEflOutIb = a_Entry.a_pfnMemberIb(uSrc1, uSrc2, fEflIn, &uResultIb) \
@@ -590 +592 @@
                                                  uResult, (uint16_t)(fEflOut | RT_BIT_32(BS3CPUINSTR2BIN_EFL_CARRY_IN_BIT))); \
                                 else \
-                                {   /* Seems that 'rol reg,Ib' (and possibly others) produces different OF results on intel. */ \
+                                { \
+                                    /* Seems that 'rol reg,Ib' & 'ror reg,Ib' produces different OF results on intel. \
+                                       Observed on 8700B, 9980HK, 10980xe, 1260p, ++. */ \
                                     a_ValueType    uResultIb = 0; \
                                     uint32_t const fEflOutIb = a_Entry.a_pfnMemberIb(uSrc1, uSrc2, fEflIn | X86_EFL_CF, &uResultIb) \

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-2-template.c

@@ -1021 +1021 @@
                 CtxExpect.rflags.u16 &= ~X86_EFL_STATUS_BITS; \
                 CtxExpect.rflags.u16 |= paTestData[iTestData].fEflOut & X86_EFL_STATUS_BITS; \
+                /* Intel: 'ROL reg,imm8' and 'ROR reg,imm8' produces different OF values. \
+                          stored in bit 3 of the output.  Observed on 8700B, 9980HK, 10980xe, \
+                          1260p, ++. */ \
                 if (fIntelIbProblem && cBitsImm == 8 && !paTests[iTest].fDstMem) \
-                {   /* Intel 10890xe: 'ROL reg,imm8' and 'ROR reg,imm8' produces different OF values. \
-                                      stored in bit 3 of the output. */ \
+                { \
                     CtxExpect.rflags.u16 &= ~X86_EFL_OF; \
                     CtxExpect.rflags.u16 |= (paTestData[iTestData].fEflOut & RT_BIT_32(BS3CPUINSTR2SHIFT_EFL_IB_OVERFLOW_OUT_BIT)) \
@@ -1040 +1042 @@
                     if (fUndefEfl) /* When executing tests for the other CPU vendor. */ \
                         CtxExpect.rflags.u16 = (CtxExpect.rflags.u16 & ~fUndefEfl) | (TrapFrame.Ctx.rflags.u16 & fUndefEfl); \
-                    /* Alternative overflow flag workaround: else if (fIntelIbProblem && cBitsImm == 8 && !paTests[iTest].fDstMem) \
-                    { \
-                        Bs3TestPrintf("tweaked in=%#x out=%#x exp=%#x\n", Ctx.rflags.u16, TrapFrame.Ctx.rflags.u16, CtxExpect.rflags.u16); \
-                        CtxExpect.rflags.u16 = (CtxExpect.rflags.u16 & ~X86_EFL_OF) | (TrapFrame.Ctx.rflags.u16 & X86_EFL_OF); \
-                    } else if (cBitsImm == 8) Bs3TestPrintf("as is\n"); */\
                     \
                     if (TrapFrame.bXcpt != X86_XCPT_UD) \