Changeset 104195 in vbox for trunk/src

Timestamp:

Apr 5, 2024 2:45:23 PM (10 months ago)

Author:

vboxsync

Message:

VMM/IEM: Refactoring assembly helpers to not pass eflags by reference but instead by value and return the updated value (via eax/w0) - first chunk: ADD,ADC,SUB,SBB,CMP,TEST,AND,OR,XOR. bugref:10376

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl-arm64.S (modified) (7 diffs)
• VMMAll/IEMAllAImpl.asm (modified) (134 diffs)
• VMMAll/IEMAllAImplC.cpp (modified) (38 diffs)
• VMMAll/IEMAllCImpl.cpp (modified) (4 diffs)
• VMMAll/IEMAllCImplStrInstr.cpp.h (modified) (10 diffs)
• VMMAll/IEMAllInstCommon.cpp.h (modified) (15 diffs)
• VMMAll/IEMAllInstCommonBodyMacros.h (modified) (28 diffs)
• VMMAll/IEMAllInstOneByte.cpp.h (modified) (114 diffs)
• VMMAll/IEMAllInstPython.py (modified) (3 diffs)
• VMMAll/IEMAllInstTwoByte0f.cpp.h (modified) (8 diffs)
• VMMAll/IEMAllN8veLiveness.cpp (modified) (1 diff)
• VMMAll/IEMAllN8vePython.py (modified) (1 diff)
• VMMAll/IEMAllN8veRecompFuncs.h (modified) (2 diffs)
• VMMAll/IEMAllThrdPython.py (modified) (2 diffs)
• include/IEMInternal.h (modified) (10 diffs)
• include/IEMMc.h (modified) (2 diffs)
• testcase/tstIEMAImpl.cpp (modified) (13 diffs)
• testcase/tstIEMCheckMc.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl-arm64.S

@@ -191 +191 @@
  */
 
-/* void iemAImpl_cmp_u8(uint8_t const *puDst, uint8_t uSrc, uint32_t *pEFlags); */
+/* uint32_t iemAImpl_cmp_u8(uint32_t fEFlags, uint8_t const *puDst, uint8_t uSrc); */
         .p2align        2
         .private_extern NAME(iemAImpl_sub_u8)
@@ -198 +198 @@
         .cfi_startproc
         /* Do the subtraction. */
-        ldrb    w8, [x0]
-        /*and     w1, w1, #0xff - should not be necessary. */
-        subs    w9, w8, w1                      /* w9 = w8 (*puDst) - w1 (uSrc)  */
+        ldrb    w8, [x1]
+        /*and     w2, w2, #0xff - should not be necessary. */
+        subs    w9, w8, w2                      /* w9 = w8 (*puDst) - w2 (uSrc)  */
+        strb    w9, [x1]
         setf8   w9
-        strb    w9, [x0]
-
-        /* Load EFLAGS. */
-        ldr     w10, [x2]                       /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */
+
+        /* Calculate EFLAGS (passed in and returned via x0). */
         and     w9, w9, #0xffff
-        CALC_EFLAGS x10, x9, x8, x1, x11, X86_EFL_OF
+        CALC_EFLAGS x0, x9, x8, x2, x11, X86_EFL_OF
 
         /* The overflow flag calc done by setf16 isn't correct for subtraction, so we have to
            figure it out ourselves. (See IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC for details.) */
-        eor     w11, w8, w1                     /* input dst ^ source (simplified from ~(dst ^ (source ^ 0x8000)) ). */
+        eor     w11, w8, w2                     /* input dst ^ source (simplified from ~(dst ^ (source ^ 0x8000)) ). */
         eor     w12, w8, w9
         and     w11, w12, w11
         lsr     w11, w11, #7
-        bfi     w10, w11, #X86_EFL_OF_BIT, #1
-
-        /* Done with EFLAGS. */
-        str     w10, [x2]
-        ret
-        .cfi_endproc
-
-
-/* void iemAImpl_cmp_u16(uint16_t const *puDst, uint16_t uSrc, uint32_t *pEFlags); */
+        bfi     w0, w11, #X86_EFL_OF_BIT, #1
+
+        ret
+        .cfi_endproc
+
+
+/* uint32_t iemAImpl_cmp_u16(uint32_t fEFlags, uint16_t const *puDst, uint16_t uSrc); */
         .p2align        2
         .private_extern NAME(iemAImpl_sub_u16)
@@ -230 +227 @@
         .cfi_startproc
         /* Do the subtraction. */
-        ldrh    w8, [x0]
-        /*and     w1, w1, #0xffff - should not be necessary. */
-        subs    w9, w8, w1                      /* w9 = w8 (*puDst) - w1 (uSrc)  */
+        ldrh    w8, [x1]
+        /*and     w2, w2, #0xffff - should not be necessary. */
+        subs    w9, w8, w2                      /* w9 = w8 (*puDst) - w2 (uSrc)  */
         setf16  w9
-        strh    w9, [x0]
-
-        /* Load EFLAGS. */
-        ldr     w10, [x2]                       /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */
+        strh    w9, [x1]
+
+        /* Calculate EFLAGS (passed in and returned via x0). */
         and     w9, w9, #0xffff
-        CALC_EFLAGS x10, x9, x8, x1, x11, X86_EFL_OF
+        CALC_EFLAGS x0, x9, x8, x2, x11, X86_EFL_OF
 
         /* The overflow flag calc done by setf16 isn't correct for subtraction, so we have to
            figure it out ourselves. (See IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC for details.) */
-        eor     w11, w8, w1                     /* input dst ^ source (simplified from ~(dst ^ (source ^ 0x8000)) ). */
+        eor     w11, w8, w2                     /* input dst ^ source (simplified from ~(dst ^ (source ^ 0x8000)) ). */
         eor     w12, w8, w9
         and     w11, w12, w11
         lsr     w11, w11, #15
-        bfi     w10, w11, #X86_EFL_OF_BIT, #1
-
-        /* Done with EFLAGS. */
-        str     w10, [x2]
-        ret
-        .cfi_endproc
-
-
-/* void iemAImpl_cmp_u32(uint32_t const *puDst, uint32_t uSrc, uint32_t *pEFlags); */
+        bfi     w0, w11, #X86_EFL_OF_BIT, #1
+
+        ret
+        .cfi_endproc
+
+
+/* uint32_t iemAImpl_cmp_u32(uint32_t fEFlags, uint32_t const *puDst, uint32_t uSrc); */
         .p2align        2
         .private_extern NAME(iemAImpl_sub_u32)
@@ -262 +256 @@
         .cfi_startproc
         /* Do the subtraction. */
-        ldr     w8, [x0]
-        subs    w9, w8, w1                      /* w9 = w8 (*puDst) - w1 (uSrc)  */
-        str     w9, [x0]
-
-        /* Load EFLAGS. */
-        ldr     w10, [x2]                       /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */
+        ldr     w8, [x1]
+        subs    w9, w8, w2                      /* w9 = w8 (*puDst) - w2 (uSrc)  */
+        str     w9, [x1]
+
+        /* Calculate EFLAGS (passed in and returned via x0). */
 
 #if 0
@@ -274 +267 @@
         mrs     x11, NZCV                       /* w11[31] = N; w11[30] = Z; w11[29] = C; w11[29] = V */
         lsr     w11, w11, #28
-        bfi     w10, w11, #X86_EFL_OF_BIT, #1
+        bfi     w0, w11, #X86_EFL_OF_BIT, #1
         lsr     w11, w11, #1
         eor     w11, w11, #1                    /* inverts the carry flag to x86 style. */
-        bfi     w10, w11, #X86_EFL_CF_BIT, #1   /* CF(0) = C */
+        bfi     w0, w11, #X86_EFL_CF_BIT, #1    /* CF(0) = C */
         lsr     w11, w11, #1
-        bfi     w10, w11, #X86_EFL_ZF_BIT, #2   /* SF(7),ZF(6) = NZ */
+        bfi     w0, w11, #X86_EFL_ZF_BIT, #2    /* SF(7),ZF(6) = NZ */
 #elif 1 /* seems the faster one... */
         cfinv
         mrs     x11, NZCV                       /* w11[31] = N; w11[30] = Z; w11[29] = C; w11[29] = V */
         lsr     w11, w11, #28
-        bfi     w10, w11, #X86_EFL_OF_BIT, #1
+        bfi     w0, w11, #X86_EFL_OF_BIT, #1
         lsr     w11, w11, #1
-        bfi     w10, w11, #X86_EFL_CF_BIT, #1   /* CF(0) = C */
+        bfi     w0, w11, #X86_EFL_CF_BIT, #1    /* CF(0) = C */
         lsr     w11, w11, #1
-        bfi     w10, w11, #X86_EFL_ZF_BIT, #2   /* SF(7),ZF(6) = NZ */
+        bfi     w0, w11, #X86_EFL_ZF_BIT, #2    /* SF(7),ZF(6) = NZ */
 #else
         cset    w11, eq
-        bfi     w10, w11, #X86_EFL_ZF_BIT, #1
+        bfi     w0, w11, #X86_EFL_ZF_BIT, #1
         cset    w11, cc
-        bfi     w10, w11, #X86_EFL_CF_BIT, #1
+        bfi     w0, w11, #X86_EFL_CF_BIT, #1
         cset    w11, vs
-        bfi     w10, w11, #X86_EFL_OF_BIT, #1
+        bfi     w0, w11, #X86_EFL_OF_BIT, #1
         cset    w11, mi
-        bfi     w10, w11, #X86_EFL_SF_BIT, #1
+        bfi     w0, w11, #X86_EFL_SF_BIT, #1
 #endif
 
@@ -305 +298 @@
         eor     w11, w11, w11, LSR #1
         eor     w11, w11, #1
-        bfi     w10, w11, #X86_EFL_PF_BIT, #1   /* PF(2) = popcount(w9 & 0xff) & 1 ^ 1 */
+        bfi     w0, w11, #X86_EFL_PF_BIT, #1    /* PF(2) = popcount(w9 & 0xff) & 1 ^ 1 */
 
         /* Auxilary carry / borrow flag.  This is related to 8-bit BCD. */
-        eor     w11, w8, w1
+        eor     w11, w8, w2
         eor     w11, w11, w9
         lsr     w11, w11, #X86_EFL_AF_BIT
-        bfi     w10, w11, #X86_EFL_AF_BIT, #1   /* AF(4) = (w8 ^ w1 ^ w9 & X86_EFL_AF) >> X86_EFL_AF_BIT */
+        bfi     w0, w11, #X86_EFL_AF_BIT, #1    /* AF(4) = (w8 ^ w2 ^ w9 & X86_EFL_AF) >> X86_EFL_AF_BIT */
 #else
-        CALC_EFLAGS x10, x9, x8, x1, x11
+        CALC_EFLAGS x0, x9, x8, x2, x11
 #endif
 
-        str     w10, [x2]
-        ret
-        .cfi_endproc
-
-
-/* void iemAImpl_cmp_u64(uint64_t const *puDst, uint64_t uSrc, uint32_t *pEFlags); */
+        ret
+        .cfi_endproc
+
+
+/* uint32_t iemAImpl_cmp_u64(uint32_t fEFlags, uint64_t const *puDst, uint64_t uSrc); */
         .p2align        2
         .private_extern NAME(iemAImpl_sub_u64)
@@ -328 +320 @@
         .cfi_startproc
         /* Do the subtraction. */
-        ldr     x8, [x0]
-        subs    x9, x8, x1                      /* x9 = x8 (*puDst) - x1 (uSrc)  */
-        str     x9, [x0]
-
-        /* Load EFLAGS. */
-        ldr     w10, [x2]                       /* w10 = eflags; CF=0 PF=2 AF=4 ZF=6 SF=7 OF=11 */
-        CALC_EFLAGS x10, x9, x8, x1, x11
-
-        str     w10, [x2]
+        ldr     x8, [x1]
+        subs    x9, x8, x2                      /* x9 = x8 (*puDst) - x2 (uSrc)  */
+        str     x9, [x1]
+
+        /* Calculate EFLAGS (passed in and returned via x0). */
+        CALC_EFLAGS x0, x9, x8, x2, x11
+
         ret
         .cfi_endproc

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -41 +41 @@
 ;;
 ; This is handy for generating absolutly correct EFLAGS.
-%define IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
+;%define IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
 
 
@@ -291 +291 @@
 ;
 ; @remarks      Clobbers T0, stack. Changes EFLAGS.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       The set of modified flags.
+; @param        3       The set of undefined flags.
+; @param        4       The flags that must be loaded.
+;
+%macro IEM_MAYBE_LOAD_FLAGS 4
+ %ifdef IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
+        pushf                                                   ; store current flags
+        mov     T0_32, %1                                       ; load the guest flags
+        and     dword [xSP], ~(%2 | %3 | X86_EFL_STATUS_BITS)   ; mask out the modified and undefined flags
+        and     T0_32, (%2 | %3 | X86_EFL_STATUS_BITS)          ; select the modified and undefined flags.
+        or      [xSP], T0                                       ; merge guest flags with host flags.
+        popf                                                    ; load the mixed flags.
+
+ %elif (%3 + %4) != 0
+  %if 1        ; This approach seems faster on intel 10980XE
+   %if (%3 | %4) == X86_EFL_CF
+        ; Use bt to load bit into CF
+        bt      %1, X86_EFL_CF_BIT
+   %else
+        ; Use ADD to set OF and SHAF for the rest. ASSUMES T0_32 is eax!
+        mov     eax, %1
+    %if (%3 | %4) == X86_EFL_OF
+        ; Use ADD to set OF.
+        shl     eax, 31 - X86_EFL_OF_BIT
+        add     eax, 80000000h
+    %elif ((%3 | %4) & X86_EFL_OF) != 0
+        ; Use ADD to set OF.
+        xchg    al, ah
+        shl     al, 15 - X86_EFL_OF_BIT
+        add     al, 80h
+        ; Use SAHF to set the other status flags.
+        sahf
+    %else ; OF not needed; so al -> ah and load ah into eflags.
+     %if 1 ; Pretty similar on 10980XE, but shl seems faster on average.
+        shl     eax, 8
+     %else
+        xchg    al, ah
+     %endif
+        sahf
+    %endif
+   %endif
+
+  %else
+        pushf                           ; store current flags
+        mov     T0_32, %1               ; load the guest flags
+        and     dword [xSP], ~(%2 | %3) ; mask out the modified and undefined flags
+        and     T0_32, (%2 | %3)        ; select the modified and undefined flags.
+        or      [xSP], T0               ; merge guest flags with host flags.
+        popf                            ; load the mixed flags.
+  %endif
+ %endif
+%endmacro
+
+;;
+; Load the relevant flags from [%1].
+;
+; @remarks      Clobbers T0, stack. Changes EFLAGS.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       The set of flags to load.
+; @param        3       The set of undefined flags.
+;
+%macro IEM_LOAD_FLAGS 3
+ %ifdef IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
+        pushf                                                   ; store current flags
+        mov     T0_32, %1                                       ; load the guest flags
+        and     dword [xSP], ~(%2 | %3 | X86_EFL_STATUS_BITS)   ; mask out the modified, undefined and status flags
+        and     T0_32, (%2 | %3 | X86_EFL_STATUS_BITS)          ; select the modified, undefined and status flags.
+        or      [xSP], T0                                       ; merge guest flags with host flags.
+        popf                                                    ; load the mixed flags.
+
+ %elif 1        ; This approach seems faster on intel 10980XE
+  %if (%3 | %2) == X86_EFL_CF
+        ; Use bt to load bit into CF
+        bt      %1, X86_EFL_CF_BIT
+  %else
+        mov     eax, %1                   ; ASSUMES T0_32 is eax!!
+   %if (%3 | %2) == X86_EFL_OF
+        ; Use ADD to set OF.
+        shl     eax, 31 - X86_EFL_OF_BIT
+        add     eax, 80000000h
+   %elif ((%3 | %2) & X86_EFL_OF) != 0
+        ; Use ADD to set OF.
+        xchg    al, ah
+        shl     al, 15 - X86_EFL_OF_BIT
+        add     al, 80h
+        ; Use SAHF to set the other status flags.
+        sahf
+   %else ; OF not needed; so al -> ah and load ah into eflags.
+    %if 1 ; Pretty similar on 10980XE, but shl seems faster on average.
+        shl     eax, 8
+    %else
+        xchg    al, ah
+    %endif
+        sahf
+   %endif
+  %endif ; (%3 | %2) != X86_EFL_CF
+
+ %else
+        pushf                           ; store current flags
+        mov     T0_32, %1               ; load the guest flags
+        and     dword [xSP], ~(%2 | %3) ; mask out the modified and undefined flags
+        and     T0_32, (%2 | %3)        ; select the modified and undefined flags.
+        or      [xSP], T0               ; merge guest flags with host flags.
+        popf                            ; load the mixed flags.
+ %endif
+%endmacro
+
+;;
+; Merge incoming guest EFLAGS (%1) with host EFLAGS into EAX (T0).
+;
+; @remarks  Clobbers T0, T1, %1, stack.
+; @param        1       The parameter (A0..A3) holding the OLD eflags value. Clobbered.
+; @param        2       The mask of modified flags to save.
+; @param        3       The mask of undefined flags to (maybe) save.
+; @param        4       The mask of flags that are zeroed (and thus doesn't require loading, just clearing)
+;
+%macro IEM_SAVE_FLAGS_RETVAL 4 0
+ %if (%2 | %3 | %4) != 0
+        mov     T1_32, %1                                       ; flags
+  %ifdef IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
+        pushf
+        pop     T0
+        and     %1, ~(%2 | %3 | %4 | X86_EFL_STATUS_BITS)       ; clear the modified & undefined & zeroed & status flags.
+        and     T0_32, (%2 | %3 | X86_EFL_STATUS_BITS)          ; select the modified, undefined and status flags.
+  %else
+   %if (%2 | %3 | %4) == X86_EFL_CF
+        setc    T0_8
+   %elif (%2 | %3) == X86_EFL_OF
+        seto    T0_8
+        shl     T0_32, X86_EFL_OF_BIT
+   %elif (%2 | %3) == X86_EFL_ZF
+        setz    T0_8                    ; On 10980XE this is faster than the next option 5596 vs 5936 ps/call (cmpxchg8b-positive).
+        shl     T0_32, X86_EFL_ZF_BIT
+   %elif (%2 | %3) <= 0xff
+        lahf
+        movzx   eax, ah                 ; ASSUMES T0_32 is eax!
+   %elif 1                              ; The locked functions are generally faster on 10980XE with this approach
+        lahf                            ; while there seems only to be a tiny advantage in most other test.
+        movzx   eax, ah                 ; ASSUMES T0_32 is eax!
+        jno     .of_is_clear
+        or      eax, X86_EFL_OF
+.of_is_clear:
+   %else
+        pushf                           ; this is a bit slow
+        pop     T0
+   %endif
+        and     %1, ~(%2 | %3 | %4)     ; clear the modified & undefined & zeroed flags.
+        and     T0_32, (%2 | %3)        ; select the modified and undefined flags.
+  %endif
+        or      T0_32, %1               ; combine the flags. ASSUMES T0 = eax!
+        ;mov     %1, T0_32               ; save the flags.
+ %endif
+%endmacro
+
+;;
+; Calculates the new EFLAGS based on the CPU EFLAGS and fixed clear and set bit masks.
+;
+; @remarks  Clobbers T0, T1, stack.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       The mask of modified flags to save.
+; @param        3       Mask of additional flags to always clear
+; @param        4       Mask of additional flags to always set.
+;
+;; @todo make it stuff the result into EAX?
+%macro IEM_SAVE_AND_ADJUST_FLAGS 4
+ %if (%2 | %3 | %4) != 0
+        pushf
+        pop     T1
+        mov     T0_32, %1               ; load flags.
+        and     T0_32, ~(%2 | %3)       ; clear the modified and always cleared flags.
+        and     T1_32, (%2)             ; select the modified flags.
+        or      T0_32, T1_32            ; combine the flags.
+  %if (%4) != 0
+        or      T0_32, %4               ; add the always set flags.
+  %endif
+        mov     %1, T0_32               ; save the result.
+ %endif
+%endmacro
+
+;;
+; Calculates the new EFLAGS based on the CPU EFLAGS (%2), a clear mask (%3),
+; signed input (%4[%5]) and parity index (%6).
+;
+; This is used by MUL and IMUL, where we got result (%4 & %6) in xAX which is
+; also T0. So, we have to use T1 for the EFLAGS calculation and save T0/xAX
+; while we extract the %2 flags from the CPU EFLAGS or use T2 (only AMD64).
+;
+; @remarks  Clobbers T0, T1, stack, %6, EFLAGS.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       The mask of modified flags to save.
+; @param        3       Mask of additional flags to always clear
+; @param        4       The result register to set SF by.
+; @param        5       The width of the %4 register in bits (8, 16, 32, or 64).
+; @param        6       The (full) register containing the parity table index. Will be modified!
+
+%macro IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF 6
+ %ifdef RT_ARCH_AMD64
+        pushf
+        pop     T2
+ %else
+        push    T0
+        pushf
+        pop     T0
+ %endif
+        mov     T1_32, %1               ; load flags.
+        and     T1_32, ~(%2 | %3 | X86_EFL_PF | X86_EFL_SF)  ; clear the modified, always cleared flags and the two flags we calc.
+ %ifdef RT_ARCH_AMD64
+        and     T2_32, (%2)             ; select the modified flags.
+        or      T1_32, T2_32            ; combine the flags.
+ %else
+        and     T0_32, (%2)             ; select the modified flags.
+        or      T1_32, T0_32            ; combine the flags.
+        pop     T0
+ %endif
+
+        ; First calculate SF as it's likely to be refereing to the same register as %6 does.
+        bt      %4, %5 - 1
+        jnc     %%sf_clear
+        or      T1_32, X86_EFL_SF
+ %%sf_clear:
+
+        ; Parity last.
+        and     %6, 0xff
+ %ifdef RT_ARCH_AMD64
+        lea     T2, [NAME(g_afParity) xWrtRIP]
+        or      T1_8, [T2 + %6]
+ %else
+        or      T1_8, [NAME(g_afParity) + %6]
+ %endif
+
+        mov     %1, T1_32               ; save the result.
+%endmacro
+
+;;
+; Calculates the new EFLAGS using fixed clear and set bit masks.
+;
+; @remarks  Clobbers T0.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       Mask of additional flags to always clear
+; @param        3       Mask of additional flags to always set.
+;
+%macro IEM_ADJUST_FLAGS 3
+ %if (%2 | %3) != 0
+        mov     T0_32, %1               ; Load flags.
+  %if (%2) != 0
+        and     T0_32, ~(%2)            ; Remove the always cleared flags.
+  %endif
+  %if (%3) != 0
+        or      T0_32, %3               ; Add the always set flags.
+  %endif
+        mov     %1, T0_32               ; Save the result.
+ %endif
+%endmacro
+
+;;
+; Calculates the new EFLAGS using fixed clear and set bit masks.
+;
+; @remarks  Clobbers T0, %4, EFLAGS.
+; @param        1       The parameter (A0..A3) holding the eflags value.
+; @param        2       Mask of additional flags to always clear
+; @param        3       Mask of additional flags to always set.
+; @param        4       The (full) register containing the parity table index. Will be modified!
+;
+%macro IEM_ADJUST_FLAGS_WITH_PARITY 4
+        mov     T0_32, %1               ; Load flags.
+        and     T0_32, ~(%2 | X86_EFL_PF) ; Remove PF and the always cleared flags.
+ %if (%3) != 0
+        or      T0_32, %3               ; Add the always set flags.
+ %endif
+        and     %4, 0xff
+ %ifdef RT_ARCH_AMD64
+        lea     T2, [NAME(g_afParity) xWrtRIP]
+        or      T0_8, [T2 + %4]
+ %else
+        or      T0_8, [NAME(g_afParity) + %4]
+ %endif
+        mov     %1, T0_32               ; Save the result.
+%endmacro
+
+
+;;;; OLD EFLAGS macros.
+;;;; OLD EFLAGS macros.
+;;;; OLD EFLAGS macros.
+;;;; OLD EFLAGS macros.
+;;;; OLD EFLAGS macros.
+
+;;
+; Load the relevant flags from [%1] if there are undefined flags (%3).
+;
+; @remarks      Clobbers T0, stack. Changes EFLAGS.
 ; @param        1       The parameter (A0..A3) pointing to the eflags.
 ; @param        2       The set of modified flags.
@@ -296 +587 @@
 ; @param        4       The flags that must be loaded.
 ;
-%macro IEM_MAYBE_LOAD_FLAGS 4
+%macro IEM_MAYBE_LOAD_FLAGS_OLD 4
  %ifdef IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
         pushf                                                   ; store current flags
@@ -353 +644 @@
 ; @param        3       The set of undefined flags.
 ;
-%macro IEM_LOAD_FLAGS 3
+%macro IEM_LOAD_FLAGS_OLD 3
  %ifdef IEM_AIMPL_WITH_LOAD_AND_SAVE_ALL_STATUS_FLAGS
         pushf                                                   ; store current flags
@@ -408 +699 @@
 ; @param        4       The mask of flags that are zeroed (and thus doesn't require loading, just clearing)
 ;
-%macro IEM_SAVE_FLAGS 4 0
+%macro IEM_SAVE_FLAGS_OLD 4 0
  %if (%2 | %3 | %4) != 0
         mov     T1_32, [%1]                                     ; flags
@@ -455 +746 @@
 ; @param        4       Mask of additional flags to always set.
 ;
-%macro IEM_SAVE_AND_ADJUST_FLAGS 4
+%macro IEM_SAVE_AND_ADJUST_FLAGS_OLD 4
  %if (%2 | %3 | %4) != 0
         pushf
@@ -486 +777 @@
 ; @param        6       The (full) register containing the parity table index. Will be modified!
 
-%macro IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF 6
+%macro IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD 6
  %ifdef RT_ARCH_AMD64
         pushf
@@ -532 +823 @@
 ; @param        3       Mask of additional flags to always set.
 ;
-%macro IEM_ADJUST_FLAGS 3
+%macro IEM_ADJUST_FLAGS_OLD 3
  %if (%2 | %3) != 0
         mov     T0_32, [%1]             ; Load flags.
@@ -554 +845 @@
 ; @param        4       The (full) register containing the parity table index. Will be modified!
 ;
-%macro IEM_ADJUST_FLAGS_WITH_PARITY 4
+%macro IEM_ADJUST_FLAGS_WITH_PARITY_OLD 4
         mov     T0_32, [%1]                 ; Load flags.
         and     T0_32, ~(%2 | X86_EFL_PF)   ; Remove PF and the always cleared flags.
@@ -569 +860 @@
         mov     [%1], T0_32             ; Save the result.
 %endmacro
+
 
 
@@ -676 +968 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        %1      byte [A0], A1_8
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        %1      byte [A1], A2_8
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u8
@@ -684 +976 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        %1      word [A0], A1_16
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        %1      word [A1], A2_16
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -692 +984 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        %1      dword [A0], A1_32
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        %1      dword [A1], A2_32
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -701 +993 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        %1      qword [A0], A1
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        %1      qword [A1], A2
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -712 +1004 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        lock %1 byte [A0], A1_8
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        lock %1 byte [A1], A2_8
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u8_locked
@@ -720 +1012 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        lock %1 word [A0], A1_16
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        lock %1 word [A1], A2_16
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
@@ -728 +1020 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        lock %1 dword [A0], A1_32
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        lock %1 dword [A1], A2_32
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
@@ -737 +1029 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, %5
-        lock %1 qword [A0], A1
-        IEM_SAVE_FLAGS                 A2, %3, %4, %6
+        IEM_MAYBE_LOAD_FLAGS               A0_32, %3, %4, %5
+        lock %1 qword [A1], A2
+        IEM_SAVE_FLAGS_RETVAL              A0_32, %3, %4, %6
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
@@ -776 +1068 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A3, %2, %3, 0 ;; @todo do we need to load undefined flags for any platform?
+        IEM_MAYBE_LOAD_FLAGS_OLD           A3, %2, %3, 0 ;; @todo do we need to load undefined flags for any platform?
         %1      T0_32, A1_32, A2_32
         mov     [A0], T0_32
-        IEM_SAVE_FLAGS                 A3, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A3, %2, %3, %4
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -786 +1078 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A3, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A3, %2, %3, 0
         %1      T0, A1, A2
         mov     [A0], T0
-        IEM_SAVE_FLAGS                 A3, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A3, %2, %3, %4
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -817 +1109 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, 0 ;; @todo check if any undefined flags are passed thru
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0 ;; @todo check if any undefined flags are passed thru
         mov     T0_32, [A0]
         %1      T0_32, A1_32
         mov     [A0], T0_32
-        IEM_SAVE_FLAGS                 A2, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -828 +1120 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
         mov     T0, [A0]
         %1      T0, A1
         mov     [A0], T0
-        IEM_SAVE_FLAGS                 A2, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1052 +1344 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         %1      word [A0], A1_16
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1060 +1352 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         %1      dword [A0], A1_32
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1069 +1361 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         %1      qword [A0], A1
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1080 +1372 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         lock %1 word [A0], A1_16
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
@@ -1088 +1380 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         lock %1 dword [A0], A1_32
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
@@ -1097 +1389 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %3, %4, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %3, %4, 0
         lock %1 qword [A0], A1
-        IEM_SAVE_FLAGS                 A2, %3, %4, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %3, %4, 0
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
@@ -1142 +1434 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
         %1      T0_16, A1_16
 %if %4 != 0
@@ -1149 +1441 @@
         mov     [A0], T0_16
 .unchanged_dst:
-        IEM_SAVE_FLAGS                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1158 +1450 @@
 ;bad;        jz      .unchanged_dst
 ;bad;        mov     [A0], T1_16
-;bad;        IEM_ADJUST_FLAGS_WITH_PARITY    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
+;bad;        IEM_ADJUST_FLAGS_WITH_PARITY_OLD    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
 ;bad;        EPILOGUE_3_ARGS
 ;bad;.unchanged_dst:
@@ -1164 +1456 @@
 ;bad;        mov     [A0], T1_16
 ;bad;%endif
-;bad;        IEM_ADJUST_FLAGS                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
+;bad;        IEM_ADJUST_FLAGS_OLD                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
 ;bad;        EPILOGUE_3_ARGS
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u16_intel
@@ -1176 +1468 @@
 ;bad;        mov     [A0], T0_16
 ;bad;.unchanged_dst:
-;bad;        IEM_SAVE_AND_ADJUST_FLAGS       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
+;bad;        IEM_SAVE_AND_ADJUST_FLAGS_OLD       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
 ;bad;        EPILOGUE_3_ARGS
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u16_amd
@@ -1184 +1476 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
         %1      T0_32, A1_32
 %if %4 != 0
@@ -1191 +1483 @@
         mov     [A0], T0_32
 .unchanged_dst:
-        IEM_SAVE_FLAGS                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1202 +1494 @@
 ;bad;%endif
 ;bad;        mov     [A0], T1_32
-;bad;        IEM_ADJUST_FLAGS_WITH_PARITY    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
+;bad;        IEM_ADJUST_FLAGS_WITH_PARITY_OLD    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
 ;bad;        EPILOGUE_3_ARGS
 ;bad;.unchanged_dst:
-;bad;        IEM_ADJUST_FLAGS                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
+;bad;        IEM_ADJUST_FLAGS_OLD                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
 ;bad;        EPILOGUE_3_ARGS
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u32_intel
@@ -1217 +1509 @@
 ;bad;        mov     [A0], T0_32
 ;bad;.unchanged_dst:
-;bad;        IEM_SAVE_AND_ADJUST_FLAGS       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
+;bad;        IEM_SAVE_AND_ADJUST_FLAGS_OLD       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
 ;bad;        EPILOGUE_3_ARGS
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u32_amd
@@ -1227 +1519 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, %3 ; Must load undefined flags since AMD passes them thru
         %1      T0, A1
 %if %4 != 0
@@ -1234 +1526 @@
         mov     [A0], T0
 .unchanged_dst:
-        IEM_SAVE_FLAGS                 A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, 0
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1245 +1537 @@
 ;bad;%endif
 ;bad;        mov     [A0], T1
-;bad;        IEM_ADJUST_FLAGS_WITH_PARITY    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
+;bad;        IEM_ADJUST_FLAGS_WITH_PARITY_OLD    A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF | X86_EFL_ZF, 0, T1
 ;bad;        EPILOGUE_3_ARGS
 ;bad;.unchanged_dst:
-;bad;        IEM_ADJUST_FLAGS                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
+;bad;        IEM_ADJUST_FLAGS_OLD                A2, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_PF
 ;bad;        EPILOGUE_3_ARGS
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u64_intel
@@ -1260 +1552 @@
 ;bad;        mov     [A0], T0
 ;bad;.unchanged_dst:
-;bad;        IEM_SAVE_AND_ADJUST_FLAGS       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
+;bad;        IEM_SAVE_AND_ADJUST_FLAGS_OLD       A2, %2, 0, 0    ; Only the ZF flag is modified on AMD Zen 2.
 ;bad;        EPILOGUE_3_ARGS_EX 8
 ;bad;ENDPROC iemAImpl_ %+ %1 %+ _u64_amd
@@ -1295 +1587 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
         %1      T0_16, A1_16
         mov     [A0], T0_16
-        IEM_SAVE_FLAGS                 A2, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1304 +1596 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
         %1      T0_32, A1_32
         mov     [A0], T0_32
-        IEM_SAVE_FLAGS                 A2, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1314 +1606 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS           A2, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD           A2, %2, %3, 0
         %1      T0, A1
         mov     [A0], T0
-        IEM_SAVE_FLAGS                 A2, %2, %3, %4
+        IEM_SAVE_FLAGS_OLD                 A2, %2, %3, %4
         EPILOGUE_3_ARGS_EX 8
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -1338 +1630 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u16 %+ %3, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
         imul    A1_16, word [A0]
         mov     [A0], A1_16
  %if %4 != 1
-        IEM_SAVE_FLAGS                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_16, 16, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_16, 16, A1 ; intel
  %endif
         EPILOGUE_3_ARGS
@@ -1351 +1643 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u32 %+ %3, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
         imul    A1_32, dword [A0]
         mov     [A0], A1_32
  %if %4 != 1
-        IEM_SAVE_FLAGS                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_32, 32, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1_32, 32, A1 ; intel
  %endif
         EPILOGUE_3_ARGS
@@ -1365 +1657 @@
 BEGINPROC_FASTCALL iemAImpl_imul_two_u64 %+ %3, 16
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                    A2, %1, %2, %2 ; Undefined flags may be passed thru (AMD)
         imul    A1, qword [A0]
         mov     [A0], A1
  %if %4 != 1
-        IEM_SAVE_FLAGS                          A2, %1, %2, 0
+        IEM_SAVE_FLAGS_OLD                          A2, %1, %2, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1, 64, A1 ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD    A2, %1, X86_EFL_AF | X86_EFL_ZF, A1, 64, A1 ; intel
  %endif
         EPILOGUE_3_ARGS_EX 8
@@ -1477 +1769 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u8, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_8, [A1]
         xadd    [A0], T0_8
         mov     [A1], T0_8
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u8
@@ -1487 +1779 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_16, [A1]
         xadd    [A0], T0_16
         mov     [A1], T0_16
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u16
@@ -1497 +1789 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_32, [A1]
         xadd    [A0], T0_32
         mov     [A1], T0_32
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u32
@@ -1508 +1800 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u64, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0, [A1]
         xadd    [A0], T0
         mov     [A1], T0
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u64
@@ -1519 +1811 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u8_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_8, [A1]
         lock xadd [A0], T0_8
         mov     [A1], T0_8
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u8_locked
@@ -1529 +1821 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u16_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_16, [A1]
         lock xadd [A0], T0_16
         mov     [A1], T0_16
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u16_locked
@@ -1539 +1831 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u32_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0_32, [A1]
         lock xadd [A0], T0_32
         mov     [A1], T0_32
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u32_locked
@@ -1550 +1842 @@
 BEGINPROC_FASTCALL iemAImpl_xadd_u64_locked, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         mov     T0, [A1]
         lock xadd [A0], T0
         mov     [A1], T0
-        IEM_SAVE_FLAGS       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
+        IEM_SAVE_FLAGS_OLD       A2, (X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF), 0, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_xadd_u64_locked
@@ -1585 +1877 @@
         mov     ebx, [r8]
         mov     ecx, [r8 + 4]
-        IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [r11]
         mov     edx, [r11 + 4]
@@ -1593 +1885 @@
         mov     [r11], eax
         mov     [r11 + 4], edx
-        IEM_SAVE_FLAGS       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1605 +1897 @@
         mov     ebx, [r11]
         mov     ecx, [r11 + 4]
-        IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [rsi]
         mov     edx, [rsi + 4]
@@ -1613 +1905 @@
         mov     [rsi], eax
         mov     [rsi + 4], edx
-        IEM_SAVE_FLAGS       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1632 +1924 @@
         mov     ebx, [ecx]
         mov     ecx, [ecx + 4]
-        IEM_MAYBE_LOAD_FLAGS ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [esi]
         mov     edx, [esi + 4]
@@ -1640 +1932 @@
         mov     [esi], eax
         mov     [esi + 4], edx
-        IEM_SAVE_FLAGS       ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, edi)
+        IEM_SAVE_FLAGS_OLD       ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, edi)
 
         pop     ebp
@@ -1660 +1952 @@
         mov     ebx, [r8]
         mov     ecx, [r8 + 4]
-        IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [r11]
         mov     edx, [r11 + 4]
@@ -1668 +1960 @@
         mov     [r11], eax
         mov     [r11 + 4], edx
-        IEM_SAVE_FLAGS       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1680 +1972 @@
         mov     ebx, [r11]
         mov     ecx, [r11 + 4]
-        IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [rsi]
         mov     edx, [rsi + 4]
@@ -1688 +1980 @@
         mov     [rsi], eax
         mov     [rsi + 4], edx
-        IEM_SAVE_FLAGS       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1707 +1999 @@
         mov     ebx, [ecx]
         mov     ecx, [ecx + 4]
-        IEM_MAYBE_LOAD_FLAGS ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [esi]
         mov     edx, [esi + 4]
@@ -1715 +2007 @@
         mov     [esi], eax
         mov     [esi + 4], edx
-        IEM_SAVE_FLAGS       ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, edi)
+        IEM_SAVE_FLAGS_OLD       ebp, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, edi)
 
         pop     ebp
@@ -1751 +2043 @@
         mov     rbx, [r8]
         mov     rcx, [r8 + 8]
-        IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     rax, [r11]
         mov     rdx, [r11 + 8]
@@ -1759 +2051 @@
         mov     [r11], rax
         mov     [r11 + 8], rdx
-        IEM_SAVE_FLAGS       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1771 +2063 @@
         mov     rbx, [r11]
         mov     rcx, [r11 + 8]
-        IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     rax, [rsi]
         mov     rdx, [rsi + 8]
@@ -1779 +2071 @@
         mov     [rsi], rax
         mov     [rsi + 8], rdx
-        IEM_SAVE_FLAGS       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1796 +2088 @@
         mov     rbx, [r8]
         mov     rcx, [r8 + 8]
-        IEM_MAYBE_LOAD_FLAGS r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r9, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     rax, [r11]
         mov     rdx, [r11 + 8]
@@ -1804 +2096 @@
         mov     [r11], rax
         mov     [r11 + 8], rdx
-        IEM_SAVE_FLAGS       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r9, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1816 +2108 @@
         mov     rbx, [r11]
         mov     rcx, [r11 + 8]
-        IEM_MAYBE_LOAD_FLAGS r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD r10, (X86_EFL_ZF), 0, 0 ; clobbers T0 (eax)
         mov     rax, [rsi]
         mov     rdx, [rsi + 8]
@@ -1824 +2116 @@
         mov     [rsi], rax
         mov     [rsi + 8], rdx
-        IEM_SAVE_FLAGS       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
+        IEM_SAVE_FLAGS_OLD       r10, (X86_EFL_ZF), 0, 0 ; clobbers T0+T1 (eax, r11)
 
         pop     rbx
@@ -1847 +2139 @@
 BEGINPROC_FASTCALL iemAImpl_cmpxchg_u8 %+ %2, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
         mov     al, [A1]
         %1 cmpxchg [A0], A2_8
         mov     [A1], al
-        IEM_SAVE_FLAGS       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
+        IEM_SAVE_FLAGS_OLD       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_cmpxchg_u8 %+ %2
@@ -1857 +2149 @@
 BEGINPROC_FASTCALL iemAImpl_cmpxchg_u16 %+ %2, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
         mov     ax, [A1]
         %1 cmpxchg [A0], A2_16
         mov     [A1], ax
-        IEM_SAVE_FLAGS       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
+        IEM_SAVE_FLAGS_OLD       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_cmpxchg_u16 %+ %2
@@ -1867 +2159 @@
 BEGINPROC_FASTCALL iemAImpl_cmpxchg_u32 %+ %2, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
         mov     eax, [A1]
         %1 cmpxchg [A0], A2_32
         mov     [A1], eax
-        IEM_SAVE_FLAGS       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
+        IEM_SAVE_FLAGS_OLD       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_cmpxchg_u32 %+ %2
@@ -1878 +2170 @@
 %ifdef RT_ARCH_AMD64
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0 (eax)
         mov     rax, [A1]
         %1 cmpxchg [A0], A2
         mov     [A1], rax
-        IEM_SAVE_FLAGS       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
+        IEM_SAVE_FLAGS_OLD       A3, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, r11/edi)
         EPILOGUE_4_ARGS
 %else
@@ -1900 +2192 @@
         mov     ebx, [ecx]
         mov     ecx, [ecx + 4]
-        IEM_MAYBE_LOAD_FLAGS ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0  ; clobbers T0 (eax)
+        IEM_MAYBE_LOAD_FLAGS_OLD ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0  ; clobbers T0 (eax)
         mov     eax, [esi]
         mov     edx, [esi + 4]
@@ -1913 +2205 @@
         mov     [esi], eax
         mov     [esi + 4], edx
-        IEM_SAVE_FLAGS       ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, edi)
+        IEM_SAVE_FLAGS_OLD       ebp, (X86_EFL_ZF | X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_SF | X86_EFL_OF), 0, 0 ; clobbers T0+T1 (eax, edi)
 
         pop     ebp
@@ -1954 +2246 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         %1      byte [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u8
@@ -1962 +2254 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8_locked, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         lock %1 byte [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u8_locked
@@ -1970 +2262 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         %1      word [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -1978 +2270 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16_locked, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         lock %1 word [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16_locked
@@ -1986 +2278 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         %1      dword [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -1994 +2286 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32_locked, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         lock %1 dword [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32_locked
@@ -2003 +2295 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         %1      qword [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -2011 +2303 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64_locked, 8
         PROLOGUE_2_ARGS
-        IEM_MAYBE_LOAD_FLAGS A1, %2, %3, 0
+        IEM_MAYBE_LOAD_FLAGS_OLD A1, %2, %3, 0
         lock %1 qword [A0]
-        IEM_SAVE_FLAGS       A1, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A1, %2, %3, 0
         EPILOGUE_2_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64_locked
@@ -2091 +2383 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         mov     cl, A1_8
@@ -2099 +2391 @@
         %1      byte [A1], cl
  %endif
-        IEM_SAVE_FLAGS       A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A2, %2, %3, 0
 .zero_shift:
         EPILOGUE_3_ARGS
@@ -2106 +2398 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         mov     cl, A1_8
@@ -2114 +2406 @@
         %1      word [A1], cl
  %endif
-        IEM_SAVE_FLAGS       A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A2, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -2120 +2412 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         mov     cl, A1_8
@@ -2128 +2420 @@
         %1      dword [A1], cl
  %endif
-        IEM_SAVE_FLAGS       A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A2, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -2135 +2427 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS A2, %2, %3, %4
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, %2, %3, %4
   %ifdef ASM_CALL64_GCC
         mov     cl, A1_8
@@ -2143 +2435 @@
         %1      qword [A1], cl
   %endif
-        IEM_SAVE_FLAGS       A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD       A2, %2, %3, 0
         EPILOGUE_3_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -2184 +2476 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16, 16
         PROLOGUE_4_ARGS
-        ;IEM_LOAD_FLAGS      A3, %4, %3
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %4
+        ;IEM_LOAD_FLAGS_OLD      A3, %4, %3
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         xchg    A3, A2
@@ -2194 +2486 @@
         %1      [A2], A1_16, cl
  %endif
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u16
@@ -2200 +2492 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32, 16
         PROLOGUE_4_ARGS
-        ;IEM_LOAD_FLAGS      A3, %4, %3
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %4
+        ;IEM_LOAD_FLAGS_OLD      A3, %4, %3
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         xchg    A3, A2
@@ -2210 +2502 @@
         %1      [A2], A1_32, cl
  %endif
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_ %+ %1 %+ _u32
@@ -2217 +2509 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64, 20
         PROLOGUE_4_ARGS
-        ;IEM_LOAD_FLAGS      A3, %4, %3
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %4
+        ;IEM_LOAD_FLAGS_OLD      A3, %4, %3
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %4
  %ifdef ASM_CALL64_GCC
         xchg    A3, A2
@@ -2227 +2519 @@
         %1      [A2], A1, cl
  %endif
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
         EPILOGUE_4_ARGS_EX 12
 ENDPROC iemAImpl_ %+ %1 %+ _u64
@@ -2266 +2558 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u8 %+ %4, 12
         PROLOGUE_3_ARGS
-        IEM_MAYBE_LOAD_FLAGS                     A2, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                     A2, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     al, [A0]
         %1      A1_8
         mov     [A0], ax
  %if %5 != 1
-        IEM_SAVE_FLAGS                           A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                           A2, %2, %3, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF     A2, %2, X86_EFL_AF | X86_EFL_ZF, ax, 8, xAX ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD     A2, %2, X86_EFL_AF | X86_EFL_ZF, ax, 8, xAX ; intel
  %endif
         xor     eax, eax
@@ -2281 +2573 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u16 %+ %4, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     ax, [A0]
  %ifdef ASM_CALL64_GCC
@@ -2294 +2586 @@
  %endif
  %if %5 != 1
-        IEM_SAVE_FLAGS                           A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                           A3, %2, %3, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF     A3, %2, X86_EFL_AF | X86_EFL_ZF, ax, 16, xAX ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD     A3, %2, X86_EFL_AF | X86_EFL_ZF, ax, 16, xAX ; intel
  %endif
         xor     eax, eax
@@ -2304 +2596 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u32 %+ %4, 16
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     eax, [A0]
  %ifdef ASM_CALL64_GCC
@@ -2317 +2609 @@
  %endif
  %if %5 != 1
-        IEM_SAVE_FLAGS                           A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                           A3, %2, %3, 0
  %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF     A3, %2, X86_EFL_AF | X86_EFL_ZF, eax, 32, xAX ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD     A3, %2, X86_EFL_AF | X86_EFL_ZF, eax, 32, xAX ; intel
  %endif
         xor     eax, eax
@@ -2328 +2620 @@
 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u64 %+ %4, 20
         PROLOGUE_4_ARGS
-        IEM_MAYBE_LOAD_FLAGS                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD                     A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     rax, [A0]
   %ifdef ASM_CALL64_GCC
@@ -2341 +2633 @@
   %endif
   %if %5 != 1
-        IEM_SAVE_FLAGS                           A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD                           A3, %2, %3, 0
   %else
-        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF     A3, %2, X86_EFL_AF | X86_EFL_ZF, rax, 64, xAX ; intel
+        IEM_SAVE_FLAGS_ADJUST_AND_CALC_SF_PF_OLD     A3, %2, X86_EFL_AF | X86_EFL_ZF, rax, 64, xAX ; intel
   %endif
         xor     eax, eax
@@ -2462 +2754 @@
  %endif
 
-        IEM_MAYBE_LOAD_FLAGS A2, %2, %3, %3 ; Undefined flags may be passed thru (Intel)
+        IEM_MAYBE_LOAD_FLAGS_OLD A2, %2, %3, %3 ; Undefined flags may be passed thru (Intel)
         mov     ax, [A0]
         %1      A1_8
         mov     [A0], ax
  %if %6 == 2 ; AMD64 3990X: Set AF and clear PF, ZF and SF.
-        IEM_ADJUST_FLAGS    A2, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
+        IEM_ADJUST_FLAGS_OLD    A2, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
  %else
-        IEM_SAVE_FLAGS      A2, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A2, %2, %3, 0
  %endif
         xor     eax, eax
@@ -2528 +2820 @@
  %endif
 
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
  %ifdef ASM_CALL64_GCC
         mov     T1, A2
@@ -2545 +2837 @@
  %endif
  %if %6 == 2 ; AMD64 3990X: Set AF and clear PF, ZF and SF.
-        IEM_ADJUST_FLAGS    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
+        IEM_ADJUST_FLAGS_OLD    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
  %else
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
  %endif
         xor     eax, eax
@@ -2614 +2906 @@
  %endif
 
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     eax, [A0]
  %ifdef ASM_CALL64_GCC
@@ -2632 +2924 @@
  %endif
  %if %6 == 2 ; AMD64 3990X: Set AF and clear PF, ZF and SF.
-        IEM_ADJUST_FLAGS    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
+        IEM_ADJUST_FLAGS_OLD    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
  %else
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
  %endif
         xor     eax, eax
@@ -2702 +2994 @@
   %endif
 
-        IEM_MAYBE_LOAD_FLAGS A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
+        IEM_MAYBE_LOAD_FLAGS_OLD A3, %2, %3, %3 ; Undefined flags may be passed thru (AMD)
         mov     rax, [A0]
   %ifdef ASM_CALL64_GCC
@@ -2720 +3012 @@
   %endif
   %if %6 == 2 ; AMD64 3990X: Set AF and clear PF, ZF and SF.
-        IEM_ADJUST_FLAGS    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
+        IEM_ADJUST_FLAGS_OLD    A3, X86_EFL_PF | X86_EFL_ZF | X86_EFL_SF, X86_EFL_AF
   %else
-        IEM_SAVE_FLAGS      A3, %2, %3, 0
+        IEM_SAVE_FLAGS_OLD      A3, %2, %3, 0
   %endif
         xor     eax, eax
@@ -4756 +5048 @@
         movdqu  xmm1, [A1]
         ptest   xmm0, xmm1
-        IEM_SAVE_FLAGS A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
+        IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
 
         IEMIMPL_SSE_EPILOGUE
@@ -4769 +5061 @@
         vmovdqu ymm1, [A1]
         vptest  ymm0, ymm1
-        IEM_SAVE_FLAGS A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
+        IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF
 
         IEMIMPL_SSE_EPILOGUE
@@ -5643 +5935 @@
         IEMIMPL_CALL_JUMP_TABLE_TARGET T1, A3, 8
 
-        IEM_SAVE_FLAGS A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
         mov    [T2], ecx
 
@@ -5684 +5976 @@
 
         pop     xDX
-        IEM_SAVE_FLAGS A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
         mov    [T2], ecx
 
@@ -5718 +6010 @@
         IEMIMPL_CALL_JUMP_TABLE_TARGET T1, A3, 8
 
-        IEM_SAVE_FLAGS A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
         movdqu  [A0], xmm0
 
@@ -5758 +6050 @@
 
         pop     xDX
-        IEM_SAVE_FLAGS A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_CF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF, 0, X86_EFL_AF | X86_EFL_PF
         movdqu  [A0], xmm0
 
@@ -6102 +6394 @@
         movd    xmm1, A3_32
         ucomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6117 +6409 @@
         movd    xmm1, A3_32
         vucomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6142 +6434 @@
         movq    xmm1, A3
         ucomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6157 +6449 @@
         movq    xmm1, A3
         vucomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6181 +6473 @@
         movd    xmm1, A3_32
         comiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6196 +6488 @@
         movd    xmm1, A3_32
         vcomiss xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6221 +6513 @@
         movq    xmm1, A3
         comisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6236 +6528 @@
         movq    xmm1, A3
         vcomisd xmm0, xmm1
-        IEM_SAVE_FLAGS A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_AF
 
         SSE_AVX_ST_MXCSR R0_32, A0_32
@@ -6488 +6780 @@
         %1      %2
         mov     [A0], %2
-        IEM_SAVE_FLAGS A1, X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF
+        IEM_SAVE_FLAGS_OLD A1, X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF
 
         EPILOGUE_2_ARGS
@@ -6570 +6862 @@
         PROLOGUE_4_ARGS
 
-        IEM_LOAD_FLAGS A2, %2, 0
+        IEM_LOAD_FLAGS_OLD A2, %2, 0
         %1      A1_32, [A0]
         mov     [A0], A1_32
-        IEM_SAVE_FLAGS A2, %2, 0, 0
+        IEM_SAVE_FLAGS_OLD A2, %2, 0, 0
 
         EPILOGUE_4_ARGS
@@ -6590 +6882 @@
         PROLOGUE_4_ARGS
 
-        IEM_LOAD_FLAGS A2, %2, 0
+        IEM_LOAD_FLAGS_OLD A2, %2, 0
         %1      A1, [A0]
         mov     [A0], A1
-        IEM_SAVE_FLAGS A2, %2, 0, 0
+        IEM_SAVE_FLAGS_OLD A2, %2, 0, 0
 
         EPILOGUE_4_ARGS

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -120 +120 @@
  *
  * @returns Status bits.
- * @param   a_pfEFlags      Pointer to the 32-bit EFLAGS value to update.
+ * @param   a_fEFlagsVar    The 32-bit EFLAGS variable to update.
  * @param   a_uResult       Unsigned result value.
  * @param   a_uSrc          The source value (for AF calc).
@@ -128 +128 @@
  * @param   a_uSrcOf        The a_uSrc value to use for overflow calculation.
  */
-#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_pfEFlags, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
+#define IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(a_fEFlagsVar, a_uResult, a_uDst, a_uSrc, a_cBitsWidth, a_CfExpr, a_uSrcOf) \
     do { \
-        uint32_t fEflTmp = *(a_pfEFlags); \
-        fEflTmp &= ~X86_EFL_STATUS_BITS; \
-        fEflTmp |= (a_CfExpr) << X86_EFL_CF_BIT; \
-        fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \
-        fEflTmp |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
-        fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
-        fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
+        a_fEFlagsVar &= ~X86_EFL_STATUS_BITS; \
+        a_fEFlagsVar |= (a_CfExpr) << X86_EFL_CF_BIT; \
+        a_fEFlagsVar |= IEM_EFL_CALC_PARITY(a_uResult); \
+        a_fEFlagsVar |= ((uint32_t)(a_uResult) ^ (uint32_t)(a_uSrc) ^ (uint32_t)(a_uDst)) & X86_EFL_AF; \
+        a_fEFlagsVar |= X86_EFL_CALC_ZF(a_uResult); \
+        a_fEFlagsVar |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
         \
         /* Overflow during ADDition happens when both inputs have the same signed \
@@ -147 +146 @@
            \
            See also: http://teaching.idallen.com/dat2343/10f/notes/040_overflow.txt */ \
-        fEflTmp |= X86_EFL_GET_OF_ ## a_cBitsWidth(  (  ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
-                                                      & RT_BIT_64(a_cBitsWidth - 1)) \
-                                                   & ((a_uResult) ^ (a_uDst)) ); \
-        *(a_pfEFlags) = fEflTmp; \
+        a_fEFlagsVar |= X86_EFL_GET_OF_ ## a_cBitsWidth(  (  ((uint ## a_cBitsWidth ## _t)~((a_uDst) ^ (a_uSrcOf))) \
+                                                           & RT_BIT_64(a_cBitsWidth - 1)) \
+                                                        & ((a_uResult) ^ (a_uDst)) ); \
     } while (0)
 
@@ -161 +159 @@
  *
  * @returns Status bits.
- * @param   a_pfEFlags      Pointer to the 32-bit EFLAGS value to update.
+ * @param   a_fEFlagsVar    The 32-bit EFLAGS variable to update.
  * @param   a_uResult       Unsigned result value.
  * @param   a_cBitsWidth    The width of the result (8, 16, 32, 64).
  * @param   a_fExtra        Additional bits to set.
  */
-#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(a_pfEFlags, a_uResult, a_cBitsWidth, a_fExtra) \
+#define IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(a_fEFlagsVar, a_uResult, a_cBitsWidth, a_fExtra) \
     do { \
-        uint32_t fEflTmp = *(a_pfEFlags); \
-        fEflTmp &= ~X86_EFL_STATUS_BITS; \
-        fEflTmp |= IEM_EFL_CALC_PARITY(a_uResult); \
-        fEflTmp |= X86_EFL_CALC_ZF(a_uResult); \
-        fEflTmp |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
-        fEflTmp |= (a_fExtra); \
-        *(a_pfEFlags) = fEflTmp; \
+        a_fEFlagsVar &= ~X86_EFL_STATUS_BITS; \
+        a_fEFlagsVar |= IEM_EFL_CALC_PARITY(a_uResult); \
+        a_fEFlagsVar |= X86_EFL_CALC_ZF(a_uResult); \
+        a_fEFlagsVar |= X86_EFL_CALC_SF(a_uResult, a_cBitsWidth); \
+        a_fEFlagsVar |= (a_fExtra); \
     } while (0)
 
@@ -676 +672 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_add_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_add_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
 {
     uint64_t uDst    = *puDst;
     uint64_t uResult = uDst + uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 64, uResult < uDst, uSrc);
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_add_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_add_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
 {
     uint32_t uDst    = *puDst;
     uint32_t uResult = uDst + uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_add_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 32, uResult < uDst, uSrc);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_add_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
 {
     uint16_t uDst    = *puDst;
     uint16_t uResult = uDst + uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_add_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 16, uResult < uDst, uSrc);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_add_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
 {
     uint8_t uDst    = *puDst;
     uint8_t uResult = uDst + uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 8, uResult < uDst, uSrc);
+    return fEFlags;
 }
 
@@ -718 +718 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_add_u64(puDst, uSrc, pfEFlags);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_adc_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_add_u64(fEFlags, puDst, uSrc);
     else
     {
@@ -727 +727 @@
         uint64_t uResult = uDst + uSrc + 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
-    }
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 64, uResult <= uDst, uSrc);
+    }
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_add_u32(puDst, uSrc, pfEFlags);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_adc_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_add_u32(fEFlags, puDst, uSrc);
     else
     {
@@ -742 +743 @@
         uint32_t uResult = uDst + uSrc + 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
-    }
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_add_u16(puDst, uSrc, pfEFlags);
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 32, uResult <= uDst, uSrc);
+    }
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_adc_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_add_u16(fEFlags, puDst, uSrc);
     else
     {
@@ -756 +758 @@
         uint16_t uResult = uDst + uSrc + 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
-    }
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_adc_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_add_u8(puDst, uSrc, pfEFlags);
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 16, uResult <= uDst, uSrc);
+    }
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_adc_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_add_u8(fEFlags, puDst, uSrc);
     else
     {
@@ -770 +773 @@
         uint8_t uResult = uDst + uSrc + 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
-    }
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 8, uResult <= uDst, uSrc);
+    }
+    return fEFlags;
 }
 
@@ -781 +785 @@
 # if !defined(RT_ARCH_ARM64)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sub_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
 {
     uint64_t uDst    = *puDst;
     uint64_t uResult = uDst - uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 64, uDst < uSrc, uSrc ^ RT_BIT_64(63));
+    return fEFlags;
 }
 
 #  if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sub_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
 {
     uint32_t uDst    = *puDst;
     uint32_t uResult = uDst - uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 32, uDst < uSrc, uSrc ^ RT_BIT_32(31));
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sub_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
 {
     uint16_t uDst    = *puDst;
     uint16_t uResult = uDst - uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_sub_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 16, uDst < uSrc, uSrc ^ (uint16_t)0x8000);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sub_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
 {
     uint8_t uDst    = *puDst;
     uint8_t uResult = uDst - uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 8, uDst < uSrc, uSrc ^ (uint8_t)0x80);
+    return fEFlags;
 }
 
@@ -824 +832 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_sub_u64(puDst, uSrc, pfEFlags);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sbb_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_sub_u64(fEFlags, puDst, uSrc);
     else
     {
@@ -833 +841 @@
         uint64_t uResult = uDst - uSrc - 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
-    }
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 64, uDst <= uSrc, uSrc ^ RT_BIT_64(63));
+    }
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_sub_u32(puDst, uSrc, pfEFlags);
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sbb_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_sub_u32(fEFlags, puDst, uSrc);
     else
     {
@@ -848 +857 @@
         uint32_t uResult = uDst - uSrc - 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
-    }
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_sub_u16(puDst, uSrc, pfEFlags);
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 32, uDst <= uSrc, uSrc ^ RT_BIT_32(31));
+    }
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sbb_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_sub_u16(fEFlags, puDst, uSrc);
     else
     {
@@ -862 +872 @@
         uint16_t uResult = uDst - uSrc - 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
-    }
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_sbb_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
-{
-    if (!(*pfEFlags & X86_EFL_CF))
-        iemAImpl_sub_u8(puDst, uSrc, pfEFlags);
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 16, uDst <= uSrc, uSrc ^ (uint16_t)0x8000);
+    }
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_sbb_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
+{
+    if (!(fEFlags & X86_EFL_CF))
+        fEFlags = iemAImpl_sub_u8(fEFlags, puDst, uSrc);
     else
     {
@@ -876 +887 @@
         uint8_t uResult = uDst - uSrc - 1;
         *puDst = uResult;
-        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(pfEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
-    }
+        IEM_EFL_UPDATE_STATUS_BITS_FOR_ARITHMETIC(fEFlags, uResult, uDst, uSrc, 8, uDst <= uSrc, uSrc ^ (uint8_t)0x80);
+    }
+    return fEFlags;
 }
 
@@ -887 +899 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_or_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_or_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
 {
     uint64_t uResult = *puDst | uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 64, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 64, 0);
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_or_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_or_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
 {
     uint32_t uResult = *puDst | uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 32, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_or_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 32, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_or_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
 {
     uint16_t uResult = *puDst | uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 16, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_or_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 16, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_or_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
 {
     uint8_t uResult = *puDst | uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 8, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 8, 0);
+    return fEFlags;
 }
 
@@ -925 +941 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_xor_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
 {
     uint64_t uResult = *puDst ^ uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 64, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 64, 0);
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_xor_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
 {
     uint32_t uResult = *puDst ^ uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 32, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 32, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_xor_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
 {
     uint16_t uResult = *puDst ^ uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 16, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_xor_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 16, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_xor_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
 {
     uint8_t uResult = *puDst ^ uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 8, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 8, 0);
+    return fEFlags;
 }
 
@@ -963 +983 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_and_u64,(uint64_t *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_and_u64,(uint32_t fEFlags, uint64_t *puDst, uint64_t uSrc))
 {
     uint64_t const uResult = *puDst & uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 64, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 64, 0);
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_and_u32,(uint32_t *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_and_u32,(uint32_t fEFlags, uint32_t *puDst, uint32_t uSrc))
 {
     uint32_t const uResult = *puDst & uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 32, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_and_u16,(uint16_t *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 32, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_and_u16,(uint32_t fEFlags, uint16_t *puDst, uint16_t uSrc))
 {
     uint16_t const uResult = *puDst & uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 16, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_and_u8,(uint8_t *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 16, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_and_u8,(uint32_t fEFlags, uint8_t *puDst, uint8_t uSrc))
 {
     uint8_t const uResult = *puDst & uSrc;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 8, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 8, 0);
+    return fEFlags;
 }
 
@@ -1006 +1030 @@
     uint64_t const uResult = ~uSrc1 & uSrc2;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 64, 0);
+    uint32_t fEFlags = *pfEFlags;
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 64, 0);
+    *pfEFlags = fEFlags;
 }
 
@@ -1014 +1040 @@
     uint32_t const uResult = ~uSrc1 & uSrc2;
     *puDst = uResult;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 32, 0);
+    uint32_t fEFlags = *pfEFlags;
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 32, 0);
+    *pfEFlags = fEFlags;
 }
 
@@ -1039 +1067 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u64,(uint64_t const *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cmp_u64,(uint32_t fEFlags, uint64_t const *puDst, uint64_t uSrc))
 {
     uint64_t uDstTmp = *puDst;
-    iemAImpl_sub_u64(&uDstTmp, uSrc, pfEFlags);
+    return iemAImpl_sub_u64(fEFlags, &uDstTmp, uSrc);
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u32,(uint32_t const *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cmp_u32,(uint32_t fEFlags, uint32_t const *puDst, uint32_t uSrc))
 {
     uint32_t uDstTmp = *puDst;
-    iemAImpl_sub_u32(&uDstTmp, uSrc, pfEFlags);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u16,(uint16_t const *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    return iemAImpl_sub_u32(fEFlags, &uDstTmp, uSrc);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cmp_u16,(uint32_t fEFlags, uint16_t const *puDst, uint16_t uSrc))
 {
     uint16_t uDstTmp = *puDst;
-    iemAImpl_sub_u16(&uDstTmp, uSrc, pfEFlags);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_cmp_u8,(uint8_t const *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    return iemAImpl_sub_u16(fEFlags, &uDstTmp, uSrc);
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_cmp_u8,(uint32_t fEFlags, uint8_t const *puDst, uint8_t uSrc))
 {
     uint8_t uDstTmp = *puDst;
-    iemAImpl_sub_u8(&uDstTmp, uSrc, pfEFlags);
+    return iemAImpl_sub_u8(fEFlags, &uDstTmp, uSrc);
 }
 
@@ -1073 +1101 @@
  */
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_test_u64,(uint64_t const *puDst, uint64_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_test_u64,(uint32_t fEFlags, uint64_t const *puDst, uint64_t uSrc))
 {
     uint64_t uResult = *puDst & uSrc;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 64, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 64, 0);
+    return fEFlags;
 }
 
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
 
-IEM_DECL_IMPL_DEF(void, iemAImpl_test_u32,(uint32_t const *puDst, uint32_t uSrc, uint32_t *pfEFlags))
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_test_u32,(uint32_t fEFlags, uint32_t const *puDst, uint32_t uSrc))
 {
     uint32_t uResult = *puDst & uSrc;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 32, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_test_u16,(uint16_t const *puDst, uint16_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 32, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_test_u16,(uint32_t fEFlags, uint16_t const *puDst, uint16_t uSrc))
 {
     uint16_t uResult = *puDst & uSrc;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 16, 0);
-}
-
-
-IEM_DECL_IMPL_DEF(void, iemAImpl_test_u8,(uint8_t const *puDst, uint8_t uSrc, uint32_t *pfEFlags))
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 16, 0);
+    return fEFlags;
+}
+
+
+IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_test_u8,(uint32_t fEFlags, uint8_t const *puDst, uint8_t uSrc))
 {
     uint8_t uResult = *puDst & uSrc;
-    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(pfEFlags, uResult, 8, 0);
+    IEM_EFL_UPDATE_STATUS_BITS_FOR_LOGICAL(fEFlags, uResult, 8, 0);
+    return fEFlags;
 }
 
@@ -1117 +1149 @@
         { \
             uTmp = uOld; \
-            fEflTmp = *pfEFlags; \
-            iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
+            fEflTmp = iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(fEFlagsIn, &uTmp, uSrc); \
         } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
-        *pfEFlags = fEflTmp; \
+        return fEflTmp; \
     } while (0)
 
 
 #define EMIT_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth) \
-    IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ##  _locked,(uint ## a_cBitsWidth ## _t *puDst, \
-                                                                                       uint ## a_cBitsWidth ## _t uSrc, \
-                                                                                       uint32_t *pfEFlags)) \
+    IEM_DECL_IMPL_DEF(uint32_t, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ##  _locked,(uint32_t fEFlagsIn, \
+                                                                                           uint ## a_cBitsWidth ## _t *puDst, \
+                                                                                           uint ## a_cBitsWidth ## _t uSrc)) \
     { \
         DO_LOCKED_BIN_OP(a_Mnemonic, a_cBitsWidth); \
@@ -1407 +1438 @@
 
 
-EMIT_LOCKED_BIN_OP(btc, 64)
-EMIT_LOCKED_BIN_OP(btr, 64)
-EMIT_LOCKED_BIN_OP(bts, 64)
+/** 64-bit locked binary operand operation. */
+# define DO_LOCKED_BIN_TODO_OP(a_Mnemonic, a_cBitsWidth) \
+    do { \
+        uint ## a_cBitsWidth ## _t uOld = ASMAtomicUoReadU ## a_cBitsWidth(puDst); \
+        uint ## a_cBitsWidth ## _t uTmp; \
+        uint32_t fEflTmp; \
+        do \
+        { \
+            uTmp = uOld; \
+            fEflTmp = *pfEFlags; \
+            iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth(&uTmp, uSrc, &fEflTmp); \
+        } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uTmp, uOld, &uOld)); \
+        *pfEFlags = fEflTmp; \
+    } while (0)
+
+
+#define EMIT_LOCKED_BIN_TODO_OP(a_Mnemonic, a_cBitsWidth) \
+    IEM_DECL_IMPL_DEF(void, iemAImpl_ ## a_Mnemonic ## _u ## a_cBitsWidth ##  _locked,(uint ## a_cBitsWidth ## _t *puDst, \
+                                                                                       uint ## a_cBitsWidth ## _t uSrc, \
+                                                                                       uint32_t *pfEFlags)) \
+    { \
+        DO_LOCKED_BIN_TODO_OP(a_Mnemonic, a_cBitsWidth); \
+    }
+
+
+EMIT_LOCKED_BIN_TODO_OP(btc, 64)
+EMIT_LOCKED_BIN_TODO_OP(btr, 64)
+EMIT_LOCKED_BIN_TODO_OP(bts, 64)
 # if !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY)
-EMIT_LOCKED_BIN_OP(btc, 32)
-EMIT_LOCKED_BIN_OP(btr, 32)
-EMIT_LOCKED_BIN_OP(bts, 32)
-
-EMIT_LOCKED_BIN_OP(btc, 16)
-EMIT_LOCKED_BIN_OP(btr, 16)
-EMIT_LOCKED_BIN_OP(bts, 16)
+EMIT_LOCKED_BIN_TODO_OP(btc, 32)
+EMIT_LOCKED_BIN_TODO_OP(btr, 32)
+EMIT_LOCKED_BIN_TODO_OP(bts, 32)
+
+EMIT_LOCKED_BIN_TODO_OP(btc, 16)
+EMIT_LOCKED_BIN_TODO_OP(btr, 16)
+EMIT_LOCKED_BIN_TODO_OP(bts, 16)
 # endif /* !defined(RT_ARCH_X86) || defined(IEM_WITHOUT_ASSEMBLY) */
 
@@ -1757 +1813 @@
     uint32_t fEfl2 = fEfl1; \
     *puDst = uSrc; \
-    iemAImpl_sub_u ## a_cBits(&uSrc, 1, &fEfl1); \
-    iemAImpl_and_u ## a_cBits(puDst, uSrc, &fEfl2); \
+    fEfl1 = iemAImpl_sub_u ## a_cBits(fEfl1, &uSrc, 1); \
+    fEfl2 = iemAImpl_and_u ## a_cBits(fEfl2, puDst, uSrc); \
     \
     /* AMD: The carry flag is from the SUB operation. */ \
@@ -1785 +1841 @@
     uint32_t fEfl2 = fEfl1; \
     *puDst = uSrc; \
-    iemAImpl_sub_u ## a_cBits(&uSrc, 1, &fEfl1); \
-    iemAImpl_xor_u ## a_cBits(puDst, uSrc, &fEfl2); \
+    fEfl1 = iemAImpl_sub_u ## a_cBits(fEfl1, &uSrc, 1); \
+    fEfl2 = iemAImpl_xor_u ## a_cBits(fEfl2, puDst, uSrc); \
     \
     /* AMD: The carry flag is from the SUB operation. */ \
@@ -1814 +1870 @@
     *puDst = uSrc; \
     iemAImpl_neg_u ## a_cBits(&uSrc, &fEfl1); \
-    iemAImpl_and_u ## a_cBits(puDst, uSrc, &fEfl2); \
+    fEfl2 = iemAImpl_and_u ## a_cBits(fEfl2, puDst, uSrc); \
     \
     /* AMD: The carry flag is from the SUB operation. */ \
@@ -2023 +2079 @@
     a_Type uDst    = *puDst; \
     a_Type uResult = uDst; \
-    iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, pfEFlags); \
+    *pfEFlags = iemAImpl_add_u ## a_cBitsWidth(*pfEFlags, &uResult, *puReg); \
     *puDst = uResult; \
     *puReg = uDst; \
@@ -2036 +2092 @@
     { \
         uResult = uOld; \
-        fEflTmp = *pfEFlags; \
-        iemAImpl_add_u ## a_cBitsWidth(&uResult, *puReg, &fEflTmp); \
+        fEflTmp = iemAImpl_add_u ## a_cBitsWidth(*pfEFlags, &uResult, *puReg); \
     } while (!ASMAtomicCmpXchgExU ## a_cBitsWidth(puDst, uResult, uOld, &uOld)); \
     *puReg    = uOld; \
@@ -2064 +2119 @@
     if (ASMAtomicCmpXchgExU8(pu8Dst, uSrcReg, uOld, puAl))
         Assert(*puAl == uOld);
-    iemAImpl_cmp_u8(&uOld, *puAl, pEFlags);
+    *pEFlags = iemAImpl_cmp_u8(*pEFlags, &uOld, *puAl);
 }
 
@@ -2073 +2128 @@
     if (ASMAtomicCmpXchgExU16(pu16Dst, uSrcReg, uOld, puAx))
         Assert(*puAx == uOld);
-    iemAImpl_cmp_u16(&uOld, *puAx, pEFlags);
+    *pEFlags = iemAImpl_cmp_u16(*pEFlags, &uOld, *puAx);
 }
 
@@ -2082 +2137 @@
     if (ASMAtomicCmpXchgExU32(pu32Dst, uSrcReg, uOld, puEax))
         Assert(*puEax == uOld);
-    iemAImpl_cmp_u32(&uOld, *puEax, pEFlags);
+    *pEFlags = iemAImpl_cmp_u32(*pEFlags, &uOld, *puEax);
 }
 
@@ -2098 +2153 @@
     if (ASMAtomicCmpXchgExU64(pu64Dst, uSrcReg, uOld, puRax))
         Assert(*puRax == uOld);
-    iemAImpl_cmp_u64(&uOld, *puRax, pEFlags);
+    *pEFlags = iemAImpl_cmp_u64(*pEFlags, &uOld, *puRax);
 }
 
@@ -2185 +2240 @@
         {
             *pu16Dst = uSrcReg;
-            iemAImpl_cmp_u16(&uOld, uOld, pEFlags);
+            *pEFlags = iemAImpl_cmp_u16(*pEFlags, &uOld, uOld);
         }
         else
         {
             *puAx = uDst;
-            iemAImpl_cmp_u16(&uOld, uDst, pEFlags);
+            *pEFlags = iemAImpl_cmp_u16(*pEFlags, &uOld, uDst);
         }
     }
@@ -2211 +2266 @@
         {
             *pu32Dst = uSrcReg;
-            iemAImpl_cmp_u32(&uOld, uOld, pEFlags);
+            *pEFlags = iemAImpl_cmp_u32(*pEFlags, &uOld, uOld);
         }
         else
         {
             *puEax = uDst;
-            iemAImpl_cmp_u32(&uOld, uDst, pEFlags);
+            *pEFlags = iemAImpl_cmp_u32(*pEFlags, &uOld, uDst);
         }
     }
@@ -2239 +2294 @@
         {
             *pu64Dst = uSrc;
-            iemAImpl_cmp_u64(&uOld, uOld, pEFlags);
+            *pEFlags = iemAImpl_cmp_u64(*pEFlags, &uOld, uOld);
         }
         else
         {
             *puRax = uDst;
-            iemAImpl_cmp_u64(&uOld, uDst, pEFlags);
+            *pEFlags = iemAImpl_cmp_u64(*pEFlags, &uOld, uDst);
         }
     }
@@ -2264 +2319 @@
         {
             *pu64Dst = uSrcReg;
-            iemAImpl_cmp_u64(&uOld, uOld, pEFlags);
+            *pEFlags = iemAImpl_cmp_u64(*pEFlags, &uOld, uOld);
         }
         else
         {
             *puRax = uDst;
-            iemAImpl_cmp_u64(&uOld, uDst, pEFlags);
+            *pEFlags = iemAImpl_cmp_u64(*pEFlags, &uOld, uDst);
         }
     }

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -255 +255 @@
 static void iemHlpUpdateArithEFlagsU8(PVMCPUCC pVCpu, uint8_t u8Result, uint32_t fToUpdate, uint32_t fUndefined)
 {
-    uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
-    iemAImpl_test_u8(&u8Result, u8Result, &fEFlags);
+    uint32_t fEFlags = iemAImpl_test_u8(pVCpu->cpum.GstCtx.eflags.u, &u8Result, u8Result);
     pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
     pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
@@ -272 +271 @@
 static void iemHlpUpdateArithEFlagsU16(PVMCPUCC pVCpu, uint16_t u16Result, uint32_t fToUpdate, uint32_t fUndefined)
 {
-    uint32_t fEFlags = pVCpu->cpum.GstCtx.eflags.u;
-    iemAImpl_test_u16(&u16Result, u16Result, &fEFlags);
+    uint32_t fEFlags = iemAImpl_test_u16(pVCpu->cpum.GstCtx.eflags.u, &u16Result, u16Result);
     pVCpu->cpum.GstCtx.eflags.u &= ~(fToUpdate | fUndefined);
     pVCpu->cpum.GstCtx.eflags.u |= (fToUpdate | fUndefined) & fEFlags;
@@ -8430 +8428 @@
             || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
         {
-            iemAImpl_add_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth);
+            pVCpu->cpum.GstCtx.eflags.uBoth = iemAImpl_add_u16(pVCpu->cpum.GstCtx.eflags.uBoth, &pVCpu->cpum.GstCtx.ax, 0x106);
             pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
             pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;
@@ -8474 +8472 @@
             || (pVCpu->cpum.GstCtx.ax & 0xf) >= 10)
         {
-            iemAImpl_sub_u16(&pVCpu->cpum.GstCtx.ax, 0x106, &pVCpu->cpum.GstCtx.eflags.uBoth);
+            pVCpu->cpum.GstCtx.eflags.uBoth = iemAImpl_sub_u16(pVCpu->cpum.GstCtx.eflags.uBoth, &pVCpu->cpum.GstCtx.ax, 0x106);
             pVCpu->cpum.GstCtx.eflags.Bits.u1AF = 1;
             pVCpu->cpum.GstCtx.eflags.Bits.u1CF = 1;

trunk/src/VBox/VMM/VMMAll/IEMAllCImplStrInstr.cpp.h

@@ -221 +221 @@
                     {
                         /* All matches, only compare the last itme to get the right eflags. */
-                        RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&puSrc1Mem[cLeftPage-1], puSrc2Mem[cLeftPage-1], &uEFlags);
+                        uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&puSrc1Mem[cLeftPage-1], puSrc2Mem[cLeftPage-1]);
                         uSrc1AddrReg += cLeftPage * cbIncr;
                         uSrc2AddrReg += cLeftPage * cbIncr;
@@ -233 +233 @@
                         do
                         {
-                            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&puSrc1Mem[off], puSrc2Mem[off], &uEFlags);
+                            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&puSrc1Mem[off], puSrc2Mem[off]);
                             off++;
                         } while (   off < cLeftPage
@@ -275 +275 @@
             if (rcStrict != VINF_SUCCESS)
                 return rcStrict;
-            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(&uValue1, uValue2, &uEFlags);
+            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, &uValue1, uValue2);
 
             pVCpu->cpum.GstCtx.ADDR_rSI = uSrc1AddrReg += cbIncr;
@@ -387 +387 @@
                     {
                         /* All matches, only compare the last item to get the right eflags. */
-                        RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&puSrc1Mem[cLeftPage-1], puSrc2Mem[cLeftPage-1], &uEFlags);
+                        uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&puSrc1Mem[cLeftPage-1], puSrc2Mem[cLeftPage-1]);
                         uSrc1AddrReg += cLeftPage * cbIncr;
                         uSrc2AddrReg += cLeftPage * cbIncr;
@@ -399 +399 @@
                         do
                         {
-                            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&puSrc1Mem[off], puSrc2Mem[off], &uEFlags);
+                            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&puSrc1Mem[off], puSrc2Mem[off]);
                             off++;
                         } while (   off < cLeftPage
@@ -441 +441 @@
             if (rcStrict != VINF_SUCCESS)
                 return rcStrict;
-            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(&uValue1, uValue2, &uEFlags);
+            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, &uValue1, uValue2);
 
             pVCpu->cpum.GstCtx.ADDR_rSI = uSrc1AddrReg += cbIncr;
@@ -538 +538 @@
 
                 /* Update the regs. */
-                RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&uValueReg, uTmpValue, &uEFlags);
+                uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&uValueReg, uTmpValue);
                 pVCpu->cpum.GstCtx.ADDR_rCX = uCounterReg -= i;
                 pVCpu->cpum.GstCtx.ADDR_rDI = uAddrReg    += i * cbIncr;
@@ -570 +570 @@
             if (rcStrict != VINF_SUCCESS)
                 return rcStrict;
-            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&uValueReg, uTmpValue, &uEFlags);
+            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&uValueReg, uTmpValue);
 
             pVCpu->cpum.GstCtx.ADDR_rDI = uAddrReg += cbIncr;
@@ -666 +666 @@
 
                 /* Update the regs. */
-                RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&uValueReg, uTmpValue, &uEFlags);
+                uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&uValueReg, uTmpValue);
                 pVCpu->cpum.GstCtx.ADDR_rCX = uCounterReg -= i;
                 pVCpu->cpum.GstCtx.ADDR_rDI = uAddrReg    += i * cbIncr;
@@ -698 +698 @@
             if (rcStrict != VINF_SUCCESS)
                 return rcStrict;
-            RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)((OP_TYPE *)&uValueReg, uTmpValue, &uEFlags);
+            uEFlags = RT_CONCAT(iemAImpl_cmp_u,OP_SIZE)(uEFlags, (OP_TYPE *)&uValueReg, uTmpValue);
             pVCpu->cpum.GstCtx.ADDR_rDI = uAddrReg += cbIncr;
             pVCpu->cpum.GstCtx.ADDR_rCX = --uCounterReg;

trunk/src/VBox/VMM/VMMAll/IEMAllInstCommon.cpp.h

@@ -46 +46 @@
 
 /** Function table for the BSF instruction. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf =
 {
     NULL,  NULL,
@@ -55 +55 @@
 
 /** Function table for the BSF instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_amd =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf_amd =
 {
     NULL,  NULL,
@@ -64 +64 @@
 
 /** Function table for the BSF instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsf_intel =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsf_intel =
 {
     NULL,  NULL,
@@ -73 +73 @@
 
 /** EFLAGS variation selection table for the BSF instruction. */
-IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsf_eflags[] =
+IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_bsf_eflags[] =
 {
     &g_iemAImpl_bsf,
@@ -82 +82 @@
 
 /** Function table for the BSR instruction. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr =
 {
     NULL,  NULL,
@@ -91 +91 @@
 
 /** Function table for the BSR instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_amd =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr_amd =
 {
     NULL,  NULL,
@@ -100 +100 @@
 
 /** Function table for the BSR instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_bsr_intel =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_bsr_intel =
 {
     NULL,  NULL,
@@ -109 +109 @@
 
 /** EFLAGS variation selection table for the BSR instruction. */
-IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_bsr_eflags[] =
+IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_bsr_eflags[] =
 {
     &g_iemAImpl_bsr,
@@ -118 +118 @@
 
 /** Function table for the IMUL instruction. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two =
 {
     NULL,  NULL,
@@ -127 +127 @@
 
 /** Function table for the IMUL instruction, AMD EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_amd =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two_amd =
 {
     NULL,  NULL,
@@ -136 +136 @@
 
 /** Function table for the IMUL instruction, Intel EFLAGS variant. */
-IEM_STATIC const IEMOPBINSIZES g_iemAImpl_imul_two_intel =
+IEM_STATIC const IEMOPBINTODOSIZES g_iemAImpl_imul_two_intel =
 {
     NULL,  NULL,
@@ -145 +145 @@
 
 /** EFLAGS variation selection table for the IMUL instruction. */
-IEM_STATIC const IEMOPBINSIZES * const g_iemAImpl_imul_two_eflags[] =
+IEM_STATIC const IEMOPBINTODOSIZES * const g_iemAImpl_imul_two_eflags[] =
 {
     &g_iemAImpl_imul_two,
@@ -154 +154 @@
 
 /** EFLAGS variation selection table for the 16-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINU16 const g_iemAImpl_imul_two_u16_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINTODOU16 const g_iemAImpl_imul_two_u16_eflags[] =
 {
     iemAImpl_imul_two_u16,
@@ -163 +163 @@
 
 /** EFLAGS variation selection table for the 32-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINU32 const g_iemAImpl_imul_two_u32_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINTODOU32 const g_iemAImpl_imul_two_u32_eflags[] =
 {
     iemAImpl_imul_two_u32,
@@ -172 +172 @@
 
 /** EFLAGS variation selection table for the 64-bit IMUL instruction. */
-IEM_STATIC PFNIEMAIMPLBINU64 const g_iemAImpl_imul_two_u64_eflags[] =
+IEM_STATIC PFNIEMAIMPLBINTODOU64 const g_iemAImpl_imul_two_u64_eflags[] =
 {
     iemAImpl_imul_two_u64,

trunk/src/VBox/VMM/VMMAll/IEMAllInstCommonBodyMacros.h

@@ -32 +32 @@
  */
 
-
-/**
- * Special case body for word/dword/qword instruction like SUB and XOR that can
- * be used to zero a register.
- *
- * This can be used both for the rv_rm and rm_rv forms since it's working on the
- * same register.
- */
-#define IEMOP_BODY_BINARY_rv_SAME_REG_ZERO(a_bRm) \
-    if (   (a_bRm >> X86_MODRM_REG_SHIFT) == ((a_bRm & X86_MODRM_RM_MASK) | (X86_MOD_REG << X86_MODRM_REG_SHIFT)) \
-        && pVCpu->iem.s.uRexReg == pVCpu->iem.s.uRexB) \
-    { \
-        switch (pVCpu->iem.s.enmEffOpSize) \
-        { \
-            case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(0, 0); \
-                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_STORE_GREG_U16_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
-                IEM_MC_LOCAL_EFLAGS(fEFlags); \
-                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
-                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
-                IEM_MC_COMMIT_EFLAGS(fEFlags); \
-                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
-                IEM_MC_END(); \
-                break; \
-                \
-            case IEMMODE_32BIT: \
-                IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
-                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_STORE_GREG_U32_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
-                IEM_MC_LOCAL_EFLAGS(fEFlags); \
-                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
-                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
-                IEM_MC_COMMIT_EFLAGS(fEFlags); \
-                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
-                IEM_MC_END(); \
-                break; \
-                \
-            case IEMMODE_64BIT: \
-                IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
-                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_STORE_GREG_U64_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
-                IEM_MC_LOCAL_EFLAGS(fEFlags); \
-                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
-                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
-                IEM_MC_COMMIT_EFLAGS(fEFlags); \
-                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
-                IEM_MC_END(); \
-                break; \
-                \
-            IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
-        } \
-    } ((void)0)
 
 /**
@@ -103 +50 @@
                 IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint16_t,        u16Src,  1); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -113 +60 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *,  pu16Dst, 0); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -126 +73 @@
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint32_t,        u32Src,  1); \
+                IEM_MC_ARG(uint32_t,        u32Src,     2); \
                 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -136 +83 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *,  pu32Dst, 0); \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -150 +97 @@
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint64_t,        u64Src,  1); \
+                IEM_MC_ARG(uint64_t,        u64Src,     2); \
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -160 +107 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *,  pu64Dst, 0); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -185 +132 @@
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint16_t,   u16Src,  1); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
                 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -195 +142 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU16, fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -210 +157 @@
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint32_t,   u32Src,  1); \
+                IEM_MC_ARG(uint32_t,        u32Src,     2); \
                 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -220 +167 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
+                    IEM_MC_ARG(uint32_t *, pu32Dst,     1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU32, fEFlagsIn, pu32Dst, u32Src); \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -236 +183 @@
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint64_t,   u64Src,  1); \
+                IEM_MC_ARG(uint64_t,        u64Src,  2); \
                 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -246 +193 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *, pu64Dst, 0); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU64, fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -261 +208 @@
     (void)0
 
+
 /**
- * Body for word/dword/qword the instruction CMP, ++ with a register as the
- * destination.
+ * Body for word/dword/qword instructions like ADD, AND, OR, ++ with a register
+ * as the destination.
  *
  * @note Used both in OneByte and TwoByte0f.
  */
-#define IEMOP_BODY_BINARY_rv_rm_RO(a_bRm, a_InsNm, a_fNativeArchs) \
+#define IEMOP_BODY_BINARY_TODO_rv_rm(a_bRm, a_fnNormalU16, a_fnNormalU32, a_fnNormalU64, a_f16BitMcFlag, a_EmitterBasename, a_fNativeArchs) \
     /* \
      * If rm is denoting a register, no more instruction bytes. \
@@ -276 +224 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(0, 0); \
+                IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
                 IEM_MC_ARG(uint16_t,        u16Src,  1); \
@@ -284 +232 @@
                     IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -291 +240 @@
                     IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -306 +255 @@
                     IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -313 +263 @@
                     IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -328 +279 @@
                     IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -335 +287 @@
                     IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -352 +304 @@
         { \
             case IEMMODE_16BIT: \
-                IEM_MC_BEGIN(0, 0); \
+                IEM_MC_BEGIN(a_f16BitMcFlag, 0); \
                 IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
@@ -362 +314 @@
                     IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -369 +322 @@
                     IEM_MC_ARG(uint32_t *, pEFlags, 2); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -386 +339 @@
                     IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -393 +347 @@
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU32, pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -410 +365 @@
                     IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
-                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_EmitterBasename,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Dst); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
@@ -417 +373 @@
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                     IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstOneByte.cpp.h

@@ -91 +91 @@
         IEM_MC_BEGIN(0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,   2); \
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
         IEM_MC_NATIVE_IF(a_fRegRegNativeArchs) { \
@@ -101 +101 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,  1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlags, 0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlags, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS_OPT(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -114 +114 @@
         /* \
          * We're accessing memory. \
-         * Note! We're putting the eflags on the stack here so we can commit them \
-         *       after the memory. \
          */ \
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) || (pVCpu->iem.s.fExec & IEM_F_X86_DISREGARD_LOCK)) \
         { \
             IEM_MC_BEGIN(0, 0); \
-            IEM_MC_ARG(uint8_t *,  pu8Dst,           0); \
-            IEM_MC_ARG(uint8_t,    u8Src,            1); \
-            IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-            IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-            \
+            IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
             IEMOP_HLP_DONE_DECODING(); \
+            \
+            IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,         1); \
             IEM_MC_MEM_MAP_U8_RW(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+            IEM_MC_ARG(uint8_t,     u8Src,          2); \
             IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlags,        0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlags, pu8Dst, u8Src); \
             \
             IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-            IEM_MC_COMMIT_EFLAGS(EFlags); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
             IEM_MC_END(); \
@@ -140 +138 @@
         { \
             IEM_MC_BEGIN(0, 0); \
-            IEM_MC_ARG(uint8_t *,  pu8Dst,           0); \
-            IEM_MC_ARG(uint8_t,    u8Src,            1); \
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-            IEM_MC_LOCAL(uint8_t, bMapInfoDst); \
-            \
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
             IEMOP_HLP_DONE_DECODING(); \
+            \
+            IEM_MC_LOCAL(uint8_t,   bMapInfoDst); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,         1); \
             IEM_MC_MEM_MAP_U8_ATOMIC(pu8Dst, bMapInfoDst, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+            IEM_MC_ARG(uint8_t,     u8Src,          2); \
             IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8_locked), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,      0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8_locked), fEFlagsIn, pu8Dst, u8Src); \
             \
             IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bMapInfoDst); \
-            IEM_MC_COMMIT_EFLAGS(EFlags); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
             IEM_MC_END(); \
@@ -172 +170 @@
         IEM_MC_BEGIN(0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,      2); \
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
         IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -181 +179 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU8, pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU8, fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -194 +192 @@
         /* \
          * We're accessing memory. \
-         * Note! We're putting the eflags on the stack here so we can commit them \
-         *       after the memory. \
          */ \
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \
@@ -213 +209 @@
             } IEM_MC_NATIVE_ELSE() { \
                 IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                IEM_MC_ARG(uint8_t const *, pu8Dst,          0); \
+                IEM_MC_ARG(uint8_t const *, pu8Dst,     1); \
                 IEM_MC_MEM_MAP_U8_RO(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                IEM_MC_ARG(uint8_t,         u8Src,           1); \
+                IEM_MC_ARG(uint8_t,         u8Src,      2); \
                 IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags, 2); \
-                IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU8, pu8Dst, u8Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,  0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, a_fnNormalU8, fEFlagsIn, pu8Dst, u8Src); \
                 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                IEM_MC_COMMIT_EFLAGS(EFlags); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -246 +242 @@
         IEM_MC_BEGIN(0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,      2); \
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
         IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -256 +252 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -274 +270 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,      2); \
         IEM_MC_FETCH_MEM_U8(u8Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
         IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -284 +280 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -306 +302 @@
         IEM_MC_BEGIN(0, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,      2); \
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
         IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -315 +311 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -333 +329 @@
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint8_t,         u8Src,   1); \
+        IEM_MC_ARG(uint8_t,         u8Src,      2); \
         IEM_MC_FETCH_MEM_U8(u8Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
         IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -342 +338 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0); \
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -369 +365 @@
                 IEM_MC_BEGIN(0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint16_t,   u16Src,  1); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fRegRegNativeArchs) { \
-                    IEM_MC_LOCAL(uint16_t,   u16Dst); \
+                    IEM_MC_LOCAL(uint16_t,  u16Dst); \
                     IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
@@ -379 +375 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -392 +388 @@
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint32_t,   u32Src,  1); \
+                IEM_MC_ARG(uint32_t,        u32Src,  2); \
                 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fRegRegNativeArchs) { \
-                    IEM_MC_LOCAL(uint32_t,   u32Dst); \
+                    IEM_MC_LOCAL(uint32_t,  u32Dst); \
                     IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
@@ -402 +398 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -416 +412 @@
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint64_t,        u64Src,  1); \
+                IEM_MC_ARG(uint64_t,        u64Src,  2); \
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fRegRegNativeArchs) { \
@@ -426 +422 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *,  pu64Dst, 0); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -443 +439 @@
         /* \
          * We're accessing memory. \
-         * Note! We're putting the eflags on the stack here so we can commit them \
-         *       after the memory. \
          */ \
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) || (pVCpu->iem.s.fExec & IEM_F_X86_DISREGARD_LOCK)) \
@@ -452 +446 @@
                 case IEMMODE_16BIT: \
                     IEM_MC_BEGIN(0, 0); \
-                    IEM_MC_ARG(uint16_t *, pu16Dst,          0); \
-                    IEM_MC_ARG(uint16_t,   u16Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint16_t,    u16Src,     2); \
                     IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -472 +466 @@
                 case IEMMODE_32BIT: \
                     IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
-                    IEM_MC_ARG(uint32_t *, pu32Dst,          0); \
-                    IEM_MC_ARG(uint32_t,   u32Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                     IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint32_t,    u32Src,     2); \
                     IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -492 +486 @@
                 case IEMMODE_64BIT: \
                     IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
-                    IEM_MC_ARG(uint64_t *, pu64Dst,          0); \
-                    IEM_MC_ARG(uint64_t,   u64Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint64_t,    u64Src,     2); \
                     IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -522 +516 @@
                 case IEMMODE_16BIT: \
                     IEM_MC_BEGIN(0, 0); \
-                    IEM_MC_ARG(uint16_t *, pu16Dst,          0); \
-                    IEM_MC_ARG(uint16_t,   u16Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_MEM_MAP_U16_ATOMIC(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint16_t,    u16Src,     2); \
                     IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -542 +536 @@
                 case IEMMODE_32BIT: \
                     IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
-                    IEM_MC_ARG(uint32_t *, pu32Dst,          0); \
-                    IEM_MC_ARG(uint32_t,   u32Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                     IEM_MC_MEM_MAP_U32_ATOMIC(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint32_t,    u32Src,     2); \
                     IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo /* CMP,TEST */); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -562 +556 @@
                 case IEMMODE_64BIT: \
                     IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
-                    IEM_MC_ARG(uint64_t *, pu64Dst,          0); \
-                    IEM_MC_ARG(uint64_t,   u64Src,           1); \
                     IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                    IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-                    \
                     IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
                     IEMOP_HLP_DONE_DECODING(); \
+                    \
+                    IEM_MC_LOCAL(uint8_t,   bUnmapInfo); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_MEM_MAP_U64_ATOMIC(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                    IEM_MC_ARG(uint64_t,    u64Src,     2); \
                     IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(pEFlags, EFlags, 2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -601 +595 @@
                 IEM_MC_BEGIN(0, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint16_t,   u16Src,  1); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
-                    IEM_MC_LOCAL(uint16_t,   u16Dst); \
+                    IEM_MC_LOCAL(uint16_t,  u16Dst); \
                     IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
@@ -610 +604 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *, pu16Dst, 0); \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -623 +617 @@
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint32_t,   u32Src,  1); \
+                IEM_MC_ARG(uint32_t,        u32Src,     2); \
                 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
-                    IEM_MC_LOCAL(uint32_t,   u32Dst); \
+                    IEM_MC_LOCAL(uint32_t,  u32Dst); \
                     IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
                     IEM_MC_LOCAL_EFLAGS(uEFlags); \
@@ -632 +626 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *, pu32Dst, 0); \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -645 +639 @@
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-                IEM_MC_ARG(uint64_t,        u64Src,  1); \
+                IEM_MC_ARG(uint64_t,        u64Src,     2); \
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
                 IEM_MC_NATIVE_IF(a_fNativeArchs) { \
@@ -654 +648 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *,  pu64Dst, 0); \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -671 +665 @@
         /* \
          * We're accessing memory. \
-         * Note! We're putting the eflags on the stack here so we can commit them \
-         *       after the memory. \
          */ \
         if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) || (pVCpu->iem.s.fExec & IEM_F_X86_DISREGARD_LOCK)) \
@@ -692 +684 @@
                         IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                     } IEM_MC_NATIVE_ELSE() { \
-                        IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint16_t const *, pu16Dst,         0); \
+                        IEM_MC_LOCAL(uint8_t,         bUnmapInfo); \
+                        IEM_MC_ARG(uint16_t const *,  pu16Dst,      1); \
                         IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG(uint16_t,         u16Src,          1); \
+                        IEM_MC_ARG(uint16_t,          u16Src,       2); \
                         IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags, 2); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(            fEFlagsIn,    0); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -720 +712 @@
                         IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                     } IEM_MC_NATIVE_ELSE() { \
-                        IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint32_t const *, pu32Dst,         0); \
+                        IEM_MC_LOCAL(uint8_t,         bUnmapInfo); \
+                        IEM_MC_ARG(uint32_t const *,  pu32Dst,      1); \
                         IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG(uint32_t,         u32Src,          1); \
+                        IEM_MC_ARG(uint32_t,          u32Src,       2); \
                         IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags, 2); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(            fEFlagsIn,    0); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -748 +740 @@
                         IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                     } IEM_MC_NATIVE_ELSE() { \
-                        IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint64_t const *, pu64Dst,         0); \
+                        IEM_MC_LOCAL(uint8_t,         bUnmapInfo); \
+                        IEM_MC_ARG(uint64_t const *,  pu64Dst,      1); \
                         IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG(uint64_t,         u64Src,          1); \
+                        IEM_MC_ARG(uint64_t,          u64Src,       2); \
                         IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags, 2); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(            fEFlagsIn,    0); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -791 +783 @@
         IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
     } IEM_MC_NATIVE_ELSE() { \
-        IEM_MC_ARG_CONST(uint8_t,   u8Src,/*=*/ u8Imm,  1); \
-        IEM_MC_ARG(uint8_t *,       pu8Dst,             0); \
+        IEM_MC_ARG(uint8_t *,       pu8Dst,             1); \
         IEM_MC_REF_GREG_U8(pu8Dst, X86_GREG_xAX); \
-        IEM_MC_ARG(uint32_t *,      pEFlags,            2); \
-        IEM_MC_REF_EFLAGS(pEFlags); \
-        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+        IEM_MC_ARG_EFLAGS(          fEFlagsIn,          0); \
+        IEM_MC_ARG_CONST(uint8_t,   u8Src,/*=*/ u8Imm,  2); \
+        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
     } IEM_MC_NATIVE_ENDIF(); \
     IEM_MC_ADVANCE_RIP_AND_FINISH();  \
@@ -822 +814 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,    1); \
-                IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
+                IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,    2); \
+                IEM_MC_ARG(uint16_t *,      pu16Dst,                1); \
                 IEM_MC_REF_GREG_U16(pu16Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -847 +839 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,    1); \
-                IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
+                IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,    2); \
+                IEM_MC_ARG(uint32_t *,      pu32Dst,                1); \
                 IEM_MC_REF_GREG_U32(pu32Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xAX); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -873 +865 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,    1); \
-                IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
+                IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,    2); \
+                IEM_MC_ARG(uint64_t *,      pu64Dst,                1); \
                 IEM_MC_REF_GREG_U64(pu64Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -908 +900 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,    1); \
-                IEM_MC_ARG(uint16_t const *,pu16Dst,                0); \
+                IEM_MC_ARG_CONST(uint16_t,  u16Src,/*=*/ u16Imm,    2); \
+                IEM_MC_ARG(uint16_t const *,pu16Dst,                1); \
                 IEM_MC_REF_GREG_U16_CONST(pu16Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -932 +924 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,    1); \
-                IEM_MC_ARG(uint32_t const *,pu32Dst,                0); \
+                IEM_MC_ARG_CONST(uint32_t,  u32Src,/*=*/ u32Imm,    2); \
+                IEM_MC_ARG(uint32_t const *,pu32Dst,                1); \
                 IEM_MC_REF_GREG_U32_CONST(pu32Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -956 +948 @@
                 IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
             } IEM_MC_NATIVE_ELSE() { \
-                IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,    1); \
-                IEM_MC_ARG(uint64_t const *,pu64Dst,                0); \
+                IEM_MC_ARG_CONST(uint64_t,  u64Src,/*=*/ u64Imm,    2); \
+                IEM_MC_ARG(uint64_t const *,pu64Dst,                1); \
                 IEM_MC_REF_GREG_U64_CONST(pu64Dst, X86_GREG_xAX); \
-                IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -1612 +1604 @@
     IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_daa);
 }
+
+
+/**
+ * Special case body for word/dword/qword instruction like SUB and XOR that can
+ * be used to zero a register.
+ *
+ * This can be used both for the rv_rm and rm_rv forms since it's working on the
+ * same register.
+ */
+#define IEMOP_BODY_BINARY_rv_SAME_REG_ZERO(a_bRm) \
+    if (   (a_bRm >> X86_MODRM_REG_SHIFT) == ((a_bRm & X86_MODRM_RM_MASK) | (X86_MOD_REG << X86_MODRM_REG_SHIFT)) \
+        && pVCpu->iem.s.uRexReg == pVCpu->iem.s.uRexB) \
+    { \
+        switch (pVCpu->iem.s.enmEffOpSize) \
+        { \
+            case IEMMODE_16BIT: \
+                IEM_MC_BEGIN(0, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_STORE_GREG_U16_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
+                IEM_MC_LOCAL_EFLAGS(fEFlags); \
+                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
+                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
+                IEM_MC_COMMIT_EFLAGS(fEFlags); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+                \
+            case IEMMODE_32BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_STORE_GREG_U32_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
+                IEM_MC_LOCAL_EFLAGS(fEFlags); \
+                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
+                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
+                IEM_MC_COMMIT_EFLAGS(fEFlags); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+                \
+            case IEMMODE_64BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_STORE_GREG_U64_CONST(IEM_GET_MODRM_RM(pVCpu, a_bRm), 0); \
+                IEM_MC_LOCAL_EFLAGS(fEFlags); \
+                IEM_MC_AND_LOCAL_U32(fEFlags, ~(uint32_t)X86_EFL_STATUS_BITS); \
+                IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \
+                IEM_MC_COMMIT_EFLAGS(fEFlags); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+                \
+            IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
+        } \
+    } ((void)0)
 
 
@@ -1885 +1931 @@
     IEM_MC_DEFER_TO_CIMPL_0_RET(IEM_CIMPL_F_STATUS_FLAGS, RT_BIT_64(kIemNativeGstReg_GprFirst + X86_GREG_xAX), iemCImpl_aaa);
 }
+
+
+/**
+ * Body for word/dword/qword the instruction CMP, ++ with a register as the
+ * destination.
+ *
+ * @note Used both in OneByte and TwoByte0f.
+ */
+#define IEMOP_BODY_BINARY_rv_rm_RO(a_bRm, a_InsNm, a_fNativeArchs) \
+    /* \
+     * If rm is denoting a register, no more instruction bytes. \
+     */ \
+    if (IEM_IS_MODRM_REG_MODE(a_bRm)) \
+    { \
+        switch (pVCpu->iem.s.enmEffOpSize) \
+        { \
+            case IEMMODE_16BIT: \
+                IEM_MC_BEGIN(0, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
+                IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint16_t,  u16Dst); \
+                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
+                    IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            case IEMMODE_32BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint32_t,        u32Src,     2); \
+                IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint32_t,  u32Dst); \
+                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
+                    IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            case IEMMODE_64BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint64_t,        u64Src,     2); \
+                IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_RM(pVCpu, a_bRm)); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint64_t,  u64Dst); \
+                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
+                    IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
+        } \
+    } \
+    else \
+    { \
+        /* \
+         * We're accessing memory. \
+         */ \
+        switch (pVCpu->iem.s.enmEffOpSize) \
+        { \
+            case IEMMODE_16BIT: \
+                IEM_MC_BEGIN(0, 0); \
+                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
+                IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint16_t,        u16Src,     2); \
+                IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint16_t,  u16Dst); \
+                    IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u16Dst, u16Src, uEFlags, 16); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1); \
+                    IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            case IEMMODE_32BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0); \
+                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
+                IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint32_t,        u32Src,  2); \
+                IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint32_t,  u32Dst); \
+                    IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u32Dst, u32Src, uEFlags, 32); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1); \
+                    IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            case IEMMODE_64BIT: \
+                IEM_MC_BEGIN(IEM_MC_F_64BIT, 0); \
+                IEM_MC_LOCAL(RTGCPTR,  GCPtrEffDst); \
+                IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, a_bRm, 0); \
+                IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
+                IEM_MC_ARG(uint64_t,        u64Src,     2); \
+                IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
+                IEM_MC_NATIVE_IF(a_fNativeArchs) { \
+                    IEM_MC_LOCAL(uint64_t,  u64Dst); \
+                    IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); \
+                    IEM_MC_LOCAL_EFLAGS(uEFlags); \
+                    IEM_MC_NATIVE_EMIT_4(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_r_efl), u64Dst, u64Src, uEFlags, 64); \
+                    IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
+                } IEM_MC_NATIVE_ELSE() { \
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1); \
+                    IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, a_bRm)); \
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
+                } IEM_MC_NATIVE_ENDIF(); \
+                IEM_MC_ADVANCE_RIP_AND_FINISH(); \
+                IEM_MC_END(); \
+                break; \
+            \
+            IEM_NOT_REACHED_DEFAULT_CASE_RET(); \
+        } \
+    } \
+    (void)0
 
 
@@ -3172 +3386 @@
         case IEMMODE_16BIT:
         {
-            PFNIEMAIMPLBINU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
+            PFNIEMAIMPLBINTODOU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3219 +3433 @@
         case IEMMODE_32BIT:
         {
-            PFNIEMAIMPLBINU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
+            PFNIEMAIMPLBINTODOU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3267 +3481 @@
         case IEMMODE_64BIT:
         {
-            PFNIEMAIMPLBINU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
+            PFNIEMAIMPLBINTODOU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3374 +3588 @@
         case IEMMODE_16BIT:
         {
-            PFNIEMAIMPLBINU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
+            PFNIEMAIMPLBINTODOU16 const pfnAImplU16 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u16_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3424 +3638 @@
         case IEMMODE_32BIT:
         {
-            PFNIEMAIMPLBINU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
+            PFNIEMAIMPLBINTODOU32 const pfnAImplU32 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u32_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -3472 +3686 @@
         case IEMMODE_64BIT:
         {
-            PFNIEMAIMPLBINU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
+            PFNIEMAIMPLBINTODOU64 const pfnAImplU64 = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_u64_eflags);
             if (IEM_IS_MODRM_REG_MODE(bRm))
             {
@@ -4199 +4413 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
-            IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
+            IEM_MC_ARG(uint8_t *,       pu8Dst,                 1); \
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-            IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     2); \
+            IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4217 +4431 @@
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1); \
-            \
             uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
-            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
             IEMOP_HLP_DONE_DECODING(); \
             \
             IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-            IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
+            IEM_MC_ARG(uint8_t *,       pu8Dst,                 1); \
             IEM_MC_MEM_MAP_U8_RW(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-            IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     2); \
+            IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
             \
             IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-            IEM_MC_COMMIT_EFLAGS(EFlags); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
             IEM_MC_END(); \
@@ -4236 +4449 @@
         { \
             IEM_MC_BEGIN(0, 0); \
-            IEM_MC_ARG(uint8_t *,       pu8Dst,                 0); \
             IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-            IEM_MC_LOCAL(uint8_t, bUnmapInfo); \
-            \
             IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 1); \
             uint8_t u8Imm; IEM_OPCODE_GET_NEXT_U8(&u8Imm); \
-            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
             IEMOP_HLP_DONE_DECODING(); \
             \
+            IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
+            IEM_MC_ARG(uint8_t *,       pu8Dst,                 1); \
             IEM_MC_MEM_MAP_U8_ATOMIC(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-            IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8_locked), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     2); \
+            IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8_locked), fEFlagsIn, pu8Dst, u8Src); \
             \
             IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-            IEM_MC_COMMIT_EFLAGS(EFlags); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
             IEM_MC_END(); \
@@ -4271 +4483 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
         } IEM_MC_NATIVE_ELSE() { \
-            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
-            IEM_MC_ARG(uint8_t const *, pu8Dst,                 0); \
+            IEM_MC_ARG(uint8_t const *, pu8Dst,                 1); \
             IEM_MC_REF_GREG_U8_CONST(pu8Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-            IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-            IEM_MC_REF_EFLAGS(pEFlags); \
-            IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+            IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+            IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     2); \
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         } IEM_MC_NATIVE_ENDIF(); \
         IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4299 +4511 @@
             } IEM_MC_NATIVE_ELSE() { \
                 IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                IEM_MC_ARG(uint8_t const *, pu8Dst,                 0); \
+                IEM_MC_ARG(uint8_t const *, pu8Dst,                 1); \
                 IEM_MC_MEM_MAP_U8_RO(pu8Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     1); \
-                IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u8), pu8Dst, u8Src, pEFlags); \
+                IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                IEM_MC_ARG_CONST(uint8_t,   u8Src, /*=*/ u8Imm,     2); \
+                IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u8), fEFlagsIn, pu8Dst, u8Src); \
                 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                IEM_MC_COMMIT_EFLAGS(EFlags); \
+                IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
             } IEM_MC_NATIVE_ENDIF(); \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4460 +4672 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ u16Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ u16Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4486 +4698 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ u32Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ u32Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4513 +4725 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ u64Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ u64Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4545 +4757 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                1); \
                     IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  u16Imm,        1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  u16Imm,        2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4569 +4781 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                1); \
                     IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src,     u32Imm,     1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags,    EFlags,     2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src,     u32Imm,     2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4594 +4806 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                1); \
                     IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  u64Imm,        1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  u64Imm,        2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4625 +4837 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                1); \
                     IEM_MC_MEM_MAP_U16_ATOMIC(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  u16Imm,        1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  u16Imm,        2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4649 +4861 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                1); \
                     IEM_MC_MEM_MAP_U32_ATOMIC(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  u32Imm,        1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  u32Imm,        2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4673 +4885 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                1); \
                     IEM_MC_MEM_MAP_U64_ATOMIC(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  u64Imm,        1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,        2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  u64Imm,        2); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -4713 +4925 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t const *,pu16Dst,                0); \
+                    IEM_MC_ARG(uint16_t const *,pu16Dst,                1); \
                     IEM_MC_REF_GREG_U16_CONST(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ u16Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ u16Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4738 +4950 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t const *,pu32Dst,                0); \
+                    IEM_MC_ARG(uint32_t const *,pu32Dst,                1); \
                     IEM_MC_REF_GREG_U32_CONST (pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ u32Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ u32Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4763 +4975 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t const *,pu64Dst,                0); \
+                    IEM_MC_ARG(uint64_t const *,pu64Dst,                1); \
                     IEM_MC_REF_GREG_U64_CONST(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ u64Imm,   1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,              0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ u64Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4800 +5012 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint16_t const *, pu16Dst,               0); \
+                        IEM_MC_ARG(uint16_t const *, pu16Dst,               1); \
                         IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,       2); \
-                        IEM_MC_ARG_CONST(uint16_t,   u16Src,  u16Imm,       1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,             0); \
+                        IEM_MC_ARG_CONST(uint16_t,   u16Src,  u16Imm,       2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4828 +5040 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint32_t const *, pu32Dst,               0); \
+                        IEM_MC_ARG(uint32_t const *, pu32Dst,               1); \
                         IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,       2); \
-                        IEM_MC_ARG_CONST(uint32_t,   u32Src,  u32Imm,       1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,             0); \
+                        IEM_MC_ARG_CONST(uint32_t,   u32Src,  u32Imm,       2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -4856 +5068 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint64_t const *, pu64Dst,               0); \
+                        IEM_MC_ARG(uint64_t const *, pu64Dst,               1); \
                         IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,       2); \
-                        IEM_MC_ARG_CONST(uint64_t,   u64Src,  u64Imm,       1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,             0); \
+                        IEM_MC_ARG_CONST(uint64_t,   u64Src,  u64Imm,       2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5035 +5247 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                        0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                        1); \
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                                        2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ (uint16_t)(int16_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ (uint16_t)(int16_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5058 +5270 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                        0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                        1); \
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                                        2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ (uint32_t)(int32_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ (uint32_t)(int32_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5082 +5294 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                        0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                        1); \
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,      pEFlags,                                        2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ (uint64_t)(int64_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ (uint64_t)(int64_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5114 +5326 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                    0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                    1); \
                     IEM_MC_MEM_MAP_U16_RW(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  (uint16_t)(int16_t)(int8_t)u8Imm,  1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  (uint16_t)(int16_t)(int8_t)u8Imm,  2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5136 +5348 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                    0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                    1); \
                     IEM_MC_MEM_MAP_U32_RW(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  (uint32_t)(int32_t)(int8_t)u8Imm,  1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  (uint32_t)(int32_t)(int8_t)u8Imm,  2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5158 +5370 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                    0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                    1); \
                     IEM_MC_MEM_MAP_U64_RW(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  (uint64_t)(int64_t)(int8_t)u8Imm,  1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src,  (uint64_t)(int64_t)(int8_t)u8Imm,  2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5187 +5399 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                    0); \
+                    IEM_MC_ARG(uint16_t *,      pu16Dst,                                    1); \
                     IEM_MC_MEM_MAP_U16_ATOMIC(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  (uint16_t)(int16_t)(int8_t)u8Imm,  1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src,  (uint16_t)(int16_t)(int8_t)u8Imm,  2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16_locked), fEFlagsIn, pu16Dst, u16Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5209 +5421 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                    0); \
+                    IEM_MC_ARG(uint32_t *,      pu32Dst,                                    1); \
                     IEM_MC_MEM_MAP_U32_ATOMIC(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  (uint32_t)(int32_t)(int8_t)u8Imm,  1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src,  (uint32_t)(int32_t)(int8_t)u8Imm,  2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32_locked), fEFlagsIn, pu32Dst, u32Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5231 +5443 @@
                     \
                     IEM_MC_LOCAL(uint8_t,       bUnmapInfo); \
-                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                    0); \
+                    IEM_MC_ARG(uint64_t *,      pu64Dst,                                    1); \
                     IEM_MC_MEM_MAP_U64_ATOMIC(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
                     \
-                    IEM_MC_ARG_CONST(uint64_t,  u64Src, (uint64_t)(int64_t)(int8_t)u8Imm,   1); \
-                    IEM_MC_ARG_LOCAL_EFLAGS(    pEFlags, EFlags,                            2); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                  0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src, (uint64_t)(int64_t)(int8_t)u8Imm,   2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64_locked), fEFlagsIn, pu64Dst, u64Src); \
                     \
                     IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \
-                    IEM_MC_COMMIT_EFLAGS(EFlags); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
                     IEM_MC_END(); \
@@ -5266 +5478 @@
                     IEM_MC_LOCAL(uint16_t,      u16Dst); \
                     IEM_MC_FETCH_GREG_U16(u16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_LOCAL(uint32_t,      uEFlags); \
-                    IEM_MC_FETCH_EFLAGS(uEFlags); \
+                    IEM_MC_LOCAL_EFLAGS(        uEFlags); \
                     IEM_MC_NATIVE_EMIT_5(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_i_efl), u16Dst, (uint16_t)(int16_t)(int8_t)u8Imm, uEFlags, 16, 8); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint16_t const *,    pu16Dst,                                        0); \
+                    IEM_MC_ARG(uint16_t const *,pu16Dst,                                        1); \
                     IEM_MC_REF_GREG_U16_CONST(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,          pEFlags,                                        2); \
-                    IEM_MC_ARG_CONST(uint16_t,      u16Src, /*=*/ (uint16_t)(int16_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint16_t,  u16Src, /*=*/ (uint16_t)(int16_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5288 +5499 @@
                     IEM_MC_LOCAL(uint32_t,      u32Dst); \
                     IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_LOCAL(uint32_t,      uEFlags); \
-                    IEM_MC_FETCH_EFLAGS(uEFlags); \
+                    IEM_MC_LOCAL_EFLAGS(        uEFlags); \
                     IEM_MC_NATIVE_EMIT_5(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_i_efl), u32Dst, (uint32_t)(int32_t)(int8_t)u8Imm, uEFlags, 32, 8); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint32_t const *,    pu32Dst,                                        0); \
+                    IEM_MC_ARG(uint32_t const *,pu32Dst,                                        1); \
                     IEM_MC_REF_GREG_U32_CONST(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,          pEFlags,                                        2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint32_t,      u32Src, /*=*/ (uint32_t)(int32_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint32_t,  u32Src, /*=*/ (uint32_t)(int32_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5310 +5520 @@
                     IEM_MC_LOCAL(uint64_t,      u64Dst); \
                     IEM_MC_FETCH_GREG_U64(u64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_LOCAL(uint32_t,      uEFlags); \
-                    IEM_MC_FETCH_EFLAGS(uEFlags); \
+                    IEM_MC_LOCAL_EFLAGS(        uEFlags); \
                     IEM_MC_NATIVE_EMIT_5(RT_CONCAT3(iemNativeEmit_,a_InsNm,_r_i_efl), u64Dst, (uint64_t)(int64_t)(int8_t)u8Imm, uEFlags, 64, 8); \
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags); \
                 } IEM_MC_NATIVE_ELSE() { \
-                    IEM_MC_ARG(uint64_t const *,    pu64Dst,                                        0); \
+                    IEM_MC_ARG(uint64_t const *,pu64Dst,                                        1); \
                     IEM_MC_REF_GREG_U64_CONST(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \
-                    IEM_MC_ARG(uint32_t *,          pEFlags,                                        2); \
-                    IEM_MC_REF_EFLAGS(pEFlags); \
-                    IEM_MC_ARG_CONST(uint64_t,      u64Src, /*=*/ (uint64_t)(int64_t)(int8_t)u8Imm, 1); \
-                    IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                    IEM_MC_ARG_EFLAGS(          fEFlagsIn,                                      0); \
+                    IEM_MC_ARG_CONST(uint64_t,  u64Src, /*=*/ (uint64_t)(int64_t)(int8_t)u8Imm, 2); \
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                 } IEM_MC_NATIVE_ENDIF(); \
                 IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5352 +5561 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint16_t const *, pu16Dst,                                   0); \
+                        IEM_MC_ARG(uint16_t const *, pu16Dst,                                   1); \
                         IEM_MC_MEM_MAP_U16_RO(pu16Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,                           2); \
-                        IEM_MC_ARG_CONST(uint16_t,   u16Src, (uint16_t)(int16_t)(int8_t)u8Imm,  1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u16), pu16Dst, u16Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,                                 0); \
+                        IEM_MC_ARG_CONST(uint16_t,   u16Src, (uint16_t)(int16_t)(int8_t)u8Imm,  2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u16), fEFlagsIn, pu16Dst, u16Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5378 +5587 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint32_t const *, pu32Dst,                                   0); \
+                        IEM_MC_ARG(uint32_t const *, pu32Dst,                                   1); \
                         IEM_MC_MEM_MAP_U32_RO(pu32Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,                           2); \
-                        IEM_MC_ARG_CONST(uint32_t,   u32Src, (uint32_t)(int32_t)(int8_t)u8Imm,  1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u32), pu32Dst, u32Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,                                 0); \
+                        IEM_MC_ARG_CONST(uint32_t,   u32Src, (uint32_t)(int32_t)(int8_t)u8Imm,  2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u32), fEFlagsIn, pu32Dst, u32Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5404 +5613 @@
                     } IEM_MC_NATIVE_ELSE() { \
                         IEM_MC_LOCAL(uint8_t,        bUnmapInfo); \
-                        IEM_MC_ARG(uint64_t const *, pu64Dst,                                   0); \
+                        IEM_MC_ARG(uint64_t const *, pu64Dst,                                   1); \
                         IEM_MC_MEM_MAP_U64_RO(pu64Dst, bUnmapInfo, pVCpu->iem.s.iEffSeg, GCPtrEffDst); \
-                        IEM_MC_ARG_LOCAL_EFLAGS(     pEFlags, EFlags,                           2); \
-                        IEM_MC_ARG_CONST(uint64_t,  u64Src, (uint64_t)(int64_t)(int8_t)u8Imm,   1); \
-                        IEM_MC_CALL_VOID_AIMPL_3(RT_CONCAT3(iemAImpl_,a_InsNm,_u64), pu64Dst, u64Src, pEFlags); \
+                        IEM_MC_ARG_EFLAGS(           fEFlagsIn,                                 0); \
+                        IEM_MC_ARG_CONST(uint64_t,  u64Src, (uint64_t)(int64_t)(int8_t)u8Imm,   2); \
+                        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, RT_CONCAT3(iemAImpl_,a_InsNm,_u64), fEFlagsIn, pu64Dst, u64Src); \
                         IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \
-                        IEM_MC_COMMIT_EFLAGS(EFlags); \
+                        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
                     } IEM_MC_NATIVE_ENDIF(); \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -5567 +5776 @@
         IEM_MC_BEGIN(0, 0);
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-        IEM_MC_ARG(uint8_t,         u8Src,   1);
+        IEM_MC_ARG(uint8_t,         u8Src,      2);
         IEM_MC_FETCH_GREG_U8(u8Src, IEM_GET_MODRM_REG(pVCpu, bRm));
         IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
@@ -5574 +5783 @@
             IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
         } IEM_MC_NATIVE_ELSE() {
-            IEM_MC_ARG(uint8_t *,   pu8Dst,  0);
+            IEM_MC_ARG(uint8_t *,   pu8Dst,     1);
             IEM_MC_REF_GREG_U8(pu8Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); /* == IEM_GET_MODRM_RM(pVCpu, bRm) */
-            IEM_MC_ARG(uint32_t *,  pEFlags, 2);
-            IEM_MC_REF_EFLAGS(pEFlags);
-            IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u8, pu8Dst, u8Src, pEFlags);
+            IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0);
+            IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_test_u8, fEFlagsIn, pu8Dst, u8Src);
+            IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
         } IEM_MC_NATIVE_ENDIF();
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -5611 +5820 @@
                 IEM_MC_BEGIN(0, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_ARG(uint16_t,   u16Src,  1);
+                IEM_MC_ARG(uint16_t,        u16Src,     2);
                 IEM_MC_FETCH_GREG_U16(u16Src, IEM_GET_MODRM_REG(pVCpu, bRm));
                 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
@@ -5618 +5827 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
                 } IEM_MC_NATIVE_ELSE() {
-                    IEM_MC_ARG(uint16_t *, pu16Dst, 0);
+                    IEM_MC_ARG(uint16_t *,  pu16Dst,    1);
                     IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); /* == IEM_GET_MODRM_RM(pVCpu, bRm) */
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2);
-                    IEM_MC_REF_EFLAGS(pEFlags);
-                    IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags);
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0);
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_test_u16, fEFlagsIn, pu16Dst, u16Src);
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
                 } IEM_MC_NATIVE_ENDIF();
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -5631 +5840 @@
                 IEM_MC_BEGIN(IEM_MC_F_MIN_386, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_ARG(uint32_t,   u32Src,  1);
+                IEM_MC_ARG(uint32_t,        u32Src,     2);
                 IEM_MC_FETCH_GREG_U32(u32Src, IEM_GET_MODRM_REG(pVCpu, bRm));
                 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
@@ -5638 +5847 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
                 } IEM_MC_NATIVE_ELSE() {
-                    IEM_MC_ARG(uint32_t *, pu32Dst, 0);
+                    IEM_MC_ARG(uint32_t *,  pu32Dst,    1);
                     IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); /* == IEM_GET_MODRM_RM(pVCpu, bRm) */
-                    IEM_MC_ARG(uint32_t *, pEFlags, 2);
-                    IEM_MC_REF_EFLAGS(pEFlags);
-                    IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags);
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0);
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_test_u32, fEFlagsIn, pu32Dst, u32Src);
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
                 } IEM_MC_NATIVE_ENDIF();
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -5651 +5860 @@
                 IEM_MC_BEGIN(IEM_MC_F_64BIT, 0);
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
-                IEM_MC_ARG(uint64_t,        u64Src,  1);
+                IEM_MC_ARG(uint64_t,        u64Src,     2);
                 IEM_MC_FETCH_GREG_U64(u64Src, IEM_GET_MODRM_REG(pVCpu, bRm));
                 IEM_MC_NATIVE_IF(RT_ARCH_VAL_AMD64 | RT_ARCH_VAL_ARM64) {
@@ -5658 +5867 @@
                     IEM_MC_COMMIT_EFLAGS_OPT(uEFlags);
                 } IEM_MC_NATIVE_ELSE() {
-                    IEM_MC_ARG(uint64_t *,  pu64Dst, 0);
+                    IEM_MC_ARG(uint64_t *,  pu64Dst,    1);
                     IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_REG(pVCpu, bRm)); /* == IEM_GET_MODRM_RM(pVCpu, bRm) */
-                    IEM_MC_ARG(uint32_t *,  pEFlags, 2);
-                    IEM_MC_REF_EFLAGS(pEFlags);
-                    IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags);
+                    IEM_MC_ARG_EFLAGS(      fEFlagsIn,  0);
+                    IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_test_u64, fEFlagsIn, pu64Dst, u64Src);
+                    IEM_MC_COMMIT_EFLAGS(fEFlagsRet);
                 } IEM_MC_NATIVE_ENDIF();
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7395 +7604 @@
         IEM_MC_LOCAL(RTGCPTR,           uAddr2); \
         IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr2, X86_GREG_xDI); \
-        IEM_MC_ARG(uint##ValBits##_t,               uValue2,            1); \
+        IEM_MC_ARG(uint##ValBits##_t,               uValue2,            2); \
         IEM_MC_FETCH_MEM_U##ValBits(uValue2, X86_SREG_ES, uAddr2); \
         \
-        IEM_MC_ARG(uint32_t *,                      pEFlags,            2); \
-        IEM_MC_REF_EFLAGS(pEFlags); \
-        IEM_MC_ARG_LOCAL_REF(uint##ValBits##_t *,   puValue1, uValue1,  0); \
-        IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_cmp_u##ValBits, puValue1, uValue2, pEFlags); \
+        IEM_MC_ARG_LOCAL_REF(uint##ValBits##_t *,   puValue1, uValue1,  1); \
+        IEM_MC_ARG_EFLAGS(                          fEFlagsIn,          0); \
+        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_cmp_u##ValBits, fEFlagsIn, puValue1, uValue2); \
         \
+        IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
             IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
@@ -8098 +8307 @@
         IEM_MC_BEGIN(a_fMcFlags, 0); \
         IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \
-        IEM_MC_ARG(uint##ValBits##_t *, puRax,   0); \
-        IEM_MC_ARG(uint##ValBits##_t,   uValue,  1); \
-        IEM_MC_ARG(uint32_t *,          pEFlags, 2); \
+        \
         IEM_MC_LOCAL(RTGCPTR,           uAddr); \
+        IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
         \
-        IEM_MC_FETCH_GREG_U##AddrBits##_ZX_U64(uAddr, X86_GREG_xDI); \
+        IEM_MC_ARG(uint##ValBits##_t,   uValue,     2); \
         IEM_MC_FETCH_MEM_U##ValBits(uValue, X86_SREG_ES, uAddr); \
+        IEM_MC_ARG(uint##ValBits##_t *, puRax,      1); \
         IEM_MC_REF_GREG_U##ValBits(puRax, X86_GREG_xAX); \
-        IEM_MC_REF_EFLAGS(pEFlags); \
-        IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_cmp_u##ValBits, puRax, uValue, pEFlags); \
+        IEM_MC_ARG_EFLAGS(              fEFlagsIn,  0); \
+        IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, iemAImpl_cmp_u##ValBits, fEFlagsIn, puRax, uValue); \
         \
+        IEM_MC_COMMIT_EFLAGS(fEFlagsRet);\
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_DF) { \
             IEM_MC_SUB_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \
@@ -14358 +14568 @@
         IEM_MC_ARG(uint8_t,         u8Value,    1); \
         IEM_MC_ARG(uint32_t *,      pEFlags,    2); \
-        IEM_MC_LOCAL(int32_t,       rc); \
         \
         IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_RM(pVCpu, bRm)); \
         IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX); \
         IEM_MC_REF_EFLAGS(pEFlags); \
-        IEM_MC_CALL_AIMPL_3(rc, pfnU8, pu16AX, u8Value, pEFlags); \
+        IEM_MC_CALL_AIMPL_3(int32_t, rc, pfnU8, pu16AX, u8Value, pEFlags); \
         IEM_MC_IF_LOCAL_IS_Z(rc) { \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -14380 +14589 @@
         IEM_MC_ARG(uint32_t *,      pEFlags,    2); \
         IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-        IEM_MC_LOCAL(int32_t,       rc); \
         \
         IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
@@ -14387 +14595 @@
         IEM_MC_REF_GREG_U16(pu16AX, X86_GREG_xAX); \
         IEM_MC_REF_EFLAGS(pEFlags); \
-        IEM_MC_CALL_AIMPL_3(rc, pfnU8, pu16AX, u8Value, pEFlags); \
+        IEM_MC_CALL_AIMPL_3(int32_t, rc, pfnU8, pu16AX, u8Value, pEFlags); \
         IEM_MC_IF_LOCAL_IS_Z(rc) { \
             IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -14413 +14621 @@
                 IEM_MC_ARG(uint16_t,        u16Value,   2); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); \
@@ -14419 +14626 @@
                 IEM_MC_REF_GREG_U16(pu16DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -14436 +14643 @@
                 IEM_MC_ARG(uint32_t,        u32Value,   2); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); \
@@ -14442 +14648 @@
                 IEM_MC_REF_GREG_U32(pu32DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xAX); \
@@ -14461 +14667 @@
                 IEM_MC_ARG(uint64_t,        u64Value,   2); \
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); \
@@ -14467 +14672 @@
                 IEM_MC_REF_GREG_U64(pu64DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -14492 +14697 @@
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
@@ -14500 +14704 @@
                 IEM_MC_REF_GREG_U16(pu16DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU16, pu16AX, pu16DX, u16Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \
@@ -14517 +14721 @@
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
@@ -14525 +14728 @@
                 IEM_MC_REF_GREG_U32(pu32DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU32, pu32AX, pu32DX, u32Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xAX); \
@@ -14544 +14747 @@
                 IEM_MC_ARG(uint32_t *,      pEFlags,    3); \
                 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \
-                IEM_MC_LOCAL(int32_t,       rc); \
                 \
                 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \
@@ -14552 +14754 @@
                 IEM_MC_REF_GREG_U64(pu64DX, X86_GREG_xDX); \
                 IEM_MC_REF_EFLAGS(pEFlags); \
-                IEM_MC_CALL_AIMPL_4(rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags); \
+                IEM_MC_CALL_AIMPL_4(int32_t, rc, pImpl->pfnU64, pu64AX, pu64DX, u64Value, pEFlags); \
                 IEM_MC_IF_LOCAL_IS_Z(rc) { \
                     IEM_MC_ADVANCE_RIP_AND_FINISH(); \

trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py

@@ -2264 +2264 @@
 
     @staticmethod
+    def parseMcArgEFlags(oSelf, sName, asParams):
+        """ IEM_MC_ARG_EFLAGS """
+        oSelf.checkStmtParamCount(sName, asParams, 2);
+        # Note! We split this one up into IEM_MC_ARG and IEM_MC_FETCH_EFLAGS.
+        oStmtArg   = McStmtArg('IEM_MC_ARG', ['uint32_t', asParams[0], asParams[1]], 'uint32_t', asParams[0], int(asParams[1]));
+        oSelf.aoArgs.append(oStmtArg);
+        oStmtFetch = McStmt('IEM_MC_FETCH_EFLAGS', [asParams[0]]);
+        return (oStmtArg, oStmtFetch,);
+
+    @staticmethod
     def parseMcArgLocalEFlags(oSelf, sName, asParams):
         """ IEM_MC_ARG_LOCAL_EFLAGS """
@@ -2314 +2324 @@
         """ IEM_MC_CALL_AIMPL_3|4 """
         cArgs = int(sName[-1]);
-        oSelf.checkStmtParamCount(sName, asParams, 2 + cArgs);
-        return McStmtCall(sName, asParams, 1, 0);
+        oSelf.checkStmtParamCount(sName, asParams, 3 + cArgs);
+        oSelf.aoLocals.append(McStmtVar('IEM_MC_LOCAL', [asParams[0], asParams[1]], asParams[0], asParams[1]));
+        return McStmtCall(sName, asParams, 2, 1);
 
     @staticmethod
@@ -2974 +2985 @@
     'IEM_MC_ARG':                                                (McBlock.parseMcArg,               False, False, True,  ),
     'IEM_MC_ARG_CONST':                                          (McBlock.parseMcArgConst,          False, False, True,  ),
+    'IEM_MC_ARG_EFLAGS':                                         (McBlock.parseMcArgEFlags,         False, False, True,  ),
     'IEM_MC_ARG_LOCAL_EFLAGS':                                   (McBlock.parseMcArgLocalEFlags,    False, False, True,  ),
     'IEM_MC_ARG_LOCAL_REF':                                      (McBlock.parseMcArgLocalRef,       False, False, True,  ),

trunk/src/VBox/VMM/VMMAll/IEMAllInstTwoByte0f.cpp.h

@@ -10004 +10004 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_SF | X86_EFL_ZF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags);
+    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_imul_two_eflags);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_MIN_386, imul, 0);
+    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_MIN_386, imul, 0);
 }
 
@@ -10501 +10501 @@
 #ifndef TST_IEM_CHECK_MC
 # if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY)
-    static const IEMOPBINSIZES s_Native =
+    static const IEMOPBINTODOSIZES s_Native =
     {   NULL, NULL, iemAImpl_popcnt_u16, NULL, iemAImpl_popcnt_u32, NULL, iemAImpl_popcnt_u64, NULL };
 # endif
-    static const IEMOPBINSIZES s_Fallback =
+    static const IEMOPBINTODOSIZES s_Fallback =
     {   NULL, NULL, iemAImpl_popcnt_u16_fallback, NULL, iemAImpl_popcnt_u32_fallback, NULL, iemAImpl_popcnt_u64_fallback, NULL };
 #endif
-    const IEMOPBINSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback);
+    const IEMOPBINTODOSIZES * const pImpl = IEM_SELECT_HOST_OR_FALLBACK(fPopCnt, &s_Native, &s_Fallback);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, popcnt, 0);
+    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, popcnt, 0);
 }
 
@@ -11138 +11138 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
-    PCIEMOPBINSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsf_eflags);
+    PCIEMOPBINTODOSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsf_eflags);
     IEMOP_BODY_BIT_SCAN_OPERATOR_RV_RM(pImpl);
 }
@@ -11159 +11159 @@
 
 #ifndef TST_IEM_CHECK_MC
-    static const IEMOPBINSIZES s_iemAImpl_tzcnt =
+    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt =
     {   NULL, NULL,     iemAImpl_tzcnt_u16, NULL,       iemAImpl_tzcnt_u32, NULL,       iemAImpl_tzcnt_u64, NULL };
-    static const IEMOPBINSIZES s_iemAImpl_tzcnt_amd =
+    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt_amd =
     {   NULL, NULL,     iemAImpl_tzcnt_u16_amd, NULL,   iemAImpl_tzcnt_u32_amd, NULL,   iemAImpl_tzcnt_u64_amd, NULL };
-    static const IEMOPBINSIZES s_iemAImpl_tzcnt_intel =
+    static const IEMOPBINTODOSIZES s_iemAImpl_tzcnt_intel =
     {   NULL, NULL,     iemAImpl_tzcnt_u16_intel, NULL, iemAImpl_tzcnt_u32_intel, NULL, iemAImpl_tzcnt_u64_intel, NULL };
-    static const IEMOPBINSIZES * const s_iemAImpl_tzcnt_eflags[2][4] =
+    static const IEMOPBINTODOSIZES * const s_iemAImpl_tzcnt_eflags[2][4] =
     {
         { &s_iemAImpl_tzcnt_intel, &s_iemAImpl_tzcnt_intel, &s_iemAImpl_tzcnt_amd, &s_iemAImpl_tzcnt_intel },
@@ -11172 +11172 @@
 #endif
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_tzcnt_eflags,
+    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_tzcnt_eflags,
                                                                             IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, tzcnt, 0);
+    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, tzcnt, 0);
 }
 
@@ -11193 +11193 @@
     IEMOP_HLP_MIN_386();
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF | X86_EFL_CF);
-    PCIEMOPBINSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsr_eflags);
+    PCIEMOPBINTODOSIZES const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT(g_iemAImpl_bsr_eflags);
     IEMOP_BODY_BIT_SCAN_OPERATOR_RV_RM(pImpl);
 }
@@ -11214 +11214 @@
 
 #ifndef TST_IEM_CHECK_MC
-    static const IEMOPBINSIZES s_iemAImpl_lzcnt =
+    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt =
     {   NULL, NULL,     iemAImpl_lzcnt_u16, NULL,       iemAImpl_lzcnt_u32, NULL,       iemAImpl_lzcnt_u64, NULL };
-    static const IEMOPBINSIZES s_iemAImpl_lzcnt_amd =
+    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt_amd =
     {   NULL,  NULL,    iemAImpl_lzcnt_u16_amd, NULL,   iemAImpl_lzcnt_u32_amd, NULL,   iemAImpl_lzcnt_u64_amd, NULL };
-    static const IEMOPBINSIZES s_iemAImpl_lzcnt_intel =
+    static const IEMOPBINTODOSIZES s_iemAImpl_lzcnt_intel =
     {   NULL,  NULL,    iemAImpl_lzcnt_u16_intel, NULL, iemAImpl_lzcnt_u32_intel, NULL, iemAImpl_lzcnt_u64_intel, NULL };
-    static const IEMOPBINSIZES * const s_iemAImpl_lzcnt_eflags[2][4] =
+    static const IEMOPBINTODOSIZES * const s_iemAImpl_lzcnt_eflags[2][4] =
     {
         { &s_iemAImpl_lzcnt_intel, &s_iemAImpl_lzcnt_intel, &s_iemAImpl_lzcnt_amd, &s_iemAImpl_lzcnt_intel },
@@ -11227 +11227 @@
 #endif
     IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_OF | X86_EFL_SF | X86_EFL_AF | X86_EFL_PF);
-    const IEMOPBINSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_lzcnt_eflags,
+    const IEMOPBINTODOSIZES * const pImpl = IEMTARGETCPU_EFL_BEHAVIOR_SELECT_EX(s_iemAImpl_lzcnt_eflags,
                                                                             IEM_GET_HOST_CPU_FEATURES(pVCpu)->fBmi1);
     uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
-    IEMOP_BODY_BINARY_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, lzcnt, 0);
+    IEMOP_BODY_BINARY_TODO_rv_rm(bRm, pImpl->pfnNormalU16, pImpl->pfnNormalU32, pImpl->pfnNormalU64, IEM_MC_F_NOT_286_OR_OLDER, lzcnt, 0);
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllN8veLiveness.cpp

@@ -1038 +1038 @@
 #define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2)                                             NOP()
 #define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3)                                         NOP()
-#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2)                                            NOP()
-#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3)                                        NOP()
+#define IEM_MC_CALL_AIMPL_3(a_rcType, a_rc, a_pfn, a0, a1, a2)                                  NOP()
+#define IEM_MC_CALL_AIMPL_4(a_rcType, a_rc, a_pfn, a0, a1, a2, a3)                              NOP()
 
 #define IEM_MC_CALL_FPU_AIMPL_1(a_pfnAImpl, a0)                                                 NOP()

trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py

@@ -285 +285 @@
         asVarsInScope = [];
         for oStmt in aoStmts:
+            if isinstance(oStmt, iai.McStmtCall) and oStmt.sName.startswith('IEM_MC_CALL_AIMPL_'):
+                oStmt = iai.McStmtVar(oStmt.sName, oStmt.asParams[0:2], oStmt.asParams[0], oStmt.asParams[1]);
+
             if isinstance(oStmt, iai.McStmtVar):
                 if oStmt.sVarName in dVars:

trunk/src/VBox/VMM/VMMAll/IEMAllN8veRecompFuncs.h

@@ -2482 +2482 @@
     off = iemNativeEmitCallAImpl3(pReNative, off, UINT8_MAX /*idxVarRc*/, (uintptr_t)(a_pfn), a0, a1, a2)
 
-#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
+#define IEM_MC_CALL_AIMPL_3(a_rcType, a_rc, a_pfn, a0, a1, a2) \
+    IEM_MC_LOCAL(a_rcType, a_rc); \
     off = iemNativeEmitCallAImpl3(pReNative, off, a_rc,                   (uintptr_t)(a_pfn), a0, a1, a2)
 
@@ -2500 +2501 @@
     off = iemNativeEmitCallAImpl4(pReNative, off, UINT8_MAX /*idxVarRc*/, (uintptr_t)(a_pfn), a0, a1, a2, a3)
 
-#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
+#define IEM_MC_CALL_AIMPL_4(a_rcType, a_rc, a_pfn, a0, a1, a2, a3) \
+    IEM_MC_LOCAL(a_rcType, a_rc); \
     off = iemNativeEmitCallAImpl4(pReNative, off, a_rc,                   (uintptr_t)(a_pfn), a0, a1, a2, a3)
 

trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py

@@ -771 +771 @@
             offBits   = sMember.rfind('U') + 1;
             if sBaseType == 'PCIEMOPBINSIZES':          return 'PFNIEMAIMPLBINU'        + sMember[offBits:];
+            if sBaseType == 'PCIEMOPBINTODOSIZES':      return 'PFNIEMAIMPLBINTODOU'    + sMember[offBits:];
             if sBaseType == 'PCIEMOPUNARYSIZES':        return 'PFNIEMAIMPLUNARYU'      + sMember[offBits:];
             if sBaseType == 'PCIEMOPSHIFTSIZES':        return 'PFNIEMAIMPLSHIFTU'      + sMember[offBits:];
@@ -1939 +1940 @@
                     raise Exception('Variable %s is defined more than once!' % (oStmt.sVarName,));
                 self.dVariables[oStmt.sVarName] = oStmt.sVarName;
+            elif isinstance(oStmt, iai.McStmtCall) and oStmt.sName.startswith('IEM_MC_CALL_AIMPL_'):
+                if oStmt.asParams[1] in self.dVariables:
+                    raise Exception('Variable %s is defined more than once!' % (oStmt.asParams[1],));
+                self.dVariables[oStmt.asParams[1]] = iai.McStmtVar('IEM_MC_LOCAL', oStmt.asParams[0:2],
+                                                                   oStmt.asParams[0], oStmt.asParams[1]);
 
             # There shouldn't be any variables or arguments declared inside if/

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -2592 +2592 @@
 /** @name Arithmetic assignment operations on bytes (binary).
  * @{ */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU8,  (uint8_t  *pu8Dst,  uint8_t  u8Src,  uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU8, (uint32_t fEFlagsIn, uint8_t  *pu8Dst,  uint8_t  u8Src));
 typedef FNIEMAIMPLBINU8  *PFNIEMAIMPLBINU8;
 FNIEMAIMPLBINU8 iemAImpl_add_u8, iemAImpl_add_u8_locked;
@@ -2601 +2601 @@
 FNIEMAIMPLBINU8 iemAImpl_xor_u8, iemAImpl_xor_u8_locked;
 FNIEMAIMPLBINU8 iemAImpl_and_u8, iemAImpl_and_u8_locked;
+
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOU8, (uint8_t *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOU8 *PFNIEMAIMPLBINTODOU8;
 /** @} */
 
 /** @name Arithmetic assignment operations on words (binary).
  * @{ */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU16,  (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU16, (uint32_t fEFlagsIn, uint16_t *pu16Dst, uint16_t u16Src));
 typedef FNIEMAIMPLBINU16  *PFNIEMAIMPLBINU16;
 FNIEMAIMPLBINU16 iemAImpl_add_u16, iemAImpl_add_u16_locked;
@@ -2614 +2617 @@
 FNIEMAIMPLBINU16 iemAImpl_xor_u16, iemAImpl_xor_u16_locked;
 FNIEMAIMPLBINU16 iemAImpl_and_u16, iemAImpl_and_u16_locked;
+
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOU16, (uint16_t *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOU16 *PFNIEMAIMPLBINTODOU16;
 /** @}  */
 
+
 /** @name Arithmetic assignment operations on double words (binary).
  * @{ */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU32, (uint32_t fEFlagsIn, uint32_t *pu32Dst, uint32_t u32Src));
 typedef FNIEMAIMPLBINU32 *PFNIEMAIMPLBINU32;
 FNIEMAIMPLBINU32 iemAImpl_add_u32, iemAImpl_add_u32_locked;
@@ -2627 +2634 @@
 FNIEMAIMPLBINU32 iemAImpl_xor_u32, iemAImpl_xor_u32_locked;
 FNIEMAIMPLBINU32 iemAImpl_and_u32, iemAImpl_and_u32_locked;
-FNIEMAIMPLBINU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
-FNIEMAIMPLBINU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
-FNIEMAIMPLBINU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
+
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOU32, (uint32_t *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOU32 *PFNIEMAIMPLBINTODOU32;
+FNIEMAIMPLBINTODOU32 iemAImpl_blsi_u32, iemAImpl_blsi_u32_fallback;
+FNIEMAIMPLBINTODOU32 iemAImpl_blsr_u32, iemAImpl_blsr_u32_fallback;
+FNIEMAIMPLBINTODOU32 iemAImpl_blsmsk_u32, iemAImpl_blsmsk_u32_fallback;
 /** @}  */
 
 /** @name Arithmetic assignment operations on quad words (binary).
  * @{ */
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINU64, (uint32_t fEFlagsIn, uint64_t *pu64Dst, uint64_t u64Src));
 typedef FNIEMAIMPLBINU64 *PFNIEMAIMPLBINU64;
 FNIEMAIMPLBINU64 iemAImpl_add_u64, iemAImpl_add_u64_locked;
@@ -2643 +2653 @@
 FNIEMAIMPLBINU64 iemAImpl_xor_u64, iemAImpl_xor_u64_locked;
 FNIEMAIMPLBINU64 iemAImpl_and_u64, iemAImpl_and_u64_locked;
-FNIEMAIMPLBINU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
-FNIEMAIMPLBINU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
-FNIEMAIMPLBINU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
+
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOU64, (uint64_t *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOU64 *PFNIEMAIMPLBINTODOU64;
+FNIEMAIMPLBINTODOU64 iemAImpl_blsi_u64, iemAImpl_blsi_u64_fallback;
+FNIEMAIMPLBINTODOU64 iemAImpl_blsr_u64, iemAImpl_blsr_u64_fallback;
+FNIEMAIMPLBINTODOU64 iemAImpl_blsmsk_u64, iemAImpl_blsmsk_u64_fallback;
 /** @}  */
 
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU8,(uint8_t const *pu8Dst, uint8_t u8Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU8, (uint32_t fEFlagsIn, uint8_t const *pu8Dst, uint8_t u8Src));
 typedef FNIEMAIMPLBINROU8 *PFNIEMAIMPLBINROU8;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU16,(uint16_t const *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU16,(uint32_t fEFlagsIn, uint16_t const *pu16Dst, uint16_t u16Src));
 typedef FNIEMAIMPLBINROU16 *PFNIEMAIMPLBINROU16;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU32,(uint32_t const *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU32,(uint32_t fEFlagsIn, uint32_t const *pu32Dst, uint32_t u32Src));
 typedef FNIEMAIMPLBINROU32 *PFNIEMAIMPLBINROU32;
-typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINROU64,(uint64_t const *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
+typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLBINROU64,(uint32_t fEFlagsIn, uint64_t const *pu64Dst, uint64_t u64Src));
 typedef FNIEMAIMPLBINROU64 *PFNIEMAIMPLBINROU64;
 
@@ -2673 +2686 @@
 /** @}  */
 
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOROU16,(uint16_t const *pu16Dst, uint16_t u16Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOROU16 *PFNIEMAIMPLBINTODOROU16;
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOROU32,(uint32_t const *pu32Dst, uint32_t u32Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOROU32 *PFNIEMAIMPLBINTODOROU32;
+typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLBINTODOROU64,(uint64_t const *pu64Dst, uint64_t u64Src, uint32_t *pEFlags));
+typedef FNIEMAIMPLBINTODOROU64 *PFNIEMAIMPLBINTODOROU64;
+
 /** @name Bit operations operations (thrown in with the binary ops).
  * @{ */
-FNIEMAIMPLBINROU16 iemAImpl_bt_u16;
-FNIEMAIMPLBINROU32 iemAImpl_bt_u32;
-FNIEMAIMPLBINROU64 iemAImpl_bt_u64;
-FNIEMAIMPLBINU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
-FNIEMAIMPLBINU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
-FNIEMAIMPLBINU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
-FNIEMAIMPLBINU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
-FNIEMAIMPLBINU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
-FNIEMAIMPLBINU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
-FNIEMAIMPLBINU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
-FNIEMAIMPLBINU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
-FNIEMAIMPLBINU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
+FNIEMAIMPLBINTODOROU16 iemAImpl_bt_u16;
+FNIEMAIMPLBINTODOROU32 iemAImpl_bt_u32;
+FNIEMAIMPLBINTODOROU64 iemAImpl_bt_u64;
+FNIEMAIMPLBINTODOU16 iemAImpl_btc_u16, iemAImpl_btc_u16_locked;
+FNIEMAIMPLBINTODOU32 iemAImpl_btc_u32, iemAImpl_btc_u32_locked;
+FNIEMAIMPLBINTODOU64 iemAImpl_btc_u64, iemAImpl_btc_u64_locked;
+FNIEMAIMPLBINTODOU16 iemAImpl_btr_u16, iemAImpl_btr_u16_locked;
+FNIEMAIMPLBINTODOU32 iemAImpl_btr_u32, iemAImpl_btr_u32_locked;
+FNIEMAIMPLBINTODOU64 iemAImpl_btr_u64, iemAImpl_btr_u64_locked;
+FNIEMAIMPLBINTODOU16 iemAImpl_bts_u16, iemAImpl_bts_u16_locked;
+FNIEMAIMPLBINTODOU32 iemAImpl_bts_u32, iemAImpl_bts_u32_locked;
+FNIEMAIMPLBINTODOU64 iemAImpl_bts_u64, iemAImpl_bts_u64_locked;
 /** @}  */
 
@@ -2827 +2847 @@
 /** @name Bit search operations (thrown in with the binary ops).
  * @{ */
-FNIEMAIMPLBINU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
-FNIEMAIMPLBINU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
-FNIEMAIMPLBINU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
-FNIEMAIMPLBINU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
-FNIEMAIMPLBINU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
-FNIEMAIMPLBINU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
-FNIEMAIMPLBINU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
-FNIEMAIMPLBINU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
-FNIEMAIMPLBINU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
-FNIEMAIMPLBINU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
-FNIEMAIMPLBINU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
-FNIEMAIMPLBINU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
-FNIEMAIMPLBINU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
-FNIEMAIMPLBINU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
-FNIEMAIMPLBINU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
+FNIEMAIMPLBINTODOU16 iemAImpl_bsf_u16, iemAImpl_bsf_u16_amd, iemAImpl_bsf_u16_intel;
+FNIEMAIMPLBINTODOU32 iemAImpl_bsf_u32, iemAImpl_bsf_u32_amd, iemAImpl_bsf_u32_intel;
+FNIEMAIMPLBINTODOU64 iemAImpl_bsf_u64, iemAImpl_bsf_u64_amd, iemAImpl_bsf_u64_intel;
+FNIEMAIMPLBINTODOU16 iemAImpl_bsr_u16, iemAImpl_bsr_u16_amd, iemAImpl_bsr_u16_intel;
+FNIEMAIMPLBINTODOU32 iemAImpl_bsr_u32, iemAImpl_bsr_u32_amd, iemAImpl_bsr_u32_intel;
+FNIEMAIMPLBINTODOU64 iemAImpl_bsr_u64, iemAImpl_bsr_u64_amd, iemAImpl_bsr_u64_intel;
+FNIEMAIMPLBINTODOU16 iemAImpl_lzcnt_u16, iemAImpl_lzcnt_u16_amd, iemAImpl_lzcnt_u16_intel;
+FNIEMAIMPLBINTODOU32 iemAImpl_lzcnt_u32, iemAImpl_lzcnt_u32_amd, iemAImpl_lzcnt_u32_intel;
+FNIEMAIMPLBINTODOU64 iemAImpl_lzcnt_u64, iemAImpl_lzcnt_u64_amd, iemAImpl_lzcnt_u64_intel;
+FNIEMAIMPLBINTODOU16 iemAImpl_tzcnt_u16, iemAImpl_tzcnt_u16_amd, iemAImpl_tzcnt_u16_intel;
+FNIEMAIMPLBINTODOU32 iemAImpl_tzcnt_u32, iemAImpl_tzcnt_u32_amd, iemAImpl_tzcnt_u32_intel;
+FNIEMAIMPLBINTODOU64 iemAImpl_tzcnt_u64, iemAImpl_tzcnt_u64_amd, iemAImpl_tzcnt_u64_intel;
+FNIEMAIMPLBINTODOU16 iemAImpl_popcnt_u16, iemAImpl_popcnt_u16_fallback;
+FNIEMAIMPLBINTODOU32 iemAImpl_popcnt_u32, iemAImpl_popcnt_u32_fallback;
+FNIEMAIMPLBINTODOU64 iemAImpl_popcnt_u64, iemAImpl_popcnt_u64_fallback;
 /** @}  */
 
 /** @name Signed multiplication operations (thrown in with the binary ops).
  * @{ */
-FNIEMAIMPLBINU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
-FNIEMAIMPLBINU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
-FNIEMAIMPLBINU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
+FNIEMAIMPLBINTODOU16 iemAImpl_imul_two_u16, iemAImpl_imul_two_u16_amd, iemAImpl_imul_two_u16_intel;
+FNIEMAIMPLBINTODOU32 iemAImpl_imul_two_u32, iemAImpl_imul_two_u32_amd, iemAImpl_imul_two_u32_intel;
+FNIEMAIMPLBINTODOU64 iemAImpl_imul_two_u64, iemAImpl_imul_two_u64_amd, iemAImpl_imul_two_u64_intel;
 /** @}  */
 
@@ -2984 +3004 @@
 /** @name Misc.
  * @{ */
-FNIEMAIMPLBINU16 iemAImpl_arpl;
+FNIEMAIMPLBINTODOU16 iemAImpl_arpl;
 /** @} */
 
@@ -3006 +3026 @@
 /** @name ADOX and ADCX
  * @{ */
-FNIEMAIMPLBINU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
-FNIEMAIMPLBINU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
-FNIEMAIMPLBINU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
-FNIEMAIMPLBINU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
+FNIEMAIMPLBINTODOU32 iemAImpl_adcx_u32, iemAImpl_adcx_u32_fallback;
+FNIEMAIMPLBINTODOU64 iemAImpl_adcx_u64, iemAImpl_adcx_u64_fallback;
+FNIEMAIMPLBINTODOU32 iemAImpl_adox_u32, iemAImpl_adox_u32_fallback;
+FNIEMAIMPLBINTODOU64 iemAImpl_adox_u64, iemAImpl_adox_u64_fallback;
 /** @} */
 
@@ -3971 +3991 @@
 /** Pointer to a binary operator function table. */
 typedef IEMOPBINSIZES const *PCIEMOPBINSIZES;
+
+
+/**
+ * Function table for a binary operator providing implementation based on
+ * operand size.
+ */
+typedef struct IEMOPBINTODOSIZES
+{
+    PFNIEMAIMPLBINTODOU8  pfnNormalU8,    pfnLockedU8;
+    PFNIEMAIMPLBINTODOU16 pfnNormalU16,   pfnLockedU16;
+    PFNIEMAIMPLBINTODOU32 pfnNormalU32,   pfnLockedU32;
+    PFNIEMAIMPLBINTODOU64 pfnNormalU64,   pfnLockedU64;
+} IEMOPBINTODOSIZES;
+/** Pointer to a binary operator function table. */
+typedef IEMOPBINTODOSIZES const *PCIEMOPBINTODOSIZES;
 
 

trunk/src/VBox/VMM/include/IEMMc.h

@@ -197 +197 @@
 #define IEM_MC_ARG_CONST(a_Type, a_Name, a_Value, a_iArg)       a_Type const a_Name = (a_Value)
 #define IEM_MC_ARG_LOCAL_REF(a_Type, a_Name, a_Local, a_iArg)   a_Type const a_Name = &(a_Local)
+/** @note IEMAllInstPython.py duplicates the expansion. */
+#define IEM_MC_ARG_EFLAGS(a_Name, a_iArg)               uint32_t const a_Name = pVCpu->cpum.GstCtx.eflags.u
 /** @note IEMAllInstPython.py duplicates the expansion. */
 #define IEM_MC_ARG_LOCAL_EFLAGS(a_pName, a_Name, a_iArg) \
@@ -2622 +2624 @@
 #define IEM_MC_CALL_VOID_AIMPL_3(a_pfn, a0, a1, a2)       (a_pfn)((a0), (a1), (a2))
 #define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3)   (a_pfn)((a0), (a1), (a2), (a3))
-#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2)      (a_rc) = (a_pfn)((a0), (a1), (a2))
-#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3)  (a_rc) = (a_pfn)((a0), (a1), (a2), (a3))
+#define IEM_MC_CALL_AIMPL_3(a_rcType, a_rc, a_pfn, a0, a1, a2)      a_rcType const a_rc = (a_pfn)((a0), (a1), (a2))
+#define IEM_MC_CALL_AIMPL_4(a_rcType, a_rc, a_pfn, a0, a1, a2, a3)  a_rcType const a_rc = (a_pfn)((a0), (a1), (a2), (a3))
 
 

trunk/src/VBox/VMM/testcase/tstIEMAImpl.cpp

@@ -1761 +1761 @@
             a_TestType Test; \
             Test.fEflIn    = RandEFlags(); \
-            Test.fEflOut   = Test.fEflIn; \
             Test.uDstIn    = RandU ## a_cBits ## Dst(iTest); \
             Test.uDstOut   = Test.uDstIn; \
@@ -1768 +1767 @@
                 Test.uSrcIn &= a_cBits - 1; /* Restrict bit index according to operand width */ \
             Test.uMisc     = 0; \
-            pfn(&Test.uDstOut, Test.uSrcIn, &Test.fEflOut); \
+            Test.fEflOut   = pfn(Test.fEflIn, &Test.uDstOut, Test.uSrcIn); \
             GenerateBinaryWrite(&BinOut, &Test, sizeof(Test)); \
         } \
@@ -1776 +1775 @@
             Test.fEflIn    = g_aBinU ## a_cBits[iFn].paFixedTests[iTest].fEflIn == UINT32_MAX ? RandEFlags() \
                            : g_aBinU ## a_cBits[iFn].paFixedTests[iTest].fEflIn; \
-            Test.fEflOut   = Test.fEflIn; \
             Test.uDstIn    = g_aBinU ## a_cBits[iFn].paFixedTests[iTest].uDstIn; \
             Test.uDstOut   = Test.uDstIn; \
             Test.uSrcIn    = g_aBinU ## a_cBits[iFn].paFixedTests[iTest].uSrcIn; \
             Test.uMisc     = g_aBinU ## a_cBits[iFn].paFixedTests[iTest].uMisc; \
-            pfn(&Test.uDstOut, Test.uSrcIn, &Test.fEflOut); \
+            Test.fEflOut   = pfn(Test.fEflIn, &Test.uDstOut, Test.uSrcIn); \
             GenerateBinaryWrite(&BinOut, &Test, sizeof(Test)); \
         } \
@@ -1818 +1816 @@
     cIterations /= 4; \
     RTThreadYield(); \
-    uint64_t const nsStart     = RTTimeNanoTS(); \
+    uint64_t const nsStart = RTTimeNanoTS(); \
     for (uint32_t i = 0; i < cIterations; i++) \
     { \
-        uint32_t fBenchEfl = fEflIn; \
-        a_uType  uBenchDst = uDstIn;  \
-        pfn(&uBenchDst, uSrcIn, &fBenchEfl); \
+        a_uType uBenchDst = uDstIn;  \
+        pfn(fEflIn, &uBenchDst, uSrcIn); \
         \
-        fBenchEfl = fEflIn; \
         uBenchDst = uDstIn;  \
-        pfn(&uBenchDst, uSrcIn, &fBenchEfl); \
+        pfn(fEflIn, &uBenchDst, uSrcIn); \
         \
-        fBenchEfl = fEflIn; \
         uBenchDst = uDstIn;  \
-        pfn(&uBenchDst, uSrcIn, &fBenchEfl); \
+        pfn(fEflIn, &uBenchDst, uSrcIn); \
         \
-        fBenchEfl = fEflIn; \
         uBenchDst = uDstIn;  \
-        pfn(&uBenchDst, uSrcIn, &fBenchEfl); \
+        pfn(fEflIn, &uBenchDst, uSrcIn); \
     } \
     return RTTimeNanoTS() - nsStart; \
@@ -1855 +1849 @@
             for (uint32_t iTest = 0; iTest < cTests; iTest++ ) \
             { \
-                uint32_t fEfl = paTests[iTest].fEflIn; \
                 a_uType  uDst = paTests[iTest].uDstIn; \
-                pfn(&uDst, paTests[iTest].uSrcIn, &fEfl); \
+                uint32_t fEfl = pfn(paTests[iTest].fEflIn, &uDst, paTests[iTest].uSrcIn); \
                 if (   uDst != paTests[iTest].uDstOut \
-                    || fEfl != paTests[iTest].fEflOut ) \
+                    || fEfl != paTests[iTest].fEflOut) \
                     RTTestFailed(g_hTest, "#%u%s: efl=%#08x dst=" a_Fmt " src=" a_Fmt " -> efl=%#08x dst=" a_Fmt ", expected %#08x & " a_Fmt "%s - %s\n", \
                                  iTest, !iVar ? "" : "/n", paTests[iTest].fEflIn, paTests[iTest].uDstIn, paTests[iTest].uSrcIn, \
@@ -1868 +1861 @@
                 { \
                      *g_pu ## a_cBits  = paTests[iTest].uDstIn; \
-                     *g_pfEfl = paTests[iTest].fEflIn; \
-                     pfn(g_pu ## a_cBits, paTests[iTest].uSrcIn, g_pfEfl); \
+                     fEfl = pfn(paTests[iTest].fEflIn, g_pu ## a_cBits, paTests[iTest].uSrcIn); \
                      RTTEST_CHECK(g_hTest, *g_pu ## a_cBits  == paTests[iTest].uDstOut); \
-                     RTTEST_CHECK(g_hTest, *g_pfEfl == paTests[iTest].fEflOut); \
+                     RTTEST_CHECK(g_hTest, fEfl == paTests[iTest].fEflOut); \
                 } \
             } \
@@ -1946 +1938 @@
     ENTRY_BIN_PFN_CAST(cmp_u16,   PFNIEMAIMPLBINU16),
     ENTRY_BIN_PFN_CAST(test_u16,  PFNIEMAIMPLBINU16),
+#if 0 /** @todo convert to new eflags format  */
     ENTRY_BIN_PFN_CAST_EX(bt_u16, PFNIEMAIMPLBINU16, 1),
     ENTRY_BIN_EX(btc_u16, 1),
@@ -1960 +1953 @@
     ENTRY_BIN_INTEL(imul_two_u16, X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF),
     ENTRY_BIN(arpl),
+#endif
 };
 TEST_BINARY_OPS(16, uint16_t, "%#06x", BINU16_TEST_T, g_aBinU16)
@@ -1992 +1986 @@
     ENTRY_BIN_PFN_CAST(cmp_u32,   PFNIEMAIMPLBINU32),
     ENTRY_BIN_PFN_CAST(test_u32,  PFNIEMAIMPLBINU32),
+#if 0 /** @todo convert to new eflags format  */
     ENTRY_BIN_PFN_CAST_EX(bt_u32, PFNIEMAIMPLBINU32, 1),
     ENTRY_BIN_EX(btc_u32, 1),
@@ -2007 +2002 @@
     ENTRY_BIN(adcx_u32),
     ENTRY_BIN(adox_u32),
+#endif
 };
 TEST_BINARY_OPS(32, uint32_t, "%#010RX32", BINU32_TEST_T, g_aBinU32)
@@ -2039 +2035 @@
     ENTRY_BIN_PFN_CAST(cmp_u64,   PFNIEMAIMPLBINU64),
     ENTRY_BIN_PFN_CAST(test_u64,  PFNIEMAIMPLBINU64),
+#if 0 /** @todo convert to new eflags format  */
     ENTRY_BIN_PFN_CAST_EX(bt_u64, PFNIEMAIMPLBINU64, 1),
     ENTRY_BIN_EX(btc_u64, 1),
@@ -2054 +2051 @@
     ENTRY_BIN(adcx_u64),
     ENTRY_BIN(adox_u64),
+#endif
 };
 TEST_BINARY_OPS(64, uint64_t, "%#018RX64", BINU64_TEST_T, g_aBinU64)
@@ -2229 +2227 @@
                                  EFlagsDiff(fEfl, paTests[iTest].fEflOut)); \
                 /* positive */ \
-                uint32_t fEflExpect = paTests[iTest].fEflIn; \
                 uA                  = paTests[iTest].uDstIn; \
-                s_aFuncs[iFn].pfnSub(&uA, uA, &fEflExpect); \
+                uint32_t fEflExpect = s_aFuncs[iFn].pfnSub(paTests[iTest].fEflIn, &uA, uA); \
                 fEfl                = paTests[iTest].fEflIn; \
                 uA                  = paTests[iTest].uDstIn; \

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -662 +662 @@
     uint32_t *a_pName = &a_Name; \
     NOREF(a_pName)
+#define IEM_MC_ARG_EFLAGS(a_Name, a_iArg) IEM_MC_ARG(uint32_t, a_Name, a_iArg); IEM_MC_FETCH_EFLAGS(a_Name)
 
 #define IEM_MC_COMMIT_EFLAGS(a_EFlags)                  do { CHK_TYPE(uint32_t, a_EFlags); (void)fMcBegin; } while (0)
@@ -1002 +1003 @@
 #define IEM_MC_CALL_VOID_AIMPL_4(a_pfn, a0, a1, a2, a3) \
     do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3); (void)fMcBegin; } while (0)
-#define IEM_MC_CALL_AIMPL_3(a_rc, a_pfn, a0, a1, a2) \
+#define IEM_MC_CALL_AIMPL_3(a_rcType, a_rc, a_pfn, a0, a1, a2) \
+    IEM_MC_LOCAL(a_rcType, a_rc); \
     do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2);  (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
-#define IEM_MC_CALL_AIMPL_4(a_rc, a_pfn, a0, a1, a2, a3) \
+#define IEM_MC_CALL_AIMPL_4(a_rcType, a_rc, a_pfn, a0, a1, a2, a3) \
+    IEM_MC_LOCAL(a_rcType, a_rc); \
     do { CHK_CALL_ARG(a0, 0); CHK_CALL_ARG(a1, 1); CHK_CALL_ARG(a2, 2); CHK_CALL_ARG(a3, 3);  (a_rc) = VINF_SUCCESS; (void)fMcBegin; } while (0)
 #define IEM_MC_CALL_CIMPL_0(a_fFlags, a_fGstShwFlush, a_pfnCImpl)                       do { (void)fMcBegin; } while (0)