- Timestamp:
- Apr 10, 2024 7:01:46 AM (10 months ago)
- Location:
- trunk/src/VBox
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r104238 r104263 5065 5065 5066 5066 5067 ;; Template for the vtestp{s,d} instructions 5068 ; 5069 ; @param 1 The instruction 5070 ; 5071 ; @param A0 Pointer to the first source operand (aka readonly destination). 5072 ; @param A1 Pointer to the second source operand. 5073 ; @param A2 Pointer to the EFLAGS register. 5074 ; 5075 %macro IEMIMPL_VTESTP_SD 1 5076 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u128, 12 5077 PROLOGUE_3_ARGS 5078 IEMIMPL_AVX_PROLOGUE 5079 5080 vmovdqu xmm0, [A0] 5081 vmovdqu xmm1, [A1] 5082 %1 xmm0, xmm1 5083 IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF 5084 5085 IEMIMPL_AVX_EPILOGUE 5086 EPILOGUE_3_ARGS 5087 ENDPROC iemAImpl_ %+ %1 %+ _u128 5088 5089 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u256, 12 5090 PROLOGUE_3_ARGS 5091 IEMIMPL_AVX_PROLOGUE 5092 5093 vmovdqu ymm0, [A0] 5094 vmovdqu ymm1, [A1] 5095 %1 ymm0, ymm1 5096 IEM_SAVE_FLAGS_OLD A2, X86_EFL_ZF | X86_EFL_CF, 0, X86_EFL_OF | X86_EFL_AF | X86_EFL_PF | X86_EFL_SF 5097 5098 IEMIMPL_AVX_EPILOGUE 5099 EPILOGUE_3_ARGS 5100 ENDPROC iemAImpl_ %+ %1 %+ _u256 5101 %endmacro 5102 5103 IEMIMPL_VTESTP_SD vtestps 5104 IEMIMPL_VTESTP_SD vtestpd 5105 5106 5067 5107 ;; 5068 5108 ; Template for the [v]pmov{s,z}x* instructions -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r104240 r104263 15077 15077 15078 15078 15079 /* Worker for VEX.128 vtestp[s|d]. */ 15080 static void iemAImpl_vtestp_sd_u128_worker(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint64_t fSignMask, uint32_t *pfEFlags) 15081 { 15082 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; 15083 RTUINT128U uTemp; 15084 uTemp.au64[0] = puSrc1->au64[0] & puSrc2->au64[0]; 15085 uTemp.au64[1] = puSrc1->au64[1] & puSrc2->au64[1]; 15086 if ((( uTemp.au64[0] 15087 | uTemp.au64[1]) & fSignMask) == 0) 15088 fEfl |= X86_EFL_ZF; 15089 uTemp.au64[0] = ~puSrc1->au64[0] & puSrc2->au64[0]; 15090 uTemp.au64[1] = ~puSrc1->au64[1] & puSrc2->au64[1]; 15091 if ((( uTemp.au64[0] 15092 | uTemp.au64[1]) & fSignMask) == 0) 15093 fEfl |= X86_EFL_CF; 15094 *pfEFlags = fEfl; 15095 } 15096 15097 15098 /* Worker for VEX.256 vtestp[s|d]. */ 15099 static void iemAImpl_vtestp_sd_u256_worker(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint64_t fSignMask, uint32_t *pfEFlags) 15100 { 15101 uint32_t fEfl = *pfEFlags & ~X86_EFL_STATUS_BITS; 15102 RTUINT256U uTemp; 15103 uTemp.au64[0] = puSrc1->au64[0] & puSrc2->au64[0]; 15104 uTemp.au64[1] = puSrc1->au64[1] & puSrc2->au64[1]; 15105 uTemp.au64[2] = puSrc1->au64[2] & puSrc2->au64[2]; 15106 uTemp.au64[3] = puSrc1->au64[3] & puSrc2->au64[3]; 15107 if ((( uTemp.au64[0] 15108 | uTemp.au64[1] 15109 | uTemp.au64[2] 15110 | uTemp.au64[3]) & fSignMask) == 0) 15111 fEfl |= X86_EFL_ZF; 15112 uTemp.au64[0] = ~puSrc1->au64[0] & puSrc2->au64[0]; 15113 uTemp.au64[1] = ~puSrc1->au64[1] & puSrc2->au64[1]; 15114 uTemp.au64[2] = ~puSrc1->au64[2] & puSrc2->au64[2]; 15115 uTemp.au64[3] = ~puSrc1->au64[3] & puSrc2->au64[3]; 15116 if ((( uTemp.au64[0] 15117 | uTemp.au64[1] 15118 | uTemp.au64[2] 15119 | uTemp.au64[3]) & fSignMask) == 0) 15120 fEfl |= X86_EFL_CF; 15121 *pfEFlags = fEfl; 15122 } 15123 15124 15125 /* 15126 * VTESTPS 15127 */ 15128 IEM_DECL_IMPL_DEF(void, iemAImpl_vtestps_u128_fallback,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pfEFlags)) 15129 { 15130 uint64_t const fSignMask = RT_BIT_64(63) | RT_BIT_64(31); 15131 return iemAImpl_vtestp_sd_u128_worker(puSrc1, puSrc2, fSignMask, pfEFlags); 15132 } 15133 15134 15135 IEM_DECL_IMPL_DEF(void, iemAImpl_vtestps_u256_fallback,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pfEFlags)) 15136 { 15137 uint64_t const fSignMask = RT_BIT_64(63) | RT_BIT_64(31); 15138 return iemAImpl_vtestp_sd_u256_worker(puSrc1, puSrc2, fSignMask, pfEFlags); 15139 } 15140 15141 15142 /* 15143 * VTESTPD 15144 */ 15145 IEM_DECL_IMPL_DEF(void, iemAImpl_vtestpd_u128_fallback,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pfEFlags)) 15146 { 15147 uint64_t const fSignMask = RT_BIT_64(63); 15148 return iemAImpl_vtestp_sd_u128_worker(puSrc1, puSrc2, fSignMask, pfEFlags); 15149 } 15150 15151 15152 IEM_DECL_IMPL_DEF(void, iemAImpl_vtestpd_u256_fallback,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pfEFlags)) 15153 { 15154 uint64_t const fSignMask = RT_BIT_64(63); 15155 return iemAImpl_vtestp_sd_u256_worker(puSrc1, puSrc2, fSignMask, pfEFlags); 15156 } 15157 15158 15079 15159 /* 15080 15160 * PMOVSXBW / VPMOVSXBW -
trunk/src/VBox/VMM/VMMAll/IEMAllInstVexMap2.cpp.h
r104209 r104263 204 204 205 205 206 /** 207 * Common worker for AVX instructions on the forms: 208 * - vtestps/d xmm1, xmm2/mem128 209 * - vtestps/d ymm1, ymm2/mem256 210 * 211 * Takes function table for function w/o implicit state parameter. 212 * 213 * Exceptions type 4. AVX cpuid check for both 128-bit and 256-bit operation. 214 */ 215 FNIEMOP_DEF_1(iemOpCommonAvxAvx_Vx_Wx, PCIEMOPMEDIAF2EFL, pImpl) 216 { 217 Assert(pVCpu->iem.s.uVexLength <= 1); 218 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 219 if (IEM_IS_MODRM_REG_MODE(bRm)) 220 { 221 /* 222 * Register, register. 223 */ 224 if (pVCpu->iem.s.uVexLength) 225 { 226 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 227 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); 228 IEM_MC_LOCAL(RTUINT256U, uSrc1); 229 IEM_MC_LOCAL(RTUINT256U, uSrc2); 230 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0); 231 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1); 232 IEM_MC_ARG(uint32_t *, pEFlags, 2); 233 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 234 IEM_MC_PREPARE_AVX_USAGE(); 235 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 236 IEM_MC_FETCH_YREG_U256(uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 237 IEM_MC_REF_EFLAGS(pEFlags); 238 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puSrc1, puSrc2, pEFlags); 239 IEM_MC_ADVANCE_RIP_AND_FINISH(); 240 IEM_MC_END(); 241 } 242 else 243 { 244 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 245 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); 246 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0); 247 IEM_MC_ARG(PCRTUINT128U, puSrc2, 1); 248 IEM_MC_ARG(uint32_t *, pEFlags, 2); 249 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 250 IEM_MC_PREPARE_AVX_USAGE(); 251 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 252 IEM_MC_REF_XREG_U128_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 253 IEM_MC_REF_EFLAGS(pEFlags); 254 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puSrc1, puSrc2, pEFlags); 255 IEM_MC_ADVANCE_RIP_AND_FINISH(); 256 IEM_MC_END(); 257 } 258 } 259 else 260 { 261 /* 262 * Register, memory. 263 */ 264 if (pVCpu->iem.s.uVexLength) 265 { 266 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 267 IEM_MC_LOCAL(RTUINT256U, uSrc1); 268 IEM_MC_LOCAL(RTUINT256U, uSrc2); 269 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 270 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc1, uSrc1, 0); 271 IEM_MC_ARG_LOCAL_REF(PCRTUINT256U, puSrc2, uSrc2, 1); 272 IEM_MC_ARG(uint32_t *, pEFlags, 2); 273 274 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 275 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); 276 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 277 IEM_MC_PREPARE_AVX_USAGE(); 278 279 IEM_MC_FETCH_MEM_U256_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 280 IEM_MC_FETCH_YREG_U256(uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 281 IEM_MC_REF_EFLAGS(pEFlags); 282 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puSrc1, puSrc2, pEFlags); 283 284 IEM_MC_ADVANCE_RIP_AND_FINISH(); 285 IEM_MC_END(); 286 } 287 else 288 { 289 IEM_MC_BEGIN(IEM_MC_F_NOT_286_OR_OLDER, 0); 290 IEM_MC_LOCAL(RTUINT128U, uSrc2); 291 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 292 IEM_MC_ARG(PCRTUINT128U, puSrc1, 0); 293 IEM_MC_ARG_LOCAL_REF(PCRTUINT128U, puSrc2, uSrc2, 1); 294 IEM_MC_ARG(uint32_t *, pEFlags, 2); 295 296 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 297 IEMOP_HLP_DONE_VEX_DECODING_EX(fAvx); 298 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 299 IEM_MC_PREPARE_AVX_USAGE(); 300 301 IEM_MC_FETCH_MEM_U128_NO_AC(uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 302 IEM_MC_REF_XREG_U128_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 303 IEM_MC_REF_EFLAGS(pEFlags); 304 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puSrc1, puSrc2, pEFlags); 305 306 IEM_MC_ADVANCE_RIP_AND_FINISH(); 307 IEM_MC_END(); 308 } 309 } 310 } 311 312 206 313 /* Opcode VEX.0F38 0x0e - invalid. */ 207 /** Opcode VEX.66.0F38 0x0e. */ 208 FNIEMOP_STUB(iemOp_vtestps_Vx_Wx); 314 315 316 /** Opcode VEX.66.0F38 0x0e. 317 * AVX,AVX */ 318 FNIEMOP_DEF(iemOp_vtestps_Vx_Wx) 319 { 320 /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all 321 * CPU modes. */ 322 IEMOP_MNEMONIC2(VEX_RM, VTESTPS, vtestps, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO); 323 IEMOPMEDIAF2EFL_INIT_VARS(vtestps); 324 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback)); 325 } 326 327 209 328 /* Opcode VEX.0F38 0x0f - invalid. */ 210 /** Opcode VEX.66.0F38 0x0f. */ 211 FNIEMOP_STUB(iemOp_vtestpd_Vx_Wx); 329 330 331 /** Opcode VEX.66.0F38 0x0f. 332 * AVX,AVX */ 333 FNIEMOP_DEF(iemOp_vtestpd_Vx_Wx) 334 { 335 /** @todo We need to check VEX.W somewhere... it is documented to \#UD on all 336 * CPU modes. */ 337 IEMOP_MNEMONIC2(VEX_RM, VTESTPD, vtestpd, Vx, Wx, DISOPTYPE_HARMLESS | DISOPTYPE_X86_AVX, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_W_ZERO); 338 IEMOPMEDIAF2EFL_INIT_VARS(vtestpd); 339 return FNIEMOP_CALL_1(iemOpCommonAvxAvx_Vx_Wx, IEM_SELECT_HOST_OR_FALLBACK(fAvx, &s_Host, &s_Fallback)); 340 } 212 341 213 342 -
trunk/src/VBox/VMM/include/IEMInternal.h
r104238 r104263 3849 3849 3850 3850 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL128,(PCRTUINT128U puSrc1, PCRTUINT128U puSrc2, uint32_t *pEFlags)); 3851 typedef FNIEMAIMPLF2EFL128 *PFNIEMAIMPLF2EFL128; 3851 3852 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLF2EFL256,(PCRTUINT256U puSrc1, PCRTUINT256U puSrc2, uint32_t *pEFlags)); 3853 typedef FNIEMAIMPLF2EFL256 *PFNIEMAIMPLF2EFL256; 3852 3854 FNIEMAIMPLF2EFL128 iemAImpl_ptest_u128; 3853 3855 FNIEMAIMPLF2EFL256 iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback; 3856 FNIEMAIMPLF2EFL128 iemAImpl_vtestps_u128, iemAImpl_vtestps_u128_fallback; 3857 FNIEMAIMPLF2EFL256 iemAImpl_vtestps_u256, iemAImpl_vtestps_u256_fallback; 3858 FNIEMAIMPLF2EFL128 iemAImpl_vtestpd_u128, iemAImpl_vtestpd_u128_fallback; 3859 FNIEMAIMPLF2EFL256 iemAImpl_vtestpd_u256, iemAImpl_vtestpd_u256_fallback; 3860 3861 /** 3862 * Function table for media instruction taking two full sized media source 3863 * registers, and updating EFLAGS but no additional state (AVX). 3864 */ 3865 typedef struct IEMOPMEDIAF2EFL 3866 { 3867 PFNIEMAIMPLF2EFL128 pfnU128; 3868 PFNIEMAIMPLF2EFL256 pfnU256; 3869 } IEMOPMEDIAF2EFL; 3870 /** Pointer to a media operation function table for 3 full sized ops (AVX). */ 3871 typedef IEMOPMEDIAF2EFL const *PCIEMOPMEDIAF2EFL; 3872 3873 /** @def IEMOPMEDIAF2EFL_INIT_VARS_EX 3874 * Declares a s_Host (x86 & amd64 only) and a s_Fallback variable with the 3875 * given functions as initializers. For use in AVX functions where a pair of 3876 * functions are only used once and the function table need not be public. */ 3877 #ifndef TST_IEM_CHECK_MC 3878 # if (defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)) && !defined(IEM_WITHOUT_ASSEMBLY) 3879 # define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnHostU128, a_pfnHostU256, a_pfnFallbackU128, a_pfnFallbackU256) \ 3880 static IEMOPMEDIAF2EFL const s_Host = { a_pfnHostU128, a_pfnHostU256 }; \ 3881 static IEMOPMEDIAF2EFL const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 } 3882 # else 3883 # define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) \ 3884 static IEMOPMEDIAF2EFL const s_Fallback = { a_pfnFallbackU128, a_pfnFallbackU256 } 3885 # endif 3886 #else 3887 # define IEMOPMEDIAF2EFL_INIT_VARS_EX(a_pfnU128, a_pfnU256, a_pfnFallbackU128, a_pfnFallbackU256) (void)0 3888 #endif 3889 /** @def IEMOPMEDIAF2EFL_INIT_VARS 3890 * Generate AVX function tables for the @a a_InstrNm instruction. 3891 * @sa IEMOPMEDIAF2EFL_INIT_VARS_EX */ 3892 #define IEMOPMEDIAF2EFL_INIT_VARS(a_InstrNm) \ 3893 IEMOPMEDIAF2EFL_INIT_VARS_EX(RT_CONCAT3(iemAImpl_,a_InstrNm,_u128), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256), \ 3894 RT_CONCAT3(iemAImpl_,a_InstrNm,_u128_fallback), RT_CONCAT3(iemAImpl_,a_InstrNm,_u256_fallback)) 3854 3895 3855 3896 typedef IEM_DECL_IMPL_TYPE(uint32_t, FNIEMAIMPLSSEF2I32U64,(uint32_t uMxCsrIn, int32_t *pi32Dst, const uint64_t *pu64Src)); /* pu64Src is a double precision floating point. */ -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r104190 r104263 1770 1770 EMIT_INSTR_PLUS_ICEBP vbroadcasti128, YMM1, FSxBX 1771 1771 EMIT_INSTR_PLUS_ICEBP_C64 vbroadcasti128, YMM9, FSxBX 1772 1773 ; 1774 ; VTESTPS 1775 ; 1776 EMIT_INSTR_PLUS_ICEBP_XMM vtestps 1777 EMIT_INSTR_PLUS_ICEBP_YMM vtestps 1778 EMIT_INSTR_PLUS_ICEBP_XMM_98 vtestps 1779 EMIT_INSTR_PLUS_ICEBP_C64 vtestps, YMM9, YMM8 1780 EMIT_INSTR_PLUS_ICEBP_C64 vtestps, YMM9, FSxBX 1781 1782 ; 1783 ; VTESTPD 1784 ; 1785 EMIT_INSTR_PLUS_ICEBP_XMM vtestpd 1786 EMIT_INSTR_PLUS_ICEBP_YMM vtestpd 1787 EMIT_INSTR_PLUS_ICEBP_XMM_98 vtestpd 1788 EMIT_INSTR_PLUS_ICEBP_C64 vtestpd, YMM9, YMM8 1789 EMIT_INSTR_PLUS_ICEBP_C64 vtestpd, YMM9, FSxBX 1772 1790 1773 1791 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r104190 r104263 12790 12790 { bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 12791 12791 { bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12792 }; 12793 static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 12794 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 12795 return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 12796 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); 12797 } 12798 12799 12800 /* 12801 * VTESTPS 12802 */ 12803 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestps(uint8_t bMode) 12804 { 12805 static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = 12806 { 12807 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 12808 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 12809 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, 12810 { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 12811 /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 12812 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, 12813 { /*src2*/ RTUINT256_INIT_C(0, 0x7fffffff, 0, 0x7fffffff), 12814 /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 12815 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, 12816 { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 12817 /*src1*/ RTUINT256_INIT_C(0x7fffffff7fffffff, 0x4000000070000000, 0, 0x7fffff070000000), 12818 /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } }, 12819 { /*src2*/ RTUINT256_INIT_C(0xfacade00ffffffff, 0xf00dcafef1234567, 0, 0), 12820 /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0, 0), 12821 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } }, 12822 { /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15), 12823 /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff), 12824 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, 12825 { /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00ffffffff, 0xf00dcafef1234567), 12826 /*src1*/ RTUINT256_INIT_C(0, 0, 0xfffffffff1234567, 0xfa7edeadfadec0de), 12827 /* => */ { 0, X86_EFL_CF, 0 } }, 12828 { /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe8f1edbed, 0xfeeb1ebe8f1edbed, 0, 0x80ee8eee800080ee), 12829 /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed), 12830 /* => */ { 0, X86_EFL_ZF, 0 } }, 12831 { /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0, 0x70bacc00707a11ed), 12832 /*src1*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0x70bacc00707a11ed, 0), 12833 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } }, 12834 { /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0x8f6f6ff080608fff, 0xefdb0f5fe793f600, 0x99fb1c399ff0cce), 12835 /*src1*/ RTUINT256_INIT_C(0, 0x8ff7123497dcaeb4, 0, 0xd0d0c01dea7eeedf), 12836 /* => */ { 0, 0, 0 } }, 12837 }; 12838 12839 static BS3CPUINSTR3_TEST4_T const s_aTests16[] = 12840 { 12841 { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12842 { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12843 { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12844 { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12845 }; 12846 static BS3CPUINSTR3_TEST4_T const s_aTests32[] = 12847 { 12848 { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12849 { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12850 { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12851 { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12852 }; 12853 static BS3CPUINSTR3_TEST4_T const s_aTests64[] = 12854 { 12855 { bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12856 { bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12857 { bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12858 { bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12859 { bs3CpuInstr3_vtestps_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 12860 { bs3CpuInstr3_vtestps_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12861 { bs3CpuInstr3_vtestps_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 12862 { bs3CpuInstr3_vtestps_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12863 }; 12864 static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 12865 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 12866 return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 12867 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); 12868 } 12869 12870 12871 /* 12872 * VTESTPD 12873 */ 12874 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestpd(uint8_t bMode) 12875 { 12876 static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = 12877 { 12878 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 12879 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 12880 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, 12881 { /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8fffffff00000000, 0x80000000ffffffff, 0xffffffffffffffff), 12882 /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x80000000ffffffff, 0x80000000f000f000, 0xffffffffffffffff), 12883 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, 12884 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 12885 /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000), 12886 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, 12887 { /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000), 12888 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 12889 /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } }, 12890 { /*src2*/ RTUINT256_INIT_C(0xfacade007fffffff, 0xf00dcafe71234567, 0x7ab1ebadbad7ab1e, 0), 12891 /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0x7fffffffffffffff, 0x7ab1ebadbad7ab1e), 12892 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } }, 12893 { /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15), 12894 /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff), 12895 /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, 12896 { /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00f00e0000, 0xf00dcafef1234567), 12897 /*src1*/ RTUINT256_INIT_C(0x7fffffffffffffff, 0, 0xe1234567f1234567, 0x8a7edead0adec0de), 12898 /* => */ { 0, X86_EFL_CF, 0 } }, 12899 { /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe7f1edbed, 0xfeeb1ebe8f1edbed, 0x7fffffffffffffff, 0x80ee8eee800080ee), 12900 /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed), 12901 /* => */ { 0, X86_EFL_ZF, 0 } }, 12902 { /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0x1fa7ca751abcdef0, 0x70bacc00f07a11ed), 12903 /*src1*/ RTUINT256_INIT_C(0x7000f000f000f000, 0x70bacc00707a11ed, 0x70bacc00f07a11ed, 0x7fffffff0fff0fff), 12904 /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } }, 12905 { /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0xdf6f6ff080608fff, 0xefdb0f5f6793f600, 0x99fb1c3300f0cced), 12906 /*src1*/ RTUINT256_INIT_C(0, 0x9ff7123477dcaeb4, 0, 0xb0d0c01d7a7eeedf), 12907 /* => */ { 0, 0, 0 } }, 12908 }; 12909 12910 static BS3CPUINSTR3_TEST4_T const s_aTests16[] = 12911 { 12912 { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12913 { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12914 { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12915 { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12916 }; 12917 static BS3CPUINSTR3_TEST4_T const s_aTests32[] = 12918 { 12919 { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12920 { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12921 { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12922 { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12923 }; 12924 static BS3CPUINSTR3_TEST4_T const s_aTests64[] = 12925 { 12926 { bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12927 { bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12928 { bs3CpuInstr3_vtestpd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 12929 { bs3CpuInstr3_vtestpd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12930 { bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, 12931 { bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12932 { bs3CpuInstr3_vtestpd_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, 12933 { bs3CpuInstr3_vtestpd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, 12792 12934 }; 12793 12935 static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 14059 14201 #endif 14060 14202 #if defined(ALL_TESTS) 14203 { "vtestps", bs3CpuInstr3_vtestps, 0 }, 14204 #endif 14205 #if defined(ALL_TESTS) 14206 { "vtestpd", bs3CpuInstr3_vtestpd, 0 }, 14207 #endif 14208 #if defined(ALL_TESTS) 14061 14209 { "[v]pavgb/[v]pavgw", bs3CpuInstr3_v_pavgb_pavgw, 0 }, 14062 14210 #endif
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