VirtualBox

Ignore:
Timestamp:
Apr 10, 2024 7:01:46 AM (10 months ago)
Author:
vboxsync
Message:

VMM: bugref:9898 Implemented vtestp[s|d] instructions and their testcases.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r104190 r104263  
    1279012790        {  bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
    1279112791        {  bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12792    };
     12793    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     12794    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     12795    return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     12796                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
     12797}
     12798
     12799
     12800/*
     12801 * VTESTPS
     12802 */
     12803BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestps(uint8_t bMode)
     12804{
     12805    static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
     12806    {
     12807        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12808            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12809            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
     12810        {   /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
     12811            /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
     12812            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
     12813        {   /*src2*/ RTUINT256_INIT_C(0, 0x7fffffff, 0, 0x7fffffff),
     12814            /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
     12815            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
     12816        {   /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff),
     12817            /*src1*/ RTUINT256_INIT_C(0x7fffffff7fffffff, 0x4000000070000000, 0, 0x7fffff070000000),
     12818            /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } },
     12819        {   /*src2*/ RTUINT256_INIT_C(0xfacade00ffffffff, 0xf00dcafef1234567, 0, 0),
     12820            /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0, 0),
     12821            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } },
     12822        {   /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15),
     12823            /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff),
     12824            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
     12825        {   /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00ffffffff, 0xf00dcafef1234567),
     12826            /*src1*/ RTUINT256_INIT_C(0, 0, 0xfffffffff1234567, 0xfa7edeadfadec0de),
     12827            /* => */ { 0, X86_EFL_CF, 0 } },
     12828        {   /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe8f1edbed, 0xfeeb1ebe8f1edbed, 0, 0x80ee8eee800080ee),
     12829            /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed),
     12830            /* => */ { 0, X86_EFL_ZF, 0 } },
     12831        {   /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0, 0x70bacc00707a11ed),
     12832            /*src1*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0x70bacc00707a11ed, 0),
     12833            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } },
     12834        {   /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0x8f6f6ff080608fff, 0xefdb0f5fe793f600, 0x99fb1c399ff0cce),
     12835            /*src1*/ RTUINT256_INIT_C(0, 0x8ff7123497dcaeb4, 0, 0xd0d0c01dea7eeedf),
     12836            /* => */ { 0, 0, 0 } },
     12837    };
     12838
     12839    static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
     12840    {
     12841        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12842        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12843        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12844        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12845    };
     12846    static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
     12847    {
     12848        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12849        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12850        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12851        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12852    };
     12853    static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
     12854    {
     12855        {  bs3CpuInstr3_vtestps_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12856        {  bs3CpuInstr3_vtestps_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12857        {  bs3CpuInstr3_vtestps_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12858        {  bs3CpuInstr3_vtestps_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12859        {  bs3CpuInstr3_vtestps_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
     12860        {  bs3CpuInstr3_vtestps_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12861        {  bs3CpuInstr3_vtestps_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
     12862        {  bs3CpuInstr3_vtestps_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12863    };
     12864    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     12865    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     12866    return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     12867                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS);
     12868}
     12869
     12870
     12871/*
     12872 * VTESTPD
     12873 */
     12874BS3_DECL_FAR(uint8_t) bs3CpuInstr3_vtestpd(uint8_t bMode)
     12875{
     12876    static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] =
     12877    {
     12878        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12879            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12880            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
     12881        {   /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8fffffff00000000, 0x80000000ffffffff, 0xffffffffffffffff),
     12882            /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x80000000ffffffff, 0x80000000f000f000, 0xffffffffffffffff),
     12883            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
     12884        {   /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12885            /*src1*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000),
     12886            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } },
     12887        {   /*src2*/ RTUINT256_INIT_C(0x8000000000000000, 0x8000000000000000, 0x8000000000000000, 0x8000000000000000),
     12888            /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0),
     12889            /* => */ { 0, X86_EFL_ZF, X86_EFL_ZF } },
     12890        {   /*src2*/ RTUINT256_INIT_C(0xfacade007fffffff, 0xf00dcafe71234567, 0x7ab1ebadbad7ab1e, 0),
     12891            /*src1*/ RTUINT256_INIT_C(0xffffffff81234567, 0xfa7edeadfadec0de, 0x7fffffffffffffff, 0x7ab1ebadbad7ab1e),
     12892            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_CF } },
     12893        {   /*src2*/ RTUINT256_INIT_C(0, 0x70bacc00707a11ed, 0xf007ba11fa15efad, 0x8ffffffffe1afe15),
     12894            /*src1*/ RTUINT256_INIT_C(0x70bacc00707a11ed, 0, 0x8f00eefffeedc001, 0xfeeb1e00ffffffff),
     12895            /* => */ { 0, X86_EFL_CF, X86_EFL_CF } },
     12896        {   /*src2*/ RTUINT256_INIT_C(0xfa7edeadfadec0de, 0xfffffffff1234567, 0xfacade00f00e0000, 0xf00dcafef1234567),
     12897            /*src1*/ RTUINT256_INIT_C(0x7fffffffffffffff, 0, 0xe1234567f1234567, 0x8a7edead0adec0de),
     12898            /* => */ { 0, X86_EFL_CF, 0 } },
     12899        {   /*src2*/ RTUINT256_INIT_C(0xfeeb1ebe7f1edbed, 0xfeeb1ebe8f1edbed, 0x7fffffffffffffff, 0x80ee8eee800080ee),
     12900            /*src1*/ RTUINT256_INIT_C(0, 0x8feab0108f0f0f0f, 0x80dd000081234567, 0x70bacc00707a11ed),
     12901            /* => */ { 0, X86_EFL_ZF, 0 } },
     12902        {   /*src2*/ RTUINT256_INIT_C(0xf01dc01dba5eba11, 0xacce55ed9defec75, 0x1fa7ca751abcdef0, 0x70bacc00f07a11ed),
     12903            /*src1*/ RTUINT256_INIT_C(0x7000f000f000f000, 0x70bacc00707a11ed, 0x70bacc00f07a11ed, 0x7fffffff0fff0fff),
     12904            /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF } },
     12905        {   /*src2*/ RTUINT256_INIT_C(0xcafec01dea7e5ef, 0xdf6f6ff080608fff, 0xefdb0f5f6793f600, 0x99fb1c3300f0cced),
     12906            /*src1*/ RTUINT256_INIT_C(0, 0x9ff7123477dcaeb4, 0, 0xb0d0c01d7a7eeedf),
     12907            /* => */ { 0, 0, 0 } },
     12908    };
     12909
     12910    static BS3CPUINSTR3_TEST4_T const s_aTests16[] =
     12911    {
     12912        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c16,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12913        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12914        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c16,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12915        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12916    };
     12917    static BS3CPUINSTR3_TEST4_T const s_aTests32[] =
     12918    {
     12919        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c32,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12920        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12921        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c32,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12922        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12923    };
     12924    static BS3CPUINSTR3_TEST4_T const s_aTests64[] =
     12925    {
     12926        {  bs3CpuInstr3_vtestpd_XMM1_XMM2_icebp_c64,  255,         RM_REG, T_AVX_128,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12927        {  bs3CpuInstr3_vtestpd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12928        {  bs3CpuInstr3_vtestpd_XMM9_XMM8_icebp_c64,  255,         RM_REG, T_AVX_128,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
     12929        {  bs3CpuInstr3_vtestpd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12930        {  bs3CpuInstr3_vtestpd_YMM1_YMM2_icebp_c64,  255,         RM_REG, T_AVX_256,  1,   2, RT_ELEMENTS(s_aValues), s_aValues },
     12931        {  bs3CpuInstr3_vtestpd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  1, 255, RT_ELEMENTS(s_aValues), s_aValues },
     12932        {  bs3CpuInstr3_vtestpd_YMM9_YMM8_icebp_c64,  255,         RM_REG, T_AVX_256,  9,   8, RT_ELEMENTS(s_aValues), s_aValues },
     12933        {  bs3CpuInstr3_vtestpd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256,  9, 255, RT_ELEMENTS(s_aValues), s_aValues },
    1279212934    };
    1279312935    static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
    … …  
    1405914201#endif
    1406014202#if defined(ALL_TESTS)
     14203        { "vtestps",                                        bs3CpuInstr3_vtestps, 0 },
     14204#endif
     14205#if defined(ALL_TESTS)
     14206        { "vtestpd",                                        bs3CpuInstr3_vtestpd, 0 },
     14207#endif
     14208#if defined(ALL_TESTS)
    1406114209        { "[v]pavgb/[v]pavgw",                              bs3CpuInstr3_v_pavgb_pavgw, 0 },
    1406214210#endif
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