Changeset 104370 in vbox for trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
- Timestamp:
- Apr 19, 2024 7:24:25 AM (12 months ago)
- svn:sync-xref-src-repo-rev:
- 162859
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r104263 r104370 7094 7094 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 7095 7095 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 7096 } 7097 7098 7099 /* 7100 * [V]INSERTPS. 7101 */ 7102 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_insertps(uint8_t bMode) 7103 { 7104 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBth00[] = 7105 { 7106 { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 7107 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 7108 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 7109 { /*src2*/ RTUINT256_INIT_C(0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e, 0, 0), 7110 /*src1*/ RTUINT256_INIT_C(0xa110ca7ec01dce11, 0xdeadfacedecea5ed, 0, 0), 7111 /* => */ RTUINT256_INIT_C(0xbadf00d7a57e1e55, 0xba5eba11f007ba11, 0, 0) }, 7112 { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xb01dface0ddba115, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), 7113 /*src1*/ RTUINT256_INIT_C(0xf0f1f2f3f4f5f6f7, 0xa5a5a5a5000f0ed0, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), 7114 /* => */ RTUINT256_INIT_C(0xf0f1f2f3f4f5f6f7, 0xa5a5a5a5000f0ed0, 0xa110ca7ec01dce11, 0xdeadfacebad7ab1e) }, 7115 { /*src2*/ RTUINT256_INIT_C(1, 2, 0xf00dfa5ef100df0e, 0xf7f7f7f700000000), 7116 /*src1*/ RTUINT256_INIT_C(3, 4, 0xf0f1f2f300000000, 0x81818181ffffffff), 7117 /* => */ RTUINT256_INIT_C(3, 4, 0xf0f1f2f300000000, 0x8181818100000000) }, 7118 }; 7119 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesRegD5[] = 7120 { 7121 { /*src2*/ RTUINT256_INIT_C(1, 2, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), 7122 /*src1*/ RTUINT256_INIT_C(3, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), 7123 /* => */ RTUINT256_INIT_C(3, 4, 0xa110ca7e00000000, 0xacce55ed00000000) }, 7124 }; 7125 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesMemD5[] = 7126 { 7127 { /*src2*/ RTUINT256_INIT_C(1, 3, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), 7128 /*src1*/ RTUINT256_INIT_C(2, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), 7129 /* => */ RTUINT256_INIT_C(2, 4, 0xa110ca7e00000000, 0xbad7ab1e00000000) }, 7130 }; 7131 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBth28[] = 7132 { 7133 { /*src2*/ RTUINT256_INIT_C(1, 2, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), 7134 /*src1*/ RTUINT256_INIT_C(3, 4, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), 7135 /* => */ RTUINT256_INIT_C(3, 4, 0x00000000bad7ab1e, 0xdeadfacedecea5ed) }, 7136 }; 7137 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesBthFF[] = 7138 { 7139 { /*src2*/ RTUINT256_INIT_C(0, 0, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), 7140 /*src1*/ RTUINT256_INIT_C(0, 0, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), 7141 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 7142 { /*src2*/ RTUINT256_INIT_C(0xface1e55badb100d, 0xdeadfa11acc01ade, 0, 0), 7143 /*src1*/ RTUINT256_INIT_C(0xace0fdadca55e77e, 0xc105e1adf0015f0e, 0, 0), 7144 /* => */ RTUINT256_INIT_C(0xace0fdadca55e77e, 0xc105e1adf0015f0e, 0, 0) }, 7145 { /*src2*/ RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), 7146 /*src1*/ RTUINT256_INIT_C(3, 4, 0xffffffffffffffff, 0xffffffffffffffff), 7147 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 7148 }; 7149 7150 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 7151 { 7152 { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7153 { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7154 { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7155 { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7156 { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7157 { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7158 { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7159 { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7160 7161 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7162 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7163 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7164 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c16, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7165 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7166 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7167 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7168 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7169 }; 7170 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 7171 { 7172 { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7173 { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7174 { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7175 { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7176 { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7177 { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7178 { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7179 { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7180 7181 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7182 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7183 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7184 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c32, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7185 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7186 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7187 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7188 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7189 }; 7190 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 7191 { 7192 { bs3CpuInstr3_insertps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7193 { bs3CpuInstr3_insertps_XMM1_XMM2_0D5h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7194 { bs3CpuInstr3_insertps_XMM1_XMM2_028h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7195 { bs3CpuInstr3_insertps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, 2, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7196 { bs3CpuInstr3_insertps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7197 { bs3CpuInstr3_insertps_XMM1_FSxBX_0D5h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7198 { bs3CpuInstr3_insertps_XMM1_FSxBX_028h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7199 { bs3CpuInstr3_insertps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7200 7201 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_000h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7202 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0D5h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7203 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_028h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7204 { bs3CpuInstr3_vinsertps_XMM1_XMM2_XMM3_0FFh_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7205 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7206 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0D5h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7207 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_028h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7208 { bs3CpuInstr3_vinsertps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7209 7210 { bs3CpuInstr3_insertps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7211 { bs3CpuInstr3_insertps_XMM8_XMM9_0D5h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7212 { bs3CpuInstr3_insertps_XMM8_XMM9_028h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7213 { bs3CpuInstr3_insertps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7214 { bs3CpuInstr3_insertps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7215 { bs3CpuInstr3_insertps_XMM8_FSxBX_0D5h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7216 { bs3CpuInstr3_insertps_XMM8_FSxBX_028h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7217 { bs3CpuInstr3_insertps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7218 7219 { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_000h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7220 { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_0D5h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesRegD5), s_aValuesRegD5 }, 7221 { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_028h_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7222 { bs3CpuInstr3_vinsertps_XMM8_XMM9_XMM10_0FFh_icebp_c64, X86_XCPT_AC, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7223 { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBth00), s_aValuesBth00 }, 7224 { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_0D5h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesMemD5), s_aValuesMemD5 }, 7225 { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_028h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBth28), s_aValuesBth28 }, 7226 { bs3CpuInstr3_vinsertps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesBthFF), s_aValuesBthFF }, 7227 }; 7228 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 7229 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 7230 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 7231 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 7096 7232 } 7097 7233 … … 10158 10294 10159 10295 10296 /* 10297 * [V]EXTRACTPS. 10298 */ 10299 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_extractps(uint8_t bMode) 10300 { 10301 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00[] = 10302 { 10303 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xbad7ab1e) }, 10304 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xdecea5ed) }, 10305 { RTUINT256_INIT_C(0x00000000ffffffff, 0xffffffff00000000, 0x00000000ffffffff, 0x00000000a7a5a7a5), UINT64_C(0xa7a5a7a5) }, 10306 }; 10307 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues01[] = 10308 { 10309 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0x5e1ec7ed) }, 10310 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xdeadface) }, 10311 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xffffffff00000000, 0xf0f1f2f3a7a5a7a5), UINT64_C(0xf0f1f2f3) }, 10312 }; 10313 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues02[] = 10314 { 10315 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xda7aba5e) }, 10316 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xc01dce11) }, 10317 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x00000000ffffffff, 0x0000000000000000), UINT64_C(0xffffffff) }, 10318 }; 10319 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues03[] = 10320 { 10321 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xacce55edda7aba5e, 0x5e1ec7edbad7ab1e), UINT64_C(0xacce55ed) }, 10322 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xa110ca7ec01dce11, 0xdeadfacedecea5ed), UINT64_C(0xa110ca7e) }, 10323 { RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xffffffff00000000, 0x0000000000000000), UINT64_C(0xffffffff) }, 10324 }; 10325 10326 static BS3CPUINSTR3_TEST2_T const s_aTests16[] = 10327 { 10328 { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10329 { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10330 { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10331 { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10332 { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10333 { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10334 { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10335 { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10336 { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10337 { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10338 { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10339 { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c16, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10340 10341 { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10342 { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10343 { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10344 { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10345 { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10346 { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10347 { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10348 { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10349 { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10350 { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10351 { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10352 { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10353 }; 10354 static BS3CPUINSTR3_TEST2_T const s_aTests32[] = 10355 { 10356 { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10357 { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10358 { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10359 { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10360 { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10361 { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10362 { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10363 { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10364 { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10365 { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10366 { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10367 { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c32, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10368 10369 { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10370 { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10371 { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10372 { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10373 { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10374 { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10375 { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10376 { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10377 { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10378 { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10379 { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10380 { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10381 }; 10382 static BS3CPUINSTR3_TEST2_T const s_aTests64[] = 10383 { 10384 { bs3CpuInstr3_extractps_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10385 { bs3CpuInstr3_extractps_EDX_XMM1_001h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10386 { bs3CpuInstr3_extractps_EDX_XMM1_002h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10387 { bs3CpuInstr3_extractps_EDX_XMM1_003h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10388 { bs3CpuInstr3_extractps_EDX_XMM1_032h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10389 { bs3CpuInstr3_extractps_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10390 { bs3CpuInstr3_extractps_FSxBX_XMM1_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10391 { bs3CpuInstr3_extractps_FSxBX_XMM1_001h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10392 { bs3CpuInstr3_extractps_FSxBX_XMM1_002h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10393 { bs3CpuInstr3_extractps_FSxBX_XMM1_003h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10394 { bs3CpuInstr3_extractps_FSxBX_XMM1_032h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10395 { bs3CpuInstr3_extractps_FSxBX_XMM1_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10396 10397 { bs3CpuInstr3_vextractps_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10398 { bs3CpuInstr3_vextractps_EDX_XMM1_001h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10399 { bs3CpuInstr3_vextractps_EDX_XMM1_002h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10400 { bs3CpuInstr3_vextractps_EDX_XMM1_003h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10401 { bs3CpuInstr3_vextractps_EDX_XMM1_032h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10402 { bs3CpuInstr3_vextractps_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10403 { bs3CpuInstr3_vextractps_FSxBX_XMM1_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10404 { bs3CpuInstr3_vextractps_FSxBX_XMM1_001h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10405 { bs3CpuInstr3_vextractps_FSxBX_XMM1_002h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10406 { bs3CpuInstr3_vextractps_FSxBX_XMM1_003h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10407 { bs3CpuInstr3_vextractps_FSxBX_XMM1_032h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10408 { bs3CpuInstr3_vextractps_FSxBX_XMM1_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10409 10410 { bs3CpuInstr3_extractps_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10411 { bs3CpuInstr3_extractps_R9D_XMM8_001h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10412 { bs3CpuInstr3_extractps_R9D_XMM8_002h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10413 { bs3CpuInstr3_extractps_R9D_XMM8_003h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10414 { bs3CpuInstr3_extractps_R9D_XMM8_032h_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10415 { bs3CpuInstr3_extractps_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10416 { bs3CpuInstr3_extractps_FSxBX_XMM8_000h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10417 { bs3CpuInstr3_extractps_FSxBX_XMM8_001h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10418 { bs3CpuInstr3_extractps_FSxBX_XMM8_002h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10419 { bs3CpuInstr3_extractps_FSxBX_XMM8_003h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10420 { bs3CpuInstr3_extractps_FSxBX_XMM8_032h_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10421 { bs3CpuInstr3_extractps_FSxBX_XMM8_0FFh_icebp_c64, 255, RM_MEM32, T_SSE4_1, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10422 10423 { bs3CpuInstr3_vextractps_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10424 { bs3CpuInstr3_vextractps_R9D_XMM8_001h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10425 { bs3CpuInstr3_vextractps_R9D_XMM8_002h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10426 { bs3CpuInstr3_vextractps_R9D_XMM8_003h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10427 { bs3CpuInstr3_vextractps_R9D_XMM8_032h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10428 { bs3CpuInstr3_vextractps_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10429 { bs3CpuInstr3_vextractps_FSxBX_XMM8_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 10430 { bs3CpuInstr3_vextractps_FSxBX_XMM8_001h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues01), s_aValues01 }, 10431 { bs3CpuInstr3_vextractps_FSxBX_XMM8_002h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10432 { bs3CpuInstr3_vextractps_FSxBX_XMM8_003h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10433 { bs3CpuInstr3_vextractps_FSxBX_XMM8_032h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues02), s_aValues02 }, 10434 { bs3CpuInstr3_vextractps_FSxBX_XMM8_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 8, RT_ELEMENTS(s_aValues03), s_aValues03 }, 10435 }; 10436 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10437 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 10438 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10439 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 10440 } 10160 10441 10161 10442 … … 14282 14563 #endif 14283 14564 #if defined(ALL_TESTS) 14565 { "[v]insertps", bs3CpuInstr3_v_insertps, 0 }, 14566 { "[v]extractps", bs3CpuInstr3_v_extractps, 0 }, 14567 #endif 14568 #if defined(ALL_TESTS) 14284 14569 { "[v]psubsb/[v]psubsw", bs3CpuInstr3_v_psubsb_psubsw, 0 }, 14285 14570 { "[v]psubusb/[v]psubusw", bs3CpuInstr3_v_psubusb_psubusw, 0 },
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