Changeset 104378 in vbox for trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
- Timestamp:
- Apr 19, 2024 2:43:14 PM (12 months ago)
- svn:sync-xref-src-repo-rev:
- 162867
- File:
-
- 1 edited
-
trunk/src/VBox/VMM/include/IEMN8veRecompiler.h (modified) (10 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/include/IEMN8veRecompiler.h
r104367 r104378 55 55 /** @def IEMNATIVE_WITH_EFLAGS_SKIPPING 56 56 * Enables skipping EFLAGS calculations/updating based on liveness info. */ 57 #if (defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) && 1) || defined(DOXYGEN_RUNNING)57 #if defined(IEMNATIVE_WITH_LIVENESS_ANALYSIS) || defined(DOXYGEN_RUNNING) 58 58 # define IEMNATIVE_WITH_EFLAGS_SKIPPING 59 59 #endif … … 63 63 * Enables strict consistency checks around EFLAGS skipping. 64 64 * @note Only defined when IEMNATIVE_WITH_EFLAGS_SKIPPING is also defined. */ 65 #if (defined(VBOX_STRICT) && defined(IEMNATIVE_WITH_EFLAGS_SKIPPING)) || defined(DOXYGEN_RUNNING) 65 #ifdef IEMNATIVE_WITH_EFLAGS_SKIPPING 66 # ifdef VBOX_STRICT 67 # define IEMNATIVE_STRICT_EFLAGS_SKIPPING 68 # endif 69 #elif defined(DOXYGEN_RUNNING) 66 70 # define IEMNATIVE_STRICT_EFLAGS_SKIPPING 67 71 #endif … … 186 190 * Dedicated temporary SIMD register. */ 187 191 #endif 188 #if defined(RT_ARCH_AMD64) && !defined(DOXYGEN_RUNNING)192 #ifdef RT_ARCH_AMD64 189 193 # define IEMNATIVE_REG_FIXED_PVMCPU X86_GREG_xBX 194 # define IEMNATIVE_REG_FIXED_PVMCPU_ASM xBX 190 195 # define IEMNATIVE_REG_FIXED_TMP0 X86_GREG_x11 191 # define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \192 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \193 | RT_BIT_32(X86_GREG_xSP) \194 | RT_BIT_32(X86_GREG_xBP) )196 # define IEMNATIVE_REG_FIXED_MASK ( RT_BIT_32(IEMNATIVE_REG_FIXED_PVMCPU) \ 197 | RT_BIT_32(IEMNATIVE_REG_FIXED_TMP0) \ 198 | RT_BIT_32(X86_GREG_xSP) \ 199 | RT_BIT_32(X86_GREG_xBP) ) 195 200 196 201 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 197 # define IEMNATIVE_SIMD_REG_FIXED_TMP0 5 /* xmm5/ymm5 */ 198 # if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS) || !defined(_MSC_VER) 199 # define IEMNATIVE_SIMD_REG_FIXED_MASK (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0)) 202 # define IEMNATIVE_SIMD_REG_FIXED_TMP0 5 /* xmm5/ymm5 */ 203 # ifndef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS 204 # ifndef _MSC_VER /* On Windows xmm6 through xmm15 are marked as callee saved. */ 205 # define IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS 206 # endif 207 # endif 208 # ifdef IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS 209 # define IEMNATIVE_SIMD_REG_FIXED_MASK (RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0)) 200 210 # else 201 /** On Windows xmm6 through xmm15 are marked as callee saved. */ 202 # define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xffc0) \ 203 | RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0)) 211 # define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xffc0) \ 212 | RT_BIT_32(IEMNATIVE_SIMD_REG_FIXED_TMP0)) 204 213 # endif 205 214 # endif … … 229 238 230 239 # ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR 231 # define IEMNATIVE_SIMD_REG_FIXED_TMP0 ARMV8_A64_REG_Q30240 # define IEMNATIVE_SIMD_REG_FIXED_TMP0 ARMV8_A64_REG_Q30 232 241 # if defined(IEMNATIVE_WITH_SIMD_REG_ACCESS_ALL_REGISTERS) 233 # define IEMNATIVE_SIMD_REG_FIXED_MASK RT_BIT_32(ARMV8_A64_REG_Q30)242 # define IEMNATIVE_SIMD_REG_FIXED_MASK RT_BIT_32(ARMV8_A64_REG_Q30) 234 243 # else 235 244 /* … … 242 251 * having to save and restore them in the prologue/epilogue. 243 252 */ 244 # define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xff00) \245 | RT_BIT_32(ARMV8_A64_REG_Q31) \246 | RT_BIT_32(ARMV8_A64_REG_Q30) \247 | RT_BIT_32(ARMV8_A64_REG_Q29) \248 | RT_BIT_32(ARMV8_A64_REG_Q27) \249 | RT_BIT_32(ARMV8_A64_REG_Q25) \250 | RT_BIT_32(ARMV8_A64_REG_Q23) \251 | RT_BIT_32(ARMV8_A64_REG_Q21) \252 | RT_BIT_32(ARMV8_A64_REG_Q19) \253 | RT_BIT_32(ARMV8_A64_REG_Q17) \254 | RT_BIT_32(ARMV8_A64_REG_Q15) \255 | RT_BIT_32(ARMV8_A64_REG_Q13) \256 | RT_BIT_32(ARMV8_A64_REG_Q11) \257 | RT_BIT_32(ARMV8_A64_REG_Q9) \258 | RT_BIT_32(ARMV8_A64_REG_Q7) \259 | RT_BIT_32(ARMV8_A64_REG_Q5) \260 | RT_BIT_32(ARMV8_A64_REG_Q3) \261 | RT_BIT_32(ARMV8_A64_REG_Q1))253 # define IEMNATIVE_SIMD_REG_FIXED_MASK ( UINT32_C(0xff00) \ 254 | RT_BIT_32(ARMV8_A64_REG_Q31) \ 255 | RT_BIT_32(ARMV8_A64_REG_Q30) \ 256 | RT_BIT_32(ARMV8_A64_REG_Q29) \ 257 | RT_BIT_32(ARMV8_A64_REG_Q27) \ 258 | RT_BIT_32(ARMV8_A64_REG_Q25) \ 259 | RT_BIT_32(ARMV8_A64_REG_Q23) \ 260 | RT_BIT_32(ARMV8_A64_REG_Q21) \ 261 | RT_BIT_32(ARMV8_A64_REG_Q19) \ 262 | RT_BIT_32(ARMV8_A64_REG_Q17) \ 263 | RT_BIT_32(ARMV8_A64_REG_Q15) \ 264 | RT_BIT_32(ARMV8_A64_REG_Q13) \ 265 | RT_BIT_32(ARMV8_A64_REG_Q11) \ 266 | RT_BIT_32(ARMV8_A64_REG_Q9) \ 267 | RT_BIT_32(ARMV8_A64_REG_Q7) \ 268 | RT_BIT_32(ARMV8_A64_REG_Q5) \ 269 | RT_BIT_32(ARMV8_A64_REG_Q3) \ 270 | RT_BIT_32(ARMV8_A64_REG_Q1)) 262 271 # endif 263 272 # endif … … 309 318 # endif 310 319 311 # else 320 # else /* !RT_OS_WINDOWS */ 312 321 # define IEMNATIVE_CALL_ARG_GREG_COUNT 6 313 322 # define IEMNATIVE_CALL_ARG0_GREG X86_GREG_xDI … … 336 345 # define IEMNATIVE_CALL_VOLATILE_SIMD_REG_MASK (UINT32_C(0xffff)) 337 346 # endif 338 # endif 347 # endif /* !RT_OS_WINDOWS */ 339 348 340 349 #elif defined(RT_ARCH_ARM64) … … 384 393 385 394 /** This is the maximum argument count we'll ever be needing. */ 386 #if defined(RT_OS_WINDOWS) && defined(VBOXSTRICTRC_STRICT_ENABLED) 387 # define IEMNATIVE_CALL_MAX_ARG_COUNT 8 388 #else 389 # define IEMNATIVE_CALL_MAX_ARG_COUNT 7 395 #define IEMNATIVE_CALL_MAX_ARG_COUNT 7 396 #ifdef RT_OS_WINDOWS 397 # ifdef VBOXSTRICTRC_STRICT_ENABLED 398 # undef IEMNATIVE_CALL_MAX_ARG_COUNT 399 # define IEMNATIVE_CALL_MAX_ARG_COUNT 8 400 # endif 390 401 #endif 391 402 /** @} */ … … 427 438 428 439 429 #ifndef RT_IN_ASSEMBLER /* the rest of the file */440 #ifndef RT_IN_ASSEMBLER /* ASM-NOINC-START - the rest of the file */ 430 441 431 442 … … 2503 2514 #endif 2504 2515 2505 #endif /* !RT_IN_ASSEMBLER */2516 #endif /* !RT_IN_ASSEMBLER - ASM-NOINC-END */ 2506 2517 2507 2518 /** @} */
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