VirtualBox

Ignore:
Timestamp:
Jun 5, 2024 12:59:51 AM (8 months ago)
Author:
vboxsync
Message:

VMM/PGM: Refactored RAM ranges, MMIO2 ranges and ROM ranges and added MMIO ranges (to PGM) so we can safely access RAM ranges at runtime w/o fear of them ever being freed up. It is now only possible to create these during VM creation and loading, and they will live till VM destruction (except for MMIO2 which could be destroyed during loading (PCNet fun)). The lookup handling is by table instead of pointer tree. No more ring-0 pointers in shared data. bugref:10687 bugref:10093

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMR3/IOMR3Mmio.cpp

    r104767 r104840  
    275275    AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
    276276    *phRegion = UINT32_MAX;
    277     VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
     277    PVMCPU const pVCpu = VMMGetCpu(pVM);
     278    AssertReturn(pVCpu && pVCpu->idCpu == 0, VERR_VM_THREAD_NOT_EMT);
    278279    VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
    279280    AssertReturn(!pVM->iom.s.fMmioFrozen, VERR_WRONG_ORDER);
     
    324325        AssertReturn(idx == pVM->iom.s.cMmioRegs, VERR_IOM_MMIO_IPE_1);
    325326    }
     327
     328    /*
     329     * Create a matching ad-hoc RAM range for this MMIO region.
     330     */
     331    uint16_t idRamRange = 0;
     332    int rc = PGMR3PhysMmioRegister(pVM, pVCpu, cbRegion, pszDesc, &idRamRange);
     333    AssertRCReturn(rc,  rc);
    326334
    327335    /*
     
    341349    pVM->iom.s.paMmioRegs[idx].fMapped            = false;
    342350    pVM->iom.s.paMmioRegs[idx].fFlags             = fFlags;
     351    pVM->iom.s.paMmioRegs[idx].idRamRange         = idRamRange;
    343352    pVM->iom.s.paMmioRegs[idx].idxSelf            = idx;
    344353
     
    409418                        /* Register with PGM before we shuffle the array: */
    410419                        ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
    411                         rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
    412                                                    hRegion, pRegEntry->pszDesc);
     420                        rc = PGMR3PhysMmioMap(pVM, pVCpu, GCPhys, cbRegion, pRegEntry->idRamRange,
     421                                              pVM->iom.s.hNewMmioHandlerType, hRegion);
    413422                        AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
    414423
     
    428437                        /* Register with PGM before we shuffle the array: */
    429438                        ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
    430                         rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
    431                                                    hRegion, pRegEntry->pszDesc);
     439                        rc = PGMR3PhysMmioMap(pVM, pVCpu, GCPhys, cbRegion, pRegEntry->idRamRange,
     440                                              pVM->iom.s.hNewMmioHandlerType, hRegion);
    432441                        AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
    433442
     
    455464            /* First entry in the lookup table: */
    456465            ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
    457             rc = PGMR3PhysMmioRegister(pVM, pVCpu, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType, hRegion, pRegEntry->pszDesc);
     466            rc = PGMR3PhysMmioMap(pVM, pVCpu, GCPhys, cbRegion, pRegEntry->idRamRange,
     467                                  pVM->iom.s.hNewMmioHandlerType, hRegion);
    458468            AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
    459469
     
    572582                pVM->iom.s.cMmioLookupEntries = cEntries - 1;
    573583
    574                 rc = PGMR3PhysMmioDeregister(pVM, pVCpu, GCPhys, pRegEntry->cbRegion);
     584                rc = PGMR3PhysMmioUnmap(pVM, pVCpu, GCPhys, pRegEntry->cbRegion, pRegEntry->idRamRange);
    575585                AssertRC(rc);
    576586
     
    622632{
    623633    RT_NOREF(pVM, pDevIns, hRegion, cbRegion);
     634    AssertFailed();
    624635    return VERR_NOT_IMPLEMENTED;
    625636}
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