- Timestamp:
- Jun 5, 2024 1:02:34 AM (8 months ago)
- Location:
- trunk/src/VBox
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r103502 r104842 682 682 * needed for legacy guest drivers. */ 683 683 if (fPrefetch) 684 { 684 685 paddr = &uPciBiosSpecialVRAM; 686 687 /* Hack alert! Workaround for VRAM sizes higher than 256MB (absolute max is 1GB). */ 688 if ( u32Size > 0x10000000 /* 256MB (what we can stuff at 0xe0000000) */ 689 && uPciBiosSpecialVRAM == 0xe0000000) 690 uPciBiosSpecialVRAM = u32Size > 0x20000000 /*512MB*/ ? 0x80000000 : 0xc0000000; 691 } 685 692 } 686 693 } … … 694 701 || uNew + u32Size - 1 >= UINT32_C(0xfec00000)) 695 702 { 696 LogRel(("PCI: no space left for BAR%u of device %u/%u/%u (vendor=%#06x device=%#06x)\n", 697 i, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, vendor_id, device_id)); /** @todo make this a VM start failure later. */ 703 LogRel(("PCI: no space left for BAR%u (type=%#x size=%#RX32) of device %u/%u/%u (vendor=%#06x device=%#06x) - uNew=%#RX32 (*paddr=%#RX32)\n", 704 i, u8ResourceType, u32Size, pBus->iBus, pPciDev->uDevFn >> 3, pPciDev->uDevFn & 7, 705 vendor_id, device_id, uNew, *paddr)); /** @todo make this a VM start failure later. */ 698 706 /* Undo the mapping mess caused by the size probing. */ 699 707 devpciR3SetDWord(pDevIns, pPciDev, u32Address, UINT32_C(0)); -
trunk/src/VBox/Main/src-client/ConsoleImplConfigX86.cpp
r104702 r104842 433 433 ComPtr<IPlatform> platform; 434 434 pMachine->COMGETTER(Platform)(platform.asOutParam()); H(); 435 436 /* We have to increase the RAM hole if lots of VRAM is assigned. We stupidly 437 have to do this before the MCFG region is subtracted, even if there 438 should be ample space for it after the VRAM due to alignment. See 439 assumptions in ich9pciFakePCIBIOS(). */ 440 ComPtr<IGraphicsAdapter> ptrGraphicsAdapter; 441 hrc = pMachine->COMGETTER(GraphicsAdapter)(ptrGraphicsAdapter.asOutParam()); H(); 442 ULONG cVRamMBs = 0; 443 hrc = ptrGraphicsAdapter->COMGETTER(VRAMSize)(&cVRamMBs); H(); 444 if (cVRamMBs > 256) 445 { 446 uint32_t cVRamMBsPowerOfTwo = RT_MIN(cVRamMBs, 1024); /* 1GB is the absolute max given PCI alignment. */ 447 if (!RT_IS_POWER_OF_TWO(cVRamMBsPowerOfTwo)) 448 cVRamMBsPowerOfTwo = RT_BIT_32(ASMBitFirstSetU32(cVRamMBsPowerOfTwo)); /* returns [1..32] */ 449 if (cbRamHole / _1M < cVRamMBsPowerOfTwo * 2) 450 { 451 cbRamHole = cVRamMBsPowerOfTwo * 2 * _1M; /* We must double the VRAM size due to PCI alignment. */ 452 /** @todo sort out the MCFG placement to better use available physical memory. */ 453 //if (uMcfgBase) 454 // uMcfgBase = _4G - cbRamHole + cVRamMBsPowerOfTwo * _1M; 455 } 456 } 435 457 436 458 ChipsetType_T chipsetType;
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