Changeset 105484 in vbox for trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

Timestamp:

Jul 24, 2024 2:23:13 PM (6 months ago)

Author:

vboxsync

Message:

VMM/IEM: Better fix for the pmov* emitters when the guest source register == guest destination register, bugref:10652

File:

• trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veEmit-x86.h

@@ -2451 +2451 @@
                                                 uint8_t const idxSimdGstRegDst, uint8_t const idxSimdGstRegSrc) \
     { \
-        /* \
-         * The order of register allocation is important here when idxSimdGstRegSrc == idxSimdGstRegDst, \
-         * if _ForFullWrite is allocated first the register won't be initialized. \
-         */ \
-        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
-        uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
-        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
-        pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
-        if (idxSimdRegDst >= 8 || idxSimdRegSrc >= 8) \
-            pCodeBuf[off++] =   (idxSimdRegSrc >= 8 ? X86_OP_REX_B : 0) \
-                              | (idxSimdRegDst >= 8 ? X86_OP_REX_R : 0); \
-        pCodeBuf[off++] = 0x0f; \
-        pCodeBuf[off++] = 0x38; \
-        pCodeBuf[off++] = (a_bOpcX86); \
-        pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdRegDst & 7, idxSimdRegSrc & 7); \
-        iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
-        iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc); \
+        if (idxSimdGstRegDst == idxSimdGstRegSrc) \
+        { \
+            uint8_t const idxSimdReg = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
+            if (idxSimdReg >= 8) \
+                pCodeBuf[off++] = (idxSimdReg >= 8 ? X86_OP_REX_B | X86_OP_REX_R : 0); \
+            pCodeBuf[off++] = 0x0f; \
+            pCodeBuf[off++] = 0x38; \
+            pCodeBuf[off++] = (a_bOpcX86); \
+            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdReg & 7, idxSimdReg & 7); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdReg); \
+        } \
+        else \
+        { \
+            uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
+            uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 6); \
+            pCodeBuf[off++] = X86_OP_PRF_SIZE_OP; \
+            if (idxSimdRegDst >= 8 || idxSimdRegSrc >= 8) \
+                pCodeBuf[off++] =   (idxSimdRegSrc >= 8 ? X86_OP_REX_B : 0) \
+                                  | (idxSimdRegDst >= 8 ? X86_OP_REX_R : 0); \
+            pCodeBuf[off++] = 0x0f; \
+            pCodeBuf[off++] = 0x38; \
+            pCodeBuf[off++] = (a_bOpcX86); \
+            pCodeBuf[off++] = X86_MODRM_MAKE(X86_MOD_REG, idxSimdRegDst & 7, idxSimdRegSrc & 7); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc); \
+        } \
         IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); \
         return off; \
@@ -2510 +2523 @@
                                                 uint8_t const idxSimdGstRegDst, uint8_t const idxSimdGstRegSrc) \
     { \
-        /* \
-         * The order of register allocation is important here when idxSimdGstRegSrc == idxSimdGstRegDst, \
-         * if _ForFullWrite is allocated first the register won't be initialized. \
-         */ \
-        uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
-        uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
-                                                                              kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
-        PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); \
-        pCodeBuf[off++] = Armv8A64MkVecInstrUShll(idxSimdRegDst, idxSimdRegSrc, 0, (a_ArmElemSz), (a_fArmUnsigned)); \
-        iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
-        iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc); \
+        if (idxSimdGstRegDst == idxSimdGstRegSrc) \
+        { \
+            uint8_t const idxSimdReg = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                               kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForUpdate); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); \
+            pCodeBuf[off++] = Armv8A64MkVecInstrUShll(idxSimdReg, idxSimdReg, 0, (a_ArmElemSz), (a_fArmUnsigned)); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdReg); \
+        } \
+        else \
+        { \
+            uint8_t const idxSimdRegSrc = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegSrc), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ReadOnly); \
+            uint8_t const idxSimdRegDst = iemNativeSimdRegAllocTmpForGuestSimdReg(pReNative, &off, IEMNATIVEGSTSIMDREG_SIMD(idxSimdGstRegDst), \
+                                                                                  kIemNativeGstSimdRegLdStSz_Low128, kIemNativeGstRegUse_ForFullWrite); \
+            PIEMNATIVEINSTR const pCodeBuf = iemNativeInstrBufEnsure(pReNative, off, 1); \
+            pCodeBuf[off++] = Armv8A64MkVecInstrUShll(idxSimdRegDst, idxSimdRegSrc, 0, (a_ArmElemSz), (a_fArmUnsigned)); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegDst); \
+            iemNativeSimdRegFreeTmp(pReNative, idxSimdRegSrc); \
+        } \
         IEMNATIVE_ASSERT_INSTR_BUF_ENSURE(pReNative, off); \
         return off; \