Changeset 105614 in vbox for trunk/src/VBox/ValidationKit

Timestamp:

Aug 7, 2024 2:37:58 PM (6 months ago)

Author:

vboxsync

Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]addsd.

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32 (modified) (1 diff)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

@@ -2873 +2873 @@
               /*xcpt?    */ true, true },
     /** @todo Normals, Denormals, Overflow/Precision, Invalids etc. */
+    /*
+     * Overflow, Precision.
+     */
+    /*12*/{ { /*src2     */ { FP64_NORM_MAX(1), FP64_0(0), FP64_0(0), FP64_RAND_V1(1) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
+            { /* =>      */ { FP64_0(0),        FP64_0(1), FP64_0(1), FP64_RAND_V1(1) } },
+              /*mxcsr:in */ 0,
+              /*128:out  */ X86_MXCSR_OE,
+              /*256:out  */ X86_MXCSR_OE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_NORM_MAX(0), FP64_RAND_V3(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
+            { /*src1     */ { FP64_NORM_MAX(0), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_INF(0),      FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_RAND_V0(1),  FP64_RAND_V1(0), FP64_RAND_V1(0), FP64_RAND_V3(1) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
+            { /* =>      */ { FP64_NORM_MAX(1), FP64_RAND_V2(0), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
+              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_MAX(1), FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V0(1) } },
+            { /*src1     */ { FP64_NORM_MAX(1), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_INF(1),      FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_OM | X86_MXCSR_PM,
+              /*128:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_OM | X86_MXCSR_PM | X86_MXCSR_OE | X86_MXCSR_PE,
+              /*xcpt?    */ false, false },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(0),                            FP64_RAND_V1(1), FP64_RAND_V3(0), FP64_RAND_V0(1) } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(0),                            FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+            { /* =>      */ { FP64_V(0, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V0(1), FP64_RAND_V1(0), FP64_RAND_V2(1) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*xcpt?    */ true, true },
+          { { /*src2     */ { FP64_NORM_SAFE_INT_MIN(1),                            FP64_RAND_V1(1), FP64_RAND_V2(0), FP64_RAND_V3(1) } },
+            { /*src1     */ { FP64_NORM_SAFE_INT_MAX(1),                            FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
+            { /* =>      */ { FP64_V(1, FP64_FRAC_NORM_MAX, FP64_EXP_SAFE_INT_MAX), FP64_RAND_V2(1), FP64_RAND_V0(1), FP64_RAND_V1(0) } },
+              /*mxcsr:in */ X86_MXCSR_RC_ZERO,
+              /*128:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*256:out  */ X86_MXCSR_RC_ZERO | X86_MXCSR_PE,
+              /*xcpt?    */ true, true },
     };