VirtualBox

Ignore:
Timestamp:
Aug 9, 2024 6:38:07 AM (9 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
164321
Message:

ValidationKit/bootsectors: bugref:10658 SIMD FP testcase: [v]haddpd (W.I.P)

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4-template.mac

    r105611 r105632  
    231231
    232232;
     233;; [v]haddpd
     234;
     235EMIT_INSTR_PLUS_ICEBP       haddpd, XMM1, XMM2
     236EMIT_INSTR_PLUS_ICEBP       haddpd, XMM1, FSxBX
     237EMIT_INSTR_PLUS_ICEBP_C64   haddpd, XMM8, XMM9
     238EMIT_INSTR_PLUS_ICEBP_C64   haddpd, XMM8, FSxBX
     239
     240EMIT_INSTR_PLUS_ICEBP       vhaddpd, XMM1, XMM2, XMM3
     241EMIT_INSTR_PLUS_ICEBP       vhaddpd, XMM1, XMM2, FSxBX
     242EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, XMM8, XMM9, XMM10
     243EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, XMM8, XMM9, FSxBX
     244
     245EMIT_INSTR_PLUS_ICEBP       vhaddpd, YMM1, YMM2, YMM3
     246EMIT_INSTR_PLUS_ICEBP       vhaddpd, YMM1, YMM2, FSxBX
     247EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, YMM8, YMM9, YMM10
     248EMIT_INSTR_PLUS_ICEBP_C64   vhaddpd, YMM8, YMM9, FSxBX
     249
     250;
    233251;; [v]subps
    234252;

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-4.c32

    r105620 r105632  
    36083608              /*xcpt?    */ true, true },
    36093609    /** @todo Underflow, Precision; Rounding, FZ etc. */
     3610    };
     3611
     3612    static BS3CPUINSTR4_TEST1_T const s_aTests16[] =
     3613    {
     3614        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c16,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3615        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3616
     3617        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c16,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3618        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3619
     3620        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c16,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3621        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3622    };
     3623    static BS3CPUINSTR4_TEST1_T const s_aTests32[] =
     3624    {
     3625        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c32,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3626        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3627
     3628        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c32,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3629        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3630
     3631        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c32,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3632        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3633    };
     3634    static BS3CPUINSTR4_TEST1_T const s_aTests64[] =
     3635    {
     3636        { bs3CpuInstr4_haddps_XMM1_XMM2_icebp_c64,  255, RM_REG, T_SSE, 1, 1, 2,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3637        { bs3CpuInstr4_haddps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3638
     3639        { bs3CpuInstr4_vhaddps_XMM1_XMM2_XMM3_icebp_c64,  255, RM_REG, T_AVX_128, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3640        { bs3CpuInstr4_vhaddps_XMM1_XMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3641
     3642        { bs3CpuInstr4_vhaddps_YMM1_YMM2_YMM3_icebp_c64,  255, RM_REG, T_AVX_256, 1, 2, 3,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3643        { bs3CpuInstr4_vhaddps_YMM1_YMM2_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 1, 2, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3644
     3645        { bs3CpuInstr4_haddps_XMM8_XMM9_icebp_c64,  255, RM_REG, T_SSE, 8, 8, 9,   RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3646        { bs3CpuInstr4_haddps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3647
     3648        { bs3CpuInstr4_vhaddps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10,  RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3649        { bs3CpuInstr4_vhaddps_YMM8_YMM9_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_256, 8, 9, 255, RT_ELEMENTS(s_aValues), (BS3CPUINSTR4_TEST1_VALUES_T *)s_aValues },
     3650    };
     3651
     3652    static BS3CPUINSTR4_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR4_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     3653    unsigned const                         iTest       = BS3CPUINSTR4_TEST_MODES_INDEX(bMode);
     3654    return bs3CpuInstr4_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     3655                                        g_aXcptConfig2, RT_ELEMENTS(g_aXcptConfig2));
     3656}
     3657
     3658
     3659/*
     3660 * [V]HADDPD.
     3661 */
     3662BS3_DECL_FAR(uint8_t) bs3CpuInstr4_v_haddpd(uint8_t bMode)
     3663{
     3664    static BS3CPUINSTR4_TEST1_VALUES_PD_T const s_aValues[] =
     3665    {
     3666    /*
     3667     * Zero.
     3668     */
     3669    /* 0*/{ { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3670            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3671            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3672              /*mxcsr:in */ X86_MXCSR_XCPT_MASK,
     3673              /*128:out  */ X86_MXCSR_XCPT_MASK,
     3674              /*256:out  */ X86_MXCSR_XCPT_MASK,
     3675              /*xcpt?    */ false, false },
     3676          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3677            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3678            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3679              /*mxcsr:in */ 0,
     3680              /*128:out  */ 0,
     3681              /*256:out  */ 0,
     3682              /*xcpt?    */ false, false },
     3683          { { /*src2     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3684            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3685            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3686              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     3687              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     3688              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_UP,
     3689              /*xcpt?    */ false, false },
     3690          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3691            { /*src1     */ { FP64_0(1), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3692            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3693              /*mxcsr:in */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     3694              /*128:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     3695              /*256:out  */ X86_MXCSR_DAZ | X86_MXCSR_RC_ZERO,
     3696              /*xcpt?    */ false, false },
     3697          { { /*src2     */ { FP64_0(1), FP64_0(0), FP64_0(1), FP64_0(1) } },
     3698            { /*src1     */ { FP64_0(0), FP64_0(0), FP64_0(1), FP64_0(0) } },
     3699            { /* =>      */ { FP64_0(0), FP64_0(0), FP64_0(0), FP64_0(0) } },
     3700              /*mxcsr:in */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     3701              /*128:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     3702              /*256:out  */ X86_MXCSR_FZ | X86_MXCSR_RC_ZERO,
     3703              /*xcpt?    */ false, false },
     3704          { { /*src2     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
     3705            { /*src1     */ { FP64_0(0), FP64_0(1), FP64_0(0), FP64_0(1) } },
     3706            { /* =>      */ { FP64_0(1), FP64_0(1), FP64_0(1), FP64_0(1) } },
     3707              /*mxcsr:in */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     3708              /*128:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     3709              /*256:out  */ X86_MXCSR_XCPT_MASK | X86_MXCSR_DAZ | X86_MXCSR_FZ | X86_MXCSR_RC_DOWN,
     3710              /*xcpt?    */ false, false },
     3711    /** @todo Infinity, Normals, Denormals, Overflow/Precision, Invalids etc. */
    36103712    };
    36113713
    … …  
    59306032        { "[v]addsd",       bs3CpuInstr4_v_addsd,  0 },
    59316033        { "[v]haddps",      bs3CpuInstr4_v_haddps, 0 },
     6034        { "[v]haddpd",      bs3CpuInstr4_v_haddpd, 0 },
    59326035        { "[v]subps",       bs3CpuInstr4_v_subps,  0 },
    59336036        { "[v]subpd",       bs3CpuInstr4_v_subpd,  0 },
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