Changeset 105736 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Aug 19, 2024 5:41:36 PM (6 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

164441

Message:

Disassembler/ARMv8: Build fix and add support conditionals, bugref:10388

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmCore-armv8.cpp (modified) (4 diffs)
• DisasmFormatArmV8.cpp (modified) (2 diffs)
• DisasmTables-armv8-a64.cpp (modified) (1 diff)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -273 +273 @@
 static int disArmV8ParseCond(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
 {
+    RT_NOREF(pInsnClass, pParam, pf64Bit);
+    pDis->armv8.enmCond = (ARMV8INSTRCOND)disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    return VINF_SUCCESS;
+}
+
+
+static int disArmV8ParsePState(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
     RT_NOREF(pDis, u32Insn, pInsnClass, pParam, pInsnParm, pf64Bit);
     //AssertFailed();
@@ -280 +288 @@
 
 
-static int disArmV8ParsePState(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
-{
-    RT_NOREF(pDis, u32Insn, pInsnClass, pParam, pInsnParm, pf64Bit);
-    //AssertFailed();
-    /** @todo */
-    return VINF_SUCCESS;
-}
-
-
 static int disArmV8ParseSysReg(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
 {
@@ -296 +295 @@
     /* Assumes a op0:op1:CRn:CRm:op2 encoding in the instruction starting at the given bit position. */
     uint32_t u32ImmRaw = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
-    pParam->armv8.Reg.idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE_DYN(2 + ((u32ImmRaw >> 14) & 0x1),
-                                                                    (u32ImmRaw >> 11) & 0x7,
-                                                                    (u32ImmRaw >> 7) & 0xf,
-                                                                    (u32ImmRaw >> 3) & 0xf,
-                                                                    u32ImmRaw & 0x7);
+    pParam->armv8.Reg.idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(2 + ((u32ImmRaw >> 14) & 0x1),
+                                                                (u32ImmRaw >> 11) & 0x7,
+                                                                (u32ImmRaw >> 7) & 0xf,
+                                                                (u32ImmRaw >> 3) & 0xf,
+                                                                u32ImmRaw & 0x7);
     pParam->armv8.cb = 0;
     pParam->fUse    |= DISUSE_REG_SYSTEM;
@@ -341 +340 @@
     pDis->aParams[2].armv8.fParam = pOp->Opc.fParam3;
     pDis->aParams[3].armv8.fParam = pOp->Opc.fParam4;
-    pDis->armv8.pInsnClass    = pInsnClass;
+    pDis->armv8.pInsnClass        = pInsnClass;
+    pDis->armv8.enmCond           = kArmv8InstrCond_Al;
 
     pDis->pCurInstr = &pOp->Opc;

trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp

@@ -55 +55 @@
     "x16",   "x17",   "x18",   "x19",   "x20",   "x21",   "x22",   "x23",   "x24",   "x25",   "x26",  "x27",  "x28",  "x29",  "x30",  "xzr"
 };
+static const char g_aszArmV8Cond[16][4] =
+{
+    "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", "hi", "ls", "ge", "lt", "gt", "le", "al", "al"
+};
+
 
 /**
@@ -583 +588 @@
         PUT_PSZ(pOp->pszOpcode);
 
+        /* Add any conditionals. */
+        if (pDis->armv8.enmCond != kArmv8InstrCond_Al)
+        {
+            PUT_C('.');
+            Assert((uint16_t)pDis->armv8.enmCond < RT_ELEMENTS(g_aszArmV8Cond));
+            PUT_STR(g_aszArmV8Cond[pDis->armv8.enmCond], sizeof(g_aszArmV8Cond[0]) - 1);
+        }
+
         /*
          * Format the parameters.

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp

@@ -170 +170 @@
 /* B.cond/BC.cond */
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CondBr)
-    DIS_ARMV8_OP(0xff000010, 0x54000000, "b.",              OP_ARMV8_A64_B,         DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
-    DIS_ARMV8_OP(0xff000010, 0x54000010, "bc." ,            OP_ARMV8_A64_BC,        DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
+    DIS_ARMV8_OP(0xff000010, 0x54000000, "b",               OP_ARMV8_A64_B,         DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
+    DIS_ARMV8_OP(0xff000010, 0x54000010, "bc" ,             OP_ARMV8_A64_BC,        DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),
 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CondBr, 0 /*fClass*/,
                                           kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4)