Changeset 105779 in vbox for trunk/src/VBox/Disassembler
- Timestamp:
- Aug 21, 2024 4:39:51 PM (6 months ago)
- svn:sync-xref-src-repo-rev:
- 164491
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 5 edited
-
DisasmCore-armv8.cpp (modified) (8 diffs)
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DisasmFormatArmV8.cpp (modified) (7 diffs)
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DisasmInternal-armv8.h (modified) (3 diffs)
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DisasmTables-armv8-a64.cpp (modified) (25 diffs)
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testcase/tstDisasmArmv8-1-asm.S (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
r105738 r105779 33 33 #include <VBox/dis.h> 34 34 #include <VBox/log.h> 35 #include <iprt/asm.h> /* Required to get Armv8A64ConvertImmRImmS2Mask64() from armv8.h. */ 35 36 #include <iprt/armv8.h> 36 37 #include <iprt/assert.h> … … 83 84 static FNDISPARSEARMV8 disArmV8ParsePState; 84 85 static FNDISPARSEARMV8 disArmV8ParseSysReg; 86 static FNDISPARSEARMV8 disArmV8ParseSh12; 87 static FNDISPARSEARMV8 disArmV8ParseImmTbz; 88 static FNDISPARSEARMV8 disArmV8ParseShift; 89 static FNDISPARSEARMV8 disArmV8ParseShiftAmount; 85 90 /** @} */ 86 91 … … 110 115 disArmV8ParsePState, 111 116 NULL, 112 disArmV8ParseSysReg 117 disArmV8ParseSysReg, 118 disArmV8ParseSh12, 119 disArmV8ParseImmTbz, 120 disArmV8ParseShift, 121 disArmV8ParseShiftAmount 113 122 }; 114 123 … … 254 263 return VERR_DIS_INVALID_OPCODE; 255 264 256 /** @todo Decode according to spec. */ 257 pParam->uValue = u32ImmRaw; 258 pParam->armv8.cb = sizeof(uint32_t); 259 pParam->fUse |= DISUSE_IMMEDIATE32; 265 uint32_t uImm7SizeLen = ((u32ImmRaw & RT_BIT_32(12)) >> 6) | (u32ImmRaw & 0x3f); 266 uint32_t uImm6Rotations = (u32ImmRaw >> 6) & 0x3f; 267 pParam->uValue = *pf64Bit 268 ? Armv8A64ConvertImmRImmS2Mask64(uImm7SizeLen, uImm6Rotations) 269 : Armv8A64ConvertImmRImmS2Mask32(uImm7SizeLen, uImm6Rotations); 270 pParam->armv8.cb = pParam->uValue > UINT32_MAX ? sizeof(uint64_t) : sizeof(uint32_t); 271 pParam->fUse |= pParam->uValue > UINT32_MAX ? DISUSE_IMMEDIATE64 : DISUSE_IMMEDIATE32; 260 272 return VINF_SUCCESS; 261 273 } … … 264 276 static int disArmV8ParseHw(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 265 277 { 266 RT_NOREF(pDis, u32Insn, pInsnClass, pParam, pInsnParm, pf64Bit); 267 AssertFailed(); 268 /** @todo */ 278 RT_NOREF(pDis, pInsnClass, pParam); 279 Assert(pInsnParm->cBits == 2); 280 281 uint32_t u32 = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits); 282 /* hw<1> must be 0 if this is the 32-bit variant. */ 283 if ( !*pf64Bit 284 && (u32 & RT_BIT_32(1))) 285 return VERR_DIS_INVALID_OPCODE; 286 287 Assert(pParam->armv8.enmType == kDisArmv8OpParmImm); 288 Assert(pParam->fUse & (DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32)); 289 if (u32) 290 { 291 pParam->armv8.enmShift = kDisArmv8OpParmShiftLeft; 292 pParam->armv8.cShift = ((uint8_t)u32 & 0x3) << 4; 293 } 269 294 return VINF_SUCCESS; 270 295 } … … 306 331 307 332 333 static int disArmV8ParseSh12(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 334 { 335 RT_NOREF(pDis, pInsnClass, pf64Bit); 336 Assert(pInsnParm->cBits == 1); 337 if (u32Insn & RT_BIT_32(pInsnParm->idxBitStart)) 338 { 339 /* Shift the immediate pointed to. */ 340 pParam->uValue <<= 12; 341 342 /* Re-evaluate the immediate data size. */ 343 pParam->fUse &= ~(DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32); 344 if (pParam->uValue <= UINT8_MAX) 345 { 346 pParam->armv8.cb = sizeof(uint8_t); 347 pParam->fUse |= DISUSE_IMMEDIATE8; 348 } 349 else if (pParam->uValue <= UINT16_MAX) 350 { 351 pParam->armv8.cb = sizeof(uint16_t); 352 pParam->fUse |= DISUSE_IMMEDIATE16; 353 } 354 else if (pParam->uValue <= UINT32_MAX) 355 { 356 pParam->armv8.cb = sizeof(uint32_t); 357 pParam->fUse |= DISUSE_IMMEDIATE32; 358 } 359 else 360 AssertReleaseFailed(); 361 362 } 363 return VINF_SUCCESS; 364 } 365 366 367 static int disArmV8ParseImmTbz(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 368 { 369 RT_NOREF(pDis, pInsnClass, pf64Bit); 370 371 AssertReturn(!pInsnParm->idxBitStart && !pInsnParm->cBits, VERR_INTERNAL_ERROR_2); 372 373 pParam->uValue = disArmV8ExtractBitVecFromInsn(u32Insn, 19, 5); 374 pParam->uValue |= (u32Insn & RT_BIT_32(31)) >> 26; 375 376 pParam->armv8.cb = sizeof(uint8_t); 377 pParam->fUse |= DISUSE_IMMEDIATE8; 378 return VINF_SUCCESS; 379 } 380 381 382 static int disArmV8ParseShift(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 383 { 384 RT_NOREF(pDis, pInsnClass, pf64Bit); 385 386 AssertReturn(pInsnParm->cBits == 2, VERR_INTERNAL_ERROR_2); 387 388 uint32_t u32Shift = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits); 389 switch (u32Shift) 390 { 391 case 0: pParam->armv8.enmShift = kDisArmv8OpParmShiftLeft; break; 392 case 1: pParam->armv8.enmShift = kDisArmv8OpParmShiftRight; break; 393 case 2: pParam->armv8.enmShift = kDisArmv8OpParmShiftArithRight; break; 394 case 3: pParam->armv8.enmShift = kDisArmv8OpParmShiftRotate; break; 395 default: 396 AssertReleaseFailed(); 397 } 398 return VINF_SUCCESS; 399 } 400 401 402 static int disArmV8ParseShiftAmount(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit) 403 { 404 RT_NOREF(pDis, pInsnClass, pf64Bit); 405 406 uint32_t u32Amount = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits); 407 /* For a 32-bit operand it is impossible to shift/rotate more than 31 bits. */ 408 if ( !*pf64Bit 409 && u32Amount > 31) 410 return VERR_DIS_INVALID_OPCODE; 411 412 Assert(pParam->armv8.enmShift != kDisArmv8OpParmShiftNone); 413 Assert(u32Amount < 64); 414 pParam->armv8.cShift = (uint8_t)u32Amount; 415 /* Any shift operation with a 0 is essentially no shift being applied. */ 416 if (pParam->armv8.cShift == 0) 417 pParam->armv8.enmShift = kDisArmv8OpParmShiftNone; 418 return VINF_SUCCESS; 419 } 420 421 308 422 static uint32_t disArmV8DecodeIllegal(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass) 309 423 { … … 336 450 337 451 /* Should contain the parameter type on input. */ 338 pDis->aParams[0].armv8.fParam = pOp->Opc.fParam1; 339 pDis->aParams[1].armv8.fParam = pOp->Opc.fParam2; 340 pDis->aParams[2].armv8.fParam = pOp->Opc.fParam3; 341 pDis->aParams[3].armv8.fParam = pOp->Opc.fParam4; 342 pDis->armv8.pInsnClass = pInsnClass; 343 pDis->armv8.enmCond = kDisArmv8InstrCond_Al; 452 pDis->aParams[0].armv8.enmType = pInsnClass->aenmParamTypes[0]; 453 pDis->aParams[1].armv8.enmType = pInsnClass->aenmParamTypes[1]; 454 pDis->aParams[2].armv8.enmType = pInsnClass->aenmParamTypes[2]; 455 pDis->aParams[3].armv8.enmType = pInsnClass->aenmParamTypes[3]; 456 pDis->aParams[0].armv8.enmShift = kDisArmv8OpParmShiftNone; 457 pDis->aParams[1].armv8.enmShift = kDisArmv8OpParmShiftNone; 458 pDis->aParams[2].armv8.enmShift = kDisArmv8OpParmShiftNone; 459 pDis->aParams[3].armv8.enmShift = kDisArmv8OpParmShiftNone; 460 pDis->armv8.enmCond = kDisArmv8InstrCond_Al; 344 461 345 462 pDis->pCurInstr = &pOp->Opc; … … 372 489 pDis->pCurInstr = &g_ArmV8A64InvalidOpcode[0]; 373 490 374 pDis->aParams[0].armv8. fParam = g_ArmV8A64InvalidOpcode[0].fParam1;375 pDis->aParams[1].armv8. fParam = g_ArmV8A64InvalidOpcode[0].fParam2;376 pDis->aParams[2].armv8. fParam = g_ArmV8A64InvalidOpcode[0].fParam3;377 pDis->aParams[3].armv8. fParam = g_ArmV8A64InvalidOpcode[0].fParam4;491 pDis->aParams[0].armv8.enmType = kDisArmv8OpParmNone; 492 pDis->aParams[1].armv8.enmType = kDisArmv8OpParmNone; 493 pDis->aParams[2].armv8.enmType = kDisArmv8OpParmNone; 494 pDis->aParams[3].armv8.enmType = kDisArmv8OpParmNone; 378 495 } 379 496 pDis->rc = rc; -
trunk/src/VBox/Disassembler/DisasmFormatArmV8.cpp
r105747 r105779 48 48 { 49 49 "w0\0", "w1\0", "w2\0", "w3\0", "w4\0", "w5\0", "w6\0", "w7\0", "w8\0", "w9\0", "w10", "w11", "w12", "w13", "w14", "w15", 50 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", " zr"50 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wzr" 51 51 }; 52 52 static const char g_aszArmV8RegGen64[32][4] = … … 427 427 fFlags = (fFlags & ~DIS_FMT_FLAGS_BYTES_LEFT) | DIS_FMT_FLAGS_BYTES_RIGHT; 428 428 429 PCDISOPCODE const pOp = pDis->pCurInstr; 430 PCDISARMV8INSNCLASS const pInsnClass = pDis->armv8.pInsnClass; 429 PCDISOPCODE const pOp = pDis->pCurInstr; 431 430 432 431 /* … … 601 600 RTINTPTR off; 602 601 char szSymbol[128]; 603 for (uint32_t i = 0; i < RT_ELEMENTS(p InsnClass->aParms); i++)602 for (uint32_t i = 0; i < RT_ELEMENTS(pDis->aParams); i++) 604 603 { 605 PCDIS ARMV8INSNPARAM pInsnParam = &pInsnClass->aParms[i];606 607 /* First N OPparameter marks end of parameters. */608 if (p InsnParam->idxParse == kDisParmParseNop)604 PCDISOPPARAM pParam = &pDis->aParams[i]; 605 606 /* First None parameter marks end of parameters. */ 607 if (pParam->armv8.enmType == kDisArmv8OpParmNone) 609 608 break; 610 609 611 /* Step over decoding steps which don't produce any parameters. */ 612 if (pInsnParam->idxParse == kDisParmParseIs32Bit) 613 continue; 614 615 PCDISOPPARAM pParam = pInsnParam->idxParam != DIS_ARMV8_INSN_PARAM_UNSET 616 ? &pDis->aParams[pInsnParam->idxParam] 617 : NULL; 618 if ( pParam 619 && pInsnParam->idxParam > 0) 610 if (i > 0) 620 611 PUT_C(','); 621 612 PUT_C(' '); /** @todo Make the indenting configurable. */ 622 613 623 if (pInsnParam->fFlags & DIS_ARMV8_INSN_PARAM_F_ADDR_BEGIN) 624 PUT_C('['); 625 626 switch (pInsnParam->idxParse) 614 switch (pParam->armv8.enmType) 627 615 { 628 case kDis ParmParseImm:616 case kDisArmv8OpParmImm: 629 617 { 630 618 PUT_C('#'); … … 661 649 break; 662 650 } 663 case kDis ParmParseImmRel:664 case kDisParmParseImmAdr:651 case kDisArmv8OpParmImmRel: 652 /*case kDisParmParseImmAdr:*/ 665 653 { 666 654 int32_t offDisplacement; … … 706 694 break; 707 695 } 708 case kDis ParmParseReg:696 case kDisArmv8OpParmGpr: 709 697 { 710 698 Assert(!(pParam->fUse & (DISUSE_DISPLACEMENT8 | DISUSE_DISPLACEMENT16 | DISUSE_DISPLACEMENT32 | DISUSE_DISPLACEMENT64 | DISUSE_RIPDISPLACEMENT32))); … … 715 703 break; 716 704 } 717 case kDis ParmParseSysReg:705 case kDisArmv8OpParmSysReg: 718 706 { 719 707 Assert(pParam->fUse == DISUSE_REG_SYSTEM); … … 725 713 break; 726 714 } 727 case kDisParmParseImmsImmrN:728 case kDisParmParseHw:729 case kDisParmParseCond:730 case kDisParmParsePState:731 case kDisParmParseCRnCRm:732 break;733 case kDisParmParseIs32Bit:734 case kDisParmParseNop:735 case kDisParmParseMax:736 715 default: 737 716 AssertFailed(); 738 717 } 739 718 740 if (pInsnParam->fFlags & DIS_ARMV8_INSN_PARAM_F_ADDR_END) 741 PUT_C(']'); 719 if (pParam->armv8.enmShift != kDisArmv8OpParmShiftNone) 720 { 721 Assert( pParam->armv8.enmType == kDisArmv8OpParmImm 722 || pParam->armv8.enmType == kDisArmv8OpParmGpr); 723 PUT_SZ(", "); 724 switch (pParam->armv8.enmShift) 725 { 726 case kDisArmv8OpParmShiftLeft: 727 PUT_SZ("LSL #"); 728 break; 729 case kDisArmv8OpParmShiftRight: 730 PUT_SZ("LSR #"); 731 break; 732 case kDisArmv8OpParmShiftArithRight: 733 PUT_SZ("ASR #"); 734 break; 735 case kDisArmv8OpParmShiftRotate: 736 PUT_SZ("ROR #"); 737 break; 738 default: 739 AssertFailed(); 740 } 741 PUT_NUM_8(pParam->armv8.cShift); 742 } 742 743 } 743 744 } -
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r105731 r105779 62 62 kDisParmParseCRnCRm, 63 63 kDisParmParseSysReg, 64 kDisParmParseSh12, 65 kDisParmParseImmTbz, 66 kDisParmParseShift, 67 kDisParmParseShiftAmount, 64 68 kDisParmParseMax 65 69 } DISPARMPARSEIDX; … … 169 173 /** Number of bits to shift to get an index. */ 170 174 uint32_t cShift; 171 /** The parameters. */ 172 DISARMV8INSNPARAM aParms[4]; 175 /** Parameter types. */ 176 DISARMV8OPPARM aenmParamTypes[4]; 177 /** The decoding steps. */ 178 DISARMV8INSNPARAM aParms[5]; 173 179 } DISARMV8INSNCLASS; 174 180 /** Pointer to a constant instruction class descriptor. */ … … 185 191 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \ 186 192 static const DISARMV8OPCODE a_Name ## Opcodes[] = { 187 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \ 193 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 194 a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4) \ 188 195 }; \ 189 196 static const DISARMV8INSNCLASS a_Name = { { kDisArmV8DecodeType_InsnClass, RT_ELEMENTS(a_Name ## Opcodes) }, &a_Name ## Opcodes[0],\ 190 a_fClass, a_enmOpcDecode, a_fMask, a_cShift, { 197 a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 198 { a_enmParamType1, a_enmParamType2, a_enmParamType3, a_enmParamType4 }, { 199 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 200 a_enmParamType1, a_enmParamType2, a_enmParamType3) \ 201 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 202 a_enmParamType1, a_enmParamType2, a_enmParamType3, kDisArmv8OpParmNone) 203 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 204 a_enmParamType1, a_enmParamType2) \ 205 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 206 a_enmParamType1, a_enmParamType2, kDisArmv8OpParmNone) 207 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 208 a_enmParamType1) \ 209 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 210 a_enmParamType1, kDisArmv8OpParmNone) 211 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \ 212 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift, \ 213 kDisArmv8OpParmNone) 214 191 215 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END } } 192 216 -
trunk/src/VBox/Disassembler/DisasmTables-armv8-a64.cpp
r105737 r105779 40 40 41 41 #define DIS_ARMV8_OP(a_fMask, a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \ 42 { a_fMask, a_fValue, OP(a_szOpcode, 0, 0, 0, a_uOpcode, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, a_fOpType) }42 { a_fMask, a_fValue, OP(a_szOpcode, 0, 0, 0, a_uOpcode, 0, 0, 0, a_fOpType) } 43 43 44 44 #ifndef DIS_CORE_ONLY … … 53 53 DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] = 54 54 { 55 OP(g_szInvalidOpcode, 0, 0, 0, OP_ARMV8_INVALID, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, DISOPTYPE_INVALID)55 OP(g_szInvalidOpcode, 0, 0, 0, 0, 0, 0, 0, DISOPTYPE_INVALID) 56 56 }; 57 57 … … 60 60 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnRsvd) 61 61 DIS_ARMV8_OP(0xffff0000, 0x00000000, "udf" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID) 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_aArmV8A64InsnRsvd, 0 /*fClass*/, 63 kDisArmV8OpcDecodeNop, 0xffff0000, 16) 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_aArmV8A64InsnRsvd, 0 /*fClass*/, 63 kDisArmV8OpcDecodeNop, 0xffff0000, 16, 64 kDisArmv8OpParmImm) 64 65 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16, 0 /*idxParam*/), 66 DIS_ARMV8_INSN_PARAM_NONE, 65 67 DIS_ARMV8_INSN_PARAM_NONE, 66 68 DIS_ARMV8_INSN_PARAM_NONE, … … 73 75 DIS_ARMV8_OP(0x9f000000, 0x10000000, "adr" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS), 74 76 DIS_ARMV8_OP(0x9f000000, 0x90000000, "adrp" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS) 75 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT, 76 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31) 77 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT, 78 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 79 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel) 77 80 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 78 81 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmAdr, 0, 0, 1 /*idxParam*/), 82 DIS_ARMV8_INSN_PARAM_NONE, 79 83 DIS_ARMV8_INSN_PARAM_NONE, 80 84 DIS_ARMV8_INSN_PARAM_NONE … … 88 92 DIS_ARMV8_OP(0x7f800000, 0x51000000, "sub" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS), 89 93 DIS_ARMV8_OP(0x7f800000, 0x71000000, "subs" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS), 90 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF, 91 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 94 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF, 95 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 96 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 92 97 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 93 98 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 94 99 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 12, 2 /*idxParam*/), 100 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSh12, 22, 1, 2 /*idxParam*/), 95 101 DIS_ARMV8_INSN_PARAM_NONE 96 102 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; … … 103 109 DIS_ARMV8_OP(0x7f800000, 0x52000000, "eor" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 104 110 DIS_ARMV8_OP(0x7f800000, 0x72000000, "ands" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS), 105 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF, 106 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 107 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 108 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 6, 1 /*idxParam*/), 111 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF, 112 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 113 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 114 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 115 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 109 116 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13, 2 /*idxParam*/), 117 DIS_ARMV8_INSN_PARAM_NONE, 110 118 DIS_ARMV8_INSN_PARAM_NONE 111 119 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; … … 118 126 DIS_ARMV8_OP(0x7f800000, 0x52800000, "movz" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS), 119 127 DIS_ARMV8_OP(0x7f800000, 0x72800000, "movk" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS), 120 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF, 121 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 128 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF, 129 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 130 kDisArmv8OpParmGpr, kDisArmv8OpParmImm) 122 131 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 123 132 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 1 /*idxParam*/), 124 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseHw, 21, 2, 2 /*idxParam*/), 133 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseHw, 21, 2, 1 /*idxParam*/), 134 DIS_ARMV8_INSN_PARAM_NONE, 125 135 DIS_ARMV8_INSN_PARAM_NONE 126 136 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; … … 131 141 DIS_ARMV8_OP(0x7f800000, 0x13000000, "sbfm", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS), 132 142 DIS_ARMV8_OP(0x7f800000, 0x33000000, "bfm", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS), 133 DIS_ARMV8_OP(0x7f800000, 0x 23000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS),143 DIS_ARMV8_OP(0x7f800000, 0x53000000, "ubfm", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS), 134 144 INVALID_OPCODE, 135 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Bitfield, DISARMV8INSNCLASS_F_SF | DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT, 136 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 145 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_4(g_ArmV8A64Bitfield, DISARMV8INSNCLASS_F_SF | DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT, 146 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 147 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImm) 137 148 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 138 149 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 139 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmsImmrN, 10, 13, 2 /*idxParam*/), 150 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 6, 2 /*idxParam*/), 151 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 10, 6, 3 /*idxParam*/), 140 152 DIS_ARMV8_INSN_PARAM_NONE 141 153 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; … … 172 184 DIS_ARMV8_OP(0xff000010, 0x54000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 173 185 DIS_ARMV8_OP(0xff000010, 0x54000010, "bc" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 174 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CondBr, 0 /*fClass*/, 175 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4) 186 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64CondBr, 0 /*fClass*/, 187 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4, 188 kDisArmv8OpParmImmRel) 176 189 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCond, 0, 4, DIS_ARMV8_INSN_PARAM_UNSET), 177 190 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 0 /*idxParam*/), 191 DIS_ARMV8_INSN_PARAM_NONE, 178 192 DIS_ARMV8_INSN_PARAM_NONE, 179 193 DIS_ARMV8_INSN_PARAM_NONE … … 192 206 DIS_ARMV8_OP(0xffe0001f, 0xd4a00002, "dcps2", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 193 207 DIS_ARMV8_OP(0xffe0001f, 0xd4a00003, "dcps3", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 194 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Excp, 0 /*fClass*/, 195 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0) 208 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64Excp, 0 /*fClass*/, 209 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0, 210 kDisArmv8OpParmImm) 196 211 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16, 0 /*idxParam*/), 212 DIS_ARMV8_INSN_PARAM_NONE, 197 213 DIS_ARMV8_INSN_PARAM_NONE, 198 214 DIS_ARMV8_INSN_PARAM_NONE, … … 205 221 DIS_ARMV8_OP(0xffffffe0, 0xd5031000, "wfet", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 206 222 DIS_ARMV8_OP(0xffffffe0, 0x54000010, "wfit" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 207 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysReg, DISARMV8INSNCLASS_F_FORCED_64BIT, 208 kDisArmV8OpcDecodeNop, 0xfe0, 5) 209 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 223 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64SysReg, DISARMV8INSNCLASS_F_FORCED_64BIT, 224 kDisArmV8OpcDecodeNop, 0xfe0, 5, 225 kDisArmv8OpParmGpr) 226 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 227 DIS_ARMV8_INSN_PARAM_NONE, 210 228 DIS_ARMV8_INSN_PARAM_NONE, 211 229 DIS_ARMV8_INSN_PARAM_NONE, … … 225 243 DIS_ARMV8_OP(0xffffffff, 0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */ 226 244 /** @todo */ 227 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Hints, 0 /*fClass*/, 228 kDisArmV8OpcDecodeNop, 0xfe0, 5) 245 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64Hints, 0 /*fClass*/, 246 kDisArmV8OpcDecodeNop, 0xfe0, 5) 247 DIS_ARMV8_INSN_PARAM_NONE, 229 248 DIS_ARMV8_INSN_PARAM_NONE, 230 249 DIS_ARMV8_INSN_PARAM_NONE, … … 238 257 DIS_ARMV8_OP(0xfffff0ff, 0xd503304f, "clrex", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS), 239 258 DIS_ARMV8_OP(0xfffff0ff, 0xd50330bf, "dmb", OP_ARMV8_A64_DMB, DISOPTYPE_HARMLESS), 240 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64DecBarriers, 0 /*fClass*/, 241 kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5) 259 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64DecBarriers, 0 /*fClass*/, 260 kDisArmV8OpcDecodeNop, RT_BIT_32(5), 5, 261 kDisArmv8OpParmImm) 242 262 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 0 /*idxParam*/), 263 DIS_ARMV8_INSN_PARAM_NONE, 243 264 DIS_ARMV8_INSN_PARAM_NONE, 244 265 DIS_ARMV8_INSN_PARAM_NONE, … … 263 284 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64PState) 264 285 DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED), 265 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64PState, 0 /*fClass*/, 266 kDisArmV8OpcDecodeNop, 0, 0) 286 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64PState, 0 /*fClass*/, 287 kDisArmV8OpcDecodeNop, 0, 0, 288 kDisArmv8OpParmImm, kDisArmv8OpParmNone) /** @todo */ 267 289 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParsePState, 0, 0, 0 /*idxParam*/), /* This is special for the MSR instruction. */ 268 290 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4, 1 /*idxParam*/), /* CRm field encodes the immediate value */ 291 DIS_ARMV8_INSN_PARAM_NONE, 269 292 DIS_ARMV8_INSN_PARAM_NONE, 270 293 DIS_ARMV8_INSN_PARAM_NONE … … 276 299 DIS_ARMV8_OP(0xfffffffe, 0xd5233060, "tstart", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), /* FEAT_TME */ 277 300 DIS_ARMV8_OP(0xfffffffe, 0xd5233160, "ttest", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */ 278 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysResult, DISARMV8INSNCLASS_F_FORCED_64BIT, 279 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8) 280 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 301 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64SysResult, DISARMV8INSNCLASS_F_FORCED_64BIT, 302 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8, 303 kDisArmv8OpParmGpr) 304 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 305 DIS_ARMV8_INSN_PARAM_NONE, 281 306 DIS_ARMV8_INSN_PARAM_NONE, 282 307 DIS_ARMV8_INSN_PARAM_NONE, … … 288 313 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Sys) 289 314 DIS_ARMV8_OP(0xfff80000, 0xd5080000, "sys", OP_ARMV8_A64_SYS, DISOPTYPE_HARMLESS), 290 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS (g_ArmV8A64Sys, DISARMV8INSNCLASS_F_FORCED_64BIT,291 kDisArmV8OpcDecodeNop, 0, 0)315 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64Sys, DISARMV8INSNCLASS_F_FORCED_64BIT, 316 kDisArmV8OpcDecodeNop, 0, 0) /** @todo */ 292 317 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 0 /*idxParam*/), 293 318 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 1 /*idxParam*/), 294 319 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 2 /*idxParam*/), 295 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 3 /*idxParam*/) 320 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 3 /*idxParam*/), 321 DIS_ARMV8_INSN_PARAM_NONE 296 322 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 297 323 … … 300 326 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysL) 301 327 DIS_ARMV8_OP(0xfff80000, 0xd5280000, "sysl", OP_ARMV8_A64_SYSL, DISOPTYPE_HARMLESS), 302 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS (g_ArmV8A64SysL, DISARMV8INSNCLASS_F_FORCED_64BIT,303 kDisArmV8OpcDecodeNop, 0, 0)328 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_0(g_ArmV8A64SysL, DISARMV8INSNCLASS_F_FORCED_64BIT, 329 kDisArmV8OpcDecodeNop, 0, 0) /** @todo */ 304 330 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 305 331 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 16, 3, 1 /*idxParam*/), 306 332 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseCRnCRm, 8, 8, 2 /*idxParam*/), 307 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 3 /*idxParam*/) 333 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 3, 3 /*idxParam*/), 334 DIS_ARMV8_INSN_PARAM_NONE 308 335 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 309 336 … … 312 339 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Msr) 313 340 DIS_ARMV8_OP(0xfff00000, 0xd5100000, "msr", OP_ARMV8_A64_MSR, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 314 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Msr, DISARMV8INSNCLASS_F_FORCED_64BIT, 315 kDisArmV8OpcDecodeNop, 0, 0) 341 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Msr, DISARMV8INSNCLASS_F_FORCED_64BIT, 342 kDisArmV8OpcDecodeNop, 0, 0, 343 kDisArmv8OpParmSysReg, kDisArmv8OpParmGpr) 316 344 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 0 /*idxParam*/), 317 345 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 1 /*idxParam*/), 346 DIS_ARMV8_INSN_PARAM_NONE, 318 347 DIS_ARMV8_INSN_PARAM_NONE, 319 348 DIS_ARMV8_INSN_PARAM_NONE … … 324 353 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Mrs) 325 354 DIS_ARMV8_OP(0xfff00000, 0xd5300000, "mrs", OP_ARMV8_A64_MRS, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), 326 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Mrs, DISARMV8INSNCLASS_F_FORCED_64BIT, 327 kDisArmV8OpcDecodeNop, 0, 0) 355 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64Mrs, DISARMV8INSNCLASS_F_FORCED_64BIT, 356 kDisArmV8OpcDecodeNop, 0, 0, 357 kDisArmv8OpParmGpr, kDisArmv8OpParmSysReg) 328 358 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 329 359 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseSysReg, 5, 15, 1 /*idxParam*/), 360 DIS_ARMV8_INSN_PARAM_NONE, 330 361 DIS_ARMV8_INSN_PARAM_NONE, 331 362 DIS_ARMV8_INSN_PARAM_NONE … … 338 369 DIS_ARMV8_OP(0xfffffc1f, 0xd65f0800, "retaa", OP_ARMV8_A64_RETAA, DISOPTYPE_HARMLESS), 339 370 DIS_ARMV8_OP(0xfffffc1f, 0xd65f0c00, "retab", OP_ARMV8_A64_RETAB, DISOPTYPE_HARMLESS), 340 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Ret, DISARMV8INSNCLASS_F_FORCED_64BIT, 341 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0) 371 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64Ret, DISARMV8INSNCLASS_F_FORCED_64BIT, 372 kDisArmV8OpcDecodeLookup, 0xfffffc1f, 0, 373 kDisArmv8OpParmGpr) 342 374 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 0 /*idxParam*/), 375 DIS_ARMV8_INSN_PARAM_NONE, 343 376 DIS_ARMV8_INSN_PARAM_NONE, 344 377 DIS_ARMV8_INSN_PARAM_NONE, … … 372 405 DIS_ARMV8_OP(0xfc000000, 0x14000000, "b", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 373 406 DIS_ARMV8_OP(0xfc000000, 0x94000000, "bl", OP_ARMV8_A64_BL, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 374 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64UncondBrImm, 0 /*fClass*/, 375 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31) 407 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_1(g_ArmV8A64UncondBrImm, 0 /*fClass*/, 408 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31, 409 kDisArmv8OpParmImmRel) 376 410 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 0, 26, 0 /*idxParam*/), 411 DIS_ARMV8_INSN_PARAM_NONE, 377 412 DIS_ARMV8_INSN_PARAM_NONE, 378 413 DIS_ARMV8_INSN_PARAM_NONE, … … 385 420 DIS_ARMV8_OP(0x7f000000, 0x34000000, "cbz", OP_ARMV8_A64_CBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 386 421 DIS_ARMV8_OP(0x7f000000, 0x35000000, "cbnz", OP_ARMV8_A64_CBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 387 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CmpBrImm, DISARMV8INSNCLASS_F_SF, 388 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24) 422 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64CmpBrImm, DISARMV8INSNCLASS_F_SF, 423 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 424 kDisArmv8OpParmGpr, kDisArmv8OpParmImmRel) 389 425 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 390 426 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 19, 1 /*idxParam*/), 427 DIS_ARMV8_INSN_PARAM_NONE, 391 428 DIS_ARMV8_INSN_PARAM_NONE, 392 429 DIS_ARMV8_INSN_PARAM_NONE … … 398 435 DIS_ARMV8_OP(0x7f000000, 0x36000000, "tbz", OP_ARMV8_A64_TBZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 399 436 DIS_ARMV8_OP(0x7f000000, 0x37000000, "tbnz", OP_ARMV8_A64_TBNZ, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW), 400 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64TestBrImm, DISARMV8INSNCLASS_F_SF, 401 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24) 402 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 403 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 19, 5, 1 /*idxParam*/), 437 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_ArmV8A64TestBrImm, DISARMV8INSNCLASS_F_SF, /* Not an SF bit but has the same meaning. */ 438 kDisArmV8OpcDecodeNop, RT_BIT_32(24), 24, 439 kDisArmv8OpParmGpr, kDisArmv8OpParmImm, kDisArmv8OpParmImmRel) 440 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 441 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmTbz, 0, 0, 1 /*idxParam*/), /* Hardcoded bit offsets in parser. */ 404 442 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmRel, 5, 14, 2 /*idxParam*/), 443 DIS_ARMV8_INSN_PARAM_NONE, 405 444 DIS_ARMV8_INSN_PARAM_NONE 406 445 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; … … 426 465 427 466 467 /* AND/ORR/EOR/ANDS */ 468 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnLogShiftRegN0) 469 DIS_ARMV8_OP(0x7f200000, 0x0a000000, "and", OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS), 470 DIS_ARMV8_OP(0x7f200000, 0x2a000000, "orr", OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS), 471 DIS_ARMV8_OP(0x7f200000, 0x4a000000, "eor", OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 472 DIS_ARMV8_OP(0x7f200000, 0x6a000000, "ands", OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS) 473 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_aArmV8A64InsnLogShiftRegN0, DISARMV8INSNCLASS_F_SF, 474 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 475 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr) 476 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 477 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 478 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 16, 5, 2 /*idxParam*/), 479 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShift, 22, 2, 2 /*idxParam*/), 480 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/), 481 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 482 483 484 /* AND/ORR/EOR/ANDS */ 485 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnLogShiftRegN1) 486 DIS_ARMV8_OP(0x7f200000, 0x0a200000, "bic", OP_ARMV8_A64_BIC, DISOPTYPE_HARMLESS), 487 DIS_ARMV8_OP(0x7f200000, 0x2a200000, "orn", OP_ARMV8_A64_ORN, DISOPTYPE_HARMLESS), 488 DIS_ARMV8_OP(0x7f200000, 0x4a200000, "eon", OP_ARMV8_A64_EON, DISOPTYPE_HARMLESS), 489 DIS_ARMV8_OP(0x7f200000, 0x6a200000, "bics", OP_ARMV8_A64_BICS, DISOPTYPE_HARMLESS) 490 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_3(g_aArmV8A64InsnLogShiftRegN1, DISARMV8INSNCLASS_F_SF, 491 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29, 492 kDisArmv8OpParmGpr, kDisArmv8OpParmGpr, kDisArmv8OpParmGpr) 493 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5, 0 /*idxParam*/), 494 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5, 1 /*idxParam*/), 495 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 16, 5, 2 /*idxParam*/), 496 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShift, 22, 2, 2 /*idxParam*/), 497 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseShiftAmount, 10, 6, 2 /*idxParam*/), 498 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 499 500 501 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_aArmV8A64InsnLogShiftRegN) 502 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN0), /* Logical (shifted register) - N = 0 */ 503 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN1), /* Logical (shifted register) - N = 1 */ 504 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_aArmV8A64InsnLogShiftRegN, RT_BIT_32(21), 21); 505 506 428 507 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64LogicalAddSubReg) 429 DIS_ARMV8_DECODE_MAP_ INVALID_ENTRY,/* Logical (shifted register) */508 DIS_ARMV8_DECODE_MAP_ENTRY(g_aArmV8A64InsnLogShiftRegN), /* Logical (shifted register) */ 430 509 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /* Add/subtract (shifted/extended register) */ 431 510 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64LogicalAddSubReg, RT_BIT_32(24), 24); … … 440 519 DIS_ARMV8_OP(0xbfc00000, 0xb9400000, "ldr", OP_ARMV8_A64_LDR, DISOPTYPE_HARMLESS), 441 520 DIS_ARMV8_OP(0xbfc00000, 0xb9000000, "str", OP_ARMV8_A64_STR, DISOPTYPE_HARMLESS), 442 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LdSt, 0 /*fClass*/, 443 kDisArmV8OpcDecodeLookup, 0xbfc00000, 0) 521 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS_2(g_ArmV8A64LdSt, 0 /*fClass*/, 522 kDisArmV8OpcDecodeLookup, 0xbfc00000, 0, 523 kDisArmv8OpParmGpr, kDisArmv8OpParmAddrInGpr) 444 524 DIS_ARMV8_INSN_PARAM_CREATE( kDisParmParseIs32Bit, 30, 1, DIS_ARMV8_INSN_PARAM_UNSET), 445 525 DIS_ARMV8_INSN_PARAM_CREATE( kDisParmParseReg, 0, 5, 0 /*idxParam*/), 446 526 DIS_ARMV8_INSN_PARAM_CREATE_EX(kDisParmParseReg, 5, 5, 1 /*idxParam*/, DIS_ARMV8_INSN_PARAM_F_ADDR_BEGIN), 447 527 DIS_ARMV8_INSN_PARAM_CREATE_EX(kDisParmParseImm, 10, 12, 2 /*idxParam*/, DIS_ARMV8_INSN_PARAM_F_ADDR_END), 528 DIS_ARMV8_INSN_PARAM_NONE 448 529 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 449 530 -
trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S
r105759 r105779 28 28 .private_extern _TestProcA64 29 29 _TestProcA64: 30 ; Miscellaneous instructions without a parameter 30 31 nop 31 32 yield … … 36 37 dgh 37 38 xpaclri 39 40 ; Control flow instructions 41 svc #0xfefe 42 hvc #0xdead 43 smc #0xcafe 44 brk #0xd0d0 45 hlt #0xc0de 46 ; tcancel #0xd00f Requires FEAT_TME 47 dcps1 #0xdeca 48 dcps2 #0xdec0 49 dcps3 #0xfeed 50 b #0x100 51 b #-0x100 52 bl #0x100 53 bl #-0x100 54 b.ne #+0x1000 55 b.eq #-0x1000 56 ; bc.ne #+0x1000 Requires FEAT_HBC 57 ; bc.eq #-0x1000 Requires FEAT_HBC 58 cbz x0, #+0x100 59 cbz x0, #-0x100 60 cbz w0, #+0x100 61 cbnz x0, #+0x100 62 cbnz x0, #-0x100 63 cbnz w0, #+0x100 64 tbz w0, #13, #+0x100 65 tbz x0, #63, #-0x100 66 tbz w0, #8, #+0x100 38 67 ret x30 39 68 ret x1 … … 41 70 ret x15 42 71 72 ; System register access instructions 43 73 msr ttbr0_el1, x0 44 74 mrs x0, ttbr0_el1 45 75 46 b #0x100 47 b #-0x100 48 b.ne #+0x1000 49 b.eq #-0x1000 50 ; bc.ne #+0x1000 Requires FEAT_HBC 51 ; bc.eq #-0x1000 Requires FEAT_HBC 52 76 ; Arithmetic instructions 53 77 add x0, x0, #0x0 54 78 add w0, w1, #0x10000 … … 70 94 ; mov w0, w1 71 95 72 and x0, x0, #0xffff 73 74 ret x30 96 ; Logical instructions 97 and x0, x0, #0xffff 98 and w0, wzr, #0xffff 99 100 ands x0, x0, #0x00ffff00 101 ands w10, w23, #0x55555555 102 103 orr x0, x0, #0xffff 104 orr w0, wzr, #0xffff 105 106 eor x0, x0, #0x00ffff00 107 eor w10, w23, #0x55555555 108 109 sbfm x0, x0, #0x1, #0x2 110 sbfm w0, w0, #0xf, #0x9 111 bfm x0, x0, #0x1, #0x2 112 bfm w0, w0, #0xf, #0x9 113 ubfm x0, x0, #0x1, #0x2 114 ubfm w0, w0, #0xf, #0x9 115 116 movn x0, #0xffff 117 movn x0, #0xffff, LSL #16 118 movn w0, #0xffff 119 movn w0, #0xffff, LSL #16 120 121 movz x0, #0xffff 122 movz x0, #0xffff, LSL #48 123 movz w0, #0xffff 124 movz w0, #0xffff, LSL #16 125 126 movk x0, #0xffff 127 movk x0, #0xffff, LSL #32 128 movk w0, #0xffff 129 movk w0, #0xffff, LSL #16 130 131 ; Logical instructions with a shifted register 132 and w0, w0, w27 133 and w0, w1, w28, LSL #1 134 and w0, w1, w28, LSL #31 135 and w0, w1, w28, LSR #1 136 and w0, w1, w28, LSR #31 137 and w0, w1, w28, ASR #1 138 and w0, w1, w28, ASR #31 139 and w0, w1, w28, ROR #1 140 and w0, w1, w28, ROR #31 141 142 and x0, x0, x27 143 and x0, x1, x28, LSL #1 144 and x0, x1, x28, LSL #63 145 and x0, x1, x28, LSR #1 146 and x0, x1, x28, LSR #63 147 and x0, x1, x28, ASR #1 148 and x0, x1, x28, ASR #63 149 and x0, x1, x28, ROR #1 150 and x0, x1, x28, ROR #63 151 152 orr w0, w0, w27 153 orr w0, w1, w28, LSL #1 154 orr w0, w1, w28, LSL #31 155 orr w0, w1, w28, LSR #1 156 orr w0, w1, w28, LSR #31 157 orr w0, w1, w28, ASR #1 158 orr w0, w1, w28, ASR #31 159 orr w0, w1, w28, ROR #1 160 orr w0, w1, w28, ROR #31 161 162 orr x0, x0, x27 163 orr x0, x1, x28, LSL #1 164 orr x0, x1, x28, LSL #63 165 orr x0, x1, x28, LSR #1 166 orr x0, x1, x28, LSR #63 167 orr x0, x1, x28, ASR #1 168 orr x0, x1, x28, ASR #63 169 orr x0, x1, x28, ROR #1 170 orr x0, x1, x28, ROR #63 171 172 eor w0, w0, w27 173 eor w0, w1, w28, LSL #1 174 eor w0, w1, w28, LSL #31 175 eor w0, w1, w28, LSR #1 176 eor w0, w1, w28, LSR #31 177 eor w0, w1, w28, ASR #1 178 eor w0, w1, w28, ASR #31 179 eor w0, w1, w28, ROR #1 180 eor w0, w1, w28, ROR #31 181 182 eor x0, x0, x27 183 eor x0, x1, x28, LSL #1 184 eor x0, x1, x28, LSL #63 185 eor x0, x1, x28, LSR #1 186 eor x0, x1, x28, LSR #63 187 eor x0, x1, x28, ASR #1 188 eor x0, x1, x28, ASR #63 189 eor x0, x1, x28, ROR #1 190 eor x0, x1, x28, ROR #63 191 192 ands x0, x0, x27 193 ands x0, x1, x28, LSL #1 194 ands x0, x1, x28, LSL #63 195 ands x0, x1, x28, LSR #1 196 ands x0, x1, x28, LSR #63 197 ands x0, x1, x28, ASR #1 198 ands x0, x1, x28, ASR #63 199 ands x0, x1, x28, ROR #1 200 ands x0, x1, x28, ROR #63 201 202 bic w0, w0, w27 203 bic w0, w1, w28, LSL #1 204 bic w0, w1, w28, LSL #31 205 bic w0, w1, w28, LSR #1 206 bic w0, w1, w28, LSR #31 207 bic w0, w1, w28, ASR #1 208 bic w0, w1, w28, ASR #31 209 bic w0, w1, w28, ROR #1 210 bic w0, w1, w28, ROR #31 211 212 bic x0, x0, x27 213 bic x0, x1, x28, LSL #1 214 bic x0, x1, x28, LSL #63 215 bic x0, x1, x28, LSR #1 216 bic x0, x1, x28, LSR #63 217 bic x0, x1, x28, ASR #1 218 bic x0, x1, x28, ASR #63 219 bic x0, x1, x28, ROR #1 220 bic x0, x1, x28, ROR #63 221 222 orn w0, w0, w27 223 orn w0, w1, w28, LSL #1 224 orn w0, w1, w28, LSL #31 225 orn w0, w1, w28, LSR #1 226 orn w0, w1, w28, LSR #31 227 orn w0, w1, w28, ASR #1 228 orn w0, w1, w28, ASR #31 229 orn w0, w1, w28, ROR #1 230 orn w0, w1, w28, ROR #31 231 232 orn x0, x0, x27 233 orn x0, x1, x28, LSL #1 234 orn x0, x1, x28, LSL #63 235 orn x0, x1, x28, LSR #1 236 orn x0, x1, x28, LSR #63 237 orn x0, x1, x28, ASR #1 238 orn x0, x1, x28, ASR #63 239 orn x0, x1, x28, ROR #1 240 orn x0, x1, x28, ROR #63 241 242 eon w0, w0, w27 243 eon w0, w1, w28, LSL #1 244 eon w0, w1, w28, LSL #31 245 eon w0, w1, w28, LSR #1 246 eon w0, w1, w28, LSR #31 247 eon w0, w1, w28, ASR #1 248 eon w0, w1, w28, ASR #31 249 eon w0, w1, w28, ROR #1 250 eon w0, w1, w28, ROR #31 251 252 eon x0, x0, x27 253 eon x0, x1, x28, LSL #1 254 eon x0, x1, x28, LSL #63 255 eon x0, x1, x28, LSR #1 256 eon x0, x1, x28, LSR #63 257 eon x0, x1, x28, ASR #1 258 eon x0, x1, x28, ASR #63 259 eon x0, x1, x28, ROR #1 260 eon x0, x1, x28, ROR #63 261 262 bics w0, w0, w27 263 bics w0, w1, w28, LSL #1 264 bics w0, w1, w28, LSL #31 265 bics w0, w1, w28, LSR #1 266 bics w0, w1, w28, LSR #31 267 bics w0, w1, w28, ASR #1 268 bics w0, w1, w28, ASR #31 269 bics w0, w1, w28, ROR #1 270 bics w0, w1, w28, ROR #31 271 272 bics x0, x0, x27 273 bics x0, x1, x28, LSL #1 274 bics x0, x1, x28, LSL #63 275 bics x0, x1, x28, LSR #1 276 bics x0, x1, x28, LSR #63 277 bics x0, x1, x28, ASR #1 278 bics x0, x1, x28, ASR #63 279 bics x0, x1, x28, ROR #1 280 bics x0, x1, x28, ROR #63 281 282 ; 283 ; Keep last so the testcase can catch errors in 284 ; the disassembly of the last instruction. 285 ; 286 nop 75 287 76 288 .private_extern _TestProcA64_EndProc
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