Changeset 106610 in vbox

Timestamp:

Oct 23, 2024 7:36:09 AM (5 weeks ago)

Author:

vboxsync

Message:

iprt/x86.h: bugref:10794 Add SRBDS_CTRL CPUID bit and IA32_MCU_OPT_CTRL MSR bits.

File:

• trunk/include/iprt/x86.h (modified) (2 diffs)

trunk/include/iprt/x86.h

@@ -711 +711 @@
 #define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC            RT_BIT_32(30)
 
+/** EDX bit 9 - SRBDS_CTRL - (Special Register Buffer Data Sample Control)
+ *  Supports IA32_MCU_OPT_CTRL and IA32_MCU_OPT_CTRL.RNGDS_MITG_DIS. */
+#define X86_CPUID_STEXT_FEATURE_EDX_SRBDS_CTRL        RT_BIT_32(9)
 /** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
 #define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR          RT_BIT_32(10)
@@ -1619 +1622 @@
 /** Cache control/info. */
 #define MSR_BBL_CR_CTL3                     UINT32_C(0x11e)
+
+/** Microcode Update Operation Control (R/W). */
+#define MSR_IA32_MCU_OPT_CTRL                       0x123
+#define MSR_IA32_MCU_OPT_CTRL_RNGDS_MITG_DIS        RT_BIT_64(0)
+#define MSR_IA32_MCU_OPT_CTRL_RTM_ALLOW             RT_BIT_64(1)
+#define MSR_IA32_MCU_OPT_CTRL_RTM_LOCKED            RT_BIT_64(2)
+#define MSR_IA32_MCU_OPT_CTRL_FB_CLEAR_DIS          RT_BIT_64(3)
+#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_DIS          RT_BIT_64(4)
+#define MSR_IA32_MCU_OPT_CTRL_GDS_MITG_LOCK         RT_BIT_64(5)
+#define MSR_IA32_MCU_OPT_CTRL_IGN_UMONITOR          RT_BIT_64(6)
+#define MSR_IA32_MCU_OPT_CTRL_MON_UMON_MITG         RT_BIT_64(7)
+/* Bits 63:7 reserved. */
+#define MSR_IA32_MCU_OPT_CTRL_RSVD_MASK             UINT64_C(0xffffffffffffff80)
 
 #ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */