Changeset 106746 in vbox for trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

Timestamp:

Oct 28, 2024 1:14:22 PM (3 months ago)

Author:

vboxsync

Message:

Disassembler: Decode SIMD ldr/str instructions, bugref:10394

File:

• trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp (modified) (4 diffs)

trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp

@@ -106 +106 @@
 static FNDISPARSEARMV8 disArmV8ParseFpScale;
 static FNDISPARSEARMV8 disArmV8ParseFpFixupFCvt;
+static FNDISPARSEARMV8 disArmV8ParseSimdRegSize;
+static FNDISPARSEARMV8 disArmV8ParseSimdRegSize64;
+static FNDISPARSEARMV8 disArmV8ParseSimdRegSize128;
 static FNDISPARSEARMV8 disArmV8ParseSimdRegScalar;
 static FNDISPARSEARMV8 disArmV8ParseImmHImmB;
@@ -161 +164 @@
     disArmV8ParseFpScale,
     disArmV8ParseFpFixupFCvt,
+    disArmV8ParseSimdRegSize,
+    disArmV8ParseSimdRegSize64,
+    disArmV8ParseSimdRegSize128,
     disArmV8ParseSimdRegScalar,
     disArmV8ParseImmHImmB,
@@ -664 +670 @@
         case sizeof(uint32_t): pParam->armv8.u.offBase <<= 2; break;
         case sizeof(uint64_t): pParam->armv8.u.offBase <<= 3; break;
+        case 16:               pParam->armv8.u.offBase <<= 4; break;
         default:
             AssertReleaseFailed();
@@ -874 +881 @@
 
 
+static int disArmV8ParseSimdRegSize(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
+    RT_NOREF(pOp, pInsnClass, pParam, pf64Bit);
+
+    Assert(pInsnParm->cBits == 2);
+    uint32_t u32Size = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
+    switch (u32Size)
+    {
+        case 0: pDis->armv8.cbOperand = sizeof(uint8_t); break;
+        case 1: pDis->armv8.cbOperand = sizeof(uint16_t); break;
+        case 2: pDis->armv8.cbOperand = sizeof(uint32_t); break;
+        case 3: pDis->armv8.cbOperand = sizeof(uint64_t); break;
+        default:
+            AssertReleaseFailed();
+    }
+
+    return VINF_SUCCESS;
+}
+
+
+static int disArmV8ParseSimdRegSize64(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
+    RT_NOREF(u32Insn, pOp, pInsnClass, pParam, pInsnParm, pf64Bit);
+
+    pDis->armv8.cbOperand = sizeof(uint64_t);
+    return VINF_SUCCESS;
+}
+
+
+static int disArmV8ParseSimdRegSize128(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
+{
+    RT_NOREF(u32Insn, pOp, pInsnClass, pParam, pInsnParm, pf64Bit);
+
+    pDis->armv8.cbOperand = 16;
+    return VINF_SUCCESS;
+}
+
+
 static int disArmV8ParseSimdRegScalar(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool *pf64Bit)
 {
     RT_NOREF(pDis, pOp, pInsnClass, pParam, pInsnParm, pf64Bit);
 
+    Assert(pDis->armv8.cbOperand != 0);
     Assert(pParam->armv8.enmType == kDisArmv8OpParmNone);
 
     pParam->armv8.enmType = kDisArmv8OpParmReg;
     pParam->armv8.Op.Reg.idReg = disArmV8ExtractBitVecFromInsn(u32Insn, pInsnParm->idxBitStart, pInsnParm->cBits);
-    pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_64Bit;
+    switch (pDis->armv8.cbOperand)
+    {
+        case sizeof(uint8_t):  pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_8Bit;   break;
+        case sizeof(uint16_t): pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_16Bit;  break;
+        case sizeof(uint32_t): pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_32Bit;  break;
+        case sizeof(uint64_t): pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_64Bit;  break;
+        case 16:               pParam->armv8.Op.Reg.enmRegType = kDisOpParamArmV8RegType_Simd_Scalar_128Bit; break;
+    }
     return VINF_SUCCESS;
 }