Changeset 106752 in vbox for trunk/src/VBox/Disassembler

Timestamp:

Oct 28, 2024 2:09:29 PM (4 months ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

165636

Message:

Disassembler: Decode SIMD ldur/stur (unscaled immediate) instructions, bugref:10394

Location:

trunk/src/VBox/Disassembler

Files:

• DisasmTables-armv8-a64-ld-st.cpp.h (modified) (2 diffs)
• testcase/tstDisasmArmv8-1-asm.S (modified) (2 diffs)

trunk/src/VBox/Disassembler/DisasmTables-armv8-a64-ld-st.cpp.h

@@ -222 +222 @@
 
 
+/* SIMD STUR/LDUR */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER(LdStRegUnscaledImmSimd)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize,        30,  2, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_DECODER_ALTERNATIVE(LdStRegUnscaledImmSimd128)
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegSize128,      0,  0, DIS_ARMV8_INSN_PARAM_UNSET),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSimdRegScalar,       0,  5, 0 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseAddrGprSp,           5,  5, 1 /*idxParam*/),
+    DIS_ARMV8_INSN_DECODE(kDisParmParseSImmMemOffUnscaled, 12,  9, 1 /*idxParam*/),
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(LdStRegUnscaledImmSimd)
+    DIS_ARMV8_OP(           0x3c000000, "stur",            OP_ARMV8_A64_STUR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP(           0x3c400000, "ldur",            OP_ARMV8_A64_LDUR,      DISOPTYPE_HARMLESS),
+    DIS_ARMV8_OP_ALT_DECODE(0x3c800000, "stur",            OP_ARMV8_A64_STUR,      DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
+    DIS_ARMV8_OP_ALT_DECODE(0x3cc00000, "ldur",            OP_ARMV8_A64_LDUR,      DISOPTYPE_HARMLESS, LdStRegUnscaledImmSimd128), /** @todo size == 0. */
+DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END(LdStRegUnscaledImmSimd, 0x3fe00c00 /*fFixedInsn*/,
+                                       kDisArmV8OpcDecodeNop,
+                                       RT_BIT_32(22) | RT_BIT_32(23), 22);
+
+
 /*
  * C4.1.94 - Loads and Stores - Load/Store register (register offset) variants
@@ -234 +255 @@
 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(LdStRegUnscaledImm)
     DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmGpr),
-    DIS_ARMV8_DECODE_MAP_INVALID_ENTRY,             /** @todo */
+    DIS_ARMV8_DECODE_MAP_ENTRY(LdStRegUnscaledImmSimd),
 DIS_ARMV8_DECODE_MAP_DEFINE_END(LdStRegUnscaledImm, RT_BIT_32(26), 26);
 

trunk/src/VBox/Disassembler/testcase/tstDisasmArmv8-1-asm.S

@@ -1508 +1508 @@
 
 
+        ldur b0,  [x0]
+        ldur b0,  [x0, #-256]
+        ldur b31, [x0, #255]
+
+        ldur b0,  [sp]
+        ldur b0,  [sp, #-256]
+        ldur b31, [sp, #255]
+
+        ldur h0,  [x0]
+        ldur h0,  [x0, #-256]
+        ldur h31, [x0, #255]
+
+        ldur h0,  [sp]
+        ldur h0,  [sp, #-256]
+        ldur h31, [sp, #255]
+
+        ldur s0,  [x0]
+        ldur s0,  [x0, #-256]
+        ldur s31, [x0, #255]
+
+        ldur s0,  [sp]
+        ldur s0,  [sp, #-256]
+        ldur s31, [sp, #255]
+
+        ldur d0,  [x0]
+        ldur d0,  [x0, #-256]
+        ldur d31, [x0, #255]
+
+        ldur d0,  [sp]
+        ldur d0,  [sp, #-256]
+        ldur d31, [sp, #255]
+
+        ldur q0,  [x0]
+        ldur q0,  [x0, #-256]
+        ldur q31, [x0, #255]
+
+        ldur q0,  [sp]
+        ldur q0,  [sp, #-256]
+        ldur q31, [sp, #255]
+
+
         ; SIMD memory stores
         str b0, [x0]
@@ -1643 +1684 @@
         str  q31, [sp, w2, UXTW #4]
         str  q31, [sp, w2, SXTW #4]
+
+
+        stur b0,  [x0]
+        stur b0,  [x0, #-256]
+        stur b31, [x0, #255]
+
+        stur b0,  [sp]
+        stur b0,  [sp, #-256]
+        stur b31, [sp, #255]
+
+        stur h0,  [x0]
+        stur h0,  [x0, #-256]
+        stur h31, [x0, #255]
+
+        stur h0,  [sp]
+        stur h0,  [sp, #-256]
+        stur h31, [sp, #255]
+
+        stur s0,  [x0]
+        stur s0,  [x0, #-256]
+        stur s31, [x0, #255]
+
+        stur s0,  [sp]
+        stur s0,  [sp, #-256]
+        stur s31, [sp, #255]
+
+        stur d0,  [x0]
+        stur d0,  [x0, #-256]
+        stur d31, [x0, #255]
+
+        stur d0,  [sp]
+        stur d0,  [sp, #-256]
+        stur d31, [sp, #255]
+
+        stur q0,  [x0]
+        stur q0,  [x0, #-256]
+        stur q31, [x0, #255]
+
+        stur q0,  [sp]
+        stur q0,  [sp, #-256]
+        stur q31, [sp, #255]