VirtualBox

Changeset 107308 in vbox for trunk


Ignore:
Timestamp:
Dec 13, 2024 8:09:39 AM (5 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
166339
Message:

VMM: bugref:10759 Refactor GIC for use with different backends.

Location:
trunk
Files:
2 added
1 deleted
24 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/log.h

    r107283 r107308  
    757757    /** PDM Driver group. */
    758758    LOG_GROUP_PDM_DRIVER,
     759    /** PDM GIC group. */
     760    LOG_GROUP_PDM_GIC,
    759761    /** PDM Loader group. */
    760762    LOG_GROUP_PDM_LDR,
    … …  
    12241226    "PDM_DEVICE", \
    12251227    "PDM_DRIVER", \
     1228    "PDM_GIC", \
    12261229    "PDM_LDR", \
    12271230    "PDM_QUEUE", \

  • trunk/include/VBox/vmm/pdmapic.h

    r107118 r107308  
    844844    DECLRCCALLBACKMEMBER(int, pfnReserved9, (void));
    845845    DECLRCCALLBACKMEMBER(int, pfnReserved10, (void));
     846    DECLRCCALLBACKMEMBER(int, pfnReserved11, (void));
     847    DECLRCCALLBACKMEMBER(int, pfnReserved12, (void));
    846848    /** @} */
    847849} PDMAPICBACKENDRC;

  • trunk/include/VBox/vmm/pdmdev.h

    r107215 r107308  
    752752#endif
    753753
    754 /**
    755  * The PDM APIC device registration structure.
    756  */
     754#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
     755/** The PDM APIC device registration structure. */
    757756extern const PDMDEVREG g_DeviceAPIC;
     757#elif defined(VBOX_VMM_TARGET_ARMV8)
     758/** The PDM GIC device registration structure. */
     759extern const PDMDEVREG g_DeviceGIC;
     760/** The PDM GIC NEM device registration structure. */
     761extern const PDMDEVREG g_DeviceGICNem;
     762#endif
    758763
    759764/**
    … …  
    42644269
    42654270    /**
    4266      * Register the APIC device.
    4267      *
    4268      * @returns VBox status code.
    4269      * @param   pDevIns             The device instance.
    4270      */
    4271     DECLR3CALLBACKMEMBER(int, pfnApicRegister,(PPDMDEVINS pDevIns));
     4271     * Register the Interrupt Controller device.
     4272     *
     4273     * @returns VBox status code.
     4274     * @param   pDevIns             The device instance.
     4275     */
     4276    DECLR3CALLBACKMEMBER(int, pfnIcRegister,(PPDMDEVINS pDevIns));
    42724277
    42734278    /**
    … …  
    54305435     *
    54315436     * This must be called after ring-3 has registered the APIC using
    5432      * PDMDevHlpApicRegister().
     5437     * PDMDevHlpIcRegister().
    54335438     *
    54345439     * @returns VBox status code.
    54355440     * @param   pDevIns     The device instance.
    54365441     */
    5437     DECLRCCALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
     5442    DECLRCCALLBACKMEMBER(int, pfnIcSetUpContext,(PPDMDEVINS pDevIns));
    54385443
    54395444    /**
    … …  
    59265931     *
    59275932     * This must be called after ring-3 has registered the APIC using
    5928      * PDMDevHlpApicRegister().
     5933     * PDMDevHlpIcRegister().
    59295934     *
    59305935     * @returns VBox status code.
    59315936     * @param   pDevIns     The device instance.
    59325937     */
    5933     DECLR0CALLBACKMEMBER(int, pfnApicSetUpContext,(PPDMDEVINS pDevIns));
     5938    DECLR0CALLBACKMEMBER(int, pfnIcSetUpContext,(PPDMDEVINS pDevIns));
    59345939
    59355940    /**
    … …  
    91809185
    91819186/**
    9182  * @copydoc PDMDEVHLPR3::pfnApicRegister
    9183  */
    9184 DECLINLINE(int) PDMDevHlpApicRegister(PPDMDEVINS pDevIns)
    9185 {
    9186     return pDevIns->pHlpR3->pfnApicRegister(pDevIns);
     9187 * @copydoc PDMDEVHLPR3::pfnIcRegister
     9188 */
     9189DECLINLINE(int) PDMDevHlpIcRegister(PPDMDEVINS pDevIns)
     9190{
     9191    return pDevIns->pHlpR3->pfnIcRegister(pDevIns);
    91879192}
    91889193
    … …  
    93449349
    93459350/**
    9346  * @copydoc PDMDEVHLPR0::pfnApicSetUpContext
    9347  */
    9348 DECLINLINE(int) PDMDevHlpApicSetUpContext(PPDMDEVINS pDevIns)
    9349 {
    9350     return pDevIns->CTX_SUFF(pHlp)->pfnApicSetUpContext(pDevIns);
     9351 * @copydoc PDMDEVHLPR0::pfnIcSetUpContext
     9352 */
     9353DECLINLINE(int) PDMDevHlpIcSetUpContext(PPDMDEVINS pDevIns)
     9354{
     9355    return pDevIns->CTX_SUFF(pHlp)->pfnIcSetUpContext(pDevIns);
    93519356}
    93529357

  • trunk/src/VBox/VMM/Makefile.kmk

    r107227 r107308  
    497497        VMMAll/PDMAllCritSectRw.cpp \
    498498        VMMAll/PDMAllCritSectBoth.cpp \
     499        VMMAll/PDMAllGic.cpp \
    499500        VMMAll/PDMAllQueue.cpp \
    500501        VMMAll/PDMAllTask.cpp \

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r107117 r107308  
    33723372    AssertRCReturn(rc, rc);
    33733373
    3374     rc = PDMDevHlpApicSetUpContext(pDevIns);
     3374    rc = PDMDevHlpIcSetUpContext(pDevIns);
    33753375    AssertRCReturn(rc, rc);
    33763376

  • trunk/src/VBox/VMM/VMMAll/CPUMAllSysRegs-armv8.cpp

    r107031 r107308  
    3333#include <VBox/vmm/cpum.h>
    3434#include "CPUMInternal-armv8.h"
    35 #include <VBox/vmm/gic.h>
     35#include <VBox/vmm/pdmgic.h>
    3636#include <VBox/vmm/pmu.h>
    3737#include <VBox/vmm/vmcc.h>
    … …  
    172172{
    173173    RT_NOREF_PV(pRange);
    174     return GICReadSysReg(pVCpu, idSysReg, puValue);
     174    return PDMGicReadSysReg(pVCpu, idSysReg, puValue);
    175175}
    176176
    … …  
    180180{
    181181    RT_NOREF_PV(pRange); RT_NOREF_PV(uRawValue);
    182     return GICWriteSysReg(pVCpu, idSysReg, uValue);
     182    return PDMGicWriteSysReg(pVCpu, idSysReg, uValue);
    183183}
    184184

  • trunk/src/VBox/VMM/VMMAll/GICAll.cpp

    r107109 r107308  
    3232#define LOG_GROUP LOG_GROUP_DEV_APIC
    3333#include "GICInternal.h"
    34 #include <VBox/vmm/gic.h>
     34#include <VBox/vmm/pdmgic.h>
    3535#include <VBox/vmm/pdmdev.h>
    3636#include <VBox/vmm/pdmapi.h>
    … …  
    910910
    911911/**
    912  * Reads a GIC system register.
    913  *
    914  * @returns Strict VBox status code.
    915  * @param   pVCpu           The cross context virtual CPU structure.
    916  * @param   u32Reg          The system register being read.
    917  * @param   pu64Value       Where to store the read value.
    918  */
    919 VMM_INT_DECL(VBOXSTRICTRC) GICReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
     912 * @interface_method_impl{PDMGICBACKEND,pfnSetSpi}
     913 */
     914static DECLCALLBACK(int) gicSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)
     915{
     916    LogFlowFunc(("pVM=%p uIntId=%u fAsserted=%RTbool\n",
     917                 pVM, uIntId, fAsserted));
     918
     919    AssertReturn(uIntId < GIC_SPI_MAX, VERR_INVALID_PARAMETER);
     920
     921    PGIC       pGic    = VM_TO_GIC(pVM);
     922    PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
     923    PGICDEV    pThis   = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
     924
     925    int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
     926    PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
     927
     928    /* Update the interrupts pending state. */
     929    if (fAsserted)
     930        ASMAtomicOrU32(&pThis->bmIntPending, RT_BIT_32(uIntId));
     931    else
     932        ASMAtomicAndU32(&pThis->bmIntPending, ~RT_BIT_32(uIntId));
     933
     934    int rc = VBOXSTRICTRC_VAL(gicDistUpdateIrqState(pVM, pThis));
     935    PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
     936    return rc;
     937}
     938
     939
     940/**
     941 * @interface_method_impl{PDMGICBACKEND,pfnSetPpi}
     942 */
     943static DECLCALLBACK(int) gicSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
     944{
     945    LogFlowFunc(("pVCpu=%p{.idCpu=%u} uIntId=%u fAsserted=%RTbool\n",
     946                 pVCpu, pVCpu->idCpu, uIntId, fAsserted));
     947
     948    PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
     949    int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
     950    PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
     951
     952    AssertReturn(uIntId <= (GIC_INTID_RANGE_PPI_LAST - GIC_INTID_RANGE_PPI_START), VERR_INVALID_PARAMETER);
     953    int rc = gicReDistInterruptSet(pVCpu, uIntId + GIC_INTID_RANGE_PPI_START, fAsserted);
     954    PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
     955
     956    return rc;
     957}
     958
     959
     960/**
     961 * Sets the specified software generated interrupt starting.
     962 *
     963 * @returns VBox status code.
     964 * @param   pVCpu               The cross context virtual CPU structure.
     965 * @param   uIntId              The PPI ID (minus GIC_INTID_RANGE_SGI_START) to assert/de-assert.
     966 * @param   fAsserted           Flag whether to mark the interrupt as asserted/de-asserted.
     967 */
     968static int gicSetSgi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
     969{
     970    LogFlowFunc(("pVCpu=%p{.idCpu=%u} uIntId=%u fAsserted=%RTbool\n",
     971                 pVCpu, pVCpu->idCpu, uIntId, fAsserted));
     972
     973    PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
     974    int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
     975    PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
     976
     977    AssertReturn(uIntId <= (GIC_INTID_RANGE_SGI_LAST - GIC_INTID_RANGE_SGI_START), VERR_INVALID_PARAMETER);
     978    int rc = gicReDistInterruptSet(pVCpu, uIntId + GIC_INTID_RANGE_SGI_START, fAsserted);
     979    PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
     980
     981    return rc;
     982}
     983
     984
     985/**
     986 * @interface_method_impl{PDMGICBACKEND,pfnReadSysReg}
     987 */
     988static DECLCALLBACK(VBOXSTRICTRC) gicReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
    920989{
    921990    /*
    … …  
    11081177
    11091178/**
    1110  * Writes an GIC system register.
    1111  *
    1112  * @returns Strict VBox status code.
    1113  * @param   pVCpu           The cross context virtual CPU structure.
    1114  * @param   u32Reg          The system register being written (IPRT system  register identifier).
    1115  * @param   u64Value        The value to write.
    1116  */
    1117 VMM_INT_DECL(VBOXSTRICTRC) GICWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
     1179 * @interface_method_impl{PDMGICBACKEND,pfnWriteSysReg}
     1180 */
     1181static DECLCALLBACK(VBOXSTRICTRC) gicWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
    11181182{
    11191183    /*
    … …  
    11941258                        PVMCPUCC pVCpuDst = VMMGetCpuById(pVCpu->CTX_SUFF(pVM), i);
    11951259                        if (pVCpuDst)
    1196                             GICSgiSet(pVCpuDst, uIntId, true /*fAsserted*/);
     1260                            gicSetSgi(pVCpuDst, uIntId, true /*fAsserted*/);
    11971261                        else
    11981262                            AssertFailed();
    … …  
    12131277                        PVMCPUCC pVCpuDst = VMMGetCpuById(pVCpu->CTX_SUFF(pVM), idCpu);
    12141278                        if (pVCpuDst)
    1215                             GICSgiSet(pVCpuDst, uIntId, true /*fAsserted*/);
     1279                            gicSetSgi(pVCpuDst, uIntId, true /*fAsserted*/);
    12161280                        else
    12171281                            AssertFailed();
    … …  
    12791343    PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
    12801344    return VINF_SUCCESS;
    1281 }
    1282 
    1283 
    1284 /**
    1285  * Sets the specified shared peripheral interrupt starting.
    1286  *
    1287  * @returns VBox status code.
    1288  * @param   pVM                 The cross context virtual machine structure.
    1289  * @param   uIntId              The SPI ID (minus GIC_INTID_RANGE_SPI_START) to assert/de-assert.
    1290  * @param   fAsserted           Flag whether to mark the interrupt as asserted/de-asserted.
    1291  */
    1292 VMM_INT_DECL(int) GICSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
    1293 {
    1294     LogFlowFunc(("pVM=%p uIntId=%u fAsserted=%RTbool\n",
    1295                  pVM, uIntId, fAsserted));
    1296 
    1297     AssertReturn(uIntId < GIC_SPI_MAX, VERR_INVALID_PARAMETER);
    1298 
    1299     PGIC pGic = VM_TO_GIC(pVM);
    1300 
    1301     /** @todo r=aeichner There must be another way to do this better, maybe create some callback interface
    1302      *                   the GIC can register. */
    1303 #ifdef IN_RING3
    1304     if (pGic->fNemGic)
    1305         return GICR3NemSpiSet(pVM, uIntId, fAsserted);
    1306 #else
    1307 # error "Impossible to call the NEM in-kernel GIC from this context!"
    1308 #endif
    1309 
    1310     PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
    1311     PGICDEV    pThis   = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
    1312 
    1313     int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
    1314     PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
    1315 
    1316     /* Update the interrupts pending state. */
    1317     if (fAsserted)
    1318         ASMAtomicOrU32(&pThis->bmIntPending, RT_BIT_32(uIntId));
    1319     else
    1320         ASMAtomicAndU32(&pThis->bmIntPending, ~RT_BIT_32(uIntId));
    1321 
    1322     int rc = VBOXSTRICTRC_VAL(gicDistUpdateIrqState(pVM, pThis));
    1323     PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
    1324     return rc;
    1325 }
    1326 
    1327 
    1328 /**
    1329  * Sets the specified private peripheral interrupt starting.
    1330  *
    1331  * @returns VBox status code.
    1332  * @param   pVCpu               The cross context virtual CPU structure.
    1333  * @param   uIntId              The PPI ID (minus GIC_INTID_RANGE_PPI_START) to assert/de-assert.
    1334  * @param   fAsserted           Flag whether to mark the interrupt as asserted/de-asserted.
    1335  */
    1336 VMM_INT_DECL(int) GICPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
    1337 {
    1338     LogFlowFunc(("pVCpu=%p{.idCpu=%u} uIntId=%u fAsserted=%RTbool\n",
    1339                  pVCpu, pVCpu->idCpu, uIntId, fAsserted));
    1340 
    1341     PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
    1342 
    1343     /** @todo r=aeichner There must be another way to do this better, maybe create some callback interface
    1344      *                   the GIC can register. */
    1345 #ifdef IN_RING3
    1346     PGIC pGic = VM_TO_GIC(pVCpu->pVMR3);
    1347     if (pGic->fNemGic)
    1348         return GICR3NemPpiSet(pVCpu, uIntId, fAsserted);
    1349 #else
    1350 # error "Impossible to call the NEM in-kernel GIC from this context!"
    1351 #endif
    1352 
    1353     int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
    1354     PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
    1355 
    1356     AssertReturn(uIntId <= (GIC_INTID_RANGE_PPI_LAST - GIC_INTID_RANGE_PPI_START), VERR_INVALID_PARAMETER);
    1357     int rc = gicReDistInterruptSet(pVCpu, uIntId + GIC_INTID_RANGE_PPI_START, fAsserted);
    1358     PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
    1359 
    1360     return rc;
    1361 }
    1362 
    1363 
    1364 /**
    1365  * Sets the specified software generated interrupt starting.
    1366  *
    1367  * @returns VBox status code.
    1368  * @param   pVCpu               The cross context virtual CPU structure.
    1369  * @param   uIntId              The PPI ID (minus GIC_INTID_RANGE_SGI_START) to assert/de-assert.
    1370  * @param   fAsserted           Flag whether to mark the interrupt as asserted/de-asserted.
    1371  */
    1372 VMM_INT_DECL(int) GICSgiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
    1373 {
    1374     LogFlowFunc(("pVCpu=%p{.idCpu=%u} uIntId=%u fAsserted=%RTbool\n",
    1375                  pVCpu, pVCpu->idCpu, uIntId, fAsserted));
    1376 
    1377     PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
    1378 
    1379     /** @todo r=aeichner There must be another way to do this better, maybe create some callback interface
    1380      *                   the GIC can register. */
    1381 #ifdef IN_RING3
    1382     PGIC pGic = VM_TO_GIC(pVCpu->pVMR3);
    1383     /* These should be handled in the kernel and never be set from here. */
    1384     AssertReturn(!pGic->fNemGic, VERR_NEM_IPE_6);
    1385 #else
    1386 # error "Impossible to call the in-kernel GIC from this context!"
    1387 #endif
    1388 
    1389     int const  rcLock  = PDMDevHlpCritSectEnter(pDevIns, pDevIns->pCritSectRoR3, VERR_IGNORED);
    1390     PDM_CRITSECT_RELEASE_ASSERT_RC_DEV(pDevIns, pDevIns->pCritSectRoR3, rcLock);
    1391 
    1392     AssertReturn(uIntId <= (GIC_INTID_RANGE_SGI_LAST - GIC_INTID_RANGE_SGI_START), VERR_INVALID_PARAMETER);
    1393     int rc = gicReDistInterruptSet(pVCpu, uIntId + GIC_INTID_RANGE_SGI_START, fAsserted);
    1394     PDMDevHlpCritSectLeave(pDevIns, pDevIns->pCritSectRoR3);
    1395 
    1396     return rc;
    13971345}
    13981346
    … …  
    16201568};
    16211569
     1570/**
     1571 * The VirtualBox GIC backend.
     1572 */
     1573const PDMGICBACKEND g_GicBackend =
     1574{
     1575    /* .pfnReadSysReg = */  gicReadSysReg,
     1576    /* .pfnWriteSysReg = */ gicWriteSysReg,
     1577    /* .pfnSetSpi = */      gicSetSpi,
     1578    /* .pfnSetPpi = */      gicSetPpi,
     1579};
     1580

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r107113 r107308  
    3737#include <VBox/err.h>
    3838#ifdef VBOX_VMM_TARGET_ARMV8
    39 # include <VBox/vmm/gic.h>
     39# include <VBox/vmm/pdmgic.h>
    4040#else
    4141# include <VBox/vmm/pdmapic.h>
    … …  
    150150#ifdef VBOX_VMM_TARGET_ARMV8
    151151    int rc = VINF_SUCCESS;
    152     GICSpiSet(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
     152    PDMGicSetSpi(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
    153153#else
    154154    int rc = VERR_PDM_NO_PIC_INSTANCE;
    … …  
    207207#ifdef VBOX_VMM_TARGET_ARMV8
    208208    RT_NOREF(uBusDevFn, uTagSrc);
    209     GICSpiSet(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
     209    PDMGicSetSpi(pVM, u8Irq, u8Level == PDM_IRQ_LEVEL_HIGH ? true : false);
    210210    return VINF_SUCCESS;
    211211#else

  • trunk/src/VBox/VMM/VMMAll/PDMAllApic.cpp

    r107118 r107308  
    464464     * Register the backend.
    465465     */
    466     pVM->pdm.s.Ic.enmKind = enmBackendType;
     466    pVM->pdm.s.Ic.u.x86.enmKind = enmBackendType;
    467467#ifdef IN_RING3
    468     pVM->pdm.s.Ic.ApicBackend = *pBackend;
     468    pVM->pdm.s.Ic.u.x86.ApicBackend = *pBackend;
    469469#else
    470     pVM->pdmr0.s.Ic.ApicBackend = *pBackend;
     470    pVM->pdmr0.s.Ic.u.x86.ApicBackend = *pBackend;
    471471#endif
    472472

  • trunk/src/VBox/VMM/VMMR0/PDMR0DevHlp.cpp

    r107113 r107308  
    12131213
    12141214
    1215 /** @interface_method_impl{PDMDEVHLPR0,pfnApicSetUpContext} */
    1216 static DECLCALLBACK(int) pdmR0DevHlp_ApicSetUpContext(PPDMDEVINS pDevIns)
    1217 {
    1218     PDMDEV_ASSERT_DEVINS(pDevIns);
    1219     LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
     1215/** @interface_method_impl{PDMDEVHLPR0,pfnIcSetUpContext} */
     1216static DECLCALLBACK(int) pdmR0DevHlp_IcSetUpContext(PPDMDEVINS pDevIns)
     1217{
     1218    PDMDEV_ASSERT_DEVINS(pDevIns);
     1219    LogFlow(("pdmR0DevHlp_IcSetUpContext: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
    12201220    PGVM pGVM = pDevIns->Internal.s.pGVM;
    12211221
    … …  
    12411241
    12421242    /* set the helper pointer and return. */
    1243     LogFlow(("pdmR0DevHlp_ApicSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
     1243    LogFlow(("pdmR0DevHlp_IcSetUpContext: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
    12441244    return VINF_SUCCESS;
    12451245}
    … …  
    15031503    pdmR0DevHlp_IommuSetUpContext,
    15041504    pdmR0DevHlp_PICSetUpContext,
    1505     pdmR0DevHlp_ApicSetUpContext,
     1505    pdmR0DevHlp_IcSetUpContext,
    15061506    pdmR0DevHlp_IoApicSetUpContext,
    15071507    pdmR0DevHlp_HpetSetUpContext,
    … …  
    16161616    pdmR0DevHlp_IommuSetUpContext,
    16171617    pdmR0DevHlp_PICSetUpContext,
    1618     pdmR0DevHlp_ApicSetUpContext,
     1618    pdmR0DevHlp_IcSetUpContext,
    16191619    pdmR0DevHlp_IoApicSetUpContext,
    16201620    pdmR0DevHlp_HpetSetUpContext,

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r107217 r107308  
    14481448     * Register the APIC with PDM.
    14491449     */
    1450     rc = PDMDevHlpApicRegister(pDevIns);
     1450    rc = PDMDevHlpIcRegister(pDevIns);
    14511451    AssertLogRelRCReturn(rc, rc);
    14521452

  • trunk/src/VBox/VMM/VMMR3/GICR3.cpp

    r106999 r107308  
    3333#include <VBox/log.h>
    3434#include "GICInternal.h"
    35 #include <VBox/vmm/gic.h>
     35#include <VBox/vmm/pdmgic.h>
    3636#include <VBox/vmm/cpum.h>
    3737#include <VBox/vmm/hm.h>
    … …  
    425425     * Register the GIC with PDM.
    426426     */
    427     rc = PDMDevHlpApicRegister(pDevIns);
     427    rc = PDMDevHlpIcRegister(pDevIns);
     428    AssertLogRelRCReturn(rc, rc);
     429
     430    rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
    428431    AssertLogRelRCReturn(rc, rc);
    429432

  • trunk/src/VBox/VMM/VMMR3/GICR3Nem-darwin.cpp

    r105687 r107308  
    3333#include <VBox/log.h>
    3434#include "GICInternal.h"
    35 #include "NEMInternal.h" /* Need access to the VM file descriptor. */
    36 #include <VBox/vmm/gic.h>
     35#include "NEMInternal.h" /* Need access to the VM file descriptor and for GIC API currently implemented in NEM. */
     36#include <VBox/vmm/pdmgic.h>
    3737#include <VBox/vmm/cpum.h>
    3838#include <VBox/vmm/hm.h>
    … …  
    4646
    4747/*********************************************************************************************************************************
    48 *   Defined Constants And Macros                                                                                                 *
    49 *********************************************************************************************************************************/
    50 
    51 
    52 /*********************************************************************************************************************************
    5348*   Structures and Typedefs                                                                                                      *
    5449*********************************************************************************************************************************/
    5550
    5651/**
    57  * GICKvm PDM instance data (per-VM).
     52 * GIC Hypervisor.Framework PDM instance data (per-VM).
    5853 */
    59 typedef struct GICKVMDEV
     54typedef struct GICHVFDEV
    6055{
    6156    /** Pointer to the PDM device instance. */
    6257    PPDMDEVINSR3        pDevIns;
    63 } GICKVMDEV;
     58} GICHVFDEV;
    6459/** Pointer to a GIC KVM device. */
    65 typedef GICKVMDEV *PGICKVMDEV;
     60typedef GICHVFDEV *PGICHVFDEV;
    6661/** Pointer to a const GIC KVM device. */
    67 typedef GICKVMDEV const *PCGICKVMDEV;
    68 
    69 
    70 /*********************************************************************************************************************************
    71 *   Global Variables                                                                                                             *
    72 *********************************************************************************************************************************/
    73 
     62typedef GICHVFDEV const *PCGICHVFDEV;
    7463
    7564
    … …  
    7766 * @interface_method_impl{PDMDEVREG,pfnConstruct}
    7867 */
    79 DECLCALLBACK(int) gicR3NemConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
     68DECLCALLBACK(int) gicR3HvfConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
    8069{
    8170    PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
    82     PGICKVMDEV      pThis    = PDMDEVINS_2_DATA(pDevIns, PGICKVMDEV);
     71    PGICHVFDEV      pThis    = PDMDEVINS_2_DATA(pDevIns, PGICHVFDEV);
    8372    PVM             pVM      = PDMDevHlpGetVM(pDevIns);
    8473    PGIC            pGic     = VM_TO_GIC(pVM);
    … …  
    9180     */
    9281    pGic->pDevInsR3 = pDevIns;
    93     pGic->fNemGic   = true;
    9482    pThis->pDevIns  = pDevIns;
    9583
    … …  
    10391     * Register the GIC with PDM.
    10492     */
    105     rc = PDMDevHlpApicRegister(pDevIns);
     93    rc = PDMDevHlpIcRegister(pDevIns);
     94    AssertLogRelRCReturn(rc, rc);
     95
     96    rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_HVF, &g_GicHvfBackend);
    10697    AssertLogRelRCReturn(rc, rc);
    10798
    … …  
    131122    /* .szRCMod = */                "VMMRC.rc",
    132123    /* .szR0Mod = */                "VMMR0.r0",
    133     /* .pfnConstruct = */           gicR3NemConstruct,
     124    /* .pfnConstruct = */           gicR3HvfConstruct,
    134125    /* .pfnDestruct = */            NULL,
    135126    /* .pfnRelocate = */            NULL,
    … …  
    159150};
    160151
     152
     153/**
     154 * The Hypervisor.Framework GIC backend.
     155 */
     156const PDMGICBACKEND g_GicHvfBackend =
     157{
     158    /* .pfnReadSysReg = */  NEMR3GicReadSysReg,
     159    /* .pfnWriteSysReg = */ NEMR3GicWriteSysReg,
     160    /* .pfnSetSpi = */      NEMR3GicSetSpi,
     161    /* .pfnSetPpi = */      NEMR3GicSetPpi,
     162};
     163
    161164#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
    162165

  • trunk/src/VBox/VMM/VMMR3/GICR3Nem-linux.cpp

    r105687 r107308  
    3434#include "GICInternal.h"
    3535#include "NEMInternal.h" /* Need access to the VM file descriptor. */
    36 #include <VBox/vmm/gic.h>
     36#include <VBox/vmm/pdmgic.h>
    3737#include <VBox/vmm/cpum.h>
    3838#include <VBox/vmm/hm.h>
    … …  
    101101
    102102/**
    103  * Common worker for GICR3KvmSpiSet() and GICR3KvmPpiSet().
     103 * Common worker for gicR3KvmSpiSet() and gicR3KvmPpiSet().
    104104 *
    105105 * @returns VBox status code.
    … …  
    138138 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    139139 */
    140 VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
     140static DECLCALLBACK(int) gicR3KvmSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)
    141141{
    142142    PGIC pGic = VM_TO_GIC(pVM);
    … …  
    157157 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    158158 */
    159 VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
     159static DECLCALLBACK(int) gicR3KvmSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
    160160{
    161161    PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
    162162
    163     return gicR3KvmSetIrq(pDevIns, pVCpu->idCpu, KVM_ARM_IRQ_TYPE_SPI,
     163    return gicR3KvmSetIrq(pDevIns, pVCpu->idCpu, KVM_ARM_IRQ_TYPE_PPI,
    164164                          uIntId + GIC_INTID_RANGE_PPI_START, fAsserted);
    165165}
    … …  
    294294     * Register the GIC with PDM.
    295295     */
    296     rc = PDMDevHlpApicRegister(pDevIns);
     296    rc = PDMDevHlpIcRegister(pDevIns);
     297    AssertLogRelRCReturn(rc, rc);
     298
     299    rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_KVM, &g_GicKvmBackend);
    297300    AssertLogRelRCReturn(rc, rc);
    298301
    … …  
    405408};
    406409
     410/**
     411 * The KVM GIC backend.
     412 */
     413const PDMGICBACKEND g_GicKvmBackend =
     414{
     415    /* .pfnReadSysReg = */  NULL,
     416    /* .pfnWriteSysReg = */ NULL,
     417    /* .pfnSetSpi = */      gicR3KvmSetSpi,
     418    /* .pfnSetPpi = */      gicR3KvmSetPpi,
     419};
     420
    407421#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
    408422

  • trunk/src/VBox/VMM/VMMR3/GICR3Nem-win.cpp

    r106952 r107308  
    3838#include "GICInternal.h"
    3939#include "NEMInternal.h" /* Need access to the partition handle. */
    40 #include <VBox/vmm/gic.h>
     40#include <VBox/vmm/pdmgic.h>
    4141#include <VBox/vmm/cpum.h>
    4242#include <VBox/vmm/hm.h>
    … …  
    7070    WHV_PARTITION_HANDLE hPartition;
    7171} GICHVDEV;
    72 /** Pointer to a GIC KVM device. */
     72/** Pointer to a GIC Hyper-V device. */
    7373typedef GICHVDEV *PGICHVDEV;
    74 /** Pointer to a const GIC KVM device. */
     74/** Pointer to a const GIC Hyper-V device. */
    7575typedef GICHVDEV const *PCGICHVDEV;
    7676
    … …  
    124124
    125125/**
    126  * Common worker for GICR3KvmSpiSet() and GICR3KvmPpiSet().
     126 * Common worker for gicR3HvSetSpi() and gicR3HvSetPpi().
    127127 *
    128128 * @returns VBox status code.
    129  * @param   pDevIns     The PDM KVM GIC device instance.
     129 * @param   pDevIns     The PDM Hyper-V GIC device instance.
    130130 * @param   idCpu       The CPU ID for which the interrupt is updated (only valid for PPIs).
    131131 * @param   fPpi        Flag whether this is a PPI or SPI.
    … …  
    163163
    164164/**
    165  * Sets the given SPI inside the in-kernel KVM GIC.
     165 * Sets the given SPI inside the in-kernel Hyper-V GIC.
    166166 *
    167167 * @returns VBox status code.
    … …  
    170170 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    171171 */
    172 VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
     172static DECLCALLBACK(int) gicR3HvSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)
    173173{
    174174    PGIC pGic = VM_TO_GIC(pVM);
    … …  
    182182
    183183/**
    184  * Sets the given PPI inside the in-kernel KVM GIC.
     184 * Sets the given PPI inside the in-kernel Hyper-V GIC.
    185185 *
    186186 * @returns VBox status code.
    … …  
    189189 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    190190 */
    191 VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
     191static DECLCALLBACK(int) gicR3HvSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
    192192{
    193193    PPDMDEVINS pDevIns = VMCPU_TO_DEVINS(pVCpu);
    … …  
    259259     * Register the GIC with PDM.
    260260     */
    261     rc = PDMDevHlpApicRegister(pDevIns);
     261    rc = PDMDevHlpIcRegister(pDevIns);
     262    AssertLogRelRCReturn(rc, rc);
     263
     264    rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_HYPERV, &g_GicHvBackend);
    262265    AssertLogRelRCReturn(rc, rc);
    263266
    … …  
    331334};
    332335
     336/**
     337 * The Hypervisor.Framework GIC backend.
     338 */
     339const PDMGICBACKEND g_GicHvfBackend =
     340{
     341    /* .pfnReadSysReg = */  NULL,
     342    /* .pfnWriteSysReg = */ NULL,
     343    /* .pfnSetSpi = */      gicR3HvSetSpi,
     344    /* .pfnSetPpi = */      gicR3HvSetPpi,
     345};
     346
    333347#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
    334348

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

    r107132 r107308  
    3939#include <VBox/vmm/iem.h>
    4040#include <VBox/vmm/em.h>
    41 #include <VBox/vmm/gic.h>
     41#include <VBox/vmm/pdmgic.h>
    4242#include <VBox/vmm/pdm.h>
    4343#include <VBox/vmm/dbgftrace.h>
    … …  
    9191typedef enum hv_gic_icc_reg_t : uint16_t
    9292{
    93     HV_GIC_ICC_REG_AP0R0_EL1
     93    HV_GIC_ICC_REG_PMR_EL1,
     94    HV_GIC_ICC_REG_BPR0_EL1,
     95    HV_GIC_ICC_REG_AP0R0_EL1,
     96    HV_GIC_ICC_REG_AP1R0_EL1,
     97    HV_GIC_ICC_REG_RPR_EL1,
     98    HV_GIC_ICC_REG_BPR1_EL1,
     99    HV_GIC_ICC_REG_CTLR_EL1,
     100    HV_GIC_ICC_REG_SRE_EL1,
     101    HV_GIC_ICC_REG_IGRPEN0_EL1,
     102    HV_GIC_ICC_REG_IGRPEN1_EL1,
     103    HV_GIC_ICC_REG_INVALID,
    94104    /** @todo */
    95105} hv_gic_icc_reg_t;
    … …  
    623633    }
    624634    return "";
     635}
     636
     637
     638/**
     639 * Converts an ICC system register into Darwin's Hypervisor.Framework equivalent.
     640 *
     641 * @returns HvF's ICC system register.
     642 * @param   u32Reg      The ARMv8 ICC system register.
     643 */
     644static hv_gic_icc_reg_t nemR3DarwinIccRegFromSysReg(uint32_t u32Reg)
     645{
     646    switch (u32Reg)
     647    {
     648        case ARMV8_AARCH64_SYSREG_ICC_PMR_EL1:      return HV_GIC_ICC_REG_PMR_EL1;
     649        case ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1:     return HV_GIC_ICC_REG_INVALID;
     650        case ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1:    return HV_GIC_ICC_REG_INVALID;
     651        case ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1:   return HV_GIC_ICC_REG_INVALID;
     652        case ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1:     return HV_GIC_ICC_REG_BPR0_EL1;
     653        case ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1:    return HV_GIC_ICC_REG_AP0R0_EL1;
     654        case ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1:    return HV_GIC_ICC_REG_INVALID;
     655        case ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1:    return HV_GIC_ICC_REG_INVALID;
     656        case ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1:    return HV_GIC_ICC_REG_INVALID;
     657        case ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1:    return HV_GIC_ICC_REG_AP1R0_EL1;
     658        case ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1:    return HV_GIC_ICC_REG_INVALID;
     659        case ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1:    return HV_GIC_ICC_REG_INVALID;
     660        case ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1:    return HV_GIC_ICC_REG_INVALID;
     661        case ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1:   return HV_GIC_ICC_REG_INVALID;
     662        case ARMV8_AARCH64_SYSREG_ICC_DIR_EL1:      return HV_GIC_ICC_REG_INVALID;
     663        case ARMV8_AARCH64_SYSREG_ICC_RPR_EL1:      return HV_GIC_ICC_REG_RPR_EL1;
     664        case ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1:    return HV_GIC_ICC_REG_INVALID;
     665        case ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1:   return HV_GIC_ICC_REG_INVALID;
     666        case ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1:    return HV_GIC_ICC_REG_INVALID;
     667        case ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1:     return HV_GIC_ICC_REG_INVALID;
     668        case ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1:    return HV_GIC_ICC_REG_INVALID;
     669        case ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1:   return HV_GIC_ICC_REG_INVALID;
     670        case ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1:     return HV_GIC_ICC_REG_BPR1_EL1;
     671        case ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1:     return HV_GIC_ICC_REG_CTLR_EL1;
     672        case ARMV8_AARCH64_SYSREG_ICC_SRE_EL1:      return HV_GIC_ICC_REG_SRE_EL1;
     673        case ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1:  return HV_GIC_ICC_REG_IGRPEN0_EL1;
     674        case ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1:  return HV_GIC_ICC_REG_IGRPEN1_EL1;
     675    }
     676    AssertReleaseFailed();
     677    return HV_GIC_ICC_REG_INVALID;
    625678}
    626679
    … …  
    11411194
    11421195/**
    1143  * Sets the given SPI inside the in-kernel KVM GIC.
     1196 * Sets the given SPI inside the in-kernel HvF GIC.
    11441197 *
    11451198 * @returns VBox status code.
    … …  
    11481201 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    11491202 */
    1150 VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
     1203VMM_INT_DECL(int) NEMR3GicSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)
    11511204{
    11521205    RT_NOREF(pVM);
    … …  
    11591212
    11601213/**
    1161  * Sets the given PPI inside the in-kernel KVM GIC.
     1214 * Sets the given PPI inside the in-kernel HvF GIC.
    11621215 *
    11631216 * @returns VBox status code.
    1164  * @param   pVCpu       The vCPU for whih the PPI state is updated.
     1217 * @param   pVCpu       The vCPU for which the PPI state is to be updated.
    11651218 * @param   uIntId      The PPI ID to update.
    11661219 * @param   fAsserted   Flag whether the interrupt is asserted (true) or not (false).
    11671220 */
    1168 VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
     1221VMM_INT_DECL(int) NEMR3GicSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
    11691222{
    11701223    RT_NOREF(pVCpu, uIntId, fAsserted);
    … …  
    11731226    AssertFailed();
    11741227    return VERR_NEM_IPE_9;
     1228}
     1229
     1230
     1231/**
     1232 * Writes a system ICC register inside the in-kernel HvF GIC.
     1233 *
     1234 * @returns VBox status code.
     1235 * @param   pVCpu       The cross context virtual CPU structure.
     1236 * @param   u32Reg      The ICC register.
     1237 * @param   u64Value    The value being set.
     1238 */
     1239VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
     1240{
     1241    hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);
     1242    hv_return_t const hrc = hv_gic_set_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, u64Value);
     1243    return nemR3DarwinHvSts2Rc(hrc);
     1244}
     1245
     1246
     1247/**
     1248 * Reads a system ICC register inside the in-kernel HvF GIC.
     1249 *
     1250 * @returns VBox status code.
     1251 * @param   pVCpu       The cross context virtual CPU structure.
     1252 * @param   u32Reg      The ICC register.
     1253 * @param   u64Value    Where to store value.
     1254 */
     1255VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
     1256{
     1257    hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);
     1258    hv_return_t const hrc = hv_gic_get_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, pu64Value);
     1259    return nemR3DarwinHvSts2Rc(hrc);
    11751260}
    11761261
    … …  
    21212206            TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
    21222207            pVCpu->nem.s.fVTimerActivated = true;
    2123             return GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /*fAsserted*/);
     2208            return PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /*fAsserted*/);
    21242209        }
    21252210        default:
    … …  
    22062291        {
    22072292            /* Clear the interrupt. */
    2208             GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /*fAsserted*/);
     2293            PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /*fAsserted*/);
    22092294
    22102295            pVCpu->nem.s.fVTimerActivated = false;

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux-armv8.cpp

    r107026 r107308  
    3535#include <VBox/vmm/iem.h>
    3636#include <VBox/vmm/em.h>
    37 #include <VBox/vmm/gic.h>
     37#include <VBox/vmm/pdmgic.h>
    3838#include <VBox/vmm/pdm.h>
    3939#include <VBox/vmm/trpm.h>
    … …  
    11921192        {
    11931193            TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
    1194             GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, RT_BOOL(pRun->s.regs.device_irq_level & KVM_ARM_DEV_EL1_VTIMER));
     1194            PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, RT_BOOL(pRun->s.regs.device_irq_level & KVM_ARM_DEV_EL1_VTIMER));
    11951195        }
    11961196
    … …  
    11981198        {
    11991199            //TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
    1200             GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, RT_BOOL(pRun->s.regs.device_irq_level & KVM_ARM_DEV_EL1_PTIMER));
     1200            PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, RT_BOOL(pRun->s.regs.device_irq_level & KVM_ARM_DEV_EL1_PTIMER));
    12011201        }
    12021202

  • trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp

    r107215 r107308  
    41864186
    41874187
    4188 /** @interface_method_impl{PDMDEVHLPR3,pfnApicRegister} */
    4189 static DECLCALLBACK(int) pdmR3DevHlp_ApicRegister(PPDMDEVINS pDevIns)
     4188/** @interface_method_impl{PDMDEVHLPR3,pfnIcRegister} */
     4189static DECLCALLBACK(int) pdmR3DevHlp_IcRegister(PPDMDEVINS pDevIns)
    41904190{
    41914191    PDMDEV_ASSERT_DEVINS(pDevIns);
    … …  
    42214221    RTCritSectRwLeaveExcl(&pVM->pdm.s.CoreListCritSectRw);
    42224222
    4223     LogFlow(("pdmR3DevHlp_ApicRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
     4223    LogFlow(("pdmR3DevHlp_IcRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
    42244224    return VINF_SUCCESS;
    42254225}
    … …  
    52755275    pdmR3DevHlp_IommuRegister,
    52765276    pdmR3DevHlp_PICRegister,
    5277     pdmR3DevHlp_ApicRegister,
     5277    pdmR3DevHlp_IcRegister,
    52785278    pdmR3DevHlp_IoApicRegister,
    52795279    pdmR3DevHlp_HpetRegister,
    … …  
    56765676    pdmR3DevHlp_IommuRegister,
    56775677    pdmR3DevHlp_PICRegister,
    5678     pdmR3DevHlp_ApicRegister,
     5678    pdmR3DevHlp_IcRegister,
    56795679    pdmR3DevHlp_IoApicRegister,
    56805680    pdmR3DevHlp_HpetRegister,
    … …  
    64056405    pdmR3DevHlp_IommuRegister,
    64066406    pdmR3DevHlp_PICRegister,
    6407     pdmR3DevHlp_ApicRegister,
     6407    pdmR3DevHlp_IcRegister,
    64086408    pdmR3DevHlp_IoApicRegister,
    64096409    pdmR3DevHlp_HpetRegister,

  • trunk/src/VBox/VMM/VMMR3/PDMDevice.cpp

    r107227 r107308  
    3535#include <VBox/vmm/pdm.h>
    3636#ifdef VBOX_VMM_TARGET_ARMV8
    37 # include <VBox/vmm/gic.h>
     37# include <VBox/vmm/pdmgic.h>
    3838# include <VBox/vmm/pmu.h>
    3939#elif defined(VBOX_VMM_TARGET_X86)

  • trunk/src/VBox/VMM/VMMR3/PMUR3.cpp

    r106479 r107308  
    3333#include <VBox/log.h>
    3434#include "PMUInternal.h"
    35 #include <VBox/vmm/gic.h>
     35#include <VBox/vmm/pdmgic.h>
    3636#include <VBox/vmm/cpum.h>
    3737#include <VBox/vmm/hm.h>

  • trunk/src/VBox/VMM/VMMR3/VMM.cpp

    r107227 r107308  
    131131#include <VBox/vmm/dbgf.h>
    132132#ifdef VBOX_VMM_TARGET_ARMV8
    133 # include <VBox/vmm/gic.h>
     133# include <VBox/vmm/pdmgic.h>
    134134#elif defined(VBOX_VMM_TARGET_X86)
    135135# include <VBox/vmm/pdmapic.h>

  • trunk/src/VBox/VMM/include/GICInternal.h

    r106419 r107308  
    3434#include <VBox/gic.h>
    3535#include <VBox/vmm/pdmdev.h>
     36#include <VBox/vmm/pdmgic.h>
     37#include <VBox/vmm/stam.h>
    3638
    3739
    … …  
    4143 * @{
    4244 */
     45
     46#ifdef VBOX_INCLUDED_vmm_pdmgic_h
     47/** The VirtualBox GIC backend. */
     48extern const PDMGICBACKEND g_GicBackend;
     49# ifdef RT_OS_DARWIN
     50/** The Hypervisor.Framework GIC backend. */
     51extern const PDMGICBACKEND g_GicHvfBackend;
     52# endif
     53#endif
    4354
    4455#define VMCPU_TO_GICCPU(a_pVCpu)             (&(a_pVCpu)->gic.s)
    … …  
    103114    /** The ring-3 device instance. */
    104115    PPDMDEVINSR3                pDevInsR3;
    105     /** Flag whether the in-kernel (KVM/Hyper-V) GIC of the NEM backend is used. */
    106     bool                        fNemGic;
    107116} GIC;
    108117/** Pointer to GIC VM instance data. */

  • trunk/src/VBox/VMM/include/NEMInternal.h

    r107227 r107308  
    710710bool            nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable);
    711711
     712/** GIC API is currently implemented in NEM rather than in GIC. */
     713VMM_INT_DECL(int)          NEMR3GicSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted);
     714VMM_INT_DECL(int)          NEMR3GicSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted);
     715VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value);
     716VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value);
     717
    712718/**
    713719 * Forced flag notification call from VMEmt.h.

  • trunk/src/VBox/VMM/include/PDMInternal.h

    r107115 r107308  
    4848#include <VBox/vmm/pdmcommon.h>
    4949#include <VBox/vmm/pdmtask.h>
    50 #include <VBox/vmm/pdmapic.h>
     50#ifdef VBOX_VMM_TARGET_ARMV8
     51# include <VBox/vmm/pdmgic.h>
     52#else
     53# include <VBox/vmm/pdmapic.h>
     54#endif
    5155#include <VBox/sup.h>
    5256#include <VBox/msi.h>
    … …  
    802806    /** Pointer to the interrupt controller instance - R3 Ptr. */
    803807    PPDMDEVINSR3                       pDevInsR3;
    804 #ifndef VBOX_VMM_TARGET_ARMV8
    805     /** The type of APIC backend. */
    806     PDMAPICBACKENDTYPE                 enmKind;
    807     uint32_t                           uPadding;
    808     /** The APIC backend. */
    809     PDMAPICBACKENDR3                   ApicBackend;
    810 #else
    811     /** @todo The GIC backend. Currently the padding helps keep alignment common
    812      *        between x86 and arm. */
    813     uint8_t                            auPadding[4+4+240];
    814 #endif
     808    union
     809    {
     810#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
     811        struct
     812        {
     813            /** The type of APIC backend. */
     814            PDMAPICBACKENDTYPE         enmKind;
     815            uint32_t                   uPadding;
     816            /** The APIC backend. */
     817            PDMAPICBACKENDR3           ApicBackend;
     818        } x86;
     819#endif
     820#ifdef VBOX_VMM_TARGET_ARMV8
     821        struct
     822        {
     823            /** The type of GIC backend. */
     824            PDMGICBACKENDTYPE          enmKind;
     825            uint32_t                   uPadding;
     826            /** The APIC backend. */
     827            PDMGICBACKENDR3            GicBackend;
     828        } armv8;
     829#endif
     830        uint8_t                        abPadding[256-8];
     831    } u;
    815832} PDMICR3;
    816833AssertCompileSizeAlignment(PDMICR3, 8);
    … …  
    823840    /** Pointer to the interrupt controller instance - R0 Ptr. */
    824841    PPDMDEVINSR0                       pDevInsR0;
    825 #ifndef VBOX_VMM_TARGET_ARMV8
    826     /** The APIC backend. */
    827     PDMAPICBACKENDR0                   ApicBackend;
    828 #else
    829     /** @todo The GIC backend. Currently the padding helps keep alignment common
    830      *        between x86 and arm. */
    831     uint8_t                            auPadding[240];
    832 #endif
     842    union
     843    {
     844#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
     845        struct
     846        {
     847            /** The APIC backend. */
     848            PDMAPICBACKENDR0           ApicBackend;
     849        } x86;
     850#endif
     851        /** Padding to keep alignment common between x86 and arm (there's no ring-0
     852         *  armv8 code. */
     853        uint8_t                        abPadding[256-8];
     854    } u;
    833855} PDMICR0;
    834856AssertCompileSizeAlignment(PDMICR0, 8);
    … …  
    839861typedef struct PDMICRC
    840862{
    841     /** Pointer to the interrupt controller instance - R0 Ptr. */
     863    /** Pointer to the interrupt controller instance - RC Ptr. */
    842864    PPDMDEVINSRC                       pDevInsR0;
    843865    RTRCPTR                            avPadding;
    844 #ifndef VBOX_VMM_TARGET_ARMV8
    845     /** The APIC backend. */
    846     PDMAPICBACKENDRC                   ApicBackend;
    847 #else
    848     /** @todo The GIC backend. Currently the padding helps keep alignment common
    849      *        between x86 and arm. */
    850     uint8_t                            auPadding[232];
    851 #endif
     866    union
     867    {
     868#if defined(VBOX_VMM_TARGET_X86) || defined(VBOX_VMM_TARGET_AGNOSTIC)
     869        struct
     870        {
     871            /** The APIC backend. */
     872            PDMAPICBACKENDRC           ApicBackend;
     873        } x86;
     874#endif
     875        /** Padding to keep alignment common between x86 and arm (there's no ring-context
     876         *  armv8 code. */
     877        uint8_t                        abPadding[256-4-4];
     878    } u;
    852879} PDMICRC;
    853880AssertCompileSizeAlignment(PDMICRC, 8);
    … …  
    17991826 */
    18001827# ifdef IN_RING3
    1801 #  define PDM_TO_APICBACKEND(a_pVM)          (&((a_pVM)->pdm.s.Ic.ApicBackend))
    1802 #  define PDMCPU_TO_APICBACKEND(a_pVCpu)     (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.ApicBackend))
     1828#  define PDM_TO_APICBACKEND(a_pVM)          (&((a_pVM)->pdm.s.Ic.u.x86.ApicBackend))
     1829#  define PDMCPU_TO_APICBACKEND(a_pVCpu)     (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.x86.ApicBackend))
    18031830#else
    1804 #  define PDM_TO_APICBACKEND(a_pVM)          (&((a_pVM)->pdmr0.s.Ic.ApicBackend))
    1805 #  define PDMCPU_TO_APICBACKEND(a_pVCpu)     (&((a_pVCpu)->CTX_SUFF(pVM)->pdmr0.s.Ic.ApicBackend))
     1831#  define PDM_TO_APICBACKEND(a_pVM)          (&((a_pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
     1832#  define PDMCPU_TO_APICBACKEND(a_pVCpu)     (&((a_pVCpu)->CTX_SUFF(pVM)->pdmr0.s.Ic.u.x86.ApicBackend))
    18061833#endif
    18071834#else
    1808 /** @todo GIC backend. */
     1835# ifdef IN_RING3
     1836#  define PDM_TO_GICBACKEND(a_pVM)           (&((a_pVM)->pdm.s.Ic.u.armv8.GicBackend))
     1837#  define PDMCPU_TO_GICBACKEND(a_pVCpu)      (&((a_pVCpu)->CTX_SUFF(pVM)->pdm.s.Ic.u.armv8.GicBackend))
     1838#else
     1839# error "Implement me"
     1840#endif
    18091841#endif
    18101842
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