- Timestamp:
- Jan 28, 2025 8:38:40 AM (3 months ago)
- svn:sync-xref-src-repo-rev:
- 167204
- Location:
- trunk
- Files:
-
- 4 edited
-
include/VBox/gic.h (modified) (3 diffs)
-
src/VBox/VMM/VMMAll/GICAll.cpp (modified) (14 diffs)
-
src/VBox/VMM/VMMR3/GICR3.cpp (modified) (4 diffs)
-
src/VBox/VMM/include/GICInternal.h (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/gic.h
r107929 r107957 212 212 213 213 /** Interrupt Priority Registers, start offset - RW. */ 214 #define GIC_DIST_REG_IPRIORITY n_OFF_START0x0400214 #define GIC_DIST_REG_IPRIORITYRn_OFF_START 0x0400 215 215 /** Interrupt Priority Registers, last offset - RW. */ 216 #define GIC_DIST_REG_IPRIORITY n_OFF_LAST0x07f8216 #define GIC_DIST_REG_IPRIORITYRn_OFF_LAST 0x07f8 217 217 218 218 /** Interrupt Processor Targets Registers, start offset - RO/RW. */ … … 287 287 288 288 /** Interrupt Priority Registers for extended SPI range, start offset - RW. */ 289 #define GIC_DIST_REG_IPRIORITY nE_OFF_START0x2000289 #define GIC_DIST_REG_IPRIORITYRnE_OFF_START 0x2000 290 290 /** Interrupt Priority Registers for extended SPI range, last offset - RW. */ 291 #define GIC_DIST_REG_IPRIORITY nE_OFF_LAST0x23fc291 #define GIC_DIST_REG_IPRIORITYRnE_OFF_LAST 0x23fc 292 292 293 293 /** Interrupt Configuration Registers for extended SPI range, start offset - RW. */ … … 502 502 503 503 /** Interrupt Priority Registers, start offset - RW. */ 504 #define GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START0x0400504 #define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START 0x0400 505 505 /** Interrupt Priority Registers, last offset - RW. */ 506 #define GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_LAST0x041c506 #define GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_LAST 0x041c 507 507 /** Interrupt Priority Registers for extended PPI range, start offset - RW. */ 508 #define GIC_REDIST_SGI_PPI_REG_IPRIORITY nE_OFF_START0x0420508 #define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_START 0x0420 509 509 /** Interrupt Priority Registers for extended PPI range, last offset - RW. */ 510 #define GIC_REDIST_SGI_PPI_REG_IPRIORITY nE_OFF_LAST0x045c510 #define GIC_REDIST_SGI_PPI_REG_IPRIORITYRnE_OFF_LAST 0x045c 511 511 512 512 /** SGI Configuration Register - RW. */ -
trunk/src/VBox/VMM/VMMAll/GICAll.cpp
r107929 r107957 300 300 301 301 /** 302 * Updates the internal IRQ state and sets or clears the appropirate force action flags. 302 * Updates the internal IRQ state and sets or clears the appropriate force action 303 * flags. 303 304 * 304 305 * @returns Strict VBox status code. … … 385 386 { 386 387 VMCPU_ASSERT_EMT(pVCpu); 387 PGICDEV pThis 388 PGICDEV pThis = PDMDEVINS_2_DATA(pDevIns, PGICDEV); 388 389 389 390 if (offReg >= GIC_DIST_REG_IROUTERn_OFF_START && offReg <= GIC_DIST_REG_IROUTERn_OFF_LAST) … … 437 438 AssertReleaseFailed(); 438 439 break; 439 case GIC_DIST_REG_IPRIORITY n_OFF_START:440 case GIC_DIST_REG_IPRIORITY n_OFF_START + 4: /* These are banked for the PEs and access the redistributor. */440 case GIC_DIST_REG_IPRIORITYRn_OFF_START: 441 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 4: /* These are banked for the PEs and access the redistributor. */ 441 442 { 442 443 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu); 443 444 444 445 /* Figure out the register which is written. */ 445 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITY n_OFF_START;446 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITYRn_OFF_START; 446 447 Assert(idxPrio <= RT_ELEMENTS(pThis->abIntPriority) - sizeof(uint32_t)); 447 448 … … 453 454 break; 454 455 } 455 case GIC_DIST_REG_IPRIORITY n_OFF_START + 32: /* Only 32 lines for now. */456 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 32: /* Only 32 lines for now. */ 456 457 { 457 458 /* Figure out the register which is written. */ 458 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITY n_OFF_START - 32;459 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITYRn_OFF_START - 32; 459 460 Assert(idxPrio <= RT_ELEMENTS(pThis->abIntPriority) - sizeof(uint32_t)); 460 461 … … 491 492 break; 492 493 case GIC_DIST_REG_PIDR2_OFF: 493 *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3); 494 Assert(pThis->uArchRev <= GIC_DIST_REG_PIDR2_ARCH_REV_GICV4); 495 *puValue = GIC_DIST_REG_PIDR2_ARCH_REV_SET(pThis->uArchRev); 494 496 break; 495 497 case GIC_DIST_REG_IIDR_OFF: … … 519 521 { 520 522 VMCPU_ASSERT_EMT(pVCpu); RT_NOREF(pVCpu); 521 PGICDEV pThis 522 PVMCC 523 PGICDEV pThis = PDMDEVINS_2_DATA(pDevIns, PGICDEV); 524 PVMCC pVM = PDMDevHlpGetVM(pDevIns); 523 525 524 526 if (offReg >= GIC_DIST_REG_IROUTERn_OFF_START && offReg <= GIC_DIST_REG_IROUTERn_OFF_LAST) … … 586 588 rcStrict = gicDistUpdateIrqState(pVM, pThis); 587 589 break; 588 case GIC_DIST_REG_IPRIORITY n_OFF_START: /* These are banked for the PEs and access the redistributor. */589 case GIC_DIST_REG_IPRIORITY n_OFF_START + 4:590 case GIC_DIST_REG_IPRIORITY n_OFF_START + 8:591 case GIC_DIST_REG_IPRIORITY n_OFF_START + 12:592 case GIC_DIST_REG_IPRIORITY n_OFF_START + 16:593 case GIC_DIST_REG_IPRIORITY n_OFF_START + 20:594 case GIC_DIST_REG_IPRIORITY n_OFF_START + 24:595 case GIC_DIST_REG_IPRIORITY n_OFF_START + 28:590 case GIC_DIST_REG_IPRIORITYRn_OFF_START: /* These are banked for the PEs and access the redistributor. */ 591 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 4: 592 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 8: 593 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 12: 594 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 16: 595 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 20: 596 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 24: 597 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 28: 596 598 { 597 599 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu); 598 600 599 601 /* Figure out the register which is written. */ 600 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITY n_OFF_START;602 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITYRn_OFF_START; 601 603 Assert(idxPrio <= RT_ELEMENTS(pGicVCpu->abIntPriority) - sizeof(uint32_t)); 602 604 for (uint32_t i = idxPrio; i < idxPrio + sizeof(uint32_t); i++) … … 607 609 break; 608 610 } 609 case GIC_DIST_REG_IPRIORITY n_OFF_START + 32: /* Only 32 lines for now. */610 case GIC_DIST_REG_IPRIORITY n_OFF_START + 36:611 case GIC_DIST_REG_IPRIORITY n_OFF_START + 40:612 case GIC_DIST_REG_IPRIORITY n_OFF_START + 44:613 case GIC_DIST_REG_IPRIORITY n_OFF_START + 48:614 case GIC_DIST_REG_IPRIORITY n_OFF_START + 52:615 case GIC_DIST_REG_IPRIORITY n_OFF_START + 56:616 case GIC_DIST_REG_IPRIORITY n_OFF_START + 60:611 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 32: /* Only 32 lines for now. */ 612 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 36: 613 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 40: 614 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 44: 615 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 48: 616 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 52: 617 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 56: 618 case GIC_DIST_REG_IPRIORITYRn_OFF_START + 60: 617 619 { 618 620 /* Figure out the register which is written. */ 619 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITY n_OFF_START - 32;621 uint8_t idxPrio = offReg - GIC_DIST_REG_IPRIORITYRn_OFF_START - 32; 620 622 Assert(idxPrio <= RT_ELEMENTS(pThis->abIntPriority) - sizeof(uint32_t)); 621 623 for (uint32_t i = idxPrio; i < idxPrio + sizeof(uint32_t); i++) … … 686 688 DECLINLINE(VBOXSTRICTRC) gicReDistRegisterRead(PPDMDEVINS pDevIns, PVMCPUCC pVCpu, uint32_t idRedist, uint16_t offReg, uint32_t *puValue) 687 689 { 688 RT_NOREF(pDevIns);690 PGICDEV pThis = PDMDEVINS_2_DATA(pDevIns, PGICDEV); 689 691 690 692 switch (offReg) … … 702 704 break; 703 705 case GIC_REDIST_REG_PIDR2_OFF: 704 *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(GIC_REDIST_REG_PIDR2_ARCH_REV_GICV3); 706 Assert(pThis->uArchRev <= GIC_DIST_REG_PIDR2_ARCH_REV_GICV4); 707 *puValue = GIC_REDIST_REG_PIDR2_ARCH_REV_SET(pThis->uArchRev); 705 708 break; 706 709 default: … … 741 744 *puValue = ASMAtomicReadU32(&pThis->bmIntActive); 742 745 break; 743 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START:744 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 4:745 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 8:746 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 12:747 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 16:748 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 20:749 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 24:750 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 28:746 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START: 747 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 4: 748 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 8: 749 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 12: 750 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 16: 751 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 20: 752 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 24: 753 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 28: 751 754 { 752 755 /* Figure out the register which is written. */ 753 uint8_t idxPrio = offReg - GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START;756 uint8_t idxPrio = offReg - GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START; 754 757 Assert(idxPrio <= RT_ELEMENTS(pThis->abIntPriority) - sizeof(uint32_t)); 755 758 … … 875 878 rcStrict = gicReDistUpdateIrqState(pThis, pVCpu); 876 879 break; 877 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START:878 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 4:879 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 8:880 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 12:881 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 16:882 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 20:883 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 24:884 case GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START + 28:880 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START: 881 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 4: 882 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 8: 883 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 12: 884 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 16: 885 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 20: 886 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 24: 887 case GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START + 28: 885 888 { 886 /* Figure out the register wh ch is written. */887 uint8_t idxPrio = offReg - GIC_REDIST_SGI_PPI_REG_IPRIORITY n_OFF_START;889 /* Figure out the register which is written. */ 890 uint8_t idxPrio = offReg - GIC_REDIST_SGI_PPI_REG_IPRIORITYRn_OFF_START; 888 891 Assert(idxPrio <= RT_ELEMENTS(pThis->abIntPriority) - sizeof(uint32_t)); 889 892 for (uint32_t i = idxPrio; i < idxPrio + sizeof(uint32_t); i++) … … 1416 1419 1417 1420 /* 1418 * Determine the redistributor being targeted. Each redistributor takes GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE bytes 1421 * Determine the redistributor being targeted. Each redistributor takes 1422 * GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE bytes 1419 1423 * and the redistributors are adjacent. 1420 1424 */ … … 1456 1460 1457 1461 /* 1458 * Determine the redistributor being targeted. Each redistributor takes GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE bytes 1462 * Determine the redistributor being targeted. Each redistributor takes 1463 * GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE bytes 1459 1464 * and the redistributors are adjacent. 1460 1465 */ -
trunk/src/VBox/VMM/VMMR3/GICR3.cpp
r107929 r107957 50 50 * Defined Constants And Macros * 51 51 *********************************************************************************************************************************/ 52 /** Some ancient version... */52 /** GIC saved state version. */ 53 53 #define GIC_SAVED_STATE_VERSION 1 54 54 … … 396 396 * Validate GIC settings. 397 397 */ 398 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase|ItsMmioBase|ItLinesNumber", ""); 398 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase|ItsMmioBase" 399 "|ArchRev" 400 "|ArchExtNmi" 401 "|ItLinesNumber", ""); 399 402 400 403 #if 0 … … 407 410 int rc; 408 411 #endif 412 413 /** @devcfgm{gic, ArchRev, uint8_t, 3} 414 * Configures the GIC architecture revision (GICD_PIDR2.ArchRev and 415 * GICR_PIDR2.ArchRev). 416 * 417 * Currently we only support GICv3. */ 418 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3); 419 AssertLogRelRCReturn(rc, rc); 420 if (pGicDev->uArchRev == 3) 421 { /* likely */ } 422 else 423 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS, 424 N_("Configuration error: \"ArchRev\" %u is not supported"), pGicDev->uArchRev); 425 426 /** @devcfgm{gic, ArchExtNmi, bool, false} 427 * Configures whether NMIs are supported (GICD_TYPER.NMI). */ 428 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ArchExtNmi", &pGicDev->fNmi, false); 429 AssertLogRelRCReturn(rc, rc); 430 if ( !pGicDev->fNmi 431 || pGicDev->uArchRev >= 3) 432 { /* likely */ } 433 else 434 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS, 435 N_("Configuration error: \"ArchExtNmi\" requires architecture revision v3 or newer")); 409 436 410 437 /** @devcfgm{gic, ItLinesNumber, uint16_t, 1} … … 413 440 * For the INTID range 32-1023, configures the maximum SPI supported. Valid values 414 441 * are [1, 31] which equates to interrupt IDs [63, 1023]. A value of 0 indicates no 415 * SPIs are supported , we do not allow configuring this value as it's expected most442 * SPIs are supported. We do not allow configuring this value as it's expected most 416 443 * guests would assume support for SPIs. */ 417 444 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "ItLinesNumber", &pGicDev->uItLinesNumber, 1 /* 63 interrupt IDs */); -
trunk/src/VBox/VMM/include/GICInternal.h
r107929 r107957 56 56 #endif 57 57 58 #define VMCPU_TO_GICCPU(a_pVCpu) 59 #define VM_TO_GIC(a_pVM) 60 #define VM_TO_GICDEV(a_pVM) 58 #define VMCPU_TO_GICCPU(a_pVCpu) (&(a_pVCpu)->gic.s) 59 #define VM_TO_GIC(a_pVM) (&(a_pVM)->gic.s) 60 #define VM_TO_GICDEV(a_pVM) CTX_SUFF(VM_TO_GIC(a_pVM)->pGicDev) 61 61 #ifdef IN_RING3 62 62 # define VMCPU_TO_DEVINS(a_pVCpu) ((a_pVCpu)->pVMR3->gic.s.pDevInsR3) … … 105 105 /** @name Configurables. 106 106 * @{ */ 107 /** The GICD_TYPER.ItsLinesNumber bits. */107 /** The maximum SPI supported (GICD_TYPER.ItsLinesNumber). */ 108 108 uint16_t uItLinesNumber; 109 /** The GIC architecture (GICD_PIDR2.ArchRev and GICR_PIDR2.ArchRev). */ 110 uint8_t uArchRev; 111 /** Whether NMIs are supported (GICD_TYPER.NMI). */ 112 bool fNmi; 109 113 /** @} */ 110 114 } GICDEV; … … 172 176 /** The interrupt controller Binary Point Register for Group 1 interrupts. */ 173 177 uint8_t bBinaryPointGrp1; 174 /** The running p oriorities caused by preemption. */178 /** The running priorities caused by preemption. */ 175 179 volatile uint8_t abRunningPriorities[256]; 176 180 /** The index to the current running priority. */
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