Changeset 108267 in vbox
- Timestamp:
- Feb 17, 2025 9:20:49 PM (3 weeks ago)
- svn:sync-xref-src-repo-rev:
- 167592
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 17 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstPython.py
r108207 r108267 3027 3027 'IEM_MC_ADD_LOCAL_S32_TO_EFF_ADDR': (McBlock.parseMcGeneric, True, True, True, ), 3028 3028 'IEM_MC_ADD_LOCAL_S64_TO_EFF_ADDR': (McBlock.parseMcGeneric, True, True, True, ), 3029 'IEM_MC_ADVANCE_ RIP_AND_FINISH':(McBlock.parseMcGeneric, True, True, True, ),3029 'IEM_MC_ADVANCE_PC_AND_FINISH': (McBlock.parseMcGeneric, True, True, True, ), 3030 3030 'IEM_MC_AND_2LOCS_U32': (McBlock.parseMcGeneric, False, False, False, ), 3031 3031 'IEM_MC_AND_ARG_U16': (McBlock.parseMcGeneric, False, False, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllN8vePython.py
r107218 r108267 55 55 'IEM_MC_DEFER_TO_CIMPL_3_RET_THREADED': (None, True, True, True, ), 56 56 57 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16':(None, True, True, True, ),58 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32':(None, True, True, True, ),59 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64':(None, True, True, True, ),60 61 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS':(None, True, True, True, ),62 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS':(None, True, True, True, ),63 'IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS':(None, True, True, True, ),57 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16': (None, True, True, True, ), 58 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32': (None, True, True, True, ), 59 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64': (None, True, True, True, ), 60 61 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16_WITH_FLAGS': (None, True, True, True, ), 62 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32_WITH_FLAGS': (None, True, True, True, ), 63 'IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64_WITH_FLAGS': (None, True, True, True, ), 64 64 65 65 'IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16': (None, True, True, True, ), -
trunk/src/VBox/VMM/VMMAll/IEMAllThrdPython.py
r107218 r108267 1107 1107 self.dParamRefs['u32Disp'][0].sNewName, self.dParamRefs['cbInstr'][0].sNewName, 1108 1108 ]; 1109 # ... and IEM_MC_ADVANCE_ RIP_AND_FINISH into *_THREADED_PCxx[_WITH_FLAGS] ...1109 # ... and IEM_MC_ADVANCE_PC_AND_FINISH into *_THREADED_PCxx[_WITH_FLAGS] ... 1110 1110 elif ( oNewStmt.sName 1111 in ('IEM_MC_ADVANCE_ RIP_AND_FINISH',1111 in ('IEM_MC_ADVANCE_PC_AND_FINISH', 1112 1112 'IEM_MC_REL_JMP_S8_AND_FINISH', 'IEM_MC_REL_JMP_S16_AND_FINISH', 'IEM_MC_REL_JMP_S32_AND_FINISH', 1113 1113 'IEM_MC_SET_RIP_U16_AND_FINISH', 'IEM_MC_SET_RIP_U32_AND_FINISH', 'IEM_MC_SET_RIP_U64_AND_FINISH', … … 1151 1151 1152 1152 # This is making the wrong branch of conditionals break out of the TB. 1153 if (oStmt.sName in ('IEM_MC_ADVANCE_ RIP_AND_FINISH', 'IEM_MC_REL_JMP_S8_AND_FINISH',1153 if (oStmt.sName in ('IEM_MC_ADVANCE_PC_AND_FINISH', 'IEM_MC_REL_JMP_S8_AND_FINISH', 1154 1154 'IEM_MC_REL_JMP_S16_AND_FINISH', 'IEM_MC_REL_JMP_S32_AND_FINISH')): 1155 1155 sExitTbStatus = 'VINF_SUCCESS'; 1156 1156 if self.sVariation in self.kdVariationsWithConditional: 1157 1157 if self.sVariation in self.kdVariationsWithConditionalNoJmp: 1158 if oStmt.sName != 'IEM_MC_ADVANCE_ RIP_AND_FINISH':1158 if oStmt.sName != 'IEM_MC_ADVANCE_PC_AND_FINISH': 1159 1159 sExitTbStatus = 'VINF_IEM_REEXEC_BREAK'; 1160 elif oStmt.sName == 'IEM_MC_ADVANCE_ RIP_AND_FINISH':1160 elif oStmt.sName == 'IEM_MC_ADVANCE_PC_AND_FINISH': 1161 1161 sExitTbStatus = 'VINF_IEM_REEXEC_BREAK'; 1162 1162 oNewStmt.asParams.append(sExitTbStatus); … … 1333 1333 1334 1334 # Several statements have implicit parameters and some have different parameters. 1335 if oStmt.sName in ('IEM_MC_ADVANCE_ RIP_AND_FINISH', 'IEM_MC_REL_JMP_S8_AND_FINISH', 'IEM_MC_REL_JMP_S16_AND_FINISH',1335 if oStmt.sName in ('IEM_MC_ADVANCE_PC_AND_FINISH', 'IEM_MC_REL_JMP_S8_AND_FINISH', 'IEM_MC_REL_JMP_S16_AND_FINISH', 1336 1336 'IEM_MC_REL_JMP_S32_AND_FINISH', 1337 1337 'IEM_MC_REL_CALL_S16_AND_FINISH', 'IEM_MC_REL_CALL_S32_AND_FINISH', … … 2070 2070 2071 2071 kdReturnStmtAnnotations = { 2072 'IEM_MC_ADVANCE_ RIP_AND_FINISH':g_ksFinishAnnotation_Advance,2072 'IEM_MC_ADVANCE_PC_AND_FINISH': g_ksFinishAnnotation_Advance, 2073 2073 'IEM_MC_REL_JMP_S8_AND_FINISH': g_ksFinishAnnotation_RelJmp, 2074 2074 'IEM_MC_REL_JMP_S16_AND_FINISH': g_ksFinishAnnotation_RelJmp, … … 2324 2324 2325 2325 if not iai.McStmt.findStmtByNames(aoStmts, 2326 { 'IEM_MC_ADVANCE_ RIP_AND_FINISH':True,2326 { 'IEM_MC_ADVANCE_PC_AND_FINISH': True, 2327 2327 'IEM_MC_REL_JMP_S8_AND_FINISH': True, 2328 2328 'IEM_MC_REL_JMP_S16_AND_FINISH': True, … … 2729 2729 if not fIsConditional: 2730 2730 aoDecoderStmts.extend(self.emitThreadedCallStmts()); 2731 elif oStmt.sName == 'IEM_MC_ADVANCE_ RIP_AND_FINISH':2731 elif oStmt.sName == 'IEM_MC_ADVANCE_PC_AND_FINISH': 2732 2732 aoDecoderStmts.extend(self.emitThreadedCallStmts('NoJmp', True)); 2733 2733 else: … … 2746 2746 aoDecoderStmts.pop(); 2747 2747 if sBranchAnnotation == g_ksFinishAnnotation_Advance: 2748 assert iai.McStmt.findStmtByNames(aoStmts[iStmt:], {'IEM_MC_ADVANCE_ RIP_AND_FINISH':1,})2748 assert iai.McStmt.findStmtByNames(aoStmts[iStmt:], {'IEM_MC_ADVANCE_PC_AND_FINISH':1,}) 2749 2749 aoDecoderStmts.extend(self.emitThreadedCallStmts('NoJmp', True)); 2750 2750 elif sBranchAnnotation == g_ksFinishAnnotation_RelJmp: -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstCommon-x86.cpp.h
r108204 r108267 902 902 IEM_MC_FETCH_SREG_U16(u16Value, iReg); 903 903 IEM_MC_PUSH_U16(u16Value); 904 IEM_MC_ADVANCE_ RIP_AND_FINISH();904 IEM_MC_ADVANCE_PC_AND_FINISH(); 905 905 IEM_MC_END(); 906 906 break; … … 912 912 IEM_MC_FETCH_SREG_ZX_U32(u32Value, iReg); 913 913 IEM_MC_PUSH_U32_SREG(u32Value); /* Intel CPUs do funny things with this instruction. */ 914 IEM_MC_ADVANCE_ RIP_AND_FINISH();914 IEM_MC_ADVANCE_PC_AND_FINISH(); 915 915 IEM_MC_END(); 916 916 break; … … 922 922 IEM_MC_FETCH_SREG_ZX_U64(u64Value, iReg); 923 923 IEM_MC_PUSH_U64(u64Value); 924 IEM_MC_ADVANCE_ RIP_AND_FINISH();924 IEM_MC_ADVANCE_PC_AND_FINISH(); 925 925 IEM_MC_END(); 926 926 break; -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstCommonBodyMacros-x86.h
r108204 r108267 66 66 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 67 67 } IEM_MC_NATIVE_ENDIF(); \ 68 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \68 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 69 69 IEM_MC_END(); \ 70 70 break; \ … … 90 90 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 91 91 } IEM_MC_NATIVE_ENDIF(); \ 92 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \92 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 93 93 IEM_MC_END(); \ 94 94 break; \ … … 113 113 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 114 114 } IEM_MC_NATIVE_ENDIF(); \ 115 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \115 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 116 116 IEM_MC_END(); \ 117 117 break; \ … … 148 148 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 149 149 } IEM_MC_NATIVE_ENDIF(); \ 150 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \150 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 151 151 IEM_MC_END(); \ 152 152 break; \ … … 174 174 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 175 175 } IEM_MC_NATIVE_ENDIF(); \ 176 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \176 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 177 177 IEM_MC_END(); \ 178 178 break; \ … … 199 199 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 200 200 } IEM_MC_NATIVE_ENDIF(); \ 201 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \201 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 202 202 IEM_MC_END(); \ 203 203 break; \ … … 242 242 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 243 243 } IEM_MC_NATIVE_ENDIF(); \ 244 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \244 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 245 245 IEM_MC_END(); \ 246 246 break; \ … … 266 266 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 267 267 } IEM_MC_NATIVE_ENDIF(); \ 268 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \268 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 269 269 IEM_MC_END(); \ 270 270 break; \ … … 289 289 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 290 290 } IEM_MC_NATIVE_ENDIF(); \ 291 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \291 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 292 292 IEM_MC_END(); \ 293 293 break; \ … … 324 324 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU16, pu16Dst, u16Src, pEFlags); \ 325 325 } IEM_MC_NATIVE_ENDIF(); \ 326 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \326 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 327 327 IEM_MC_END(); \ 328 328 break; \ … … 350 350 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, a_bRm)); \ 351 351 } IEM_MC_NATIVE_ENDIF(); \ 352 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \352 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 353 353 IEM_MC_END(); \ 354 354 break; \ … … 375 375 IEM_MC_CALL_VOID_AIMPL_3(a_fnNormalU64, pu64Dst, u64Src, pEFlags); \ 376 376 } IEM_MC_NATIVE_ENDIF(); \ 377 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \377 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 378 378 IEM_MC_END(); \ 379 379 break; \ -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstOneByte-x86.cpp.h
r108204 r108267 75 75 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 76 76 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 77 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \77 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 78 78 IEM_MC_END(); \ 79 79 } ((void)0) … … 107 107 IEM_MC_COMMIT_EFLAGS_OPT(fEFlagsRet); \ 108 108 } IEM_MC_NATIVE_ENDIF(); \ 109 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \109 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 110 110 IEM_MC_END(); \ 111 111 } \ … … 132 132 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 133 133 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 134 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \134 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 135 135 IEM_MC_END(); \ 136 136 } \ … … 152 152 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bMapInfoDst); \ 153 153 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 154 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \154 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 155 155 IEM_MC_END(); \ 156 156 } \ … … 185 185 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 186 186 } IEM_MC_NATIVE_ENDIF(); \ 187 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \187 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 188 188 IEM_MC_END(); \ 189 189 } \ … … 218 218 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 219 219 } IEM_MC_NATIVE_ENDIF(); \ 220 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \220 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 221 221 IEM_MC_END(); \ 222 222 } \ … … 258 258 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 259 259 } IEM_MC_NATIVE_ENDIF(); \ 260 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \260 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 261 261 IEM_MC_END(); \ 262 262 } \ … … 286 286 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 287 287 } IEM_MC_NATIVE_ENDIF(); \ 288 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \288 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 289 289 IEM_MC_END(); \ 290 290 } \ … … 317 317 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 318 318 } IEM_MC_NATIVE_ENDIF(); \ 319 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \319 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 320 320 IEM_MC_END(); \ 321 321 } \ … … 344 344 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 345 345 } IEM_MC_NATIVE_ENDIF(); \ 346 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \346 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 347 347 IEM_MC_END(); \ 348 348 } \ … … 381 381 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 382 382 } IEM_MC_NATIVE_ENDIF(); \ 383 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \383 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 384 384 IEM_MC_END(); \ 385 385 break; \ … … 405 405 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 406 406 } IEM_MC_NATIVE_ENDIF(); \ 407 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \407 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 408 408 IEM_MC_END(); \ 409 409 break; \ … … 428 428 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 429 429 } IEM_MC_NATIVE_ENDIF(); \ 430 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \430 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 431 431 IEM_MC_END(); \ 432 432 break; \ … … 460 460 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 461 461 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 462 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \462 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 463 463 IEM_MC_END(); \ 464 464 break; \ … … 480 480 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 481 481 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 482 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \482 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 483 483 IEM_MC_END(); \ 484 484 break; \ … … 500 500 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 501 501 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 502 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \502 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 503 503 IEM_MC_END(); \ 504 504 break; \ … … 530 530 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 531 531 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 532 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \532 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 533 533 IEM_MC_END(); \ 534 534 break; \ … … 550 550 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo /* CMP,TEST */); \ 551 551 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 552 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \552 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 553 553 IEM_MC_END(); \ 554 554 break; \ … … 570 570 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 571 571 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 572 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \572 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 573 573 IEM_MC_END(); \ 574 574 break; \ … … 610 610 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 611 611 } IEM_MC_NATIVE_ENDIF(); \ 612 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \612 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 613 613 IEM_MC_END(); \ 614 614 break; \ … … 632 632 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 633 633 } IEM_MC_NATIVE_ENDIF(); \ 634 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \634 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 635 635 IEM_MC_END(); \ 636 636 break; \ … … 654 654 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 655 655 } IEM_MC_NATIVE_ENDIF(); \ 656 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \656 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 657 657 IEM_MC_END(); \ 658 658 break; \ … … 694 694 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 695 695 } IEM_MC_NATIVE_ENDIF(); \ 696 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \696 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 697 697 IEM_MC_END(); \ 698 698 break; \ … … 722 722 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 723 723 } IEM_MC_NATIVE_ENDIF(); \ 724 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \724 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 725 725 IEM_MC_END(); \ 726 726 break; \ … … 750 750 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 751 751 } IEM_MC_NATIVE_ENDIF(); \ 752 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \752 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 753 753 IEM_MC_END(); \ 754 754 break; \ … … 790 790 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 791 791 } IEM_MC_NATIVE_ENDIF(); \ 792 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \792 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 793 793 IEM_MC_END() 794 794 … … 821 821 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 822 822 } IEM_MC_NATIVE_ENDIF(); \ 823 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \823 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 824 824 IEM_MC_END(); \ 825 825 } \ … … 847 847 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 848 848 } IEM_MC_NATIVE_ENDIF(); \ 849 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \849 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 850 850 IEM_MC_END(); \ 851 851 } \ … … 872 872 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 873 873 } IEM_MC_NATIVE_ENDIF(); \ 874 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \874 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 875 875 IEM_MC_END(); \ 876 876 } \ … … 907 907 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 908 908 } IEM_MC_NATIVE_ENDIF(); \ 909 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \909 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 910 910 IEM_MC_END(); \ 911 911 } \ … … 931 931 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 932 932 } IEM_MC_NATIVE_ENDIF(); \ 933 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \933 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 934 934 IEM_MC_END(); \ 935 935 } \ … … 955 955 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 956 956 } IEM_MC_NATIVE_ENDIF(); \ 957 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \957 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 958 958 IEM_MC_END(); \ 959 959 } \ … … 1627 1627 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1628 1628 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1629 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1629 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1630 1630 IEM_MC_END(); \ 1631 1631 break; \ … … 1639 1639 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1640 1640 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1641 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1641 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1642 1642 IEM_MC_END(); \ 1643 1643 break; \ … … 1651 1651 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1652 1652 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1653 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1653 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1654 1654 IEM_MC_END(); \ 1655 1655 break; \ … … 1965 1965 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 1966 1966 } IEM_MC_NATIVE_ENDIF(); \ 1967 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1967 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1968 1968 IEM_MC_END(); \ 1969 1969 break; \ … … 1987 1987 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 1988 1988 } IEM_MC_NATIVE_ENDIF(); \ 1989 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1989 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1990 1990 IEM_MC_END(); \ 1991 1991 break; \ … … 2009 2009 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2010 2010 } IEM_MC_NATIVE_ENDIF(); \ 2011 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2011 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2012 2012 IEM_MC_END(); \ 2013 2013 break; \ … … 2043 2043 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2044 2044 } IEM_MC_NATIVE_ENDIF(); \ 2045 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2045 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2046 2046 IEM_MC_END(); \ 2047 2047 break; \ … … 2067 2067 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2068 2068 } IEM_MC_NATIVE_ENDIF(); \ 2069 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2069 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2070 2070 IEM_MC_END(); \ 2071 2071 break; \ … … 2091 2091 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2092 2092 } IEM_MC_NATIVE_ENDIF(); \ 2093 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2093 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2094 2094 IEM_MC_END(); \ 2095 2095 break; \ … … 2254 2254 IEM_MC_REF_EFLAGS(pEFlags); \ 2255 2255 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 2256 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2256 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2257 2257 IEM_MC_END(); \ 2258 2258 break; \ … … 2267 2267 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 2268 2268 IEM_MC_CLEAR_HIGH_GREG_U64(a_iReg); \ 2269 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2269 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2270 2270 IEM_MC_END(); \ 2271 2271 break; \ … … 2695 2695 IEM_MC_FETCH_GREG_U16(u16Value, iReg); 2696 2696 IEM_MC_PUSH_U16(u16Value); 2697 IEM_MC_ADVANCE_ RIP_AND_FINISH();2697 IEM_MC_ADVANCE_PC_AND_FINISH(); 2698 2698 IEM_MC_END(); 2699 2699 break; … … 2705 2705 IEM_MC_FETCH_GREG_U32(u32Value, iReg); 2706 2706 IEM_MC_PUSH_U32(u32Value); 2707 IEM_MC_ADVANCE_ RIP_AND_FINISH();2707 IEM_MC_ADVANCE_PC_AND_FINISH(); 2708 2708 IEM_MC_END(); 2709 2709 break; … … 2715 2715 IEM_MC_FETCH_GREG_U64(u64Value, iReg); 2716 2716 IEM_MC_PUSH_U64(u64Value); 2717 IEM_MC_ADVANCE_ RIP_AND_FINISH();2717 IEM_MC_ADVANCE_PC_AND_FINISH(); 2718 2718 IEM_MC_END(); 2719 2719 break; … … 2780 2780 IEM_MC_SUB_LOCAL_U16(u16Value, 2); 2781 2781 IEM_MC_PUSH_U16(u16Value); 2782 IEM_MC_ADVANCE_ RIP_AND_FINISH();2782 IEM_MC_ADVANCE_PC_AND_FINISH(); 2783 2783 IEM_MC_END(); 2784 2784 } … … 2833 2833 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2834 2834 IEM_MC_POP_GREG_U16(iReg); 2835 IEM_MC_ADVANCE_ RIP_AND_FINISH();2835 IEM_MC_ADVANCE_PC_AND_FINISH(); 2836 2836 IEM_MC_END(); 2837 2837 break; … … 2841 2841 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2842 2842 IEM_MC_POP_GREG_U32(iReg); 2843 IEM_MC_ADVANCE_ RIP_AND_FINISH();2843 IEM_MC_ADVANCE_PC_AND_FINISH(); 2844 2844 IEM_MC_END(); 2845 2845 break; … … 2849 2849 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2850 2850 IEM_MC_POP_GREG_U64(iReg); 2851 IEM_MC_ADVANCE_ RIP_AND_FINISH();2851 IEM_MC_ADVANCE_PC_AND_FINISH(); 2852 2852 IEM_MC_END(); 2853 2853 break; … … 3158 3158 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3159 3159 3160 IEM_MC_ADVANCE_ RIP_AND_FINISH();3160 IEM_MC_ADVANCE_PC_AND_FINISH(); 3161 3161 IEM_MC_END(); 3162 3162 } … … 3179 3179 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); 3180 3180 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3181 IEM_MC_ADVANCE_ RIP_AND_FINISH();3181 IEM_MC_ADVANCE_PC_AND_FINISH(); 3182 3182 IEM_MC_END(); 3183 3183 } … … 3210 3210 IEM_MC_FETCH_GREG_U32_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 3211 3211 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 3212 IEM_MC_ADVANCE_ RIP_AND_FINISH();3212 IEM_MC_ADVANCE_PC_AND_FINISH(); 3213 3213 IEM_MC_END(); 3214 3214 } … … 3225 3225 IEM_MC_FETCH_MEM_U32_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 3226 3226 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 3227 IEM_MC_ADVANCE_ RIP_AND_FINISH();3227 IEM_MC_ADVANCE_PC_AND_FINISH(); 3228 3228 IEM_MC_END(); 3229 3229 } … … 3341 3341 IEM_MC_LOCAL_CONST(uint16_t, u16Value, u16Imm); 3342 3342 IEM_MC_PUSH_U16(u16Value); 3343 IEM_MC_ADVANCE_ RIP_AND_FINISH();3343 IEM_MC_ADVANCE_PC_AND_FINISH(); 3344 3344 IEM_MC_END(); 3345 3345 break; … … 3351 3351 IEM_MC_LOCAL_CONST(uint32_t, u32Value, u32Imm); 3352 3352 IEM_MC_PUSH_U32(u32Value); 3353 IEM_MC_ADVANCE_ RIP_AND_FINISH();3353 IEM_MC_ADVANCE_PC_AND_FINISH(); 3354 3354 IEM_MC_END(); 3355 3355 break; … … 3361 3361 IEM_MC_LOCAL_CONST(uint64_t, u64Value, u64Imm); 3362 3362 IEM_MC_PUSH_U64(u64Value); 3363 IEM_MC_ADVANCE_ RIP_AND_FINISH();3363 IEM_MC_ADVANCE_PC_AND_FINISH(); 3364 3364 IEM_MC_END(); 3365 3365 break; … … 3402 3402 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3403 3403 3404 IEM_MC_ADVANCE_ RIP_AND_FINISH();3404 IEM_MC_ADVANCE_PC_AND_FINISH(); 3405 3405 IEM_MC_END(); 3406 3406 } … … 3425 3425 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3426 3426 3427 IEM_MC_ADVANCE_ RIP_AND_FINISH();3427 IEM_MC_ADVANCE_PC_AND_FINISH(); 3428 3428 IEM_MC_END(); 3429 3429 } … … 3450 3450 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3451 3451 3452 IEM_MC_ADVANCE_ RIP_AND_FINISH();3452 IEM_MC_ADVANCE_PC_AND_FINISH(); 3453 3453 IEM_MC_END(); 3454 3454 } … … 3473 3473 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3474 3474 3475 IEM_MC_ADVANCE_ RIP_AND_FINISH();3475 IEM_MC_ADVANCE_PC_AND_FINISH(); 3476 3476 IEM_MC_END(); 3477 3477 } … … 3498 3498 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3499 3499 3500 IEM_MC_ADVANCE_ RIP_AND_FINISH();3500 IEM_MC_ADVANCE_PC_AND_FINISH(); 3501 3501 IEM_MC_END(); 3502 3502 } … … 3521 3521 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3522 3522 3523 IEM_MC_ADVANCE_ RIP_AND_FINISH();3523 IEM_MC_ADVANCE_PC_AND_FINISH(); 3524 3524 IEM_MC_END(); 3525 3525 } … … 3549 3549 IEM_MC_LOCAL_CONST(uint16_t, uValue, (int16_t)i8Imm); 3550 3550 IEM_MC_PUSH_U16(uValue); 3551 IEM_MC_ADVANCE_ RIP_AND_FINISH();3551 IEM_MC_ADVANCE_PC_AND_FINISH(); 3552 3552 IEM_MC_END(); 3553 3553 break; … … 3557 3557 IEM_MC_LOCAL_CONST(uint32_t, uValue, (int32_t)i8Imm); 3558 3558 IEM_MC_PUSH_U32(uValue); 3559 IEM_MC_ADVANCE_ RIP_AND_FINISH();3559 IEM_MC_ADVANCE_PC_AND_FINISH(); 3560 3560 IEM_MC_END(); 3561 3561 break; … … 3565 3565 IEM_MC_LOCAL_CONST(uint64_t, uValue, (int64_t)i8Imm); 3566 3566 IEM_MC_PUSH_U64(uValue); 3567 IEM_MC_ADVANCE_ RIP_AND_FINISH();3567 IEM_MC_ADVANCE_PC_AND_FINISH(); 3568 3568 IEM_MC_END(); 3569 3569 break; … … 3606 3606 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3607 3607 3608 IEM_MC_ADVANCE_ RIP_AND_FINISH();3608 IEM_MC_ADVANCE_PC_AND_FINISH(); 3609 3609 IEM_MC_END(); 3610 3610 } … … 3630 3630 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3631 3631 3632 IEM_MC_ADVANCE_ RIP_AND_FINISH();3632 IEM_MC_ADVANCE_PC_AND_FINISH(); 3633 3633 IEM_MC_END(); 3634 3634 } … … 3655 3655 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3656 3656 3657 IEM_MC_ADVANCE_ RIP_AND_FINISH();3657 IEM_MC_ADVANCE_PC_AND_FINISH(); 3658 3658 IEM_MC_END(); 3659 3659 } … … 3678 3678 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3679 3679 3680 IEM_MC_ADVANCE_ RIP_AND_FINISH();3680 IEM_MC_ADVANCE_PC_AND_FINISH(); 3681 3681 IEM_MC_END(); 3682 3682 } … … 3703 3703 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3704 3704 3705 IEM_MC_ADVANCE_ RIP_AND_FINISH();3705 IEM_MC_ADVANCE_PC_AND_FINISH(); 3706 3706 IEM_MC_END(); 3707 3707 } … … 3726 3726 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3727 3727 3728 IEM_MC_ADVANCE_ RIP_AND_FINISH();3728 IEM_MC_ADVANCE_PC_AND_FINISH(); 3729 3729 IEM_MC_END(); 3730 3730 } … … 4074 4074 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4075 4075 } IEM_MC_ELSE() { 4076 IEM_MC_ADVANCE_ RIP_AND_FINISH();4076 IEM_MC_ADVANCE_PC_AND_FINISH(); 4077 4077 } IEM_MC_ENDIF(); 4078 4078 IEM_MC_END(); … … 4093 4093 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4094 4094 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) { 4095 IEM_MC_ADVANCE_ RIP_AND_FINISH();4095 IEM_MC_ADVANCE_PC_AND_FINISH(); 4096 4096 } IEM_MC_ELSE() { 4097 4097 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4115 4115 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4116 4116 } IEM_MC_ELSE() { 4117 IEM_MC_ADVANCE_ RIP_AND_FINISH();4117 IEM_MC_ADVANCE_PC_AND_FINISH(); 4118 4118 } IEM_MC_ENDIF(); 4119 4119 IEM_MC_END(); … … 4134 4134 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4135 4135 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) { 4136 IEM_MC_ADVANCE_ RIP_AND_FINISH();4136 IEM_MC_ADVANCE_PC_AND_FINISH(); 4137 4137 } IEM_MC_ELSE() { 4138 4138 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4157 4157 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4158 4158 } IEM_MC_ELSE() { 4159 IEM_MC_ADVANCE_ RIP_AND_FINISH();4159 IEM_MC_ADVANCE_PC_AND_FINISH(); 4160 4160 } IEM_MC_ENDIF(); 4161 4161 IEM_MC_END(); … … 4176 4176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4177 4177 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) { 4178 IEM_MC_ADVANCE_ RIP_AND_FINISH();4178 IEM_MC_ADVANCE_PC_AND_FINISH(); 4179 4179 } IEM_MC_ELSE() { 4180 4180 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4199 4199 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4200 4200 } IEM_MC_ELSE() { 4201 IEM_MC_ADVANCE_ RIP_AND_FINISH();4201 IEM_MC_ADVANCE_PC_AND_FINISH(); 4202 4202 } IEM_MC_ENDIF(); 4203 4203 IEM_MC_END(); … … 4218 4218 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4219 4219 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 4220 IEM_MC_ADVANCE_ RIP_AND_FINISH();4220 IEM_MC_ADVANCE_PC_AND_FINISH(); 4221 4221 } IEM_MC_ELSE() { 4222 4222 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4241 4241 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4242 4242 } IEM_MC_ELSE() { 4243 IEM_MC_ADVANCE_ RIP_AND_FINISH();4243 IEM_MC_ADVANCE_PC_AND_FINISH(); 4244 4244 } IEM_MC_ENDIF(); 4245 4245 IEM_MC_END(); … … 4260 4260 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4261 4261 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) { 4262 IEM_MC_ADVANCE_ RIP_AND_FINISH();4262 IEM_MC_ADVANCE_PC_AND_FINISH(); 4263 4263 } IEM_MC_ELSE() { 4264 4264 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4283 4283 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4284 4284 } IEM_MC_ELSE() { 4285 IEM_MC_ADVANCE_ RIP_AND_FINISH();4285 IEM_MC_ADVANCE_PC_AND_FINISH(); 4286 4286 } IEM_MC_ENDIF(); 4287 4287 IEM_MC_END(); … … 4302 4302 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4303 4303 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) { 4304 IEM_MC_ADVANCE_ RIP_AND_FINISH();4304 IEM_MC_ADVANCE_PC_AND_FINISH(); 4305 4305 } IEM_MC_ELSE() { 4306 4306 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4325 4325 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4326 4326 } IEM_MC_ELSE() { 4327 IEM_MC_ADVANCE_ RIP_AND_FINISH();4327 IEM_MC_ADVANCE_PC_AND_FINISH(); 4328 4328 } IEM_MC_ENDIF(); 4329 4329 IEM_MC_END(); … … 4344 4344 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4345 4345 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 4346 IEM_MC_ADVANCE_ RIP_AND_FINISH();4346 IEM_MC_ADVANCE_PC_AND_FINISH(); 4347 4347 } IEM_MC_ELSE() { 4348 4348 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4367 4367 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4368 4368 } IEM_MC_ELSE() { 4369 IEM_MC_ADVANCE_ RIP_AND_FINISH();4369 IEM_MC_ADVANCE_PC_AND_FINISH(); 4370 4370 } IEM_MC_ENDIF(); 4371 4371 IEM_MC_END(); … … 4386 4386 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4387 4387 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 4388 IEM_MC_ADVANCE_ RIP_AND_FINISH();4388 IEM_MC_ADVANCE_PC_AND_FINISH(); 4389 4389 } IEM_MC_ELSE() { 4390 4390 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4420 4420 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4421 4421 } IEM_MC_NATIVE_ENDIF(); \ 4422 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4422 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4423 4423 IEM_MC_END(); \ 4424 4424 } \ … … 4443 4443 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4444 4444 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4445 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4445 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4446 4446 IEM_MC_END(); \ 4447 4447 } \ … … 4463 4463 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4464 4464 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4465 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4465 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4466 4466 IEM_MC_END(); \ 4467 4467 } \ … … 4490 4490 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4491 4491 } IEM_MC_NATIVE_ENDIF(); \ 4492 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4492 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4493 4493 IEM_MC_END(); \ 4494 4494 } \ … … 4519 4519 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4520 4520 } IEM_MC_NATIVE_ENDIF(); \ 4521 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4521 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4522 4522 IEM_MC_END(); \ 4523 4523 } \ … … 4679 4679 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4680 4680 } IEM_MC_NATIVE_ENDIF(); \ 4681 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4681 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4682 4682 IEM_MC_END(); \ 4683 4683 break; \ … … 4706 4706 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4707 4707 } IEM_MC_NATIVE_ENDIF(); \ 4708 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4708 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4709 4709 IEM_MC_END(); \ 4710 4710 break; \ … … 4732 4732 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4733 4733 } IEM_MC_NATIVE_ENDIF(); \ 4734 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4734 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4735 4735 IEM_MC_END(); \ 4736 4736 break; \ … … 4766 4766 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4767 4767 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4768 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4768 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4769 4769 IEM_MC_END(); \ 4770 4770 break; \ … … 4790 4790 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4791 4791 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4792 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4792 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4793 4793 IEM_MC_END(); \ 4794 4794 break; \ … … 4815 4815 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4816 4816 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4817 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4817 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4818 4818 IEM_MC_END(); \ 4819 4819 break; \ … … 4846 4846 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4847 4847 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4848 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4848 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4849 4849 IEM_MC_END(); \ 4850 4850 break; \ … … 4870 4870 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4871 4871 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4872 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4872 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4873 4873 IEM_MC_END(); \ 4874 4874 break; \ … … 4894 4894 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4895 4895 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4896 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4896 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4897 4897 IEM_MC_END(); \ 4898 4898 break; \ … … 4932 4932 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4933 4933 } IEM_MC_NATIVE_ENDIF(); \ 4934 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4934 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4935 4935 IEM_MC_END(); \ 4936 4936 break; \ … … 4957 4957 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4958 4958 } IEM_MC_NATIVE_ENDIF(); \ 4959 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4959 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4960 4960 IEM_MC_END(); \ 4961 4961 break; \ … … 4982 4982 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4983 4983 } IEM_MC_NATIVE_ENDIF(); \ 4984 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4984 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4985 4985 IEM_MC_END(); \ 4986 4986 break; \ … … 5020 5020 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5021 5021 } IEM_MC_NATIVE_ENDIF(); \ 5022 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5022 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5023 5023 IEM_MC_END(); \ 5024 5024 break; \ … … 5048 5048 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5049 5049 } IEM_MC_NATIVE_ENDIF(); \ 5050 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5050 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5051 5051 IEM_MC_END(); \ 5052 5052 break; \ … … 5076 5076 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5077 5077 } IEM_MC_NATIVE_ENDIF(); \ 5078 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5078 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5079 5079 IEM_MC_END(); \ 5080 5080 break; \ … … 5254 5254 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5255 5255 } IEM_MC_NATIVE_ENDIF(); \ 5256 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5256 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5257 5257 IEM_MC_END(); \ 5258 5258 break; \ … … 5278 5278 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5279 5279 } IEM_MC_NATIVE_ENDIF(); \ 5280 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5280 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5281 5281 IEM_MC_END(); \ 5282 5282 break; \ … … 5301 5301 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5302 5302 } IEM_MC_NATIVE_ENDIF(); \ 5303 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5303 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5304 5304 IEM_MC_END(); \ 5305 5305 break; \ … … 5335 5335 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5336 5336 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5337 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5337 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5338 5338 IEM_MC_END(); \ 5339 5339 break; \ … … 5357 5357 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5358 5358 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5359 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5359 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5360 5360 IEM_MC_END(); \ 5361 5361 break; \ … … 5379 5379 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5380 5380 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5381 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5381 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5382 5382 IEM_MC_END(); \ 5383 5383 break; \ … … 5408 5408 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5409 5409 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5410 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5410 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5411 5411 IEM_MC_END(); \ 5412 5412 break; \ … … 5430 5430 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5431 5431 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5432 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5432 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5433 5433 IEM_MC_END(); \ 5434 5434 break; \ … … 5452 5452 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5453 5453 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5454 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5454 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5455 5455 IEM_MC_END(); \ 5456 5456 break; \ … … 5489 5489 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5490 5490 } IEM_MC_NATIVE_ENDIF(); \ 5491 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5491 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5492 5492 IEM_MC_END(); \ 5493 5493 break; \ … … 5510 5510 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5511 5511 } IEM_MC_NATIVE_ENDIF(); \ 5512 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5512 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5513 5513 IEM_MC_END(); \ 5514 5514 break; \ … … 5531 5531 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5532 5532 } IEM_MC_NATIVE_ENDIF(); \ 5533 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5533 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5534 5534 IEM_MC_END(); \ 5535 5535 break; \ … … 5569 5569 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5570 5570 } IEM_MC_NATIVE_ENDIF(); \ 5571 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5571 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5572 5572 IEM_MC_END(); \ 5573 5573 break; \ … … 5595 5595 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5596 5596 } IEM_MC_NATIVE_ENDIF(); \ 5597 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5597 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5598 5598 IEM_MC_END(); \ 5599 5599 break; \ … … 5621 5621 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5622 5622 } IEM_MC_NATIVE_ENDIF(); \ 5623 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5623 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5624 5624 IEM_MC_END(); \ 5625 5625 break; \ … … 5789 5789 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5790 5790 } IEM_MC_NATIVE_ENDIF(); 5791 IEM_MC_ADVANCE_ RIP_AND_FINISH();5791 IEM_MC_ADVANCE_PC_AND_FINISH(); 5792 5792 IEM_MC_END(); 5793 5793 } … … 5833 5833 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5834 5834 } IEM_MC_NATIVE_ENDIF(); 5835 IEM_MC_ADVANCE_ RIP_AND_FINISH();5835 IEM_MC_ADVANCE_PC_AND_FINISH(); 5836 5836 IEM_MC_END(); 5837 5837 break; … … 5853 5853 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5854 5854 } IEM_MC_NATIVE_ENDIF(); 5855 IEM_MC_ADVANCE_ RIP_AND_FINISH();5855 IEM_MC_ADVANCE_PC_AND_FINISH(); 5856 5856 IEM_MC_END(); 5857 5857 break; … … 5873 5873 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5874 5874 } IEM_MC_NATIVE_ENDIF(); 5875 IEM_MC_ADVANCE_ RIP_AND_FINISH();5875 IEM_MC_ADVANCE_PC_AND_FINISH(); 5876 5876 IEM_MC_END(); 5877 5877 break; … … 5908 5908 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5909 5909 5910 IEM_MC_ADVANCE_ RIP_AND_FINISH();5910 IEM_MC_ADVANCE_PC_AND_FINISH(); 5911 5911 IEM_MC_END(); 5912 5912 } … … 5932 5932 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 5933 5933 \ 5934 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5934 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5935 5935 IEM_MC_END() 5936 5936 … … 5973 5973 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5974 5974 5975 IEM_MC_ADVANCE_ RIP_AND_FINISH();5975 IEM_MC_ADVANCE_PC_AND_FINISH(); 5976 5976 IEM_MC_END(); 5977 5977 break; … … 5988 5988 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5989 5989 5990 IEM_MC_ADVANCE_ RIP_AND_FINISH();5990 IEM_MC_ADVANCE_PC_AND_FINISH(); 5991 5991 IEM_MC_END(); 5992 5992 break; … … 6003 6003 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 6004 6004 6005 IEM_MC_ADVANCE_ RIP_AND_FINISH();6005 IEM_MC_ADVANCE_PC_AND_FINISH(); 6006 6006 IEM_MC_END(); 6007 6007 break; … … 6035 6035 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6036 6036 \ 6037 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6037 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6038 6038 IEM_MC_END(); \ 6039 6039 break; \ … … 6055 6055 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6056 6056 \ 6057 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6057 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6058 6058 IEM_MC_END(); \ 6059 6059 break; \ … … 6075 6075 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6076 6076 \ 6077 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6077 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6078 6078 IEM_MC_END(); \ 6079 6079 break; \ … … 6114 6114 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6115 6115 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, bRm), u8Value); 6116 IEM_MC_ADVANCE_ RIP_AND_FINISH();6116 IEM_MC_ADVANCE_PC_AND_FINISH(); 6117 6117 IEM_MC_END(); 6118 6118 } … … 6129 6129 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6130 6130 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Value); 6131 IEM_MC_ADVANCE_ RIP_AND_FINISH();6131 IEM_MC_ADVANCE_PC_AND_FINISH(); 6132 6132 IEM_MC_END(); 6133 6133 } … … 6157 6157 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6158 6158 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, bRm), u16Value); 6159 IEM_MC_ADVANCE_ RIP_AND_FINISH();6159 IEM_MC_ADVANCE_PC_AND_FINISH(); 6160 6160 IEM_MC_END(); 6161 6161 break; … … 6167 6167 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6168 6168 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Value); 6169 IEM_MC_ADVANCE_ RIP_AND_FINISH();6169 IEM_MC_ADVANCE_PC_AND_FINISH(); 6170 6170 IEM_MC_END(); 6171 6171 break; … … 6177 6177 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6178 6178 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Value); 6179 IEM_MC_ADVANCE_ RIP_AND_FINISH();6179 IEM_MC_ADVANCE_PC_AND_FINISH(); 6180 6180 IEM_MC_END(); 6181 6181 break; … … 6199 6199 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6200 6200 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value); 6201 IEM_MC_ADVANCE_ RIP_AND_FINISH();6201 IEM_MC_ADVANCE_PC_AND_FINISH(); 6202 6202 IEM_MC_END(); 6203 6203 break; … … 6211 6211 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6212 6212 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value); 6213 IEM_MC_ADVANCE_ RIP_AND_FINISH();6213 IEM_MC_ADVANCE_PC_AND_FINISH(); 6214 6214 IEM_MC_END(); 6215 6215 break; … … 6223 6223 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6224 6224 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value); 6225 IEM_MC_ADVANCE_ RIP_AND_FINISH();6225 IEM_MC_ADVANCE_PC_AND_FINISH(); 6226 6226 IEM_MC_END(); 6227 6227 break; … … 6252 6252 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6253 6253 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), u8Value); 6254 IEM_MC_ADVANCE_ RIP_AND_FINISH();6254 IEM_MC_ADVANCE_PC_AND_FINISH(); 6255 6255 IEM_MC_END(); 6256 6256 } … … 6267 6267 IEM_MC_FETCH_MEM_U8(u8Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6268 6268 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), u8Value); 6269 IEM_MC_ADVANCE_ RIP_AND_FINISH();6269 IEM_MC_ADVANCE_PC_AND_FINISH(); 6270 6270 IEM_MC_END(); 6271 6271 } … … 6295 6295 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6296 6296 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 6297 IEM_MC_ADVANCE_ RIP_AND_FINISH();6297 IEM_MC_ADVANCE_PC_AND_FINISH(); 6298 6298 IEM_MC_END(); 6299 6299 break; … … 6305 6305 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6306 6306 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 6307 IEM_MC_ADVANCE_ RIP_AND_FINISH();6307 IEM_MC_ADVANCE_PC_AND_FINISH(); 6308 6308 IEM_MC_END(); 6309 6309 break; … … 6315 6315 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6316 6316 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 6317 IEM_MC_ADVANCE_ RIP_AND_FINISH();6317 IEM_MC_ADVANCE_PC_AND_FINISH(); 6318 6318 IEM_MC_END(); 6319 6319 break; … … 6337 6337 IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6338 6338 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 6339 IEM_MC_ADVANCE_ RIP_AND_FINISH();6339 IEM_MC_ADVANCE_PC_AND_FINISH(); 6340 6340 IEM_MC_END(); 6341 6341 break; … … 6349 6349 IEM_MC_FETCH_MEM_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6350 6350 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 6351 IEM_MC_ADVANCE_ RIP_AND_FINISH();6351 IEM_MC_ADVANCE_PC_AND_FINISH(); 6352 6352 IEM_MC_END(); 6353 6353 break; … … 6361 6361 IEM_MC_FETCH_MEM_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6362 6362 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 6363 IEM_MC_ADVANCE_ RIP_AND_FINISH();6363 IEM_MC_ADVANCE_PC_AND_FINISH(); 6364 6364 IEM_MC_END(); 6365 6365 break; … … 6416 6416 IEM_MC_FETCH_SREG_U16(u16Value, iSegReg); 6417 6417 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, bRm), u16Value); 6418 IEM_MC_ADVANCE_ RIP_AND_FINISH();6418 IEM_MC_ADVANCE_PC_AND_FINISH(); 6419 6419 IEM_MC_END(); 6420 6420 break; … … 6426 6426 IEM_MC_FETCH_SREG_ZX_U32(u32Value, iSegReg); 6427 6427 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Value); 6428 IEM_MC_ADVANCE_ RIP_AND_FINISH();6428 IEM_MC_ADVANCE_PC_AND_FINISH(); 6429 6429 IEM_MC_END(); 6430 6430 break; … … 6436 6436 IEM_MC_FETCH_SREG_ZX_U64(u64Value, iSegReg); 6437 6437 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Value); 6438 IEM_MC_ADVANCE_ RIP_AND_FINISH();6438 IEM_MC_ADVANCE_PC_AND_FINISH(); 6439 6439 IEM_MC_END(); 6440 6440 break; … … 6459 6459 IEM_MC_FETCH_SREG_U16(u16Value, iSegReg); 6460 6460 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value); 6461 IEM_MC_ADVANCE_ RIP_AND_FINISH();6461 IEM_MC_ADVANCE_PC_AND_FINISH(); 6462 6462 IEM_MC_END(); 6463 6463 } … … 6490 6490 IEM_MC_ASSIGN_TO_SMALLER(u16Cast, GCPtrEffSrc); 6491 6491 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Cast); 6492 IEM_MC_ADVANCE_ RIP_AND_FINISH();6492 IEM_MC_ADVANCE_PC_AND_FINISH(); 6493 6493 IEM_MC_END(); 6494 6494 break; … … 6505 6505 IEM_MC_ASSIGN_TO_SMALLER(u32Cast, GCPtrEffSrc); 6506 6506 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Cast); 6507 IEM_MC_ADVANCE_ RIP_AND_FINISH();6507 IEM_MC_ADVANCE_PC_AND_FINISH(); 6508 6508 IEM_MC_END(); 6509 6509 break; … … 6515 6515 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6516 6516 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), GCPtrEffSrc); 6517 IEM_MC_ADVANCE_ RIP_AND_FINISH();6517 IEM_MC_ADVANCE_PC_AND_FINISH(); 6518 6518 IEM_MC_END(); 6519 6519 break; … … 6855 6855 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp1); 6856 6856 IEM_MC_STORE_GREG_U16(iReg, u16Tmp2); 6857 IEM_MC_ADVANCE_ RIP_AND_FINISH();6857 IEM_MC_ADVANCE_PC_AND_FINISH(); 6858 6858 IEM_MC_END(); 6859 6859 break; … … 6868 6868 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp1); 6869 6869 IEM_MC_STORE_GREG_U32(iReg, u32Tmp2); 6870 IEM_MC_ADVANCE_ RIP_AND_FINISH();6870 IEM_MC_ADVANCE_PC_AND_FINISH(); 6871 6871 IEM_MC_END(); 6872 6872 break; … … 6881 6881 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp1); 6882 6882 IEM_MC_STORE_GREG_U64(iReg, u64Tmp2); 6883 IEM_MC_ADVANCE_ RIP_AND_FINISH();6883 IEM_MC_ADVANCE_PC_AND_FINISH(); 6884 6884 IEM_MC_END(); 6885 6885 break; … … 6923 6923 IEM_MC_BEGIN(0, 0); 6924 6924 IEMOP_HLP_DONE_DECODING(); 6925 IEM_MC_ADVANCE_ RIP_AND_FINISH();6925 IEM_MC_ADVANCE_PC_AND_FINISH(); 6926 6926 IEM_MC_END(); 6927 6927 } … … 7014 7014 IEM_MC_AND_GREG_U16(X86_GREG_xAX, UINT16_C(0x00ff)); 7015 7015 } IEM_MC_ENDIF(); 7016 IEM_MC_ADVANCE_ RIP_AND_FINISH();7016 IEM_MC_ADVANCE_PC_AND_FINISH(); 7017 7017 IEM_MC_END(); 7018 7018 break; … … 7027 7027 IEM_MC_AND_GREG_U32(X86_GREG_xAX, UINT32_C(0x0000ffff)); 7028 7028 } IEM_MC_ENDIF(); 7029 IEM_MC_ADVANCE_ RIP_AND_FINISH();7029 IEM_MC_ADVANCE_PC_AND_FINISH(); 7030 7030 IEM_MC_END(); 7031 7031 break; … … 7040 7040 IEM_MC_AND_GREG_U64(X86_GREG_xAX, UINT64_C(0x00000000ffffffff)); 7041 7041 } IEM_MC_ENDIF(); 7042 IEM_MC_ADVANCE_ RIP_AND_FINISH();7042 IEM_MC_ADVANCE_PC_AND_FINISH(); 7043 7043 IEM_MC_END(); 7044 7044 break; … … 7065 7065 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xDX, 0); 7066 7066 } IEM_MC_ENDIF(); 7067 IEM_MC_ADVANCE_ RIP_AND_FINISH();7067 IEM_MC_ADVANCE_PC_AND_FINISH(); 7068 7068 IEM_MC_END(); 7069 7069 break; … … 7078 7078 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xDX, 0); 7079 7079 } IEM_MC_ENDIF(); 7080 IEM_MC_ADVANCE_ RIP_AND_FINISH();7080 IEM_MC_ADVANCE_PC_AND_FINISH(); 7081 7081 IEM_MC_END(); 7082 7082 break; … … 7091 7091 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xDX, 0); 7092 7092 } IEM_MC_ENDIF(); 7093 IEM_MC_ADVANCE_ RIP_AND_FINISH();7093 IEM_MC_ADVANCE_PC_AND_FINISH(); 7094 7094 IEM_MC_END(); 7095 7095 break; … … 7131 7131 IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE(); 7132 7132 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 7133 IEM_MC_ADVANCE_ RIP_AND_FINISH();7133 IEM_MC_ADVANCE_PC_AND_FINISH(); 7134 7134 IEM_MC_END(); 7135 7135 } … … 7184 7184 IEM_MC_OR_2LOCS_U32(EFlags, u32Flags); 7185 7185 IEM_MC_COMMIT_EFLAGS(EFlags); 7186 IEM_MC_ADVANCE_ RIP_AND_FINISH();7186 IEM_MC_ADVANCE_PC_AND_FINISH(); 7187 7187 IEM_MC_END(); 7188 7188 } … … 7204 7204 IEM_MC_FETCH_EFLAGS_U8(u8Flags); 7205 7205 IEM_MC_STORE_GREG_U8(X86_GREG_xSP/*=AH*/, u8Flags); 7206 IEM_MC_ADVANCE_ RIP_AND_FINISH();7206 IEM_MC_ADVANCE_PC_AND_FINISH(); 7207 7207 IEM_MC_END(); 7208 7208 } … … 7254 7254 IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7255 7255 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 7256 IEM_MC_ADVANCE_ RIP_AND_FINISH();7256 IEM_MC_ADVANCE_PC_AND_FINISH(); 7257 7257 IEM_MC_END(); 7258 7258 } … … 7283 7283 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7284 7284 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp); 7285 IEM_MC_ADVANCE_ RIP_AND_FINISH();7285 IEM_MC_ADVANCE_PC_AND_FINISH(); 7286 7286 IEM_MC_END(); 7287 7287 break; … … 7294 7294 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7295 7295 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp); 7296 IEM_MC_ADVANCE_ RIP_AND_FINISH();7296 IEM_MC_ADVANCE_PC_AND_FINISH(); 7297 7297 IEM_MC_END(); 7298 7298 break; … … 7305 7305 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7306 7306 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp); 7307 IEM_MC_ADVANCE_ RIP_AND_FINISH();7307 IEM_MC_ADVANCE_PC_AND_FINISH(); 7308 7308 IEM_MC_END(); 7309 7309 break; … … 7335 7335 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7336 7336 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u8Tmp); 7337 IEM_MC_ADVANCE_ RIP_AND_FINISH();7337 IEM_MC_ADVANCE_PC_AND_FINISH(); 7338 7338 IEM_MC_END(); 7339 7339 } … … 7364 7364 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7365 7365 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u16Tmp); 7366 IEM_MC_ADVANCE_ RIP_AND_FINISH();7366 IEM_MC_ADVANCE_PC_AND_FINISH(); 7367 7367 IEM_MC_END(); 7368 7368 break; … … 7375 7375 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7376 7376 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u32Tmp); 7377 IEM_MC_ADVANCE_ RIP_AND_FINISH();7377 IEM_MC_ADVANCE_PC_AND_FINISH(); 7378 7378 IEM_MC_END(); 7379 7379 break; … … 7386 7386 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7387 7387 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u64Tmp); 7388 IEM_MC_ADVANCE_ RIP_AND_FINISH();7388 IEM_MC_ADVANCE_PC_AND_FINISH(); 7389 7389 IEM_MC_END(); 7390 7390 break; … … 7411 7411 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 7412 7412 } IEM_MC_ENDIF(); \ 7413 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7413 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7414 7414 IEM_MC_END() \ 7415 7415 … … 7619 7619 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 7620 7620 } IEM_MC_ENDIF(); \ 7621 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7621 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7622 7622 IEM_MC_END() \ 7623 7623 … … 7942 7942 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 7943 7943 } IEM_MC_ENDIF(); \ 7944 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7944 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7945 7945 IEM_MC_END() \ 7946 7946 … … 8123 8123 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 8124 8124 } IEM_MC_ENDIF(); \ 8125 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8125 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8126 8126 IEM_MC_END() \ 8127 8127 … … 8324 8324 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 8325 8325 } IEM_MC_ENDIF(); \ 8326 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8326 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8327 8327 IEM_MC_END(); 8328 8328 … … 8594 8594 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8595 8595 IEM_MC_STORE_GREG_U8_CONST(iFixedReg, u8Imm); 8596 IEM_MC_ADVANCE_ RIP_AND_FINISH();8596 IEM_MC_ADVANCE_PC_AND_FINISH(); 8597 8597 IEM_MC_END(); 8598 8598 } … … 8691 8691 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8692 8692 IEM_MC_STORE_GREG_U16_CONST(iFixedReg, u16Imm); 8693 IEM_MC_ADVANCE_ RIP_AND_FINISH();8693 IEM_MC_ADVANCE_PC_AND_FINISH(); 8694 8694 IEM_MC_END(); 8695 8695 break; … … 8700 8700 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8701 8701 IEM_MC_STORE_GREG_U32_CONST(iFixedReg, u32Imm); 8702 IEM_MC_ADVANCE_ RIP_AND_FINISH();8702 IEM_MC_ADVANCE_PC_AND_FINISH(); 8703 8703 IEM_MC_END(); 8704 8704 break; … … 8709 8709 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8710 8710 IEM_MC_STORE_GREG_U64_CONST(iFixedReg, u64Imm); 8711 IEM_MC_ADVANCE_ RIP_AND_FINISH();8711 IEM_MC_ADVANCE_PC_AND_FINISH(); 8712 8712 IEM_MC_END(); 8713 8713 break; … … 8821 8821 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 8822 8822 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8823 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8823 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8824 8824 IEM_MC_END(); \ 8825 8825 } \ … … 8844 8844 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 8845 8845 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8846 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8846 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8847 8847 IEM_MC_END(); \ 8848 8848 } (void)0 … … 8969 8969 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, cShiftArg); \ 8970 8970 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8971 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8971 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8972 8972 IEM_MC_END(); \ 8973 8973 break; \ … … 8983 8983 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 8984 8984 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8985 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8985 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8986 8986 IEM_MC_END(); \ 8987 8987 break; \ … … 8996 8996 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, cShiftArg); \ 8997 8997 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8998 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8998 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8999 8999 IEM_MC_END(); \ 9000 9000 break; \ … … 9026 9026 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9027 9027 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9028 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9028 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9029 9029 IEM_MC_END(); \ 9030 9030 break; \ … … 9048 9048 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9049 9049 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9050 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9050 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9051 9051 IEM_MC_END(); \ 9052 9052 break; \ … … 9070 9070 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9071 9071 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9072 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9072 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9073 9073 IEM_MC_END(); \ 9074 9074 break; \ … … 9378 9378 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9379 9379 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u8Imm); 9380 IEM_MC_ADVANCE_ RIP_AND_FINISH();9380 IEM_MC_ADVANCE_PC_AND_FINISH(); 9381 9381 IEM_MC_END(); 9382 9382 } … … 9390 9390 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9391 9391 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Imm); 9392 IEM_MC_ADVANCE_ RIP_AND_FINISH();9392 IEM_MC_ADVANCE_PC_AND_FINISH(); 9393 9393 IEM_MC_END(); 9394 9394 } … … 9416 9416 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9417 9417 IEM_MC_STORE_GREG_U16_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u16Imm); 9418 IEM_MC_ADVANCE_ RIP_AND_FINISH();9418 IEM_MC_ADVANCE_PC_AND_FINISH(); 9419 9419 IEM_MC_END(); 9420 9420 break; … … 9425 9425 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9426 9426 IEM_MC_STORE_GREG_U32_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u32Imm); 9427 IEM_MC_ADVANCE_ RIP_AND_FINISH();9427 IEM_MC_ADVANCE_PC_AND_FINISH(); 9428 9428 IEM_MC_END(); 9429 9429 break; … … 9434 9434 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9435 9435 IEM_MC_STORE_GREG_U64_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u64Imm); 9436 IEM_MC_ADVANCE_ RIP_AND_FINISH();9436 IEM_MC_ADVANCE_PC_AND_FINISH(); 9437 9437 IEM_MC_END(); 9438 9438 break; … … 9453 9453 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9454 9454 IEM_MC_STORE_MEM_U16_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Imm); 9455 IEM_MC_ADVANCE_ RIP_AND_FINISH();9455 IEM_MC_ADVANCE_PC_AND_FINISH(); 9456 9456 IEM_MC_END(); 9457 9457 break; … … 9464 9464 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9465 9465 IEM_MC_STORE_MEM_U32_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Imm); 9466 IEM_MC_ADVANCE_ RIP_AND_FINISH();9466 IEM_MC_ADVANCE_PC_AND_FINISH(); 9467 9467 IEM_MC_END(); 9468 9468 break; … … 9475 9475 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9476 9476 IEM_MC_STORE_MEM_U64_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Imm); 9477 IEM_MC_ADVANCE_ RIP_AND_FINISH();9477 IEM_MC_ADVANCE_PC_AND_FINISH(); 9478 9478 IEM_MC_END(); 9479 9479 break; … … 9680 9680 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 9681 9681 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9682 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9682 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9683 9683 IEM_MC_END(); \ 9684 9684 } \ … … 9701 9701 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9702 9702 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9703 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9703 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9704 9704 IEM_MC_END(); \ 9705 9705 } (void)0 … … 9817 9817 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, cShiftArg); \ 9818 9818 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9819 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9819 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9820 9820 IEM_MC_END(); \ 9821 9821 break; \ … … 9831 9831 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9832 9832 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9833 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9833 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9834 9834 IEM_MC_END(); \ 9835 9835 break; \ … … 9844 9844 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, cShiftArg); \ 9845 9845 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9846 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9846 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9847 9847 IEM_MC_END(); \ 9848 9848 break; \ … … 9872 9872 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9873 9873 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9874 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9874 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9875 9875 IEM_MC_END(); \ 9876 9876 break; \ … … 9892 9892 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9893 9893 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9894 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9894 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9895 9895 IEM_MC_END(); \ 9896 9896 break; \ … … 9912 9912 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9913 9913 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9914 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9914 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9915 9915 IEM_MC_END(); \ 9916 9916 break; \ … … 10049 10049 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 10050 10050 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10051 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10051 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10052 10052 IEM_MC_END(); \ 10053 10053 } \ … … 10072 10072 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10073 10073 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10074 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10074 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10075 10075 IEM_MC_END(); \ 10076 10076 } (void)0 … … 10200 10200 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10201 10201 } IEM_MC_NATIVE_ENDIF(); \ 10202 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10202 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10203 10203 IEM_MC_END(); \ 10204 10204 break; \ … … 10226 10226 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10227 10227 } IEM_MC_NATIVE_ENDIF(); \ 10228 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10228 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10229 10229 IEM_MC_END(); \ 10230 10230 break; \ … … 10251 10251 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10252 10252 } IEM_MC_NATIVE_ENDIF(); \ 10253 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10253 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10254 10254 IEM_MC_END(); \ 10255 10255 break; \ … … 10280 10280 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10281 10281 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10282 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10282 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10283 10283 IEM_MC_END(); \ 10284 10284 break; \ … … 10301 10301 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10302 10302 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10303 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10303 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10304 10304 IEM_MC_END(); \ 10305 10305 break; \ … … 10322 10322 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10323 10323 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10324 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10324 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10325 10325 IEM_MC_END(); \ 10326 10326 break; \ … … 10486 10486 IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0x00); 10487 10487 } IEM_MC_ENDIF(); 10488 IEM_MC_ADVANCE_ RIP_AND_FINISH();10488 IEM_MC_ADVANCE_PC_AND_FINISH(); 10489 10489 IEM_MC_END(); 10490 10490 } … … 10508 10508 IEM_MC_FETCH_MEM16_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u16Addr); 10509 10509 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10510 IEM_MC_ADVANCE_ RIP_AND_FINISH();10510 IEM_MC_ADVANCE_PC_AND_FINISH(); 10511 10511 IEM_MC_END(); 10512 10512 break; … … 10521 10521 IEM_MC_FETCH_MEM32_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u32Addr); 10522 10522 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10523 IEM_MC_ADVANCE_ RIP_AND_FINISH();10523 IEM_MC_ADVANCE_PC_AND_FINISH(); 10524 10524 IEM_MC_END(); 10525 10525 break; … … 10534 10534 IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u64Addr); 10535 10535 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10536 IEM_MC_ADVANCE_ RIP_AND_FINISH();10536 IEM_MC_ADVANCE_PC_AND_FINISH(); 10537 10537 IEM_MC_END(); 10538 10538 break; … … 10568 10568 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 10569 10569 } IEM_MC_ENDIF(); 10570 IEM_MC_ADVANCE_ RIP_AND_FINISH();10570 IEM_MC_ADVANCE_PC_AND_FINISH(); 10571 10571 10572 10572 IEM_MC_END(); … … 10599 10599 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 10600 10600 } IEM_MC_ENDIF(); 10601 IEM_MC_ADVANCE_ RIP_AND_FINISH();10601 IEM_MC_ADVANCE_PC_AND_FINISH(); 10602 10602 10603 10603 IEM_MC_END(); … … 10630 10630 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 10631 10631 } IEM_MC_ENDIF(); 10632 IEM_MC_ADVANCE_ RIP_AND_FINISH();10632 IEM_MC_ADVANCE_PC_AND_FINISH(); 10633 10633 10634 10634 IEM_MC_END(); … … 10731 10731 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 10732 10732 } IEM_MC_ENDIF(); 10733 IEM_MC_ADVANCE_ RIP_AND_FINISH();10733 IEM_MC_ADVANCE_PC_AND_FINISH(); 10734 10734 10735 10735 IEM_MC_END(); … … 10780 10780 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10781 10781 } IEM_MC_ENDIF(); 10782 IEM_MC_ADVANCE_ RIP_AND_FINISH();10782 IEM_MC_ADVANCE_PC_AND_FINISH(); 10783 10783 10784 10784 IEM_MC_END(); … … 10813 10813 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10814 10814 } IEM_MC_ENDIF(); 10815 IEM_MC_ADVANCE_ RIP_AND_FINISH();10815 IEM_MC_ADVANCE_PC_AND_FINISH(); 10816 10816 10817 10817 IEM_MC_END(); … … 10918 10918 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10919 10919 } IEM_MC_ENDIF(); 10920 IEM_MC_ADVANCE_ RIP_AND_FINISH();10920 IEM_MC_ADVANCE_PC_AND_FINISH(); 10921 10921 10922 10922 IEM_MC_END(); … … 10957 10957 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 10958 10958 } IEM_MC_ENDIF(); 10959 IEM_MC_ADVANCE_ RIP_AND_FINISH();10959 IEM_MC_ADVANCE_PC_AND_FINISH(); 10960 10960 10961 10961 IEM_MC_END(); … … 10996 10996 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 10997 10997 } IEM_MC_ENDIF(); 10998 IEM_MC_ADVANCE_ RIP_AND_FINISH();10998 IEM_MC_ADVANCE_PC_AND_FINISH(); 10999 10999 11000 11000 IEM_MC_END(); … … 11076 11076 IEM_MC_FETCH_FCW(u16Fcw); 11077 11077 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Fcw); 11078 IEM_MC_ADVANCE_ RIP_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */11078 IEM_MC_ADVANCE_PC_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */ 11079 11079 IEM_MC_END(); 11080 11080 } … … 11093 11093 * intel optimizations. Investigate. */ 11094 11094 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 11095 IEM_MC_ADVANCE_ RIP_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */11095 IEM_MC_ADVANCE_PC_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */ 11096 11096 IEM_MC_END(); 11097 11097 } … … 11119 11119 } IEM_MC_ENDIF(); 11120 11120 11121 IEM_MC_ADVANCE_ RIP_AND_FINISH();11121 IEM_MC_ADVANCE_PC_AND_FINISH(); 11122 11122 IEM_MC_END(); 11123 11123 } … … 11149 11149 } IEM_MC_ENDIF(); 11150 11150 11151 IEM_MC_ADVANCE_ RIP_AND_FINISH();11151 IEM_MC_ADVANCE_PC_AND_FINISH(); 11152 11152 IEM_MC_END(); 11153 11153 } … … 11176 11176 } IEM_MC_ENDIF(); 11177 11177 11178 IEM_MC_ADVANCE_ RIP_AND_FINISH();11178 IEM_MC_ADVANCE_PC_AND_FINISH(); 11179 11179 IEM_MC_END(); 11180 11180 } … … 11196 11196 } IEM_MC_ENDIF(); 11197 11197 11198 IEM_MC_ADVANCE_ RIP_AND_FINISH();11198 IEM_MC_ADVANCE_PC_AND_FINISH(); 11199 11199 IEM_MC_END(); 11200 11200 } … … 11225 11225 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11226 11226 } IEM_MC_ENDIF(); 11227 IEM_MC_ADVANCE_ RIP_AND_FINISH();11227 IEM_MC_ADVANCE_PC_AND_FINISH(); 11228 11228 11229 11229 IEM_MC_END(); … … 11266 11266 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 11267 11267 } IEM_MC_ENDIF(); 11268 IEM_MC_ADVANCE_ RIP_AND_FINISH();11268 IEM_MC_ADVANCE_PC_AND_FINISH(); 11269 11269 11270 11270 IEM_MC_END(); … … 11288 11288 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fxam_r80, pu16Fsw, pr80Value); 11289 11289 IEM_MC_UPDATE_FSW(u16Fsw, pVCpu->iem.s.uFpuOpcode); 11290 IEM_MC_ADVANCE_ RIP_AND_FINISH();11290 IEM_MC_ADVANCE_PC_AND_FINISH(); 11291 11291 11292 11292 IEM_MC_END(); … … 11315 11315 IEM_MC_FPU_STACK_PUSH_OVERFLOW(pVCpu->iem.s.uFpuOpcode); 11316 11316 } IEM_MC_ENDIF(); 11317 IEM_MC_ADVANCE_ RIP_AND_FINISH();11317 IEM_MC_ADVANCE_PC_AND_FINISH(); 11318 11318 11319 11319 IEM_MC_END(); … … 11416 11416 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(IEM_GET_MODRM_RM_8(bRm), pVCpu->iem.s.uFpuOpcode); 11417 11417 } IEM_MC_ENDIF(); 11418 IEM_MC_ADVANCE_ RIP_AND_FINISH();11418 IEM_MC_ADVANCE_PC_AND_FINISH(); 11419 11419 11420 11420 IEM_MC_END(); … … 11453 11453 IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(pVCpu->iem.s.uFpuOpcode); 11454 11454 } IEM_MC_ENDIF(); 11455 IEM_MC_ADVANCE_ RIP_AND_FINISH();11455 IEM_MC_ADVANCE_PC_AND_FINISH(); 11456 11456 11457 11457 IEM_MC_END(); … … 11508 11508 IEM_MC_UPDATE_FSW_CONST(0, pVCpu->iem.s.uFpuOpcode); 11509 11509 11510 IEM_MC_ADVANCE_ RIP_AND_FINISH();11510 IEM_MC_ADVANCE_PC_AND_FINISH(); 11511 11511 IEM_MC_END(); 11512 11512 } … … 11530 11530 IEM_MC_UPDATE_FSW_CONST(0, pVCpu->iem.s.uFpuOpcode); 11531 11531 11532 IEM_MC_ADVANCE_ RIP_AND_FINISH();11532 IEM_MC_ADVANCE_PC_AND_FINISH(); 11533 11533 IEM_MC_END(); 11534 11534 } … … 11703 11703 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11704 11704 } IEM_MC_ENDIF(); 11705 IEM_MC_ADVANCE_ RIP_AND_FINISH();11705 IEM_MC_ADVANCE_PC_AND_FINISH(); 11706 11706 11707 11707 IEM_MC_END(); … … 11729 11729 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11730 11730 } IEM_MC_ENDIF(); 11731 IEM_MC_ADVANCE_ RIP_AND_FINISH();11731 IEM_MC_ADVANCE_PC_AND_FINISH(); 11732 11732 11733 11733 IEM_MC_END(); … … 11755 11755 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11756 11756 } IEM_MC_ENDIF(); 11757 IEM_MC_ADVANCE_ RIP_AND_FINISH();11757 IEM_MC_ADVANCE_PC_AND_FINISH(); 11758 11758 11759 11759 IEM_MC_END(); … … 11781 11781 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11782 11782 } IEM_MC_ENDIF(); 11783 IEM_MC_ADVANCE_ RIP_AND_FINISH();11783 IEM_MC_ADVANCE_PC_AND_FINISH(); 11784 11784 11785 11785 IEM_MC_END(); … … 11812 11812 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(pVCpu->iem.s.uFpuOpcode); 11813 11813 } IEM_MC_ENDIF(); 11814 IEM_MC_ADVANCE_ RIP_AND_FINISH();11814 IEM_MC_ADVANCE_PC_AND_FINISH(); 11815 11815 11816 11816 IEM_MC_END(); … … 11857 11857 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11858 11858 } IEM_MC_ENDIF(); 11859 IEM_MC_ADVANCE_ RIP_AND_FINISH();11859 IEM_MC_ADVANCE_PC_AND_FINISH(); 11860 11860 11861 11861 IEM_MC_END(); … … 11906 11906 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 11907 11907 } IEM_MC_ENDIF(); 11908 IEM_MC_ADVANCE_ RIP_AND_FINISH();11908 IEM_MC_ADVANCE_PC_AND_FINISH(); 11909 11909 11910 11910 IEM_MC_END(); … … 11939 11939 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 11940 11940 } IEM_MC_ENDIF(); 11941 IEM_MC_ADVANCE_ RIP_AND_FINISH();11941 IEM_MC_ADVANCE_PC_AND_FINISH(); 11942 11942 11943 11943 IEM_MC_END(); … … 12046 12046 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12047 12047 } IEM_MC_ENDIF(); 12048 IEM_MC_ADVANCE_ RIP_AND_FINISH();12048 IEM_MC_ADVANCE_PC_AND_FINISH(); 12049 12049 12050 12050 IEM_MC_END(); … … 12085 12085 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12086 12086 } IEM_MC_ENDIF(); 12087 IEM_MC_ADVANCE_ RIP_AND_FINISH();12087 IEM_MC_ADVANCE_PC_AND_FINISH(); 12088 12088 12089 12089 IEM_MC_END(); … … 12124 12124 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12125 12125 } IEM_MC_ENDIF(); 12126 IEM_MC_ADVANCE_ RIP_AND_FINISH();12126 IEM_MC_ADVANCE_PC_AND_FINISH(); 12127 12127 12128 12128 IEM_MC_END(); … … 12163 12163 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12164 12164 } IEM_MC_ENDIF(); 12165 IEM_MC_ADVANCE_ RIP_AND_FINISH();12165 IEM_MC_ADVANCE_PC_AND_FINISH(); 12166 12166 12167 12167 IEM_MC_END(); … … 12195 12195 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12196 12196 } IEM_MC_ENDIF(); 12197 IEM_MC_ADVANCE_ RIP_AND_FINISH();12197 IEM_MC_ADVANCE_PC_AND_FINISH(); 12198 12198 12199 12199 IEM_MC_END(); … … 12234 12234 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12235 12235 } IEM_MC_ENDIF(); 12236 IEM_MC_ADVANCE_ RIP_AND_FINISH();12236 IEM_MC_ADVANCE_PC_AND_FINISH(); 12237 12237 12238 12238 IEM_MC_END(); … … 12260 12260 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12261 12261 } IEM_MC_ENDIF(); 12262 IEM_MC_ADVANCE_ RIP_AND_FINISH();12262 IEM_MC_ADVANCE_PC_AND_FINISH(); 12263 12263 12264 12264 IEM_MC_END(); … … 12286 12286 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12287 12287 } IEM_MC_ENDIF(); 12288 IEM_MC_ADVANCE_ RIP_AND_FINISH();12288 IEM_MC_ADVANCE_PC_AND_FINISH(); 12289 12289 12290 12290 IEM_MC_END(); … … 12312 12312 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12313 12313 } IEM_MC_ENDIF(); 12314 IEM_MC_ADVANCE_ RIP_AND_FINISH();12314 IEM_MC_ADVANCE_PC_AND_FINISH(); 12315 12315 12316 12316 IEM_MC_END(); … … 12338 12338 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12339 12339 } IEM_MC_ENDIF(); 12340 IEM_MC_ADVANCE_ RIP_AND_FINISH();12340 IEM_MC_ADVANCE_PC_AND_FINISH(); 12341 12341 12342 12342 IEM_MC_END(); … … 12351 12351 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12352 12352 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12353 IEM_MC_ADVANCE_ RIP_AND_FINISH();12353 IEM_MC_ADVANCE_PC_AND_FINISH(); 12354 12354 IEM_MC_END(); 12355 12355 } … … 12363 12363 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12364 12364 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12365 IEM_MC_ADVANCE_ RIP_AND_FINISH();12365 IEM_MC_ADVANCE_PC_AND_FINISH(); 12366 12366 IEM_MC_END(); 12367 12367 } … … 12377 12377 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 12378 12378 IEM_MC_CLEAR_FSW_EX(); 12379 IEM_MC_ADVANCE_ RIP_AND_FINISH();12379 IEM_MC_ADVANCE_PC_AND_FINISH(); 12380 12380 IEM_MC_END(); 12381 12381 } … … 12399 12399 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12400 12400 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12401 IEM_MC_ADVANCE_ RIP_AND_FINISH();12401 IEM_MC_ADVANCE_PC_AND_FINISH(); 12402 12402 IEM_MC_END(); 12403 12403 } … … 12412 12412 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12413 12413 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12414 IEM_MC_ADVANCE_ RIP_AND_FINISH();12414 IEM_MC_ADVANCE_PC_AND_FINISH(); 12415 12415 IEM_MC_END(); 12416 12416 return VINF_SUCCESS; … … 12520 12520 IEM_MC_FPU_STACK_UNDERFLOW(IEM_GET_MODRM_RM_8(bRm), pVCpu->iem.s.uFpuOpcode); 12521 12521 } IEM_MC_ENDIF(); 12522 IEM_MC_ADVANCE_ RIP_AND_FINISH();12522 IEM_MC_ADVANCE_PC_AND_FINISH(); 12523 12523 12524 12524 IEM_MC_END(); … … 12604 12604 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(0, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12605 12605 } IEM_MC_ENDIF(); 12606 IEM_MC_ADVANCE_ RIP_AND_FINISH();12606 IEM_MC_ADVANCE_PC_AND_FINISH(); 12607 12607 12608 12608 IEM_MC_END(); … … 12653 12653 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12654 12654 } IEM_MC_ENDIF(); 12655 IEM_MC_ADVANCE_ RIP_AND_FINISH();12655 IEM_MC_ADVANCE_PC_AND_FINISH(); 12656 12656 12657 12657 IEM_MC_END(); … … 12686 12686 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12687 12687 } IEM_MC_ENDIF(); 12688 IEM_MC_ADVANCE_ RIP_AND_FINISH();12688 IEM_MC_ADVANCE_PC_AND_FINISH(); 12689 12689 12690 12690 IEM_MC_END(); … … 12790 12790 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12791 12791 } IEM_MC_ENDIF(); 12792 IEM_MC_ADVANCE_ RIP_AND_FINISH();12792 IEM_MC_ADVANCE_PC_AND_FINISH(); 12793 12793 12794 12794 IEM_MC_END(); … … 12829 12829 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12830 12830 } IEM_MC_ENDIF(); 12831 IEM_MC_ADVANCE_ RIP_AND_FINISH();12831 IEM_MC_ADVANCE_PC_AND_FINISH(); 12832 12832 12833 12833 IEM_MC_END(); … … 12868 12868 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12869 12869 } IEM_MC_ENDIF(); 12870 IEM_MC_ADVANCE_ RIP_AND_FINISH();12870 IEM_MC_ADVANCE_PC_AND_FINISH(); 12871 12871 12872 12872 IEM_MC_END(); … … 12909 12909 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12910 12910 } IEM_MC_ENDIF(); 12911 IEM_MC_ADVANCE_ RIP_AND_FINISH();12911 IEM_MC_ADVANCE_PC_AND_FINISH(); 12912 12912 12913 12913 IEM_MC_END(); … … 12970 12970 IEM_MC_FETCH_FSW(u16Tmp); 12971 12971 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp); 12972 IEM_MC_ADVANCE_ RIP_AND_FINISH();12972 IEM_MC_ADVANCE_PC_AND_FINISH(); 12973 12973 12974 12974 /** @todo Debug / drop a hint to the verifier that things may differ … … 12995 12995 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 12996 12996 12997 IEM_MC_ADVANCE_ RIP_AND_FINISH();12997 IEM_MC_ADVANCE_PC_AND_FINISH(); 12998 12998 IEM_MC_END(); 12999 12999 } … … 13019 13019 } IEM_MC_ENDIF(); 13020 13020 13021 IEM_MC_ADVANCE_ RIP_AND_FINISH();13021 IEM_MC_ADVANCE_PC_AND_FINISH(); 13022 13022 IEM_MC_END(); 13023 13023 } … … 13167 13167 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 13168 13168 } IEM_MC_ENDIF(); 13169 IEM_MC_ADVANCE_ RIP_AND_FINISH();13169 IEM_MC_ADVANCE_PC_AND_FINISH(); 13170 13170 13171 13171 IEM_MC_END(); … … 13216 13216 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13217 13217 } IEM_MC_ENDIF(); 13218 IEM_MC_ADVANCE_ RIP_AND_FINISH();13218 IEM_MC_ADVANCE_PC_AND_FINISH(); 13219 13219 13220 13220 IEM_MC_END(); … … 13249 13249 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13250 13250 } IEM_MC_ENDIF(); 13251 IEM_MC_ADVANCE_ RIP_AND_FINISH();13251 IEM_MC_ADVANCE_PC_AND_FINISH(); 13252 13252 13253 13253 IEM_MC_END(); … … 13345 13345 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 13346 13346 13347 IEM_MC_ADVANCE_ RIP_AND_FINISH();13347 IEM_MC_ADVANCE_PC_AND_FINISH(); 13348 13348 IEM_MC_END(); 13349 13349 } … … 13361 13361 IEM_MC_FETCH_FSW(u16Tmp); 13362 13362 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp); 13363 IEM_MC_ADVANCE_ RIP_AND_FINISH();13363 IEM_MC_ADVANCE_PC_AND_FINISH(); 13364 13364 IEM_MC_END(); 13365 13365 } … … 13412 13412 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13413 13413 } IEM_MC_ENDIF(); 13414 IEM_MC_ADVANCE_ RIP_AND_FINISH();13414 IEM_MC_ADVANCE_PC_AND_FINISH(); 13415 13415 13416 13416 IEM_MC_END(); … … 13451 13451 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13452 13452 } IEM_MC_ENDIF(); 13453 IEM_MC_ADVANCE_ RIP_AND_FINISH();13453 IEM_MC_ADVANCE_PC_AND_FINISH(); 13454 13454 13455 13455 IEM_MC_END(); … … 13490 13490 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13491 13491 } IEM_MC_ENDIF(); 13492 IEM_MC_ADVANCE_ RIP_AND_FINISH();13492 IEM_MC_ADVANCE_PC_AND_FINISH(); 13493 13493 13494 13494 IEM_MC_END(); … … 13529 13529 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13530 13530 } IEM_MC_ENDIF(); 13531 IEM_MC_ADVANCE_ RIP_AND_FINISH();13531 IEM_MC_ADVANCE_PC_AND_FINISH(); 13532 13532 13533 13533 IEM_MC_END(); … … 13561 13561 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13562 13562 } IEM_MC_ENDIF(); 13563 IEM_MC_ADVANCE_ RIP_AND_FINISH();13563 IEM_MC_ADVANCE_PC_AND_FINISH(); 13564 13564 13565 13565 IEM_MC_END(); … … 13593 13593 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13594 13594 } IEM_MC_ENDIF(); 13595 IEM_MC_ADVANCE_ RIP_AND_FINISH();13595 IEM_MC_ADVANCE_PC_AND_FINISH(); 13596 13596 13597 13597 IEM_MC_END(); … … 13632 13632 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13633 13633 } IEM_MC_ENDIF(); 13634 IEM_MC_ADVANCE_ RIP_AND_FINISH();13634 IEM_MC_ADVANCE_PC_AND_FINISH(); 13635 13635 13636 13636 IEM_MC_END(); … … 13671 13671 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13672 13672 } IEM_MC_ENDIF(); 13673 IEM_MC_ADVANCE_ RIP_AND_FINISH();13673 IEM_MC_ADVANCE_PC_AND_FINISH(); 13674 13674 13675 13675 IEM_MC_END(); … … 13739 13739 } IEM_MC_ELSE() { 13740 13740 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 13741 IEM_MC_ADVANCE_ RIP_AND_FINISH();13741 IEM_MC_ADVANCE_PC_AND_FINISH(); 13742 13742 } IEM_MC_ENDIF(); 13743 13743 IEM_MC_END(); … … 13752 13752 } IEM_MC_ELSE() { 13753 13753 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 13754 IEM_MC_ADVANCE_ RIP_AND_FINISH();13754 IEM_MC_ADVANCE_PC_AND_FINISH(); 13755 13755 } IEM_MC_ENDIF(); 13756 13756 IEM_MC_END(); … … 13765 13765 } IEM_MC_ELSE() { 13766 13766 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 13767 IEM_MC_ADVANCE_ RIP_AND_FINISH();13767 IEM_MC_ADVANCE_PC_AND_FINISH(); 13768 13768 } IEM_MC_ENDIF(); 13769 13769 IEM_MC_END(); … … 13795 13795 } IEM_MC_ELSE() { 13796 13796 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 13797 IEM_MC_ADVANCE_ RIP_AND_FINISH();13797 IEM_MC_ADVANCE_PC_AND_FINISH(); 13798 13798 } IEM_MC_ENDIF(); 13799 13799 IEM_MC_END(); … … 13808 13808 } IEM_MC_ELSE() { 13809 13809 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 13810 IEM_MC_ADVANCE_ RIP_AND_FINISH();13810 IEM_MC_ADVANCE_PC_AND_FINISH(); 13811 13811 } IEM_MC_ENDIF(); 13812 13812 IEM_MC_END(); … … 13821 13821 } IEM_MC_ELSE() { 13822 13822 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 13823 IEM_MC_ADVANCE_ RIP_AND_FINISH();13823 IEM_MC_ADVANCE_PC_AND_FINISH(); 13824 13824 } IEM_MC_ENDIF(); 13825 13825 IEM_MC_END(); … … 13856 13856 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13857 13857 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 13858 IEM_MC_ADVANCE_ RIP_AND_FINISH();13858 IEM_MC_ADVANCE_PC_AND_FINISH(); 13859 13859 IEM_MC_END(); 13860 13860 break; … … 13864 13864 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13865 13865 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 13866 IEM_MC_ADVANCE_ RIP_AND_FINISH();13866 IEM_MC_ADVANCE_PC_AND_FINISH(); 13867 13867 IEM_MC_END(); 13868 13868 break; … … 13872 13872 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13873 13873 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 13874 IEM_MC_ADVANCE_ RIP_AND_FINISH();13874 IEM_MC_ADVANCE_PC_AND_FINISH(); 13875 13875 IEM_MC_END(); 13876 13876 break; … … 13890 13890 } IEM_MC_ELSE() { 13891 13891 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 13892 IEM_MC_ADVANCE_ RIP_AND_FINISH();13892 IEM_MC_ADVANCE_PC_AND_FINISH(); 13893 13893 } IEM_MC_ENDIF(); 13894 13894 IEM_MC_END(); … … 13903 13903 } IEM_MC_ELSE() { 13904 13904 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 13905 IEM_MC_ADVANCE_ RIP_AND_FINISH();13905 IEM_MC_ADVANCE_PC_AND_FINISH(); 13906 13906 } IEM_MC_ENDIF(); 13907 13907 IEM_MC_END(); … … 13916 13916 } IEM_MC_ELSE() { 13917 13917 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 13918 IEM_MC_ADVANCE_ RIP_AND_FINISH();13918 IEM_MC_ADVANCE_PC_AND_FINISH(); 13919 13919 } IEM_MC_ENDIF(); 13920 13920 IEM_MC_END(); … … 13941 13941 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13942 13942 IEM_MC_IF_CX_IS_NZ() { 13943 IEM_MC_ADVANCE_ RIP_AND_FINISH();13943 IEM_MC_ADVANCE_PC_AND_FINISH(); 13944 13944 } IEM_MC_ELSE() { 13945 13945 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 13952 13952 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13953 13953 IEM_MC_IF_ECX_IS_NZ() { 13954 IEM_MC_ADVANCE_ RIP_AND_FINISH();13954 IEM_MC_ADVANCE_PC_AND_FINISH(); 13955 13955 } IEM_MC_ELSE() { 13956 13956 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 13963 13963 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13964 13964 IEM_MC_IF_RCX_IS_NZ() { 13965 IEM_MC_ADVANCE_ RIP_AND_FINISH();13965 IEM_MC_ADVANCE_PC_AND_FINISH(); 13966 13966 } IEM_MC_ELSE() { 13967 13967 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 14292 14292 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14293 14293 IEM_MC_FLIP_EFL_BIT(X86_EFL_CF); 14294 IEM_MC_ADVANCE_ RIP_AND_FINISH();14294 IEM_MC_ADVANCE_PC_AND_FINISH(); 14295 14295 IEM_MC_END(); 14296 14296 } … … 14311 14311 IEM_MC_REF_EFLAGS(pEFlags); \ 14312 14312 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU8, pu8Dst, pEFlags); \ 14313 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14313 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14314 14314 IEM_MC_END(); \ 14315 14315 } \ … … 14332 14332 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14333 14333 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14334 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14334 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14335 14335 IEM_MC_END(); \ 14336 14336 } \ … … 14350 14350 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14351 14351 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14352 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14352 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14353 14353 IEM_MC_END(); \ 14354 14354 } \ … … 14376 14376 IEM_MC_REF_EFLAGS(pEFlags); \ 14377 14377 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 14378 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14378 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14379 14379 IEM_MC_END(); \ 14380 14380 break; \ … … 14389 14389 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 14390 14390 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 14391 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14391 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14392 14392 IEM_MC_END(); \ 14393 14393 break; \ … … 14401 14401 IEM_MC_REF_EFLAGS(pEFlags); \ 14402 14402 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU64, pu64Dst, pEFlags); \ 14403 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14403 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14404 14404 IEM_MC_END(); \ 14405 14405 break; \ … … 14431 14431 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14432 14432 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14433 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14433 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14434 14434 IEM_MC_END(); \ 14435 14435 break; \ … … 14449 14449 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14450 14450 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14451 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14451 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14452 14452 IEM_MC_END(); \ 14453 14453 break; \ … … 14467 14467 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14468 14468 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14469 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14469 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14470 14470 IEM_MC_END(); \ 14471 14471 break; \ … … 14495 14495 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14496 14496 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14497 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14497 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14498 14498 IEM_MC_END(); \ 14499 14499 break; \ … … 14513 14513 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14514 14514 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14515 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14515 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14516 14516 IEM_MC_END(); \ 14517 14517 break; \ … … 14531 14531 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14532 14532 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14533 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14533 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14534 14534 IEM_MC_END(); \ 14535 14535 break; \ … … 14573 14573 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14574 14574 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14575 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14575 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14576 14576 IEM_MC_END(); \ 14577 14577 } \ … … 14593 14593 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14594 14594 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14595 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14595 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14596 14596 IEM_MC_END(); \ 14597 14597 } (void)0 … … 14620 14620 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14621 14621 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14622 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14622 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14623 14623 IEM_MC_END(); \ 14624 14624 break; \ … … 14640 14640 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xAX); \ 14641 14641 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xDX); \ 14642 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14642 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14643 14643 IEM_MC_END(); \ 14644 14644 break; \ … … 14658 14658 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14659 14659 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14660 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14660 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14661 14661 IEM_MC_END(); \ 14662 14662 break; \ … … 14687 14687 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14688 14688 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14689 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14689 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14690 14690 IEM_MC_END(); \ 14691 14691 break; \ … … 14710 14710 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xDX); \ 14711 14711 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14712 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14712 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14713 14713 IEM_MC_END(); \ 14714 14714 break; \ … … 14731 14731 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14732 14732 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14733 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14733 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14734 14734 IEM_MC_END(); \ 14735 14735 break; \ … … 14962 14962 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14963 14963 IEM_MC_CLEAR_EFL_BIT(X86_EFL_CF); 14964 IEM_MC_ADVANCE_ RIP_AND_FINISH();14964 IEM_MC_ADVANCE_PC_AND_FINISH(); 14965 14965 IEM_MC_END(); 14966 14966 } … … 14978 14978 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14979 14979 IEM_MC_SET_EFL_BIT(X86_EFL_CF); 14980 IEM_MC_ADVANCE_ RIP_AND_FINISH();14980 IEM_MC_ADVANCE_PC_AND_FINISH(); 14981 14981 IEM_MC_END(); 14982 14982 } … … 15021 15021 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 15022 15022 IEM_MC_CLEAR_EFL_BIT(X86_EFL_DF); 15023 IEM_MC_ADVANCE_ RIP_AND_FINISH();15023 IEM_MC_ADVANCE_PC_AND_FINISH(); 15024 15024 IEM_MC_END(); 15025 15025 } … … 15037 15037 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 15038 15038 IEM_MC_SET_EFL_BIT(X86_EFL_DF); 15039 IEM_MC_ADVANCE_ RIP_AND_FINISH();15039 IEM_MC_ADVANCE_PC_AND_FINISH(); 15040 15040 IEM_MC_END(); 15041 15041 } … … 15400 15400 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15401 15401 IEM_MC_PUSH_U16(u16Src); 15402 IEM_MC_ADVANCE_ RIP_AND_FINISH();15402 IEM_MC_ADVANCE_PC_AND_FINISH(); 15403 15403 IEM_MC_END(); 15404 15404 break; … … 15412 15412 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15413 15413 IEM_MC_PUSH_U32(u32Src); 15414 IEM_MC_ADVANCE_ RIP_AND_FINISH();15414 IEM_MC_ADVANCE_PC_AND_FINISH(); 15415 15415 IEM_MC_END(); 15416 15416 break; … … 15424 15424 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15425 15425 IEM_MC_PUSH_U64(u64Src); 15426 IEM_MC_ADVANCE_ RIP_AND_FINISH();15426 IEM_MC_ADVANCE_PC_AND_FINISH(); 15427 15427 IEM_MC_END(); 15428 15428 break; -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstThree0f38-x86.cpp.h
r108204 r108267 64 64 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 65 65 66 IEM_MC_ADVANCE_ RIP_AND_FINISH();66 IEM_MC_ADVANCE_PC_AND_FINISH(); 67 67 IEM_MC_END(); 68 68 } … … 90 90 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 91 91 92 IEM_MC_ADVANCE_ RIP_AND_FINISH();92 IEM_MC_ADVANCE_PC_AND_FINISH(); 93 93 IEM_MC_END(); 94 94 } … … 124 124 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 125 125 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 126 IEM_MC_ADVANCE_ RIP_AND_FINISH();126 IEM_MC_ADVANCE_PC_AND_FINISH(); 127 127 IEM_MC_END(); 128 128 } … … 147 147 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 148 148 149 IEM_MC_ADVANCE_ RIP_AND_FINISH();149 IEM_MC_ADVANCE_PC_AND_FINISH(); 150 150 IEM_MC_END(); 151 151 } … … 182 182 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 183 183 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 184 IEM_MC_ADVANCE_ RIP_AND_FINISH();184 IEM_MC_ADVANCE_PC_AND_FINISH(); 185 185 IEM_MC_END(); 186 186 } … … 205 205 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 206 206 207 IEM_MC_ADVANCE_ RIP_AND_FINISH();207 IEM_MC_ADVANCE_PC_AND_FINISH(); 208 208 IEM_MC_END(); 209 209 } … … 238 238 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 239 239 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 240 IEM_MC_ADVANCE_ RIP_AND_FINISH();240 IEM_MC_ADVANCE_PC_AND_FINISH(); 241 241 IEM_MC_END(); 242 242 } … … 261 261 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 262 262 263 IEM_MC_ADVANCE_ RIP_AND_FINISH();263 IEM_MC_ADVANCE_PC_AND_FINISH(); 264 264 IEM_MC_END(); 265 265 } … … 297 297 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 298 298 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 299 IEM_MC_ADVANCE_ RIP_AND_FINISH();299 IEM_MC_ADVANCE_PC_AND_FINISH(); 300 300 IEM_MC_END(); 301 301 } … … 320 320 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 321 321 322 IEM_MC_ADVANCE_ RIP_AND_FINISH();322 IEM_MC_ADVANCE_PC_AND_FINISH(); 323 323 IEM_MC_END(); 324 324 } … … 357 357 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 358 358 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 359 IEM_MC_ADVANCE_ RIP_AND_FINISH();359 IEM_MC_ADVANCE_PC_AND_FINISH(); 360 360 IEM_MC_END(); 361 361 } … … 380 380 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 381 381 382 IEM_MC_ADVANCE_ RIP_AND_FINISH();382 IEM_MC_ADVANCE_PC_AND_FINISH(); 383 383 IEM_MC_END(); 384 384 } … … 650 650 iemAImpl_ ## a_Instr ## _u128_fallback), \ 651 651 puDst, puSrc, puMask); \ 652 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \652 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 653 653 IEM_MC_END(); \ 654 654 } \ … … 675 675 iemAImpl_ ## a_Instr ## _u128_fallback), \ 676 676 puDst, puSrc, puMask); \ 677 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \677 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 678 678 IEM_MC_END(); \ 679 679 } \ … … 750 750 IEM_MC_REF_EFLAGS(pEFlags); 751 751 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags); 752 IEM_MC_ADVANCE_ RIP_AND_FINISH();752 IEM_MC_ADVANCE_PC_AND_FINISH(); 753 753 IEM_MC_END(); 754 754 } … … 775 775 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags); 776 776 777 IEM_MC_ADVANCE_ RIP_AND_FINISH();777 IEM_MC_ADVANCE_PC_AND_FINISH(); 778 778 IEM_MC_END(); 779 779 } … … 876 876 puDst, uSrc); \ 877 877 } IEM_MC_NATIVE_ENDIF(); \ 878 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \878 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 879 879 IEM_MC_END(); \ 880 880 } \ … … 902 902 puDst, uSrc); \ 903 903 } IEM_MC_NATIVE_ENDIF(); \ 904 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \904 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 905 905 IEM_MC_END(); \ 906 906 } \ … … 1013 1013 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1014 1014 1015 IEM_MC_ADVANCE_ RIP_AND_FINISH();1015 IEM_MC_ADVANCE_PC_AND_FINISH(); 1016 1016 IEM_MC_END(); 1017 1017 } … … 1545 1545 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback), 1546 1546 puDst, puSrc, puXmm0); 1547 IEM_MC_ADVANCE_ RIP_AND_FINISH();1547 IEM_MC_ADVANCE_PC_AND_FINISH(); 1548 1548 IEM_MC_END(); 1549 1549 } … … 1570 1570 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fSha, iemAImpl_sha256rnds2_u128, iemAImpl_sha256rnds2_u128_fallback), 1571 1571 puDst, puSrc, puXmm0); 1572 IEM_MC_ADVANCE_ RIP_AND_FINISH();1572 IEM_MC_ADVANCE_PC_AND_FINISH(); 1573 1573 IEM_MC_END(); 1574 1574 } … … 1709 1709 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1710 1710 1711 IEM_MC_ADVANCE_ RIP_AND_FINISH();1711 IEM_MC_ADVANCE_PC_AND_FINISH(); 1712 1712 IEM_MC_END(); 1713 1713 break; … … 1725 1725 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1726 1726 1727 IEM_MC_ADVANCE_ RIP_AND_FINISH();1727 IEM_MC_ADVANCE_PC_AND_FINISH(); 1728 1728 IEM_MC_END(); 1729 1729 break; … … 1741 1741 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1742 1742 1743 IEM_MC_ADVANCE_ RIP_AND_FINISH();1743 IEM_MC_ADVANCE_PC_AND_FINISH(); 1744 1744 IEM_MC_END(); 1745 1745 break; … … 1780 1780 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fSse42, iemAImpl_crc32_u8, iemAImpl_crc32_u8_fallback), puDst, uSrc); 1781 1781 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1782 IEM_MC_ADVANCE_ RIP_AND_FINISH();1782 IEM_MC_ADVANCE_PC_AND_FINISH(); 1783 1783 IEM_MC_END(); 1784 1784 } … … 1801 1801 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1802 1802 1803 IEM_MC_ADVANCE_ RIP_AND_FINISH();1803 IEM_MC_ADVANCE_PC_AND_FINISH(); 1804 1804 IEM_MC_END(); 1805 1805 } … … 1831 1831 IEM_MC_BSWAP_LOCAL_U16(u16Value); 1832 1832 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value); 1833 IEM_MC_ADVANCE_ RIP_AND_FINISH();1833 IEM_MC_ADVANCE_PC_AND_FINISH(); 1834 1834 IEM_MC_END(); 1835 1835 break; … … 1844 1844 IEM_MC_BSWAP_LOCAL_U32(u32Value); 1845 1845 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value); 1846 IEM_MC_ADVANCE_ RIP_AND_FINISH();1846 IEM_MC_ADVANCE_PC_AND_FINISH(); 1847 1847 IEM_MC_END(); 1848 1848 break; … … 1857 1857 IEM_MC_BSWAP_LOCAL_U64(u64Value); 1858 1858 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value); 1859 IEM_MC_ADVANCE_ RIP_AND_FINISH();1859 IEM_MC_ADVANCE_PC_AND_FINISH(); 1860 1860 IEM_MC_END(); 1861 1861 break; … … 1900 1900 puDst, uSrc); 1901 1901 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1902 IEM_MC_ADVANCE_ RIP_AND_FINISH();1902 IEM_MC_ADVANCE_PC_AND_FINISH(); 1903 1903 IEM_MC_END(); 1904 1904 break; … … 1914 1914 puDst, uSrc); 1915 1915 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1916 IEM_MC_ADVANCE_ RIP_AND_FINISH();1916 IEM_MC_ADVANCE_PC_AND_FINISH(); 1917 1917 IEM_MC_END(); 1918 1918 break; … … 1928 1928 puDst, uSrc); 1929 1929 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1930 IEM_MC_ADVANCE_ RIP_AND_FINISH();1930 IEM_MC_ADVANCE_PC_AND_FINISH(); 1931 1931 IEM_MC_END(); 1932 1932 break; … … 1957 1957 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1958 1958 1959 IEM_MC_ADVANCE_ RIP_AND_FINISH();1959 IEM_MC_ADVANCE_PC_AND_FINISH(); 1960 1960 IEM_MC_END(); 1961 1961 break; … … 1976 1976 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1977 1977 1978 IEM_MC_ADVANCE_ RIP_AND_FINISH();1978 IEM_MC_ADVANCE_PC_AND_FINISH(); 1979 1979 IEM_MC_END(); 1980 1980 break; … … 1995 1995 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 1996 1996 1997 IEM_MC_ADVANCE_ RIP_AND_FINISH();1997 IEM_MC_ADVANCE_PC_AND_FINISH(); 1998 1998 IEM_MC_END(); 1999 1999 break; … … 2048 2048 fEFlagsIn, pu64Dst, u64Src); \ 2049 2049 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2050 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2050 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2051 2051 IEM_MC_END(); \ 2052 2052 } \ … … 2067 2067 fEFlagsIn, pu64Dst, u64Src); \ 2068 2068 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2069 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2069 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2070 2070 IEM_MC_END(); \ 2071 2071 } \ … … 2086 2086 fEFlagsIn, pu32Dst, u32Src); \ 2087 2087 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2088 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2088 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2089 2089 IEM_MC_END(); \ 2090 2090 } \ … … 2105 2105 fEFlagsIn, pu32Dst, u32Src); \ 2106 2106 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2107 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2107 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2108 2108 IEM_MC_END(); \ 2109 2109 } \ -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstThree0f3a-x86.cpp.h
r108204 r108267 62 62 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 63 63 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 64 IEM_MC_ADVANCE_ RIP_AND_FINISH();64 IEM_MC_ADVANCE_PC_AND_FINISH(); 65 65 IEM_MC_END(); 66 66 } … … 87 87 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 88 88 89 IEM_MC_ADVANCE_ RIP_AND_FINISH();89 IEM_MC_ADVANCE_PC_AND_FINISH(); 90 90 IEM_MC_END(); 91 91 } … … 121 121 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 122 122 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 123 IEM_MC_ADVANCE_ RIP_AND_FINISH();123 IEM_MC_ADVANCE_PC_AND_FINISH(); 124 124 IEM_MC_END(); 125 125 } … … 146 146 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 147 147 148 IEM_MC_ADVANCE_ RIP_AND_FINISH();148 IEM_MC_ADVANCE_PC_AND_FINISH(); 149 149 IEM_MC_END(); 150 150 } … … 185 185 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 186 186 187 IEM_MC_ADVANCE_ RIP_AND_FINISH();187 IEM_MC_ADVANCE_PC_AND_FINISH(); 188 188 IEM_MC_END(); 189 189 } … … 211 211 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 212 212 213 IEM_MC_ADVANCE_ RIP_AND_FINISH();213 IEM_MC_ADVANCE_PC_AND_FINISH(); 214 214 IEM_MC_END(); 215 215 } … … 247 247 IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 248 248 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 249 IEM_MC_ADVANCE_ RIP_AND_FINISH();249 IEM_MC_ADVANCE_PC_AND_FINISH(); 250 250 IEM_MC_END(); 251 251 } … … 270 270 IEM_MC_CALL_SSE_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 271 271 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 272 IEM_MC_ADVANCE_ RIP_AND_FINISH();272 IEM_MC_ADVANCE_PC_AND_FINISH(); 273 273 IEM_MC_END(); 274 274 } … … 305 305 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 306 306 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 307 IEM_MC_ADVANCE_ RIP_AND_FINISH();307 IEM_MC_ADVANCE_PC_AND_FINISH(); 308 308 IEM_MC_END(); 309 309 } … … 330 330 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 331 331 332 IEM_MC_ADVANCE_ RIP_AND_FINISH();332 IEM_MC_ADVANCE_PC_AND_FINISH(); 333 333 IEM_MC_END(); 334 334 } … … 388 388 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 389 389 390 IEM_MC_ADVANCE_ RIP_AND_FINISH();390 IEM_MC_ADVANCE_PC_AND_FINISH(); 391 391 IEM_MC_END(); 392 392 } … … 415 415 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 416 416 417 IEM_MC_ADVANCE_ RIP_AND_FINISH();417 IEM_MC_ADVANCE_PC_AND_FINISH(); 418 418 IEM_MC_END(); 419 419 } … … 446 446 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst); 447 447 448 IEM_MC_ADVANCE_ RIP_AND_FINISH();448 IEM_MC_ADVANCE_PC_AND_FINISH(); 449 449 IEM_MC_END(); 450 450 } … … 473 473 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst); 474 474 475 IEM_MC_ADVANCE_ RIP_AND_FINISH();475 IEM_MC_ADVANCE_PC_AND_FINISH(); 476 476 IEM_MC_END(); 477 477 } … … 532 532 pDst, uSrc, bImmArg); 533 533 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 534 IEM_MC_ADVANCE_ RIP_AND_FINISH();534 IEM_MC_ADVANCE_PC_AND_FINISH(); 535 535 IEM_MC_END(); 536 536 } … … 559 559 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 560 560 561 IEM_MC_ADVANCE_ RIP_AND_FINISH();561 IEM_MC_ADVANCE_PC_AND_FINISH(); 562 562 IEM_MC_END(); 563 563 } … … 598 598 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/); 599 599 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 600 IEM_MC_ADVANCE_ RIP_AND_FINISH();600 IEM_MC_ADVANCE_PC_AND_FINISH(); 601 601 IEM_MC_END(); 602 602 } … … 618 618 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/); 619 619 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 620 IEM_MC_ADVANCE_ RIP_AND_FINISH();620 IEM_MC_ADVANCE_PC_AND_FINISH(); 621 621 IEM_MC_END(); 622 622 } … … 642 642 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /*a_iWord*/); 643 643 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 644 IEM_MC_ADVANCE_ RIP_AND_FINISH();644 IEM_MC_ADVANCE_PC_AND_FINISH(); 645 645 IEM_MC_END(); 646 646 } … … 662 662 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7 /*a_iWord*/); 663 663 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 664 IEM_MC_ADVANCE_ RIP_AND_FINISH();664 IEM_MC_ADVANCE_PC_AND_FINISH(); 665 665 IEM_MC_END(); 666 666 } … … 693 693 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/); 694 694 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc); 695 IEM_MC_ADVANCE_ RIP_AND_FINISH();695 IEM_MC_ADVANCE_PC_AND_FINISH(); 696 696 IEM_MC_END(); 697 697 } … … 713 713 IEM_MC_FETCH_XREG_U64(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/); 714 714 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 715 IEM_MC_ADVANCE_ RIP_AND_FINISH();715 IEM_MC_ADVANCE_PC_AND_FINISH(); 716 716 IEM_MC_END(); 717 717 } … … 740 740 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 741 741 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc); 742 IEM_MC_ADVANCE_ RIP_AND_FINISH();742 IEM_MC_ADVANCE_PC_AND_FINISH(); 743 743 IEM_MC_END(); 744 744 } … … 759 759 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 760 760 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 761 IEM_MC_ADVANCE_ RIP_AND_FINISH();761 IEM_MC_ADVANCE_PC_AND_FINISH(); 762 762 IEM_MC_END(); 763 763 } … … 784 784 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 785 785 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc); 786 IEM_MC_ADVANCE_ RIP_AND_FINISH();786 IEM_MC_ADVANCE_PC_AND_FINISH(); 787 787 IEM_MC_END(); 788 788 } … … 803 803 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 804 804 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 805 IEM_MC_ADVANCE_ RIP_AND_FINISH();805 IEM_MC_ADVANCE_PC_AND_FINISH(); 806 806 IEM_MC_END(); 807 807 } … … 837 837 IEM_MC_FETCH_GREG_U8(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 838 838 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/, uSrc); 839 IEM_MC_ADVANCE_ RIP_AND_FINISH();839 IEM_MC_ADVANCE_PC_AND_FINISH(); 840 840 IEM_MC_END(); 841 841 } … … 857 857 IEM_MC_FETCH_MEM_U8(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 858 858 IEM_MC_STORE_XREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/, uSrc); 859 IEM_MC_ADVANCE_ RIP_AND_FINISH();859 IEM_MC_ADVANCE_PC_AND_FINISH(); 860 860 IEM_MC_END(); 861 861 } … … 883 883 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm); 884 884 885 IEM_MC_ADVANCE_ RIP_AND_FINISH();885 IEM_MC_ADVANCE_PC_AND_FINISH(); 886 886 IEM_MC_END(); 887 887 } … … 904 904 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc); 905 905 IEM_MC_CLEAR_XREG_U32_MASK(IEM_GET_MODRM_REG(pVCpu, bRm), bImm); 906 IEM_MC_ADVANCE_ RIP_AND_FINISH();906 IEM_MC_ADVANCE_PC_AND_FINISH(); 907 907 IEM_MC_END(); 908 908 } … … 934 934 IEM_MC_FETCH_GREG_U64(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 935 935 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/, uSrc); 936 IEM_MC_ADVANCE_ RIP_AND_FINISH();936 IEM_MC_ADVANCE_PC_AND_FINISH(); 937 937 IEM_MC_END(); 938 938 } … … 954 954 IEM_MC_FETCH_MEM_U64(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 955 955 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1 /*a_iQword*/, uSrc); 956 IEM_MC_ADVANCE_ RIP_AND_FINISH();956 IEM_MC_ADVANCE_PC_AND_FINISH(); 957 957 IEM_MC_END(); 958 958 } … … 981 981 IEM_MC_FETCH_GREG_U32(uSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 982 982 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/, uSrc); 983 IEM_MC_ADVANCE_ RIP_AND_FINISH();983 IEM_MC_ADVANCE_PC_AND_FINISH(); 984 984 IEM_MC_END(); 985 985 } … … 1001 1001 IEM_MC_FETCH_MEM_U32(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1002 1002 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/, uSrc); 1003 IEM_MC_ADVANCE_ RIP_AND_FINISH();1003 IEM_MC_ADVANCE_PC_AND_FINISH(); 1004 1004 IEM_MC_END(); 1005 1005 } … … 1096 1096 iemAImpl_pclmulqdq_u128_fallback), 1097 1097 puDst, puSrc, bImmArg); 1098 IEM_MC_ADVANCE_ RIP_AND_FINISH();1098 IEM_MC_ADVANCE_PC_AND_FINISH(); 1099 1099 IEM_MC_END(); 1100 1100 } … … 1124 1124 puDst, puSrc, bImmArg); 1125 1125 1126 IEM_MC_ADVANCE_ RIP_AND_FINISH();1126 IEM_MC_ADVANCE_PC_AND_FINISH(); 1127 1127 IEM_MC_END(); 1128 1128 } … … 1196 1196 iemAImpl_pcmpestrm_u128_fallback), 1197 1197 puDst, pEFlags, pSrc, bImmArg); 1198 IEM_MC_ADVANCE_ RIP_AND_FINISH();1198 IEM_MC_ADVANCE_PC_AND_FINISH(); 1199 1199 IEM_MC_END(); 1200 1200 } … … 1226 1226 iemAImpl_pcmpestrm_u128_fallback), 1227 1227 puDst, pEFlags, pSrc, bImmArg); 1228 IEM_MC_ADVANCE_ RIP_AND_FINISH();1228 IEM_MC_ADVANCE_PC_AND_FINISH(); 1229 1229 IEM_MC_END(); 1230 1230 } … … 1254 1254 iemAImpl_pcmpestrm_u128_fallback), 1255 1255 puDst, pEFlags, pSrc, bImmArg); 1256 IEM_MC_ADVANCE_ RIP_AND_FINISH();1256 IEM_MC_ADVANCE_PC_AND_FINISH(); 1257 1257 IEM_MC_END(); 1258 1258 } … … 1284 1284 iemAImpl_pcmpestrm_u128_fallback), 1285 1285 puDst, pEFlags, pSrc, bImmArg); 1286 IEM_MC_ADVANCE_ RIP_AND_FINISH();1286 IEM_MC_ADVANCE_PC_AND_FINISH(); 1287 1287 IEM_MC_END(); 1288 1288 } … … 1328 1328 pu32Ecx, pEFlags, pSrc, bImmArg); 1329 1329 /** @todo testcase: High dword of RCX cleared? */ 1330 IEM_MC_ADVANCE_ RIP_AND_FINISH();1330 IEM_MC_ADVANCE_PC_AND_FINISH(); 1331 1331 IEM_MC_END(); 1332 1332 } … … 1360 1360 pu32Ecx, pEFlags, pSrc, bImmArg); 1361 1361 /** @todo testcase: High dword of RCX cleared? */ 1362 IEM_MC_ADVANCE_ RIP_AND_FINISH();1362 IEM_MC_ADVANCE_PC_AND_FINISH(); 1363 1363 IEM_MC_END(); 1364 1364 } … … 1390 1390 pu32Ecx, pEFlags, pSrc, bImmArg); 1391 1391 /** @todo testcase: High dword of RCX cleared? */ 1392 IEM_MC_ADVANCE_ RIP_AND_FINISH();1392 IEM_MC_ADVANCE_PC_AND_FINISH(); 1393 1393 IEM_MC_END(); 1394 1394 } … … 1422 1422 pu32Ecx, pEFlags, pSrc, bImmArg); 1423 1423 /** @todo testcase: High dword of RCX cleared? */ 1424 IEM_MC_ADVANCE_ RIP_AND_FINISH();1424 IEM_MC_ADVANCE_PC_AND_FINISH(); 1425 1425 IEM_MC_END(); 1426 1426 } … … 1462 1462 iemAImpl_pcmpistrm_u128_fallback), 1463 1463 puDst, pEFlags, pSrc, bImmArg); 1464 IEM_MC_ADVANCE_ RIP_AND_FINISH();1464 IEM_MC_ADVANCE_PC_AND_FINISH(); 1465 1465 IEM_MC_END(); 1466 1466 } … … 1491 1491 iemAImpl_pcmpistrm_u128_fallback), 1492 1492 puDst, pEFlags, pSrc, bImmArg); 1493 IEM_MC_ADVANCE_ RIP_AND_FINISH();1493 IEM_MC_ADVANCE_PC_AND_FINISH(); 1494 1494 IEM_MC_END(); 1495 1495 } … … 1534 1534 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX); 1535 1535 1536 IEM_MC_ADVANCE_ RIP_AND_FINISH();1536 IEM_MC_ADVANCE_PC_AND_FINISH(); 1537 1537 IEM_MC_END(); 1538 1538 } … … 1567 1567 IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx); 1568 1568 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX); 1569 IEM_MC_ADVANCE_ RIP_AND_FINISH();1569 IEM_MC_ADVANCE_PC_AND_FINISH(); 1570 1570 IEM_MC_END(); 1571 1571 } … … 1628 1628 iemAImpl_sha1rnds4_u128_fallback), 1629 1629 puDst, puSrc, bImmArg); 1630 IEM_MC_ADVANCE_ RIP_AND_FINISH();1630 IEM_MC_ADVANCE_PC_AND_FINISH(); 1631 1631 IEM_MC_END(); 1632 1632 } … … 1655 1655 iemAImpl_sha1rnds4_u128_fallback), 1656 1656 puDst, puSrc, bImmArg); 1657 IEM_MC_ADVANCE_ RIP_AND_FINISH();1657 IEM_MC_ADVANCE_PC_AND_FINISH(); 1658 1658 IEM_MC_END(); 1659 1659 } -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstTwoByte0f-x86.cpp.h
r108204 r108267 65 65 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 66 66 67 IEM_MC_ADVANCE_ RIP_AND_FINISH();67 IEM_MC_ADVANCE_PC_AND_FINISH(); 68 68 IEM_MC_END(); 69 69 } … … 91 91 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 92 92 93 IEM_MC_ADVANCE_ RIP_AND_FINISH();93 IEM_MC_ADVANCE_PC_AND_FINISH(); 94 94 IEM_MC_END(); 95 95 } … … 127 127 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 128 128 129 IEM_MC_ADVANCE_ RIP_AND_FINISH();129 IEM_MC_ADVANCE_PC_AND_FINISH(); 130 130 IEM_MC_END(); 131 131 } … … 153 153 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 154 154 155 IEM_MC_ADVANCE_ RIP_AND_FINISH();155 IEM_MC_ADVANCE_PC_AND_FINISH(); 156 156 IEM_MC_END(); 157 157 } … … 187 187 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 188 188 189 IEM_MC_ADVANCE_ RIP_AND_FINISH();189 IEM_MC_ADVANCE_PC_AND_FINISH(); 190 190 IEM_MC_END(); 191 191 } … … 213 213 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 214 214 215 IEM_MC_ADVANCE_ RIP_AND_FINISH();215 IEM_MC_ADVANCE_PC_AND_FINISH(); 216 216 IEM_MC_END(); 217 217 } … … 247 247 IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 248 248 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); 249 IEM_MC_ADVANCE_ RIP_AND_FINISH();249 IEM_MC_ADVANCE_PC_AND_FINISH(); 250 250 IEM_MC_END(); 251 251 } … … 270 270 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); 271 271 272 IEM_MC_ADVANCE_ RIP_AND_FINISH();272 IEM_MC_ADVANCE_PC_AND_FINISH(); 273 273 IEM_MC_END(); 274 274 } … … 304 304 IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 305 305 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); 306 IEM_MC_ADVANCE_ RIP_AND_FINISH();306 IEM_MC_ADVANCE_PC_AND_FINISH(); 307 307 IEM_MC_END(); 308 308 } … … 327 327 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); 328 328 329 IEM_MC_ADVANCE_ RIP_AND_FINISH();329 IEM_MC_ADVANCE_PC_AND_FINISH(); 330 330 IEM_MC_END(); 331 331 } … … 358 358 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); \ 359 359 } IEM_MC_NATIVE_ENDIF(); \ 360 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \360 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 361 361 IEM_MC_END(); \ 362 362 } \ … … 382 382 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, pSrc); \ 383 383 } IEM_MC_NATIVE_ENDIF(); \ 384 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \384 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 385 385 IEM_MC_END(); \ 386 386 } void(0) … … 415 415 IEM_MC_MODIFIED_MREG_BY_REF(puDst); 416 416 417 IEM_MC_ADVANCE_ RIP_AND_FINISH();417 IEM_MC_ADVANCE_PC_AND_FINISH(); 418 418 IEM_MC_END(); 419 419 } … … 441 441 IEM_MC_MODIFIED_MREG_BY_REF(puDst); 442 442 443 IEM_MC_ADVANCE_ RIP_AND_FINISH();443 IEM_MC_ADVANCE_PC_AND_FINISH(); 444 444 IEM_MC_END(); 445 445 } … … 473 473 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 474 474 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 475 IEM_MC_ADVANCE_ RIP_AND_FINISH();475 IEM_MC_ADVANCE_PC_AND_FINISH(); 476 476 IEM_MC_END(); 477 477 } … … 501 501 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 502 502 503 IEM_MC_ADVANCE_ RIP_AND_FINISH();503 IEM_MC_ADVANCE_PC_AND_FINISH(); 504 504 IEM_MC_END(); 505 505 } … … 533 533 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 534 534 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 535 IEM_MC_ADVANCE_ RIP_AND_FINISH();535 IEM_MC_ADVANCE_PC_AND_FINISH(); 536 536 IEM_MC_END(); 537 537 } … … 561 561 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 562 562 563 IEM_MC_ADVANCE_ RIP_AND_FINISH();563 IEM_MC_ADVANCE_PC_AND_FINISH(); 564 564 IEM_MC_END(); 565 565 } … … 597 597 IEM_MC_MODIFIED_MREG_BY_REF(puDst); 598 598 599 IEM_MC_ADVANCE_ RIP_AND_FINISH();599 IEM_MC_ADVANCE_PC_AND_FINISH(); 600 600 IEM_MC_END(); 601 601 } … … 623 623 IEM_MC_MODIFIED_MREG_BY_REF(puDst); 624 624 625 IEM_MC_ADVANCE_ RIP_AND_FINISH();625 IEM_MC_ADVANCE_PC_AND_FINISH(); 626 626 IEM_MC_END(); 627 627 } … … 655 655 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 656 656 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 657 IEM_MC_ADVANCE_ RIP_AND_FINISH();657 IEM_MC_ADVANCE_PC_AND_FINISH(); 658 658 IEM_MC_END(); 659 659 } … … 683 683 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 684 684 685 IEM_MC_ADVANCE_ RIP_AND_FINISH();685 IEM_MC_ADVANCE_PC_AND_FINISH(); 686 686 IEM_MC_END(); 687 687 } … … 719 719 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 720 720 721 IEM_MC_ADVANCE_ RIP_AND_FINISH();721 IEM_MC_ADVANCE_PC_AND_FINISH(); 722 722 IEM_MC_END(); 723 723 } … … 745 745 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 746 746 747 IEM_MC_ADVANCE_ RIP_AND_FINISH();747 IEM_MC_ADVANCE_PC_AND_FINISH(); 748 748 IEM_MC_END(); 749 749 } … … 780 780 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); \ 781 781 } IEM_MC_NATIVE_ENDIF(); \ 782 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \782 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 783 783 IEM_MC_END(); \ 784 784 } \ … … 808 808 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); \ 809 809 } IEM_MC_NATIVE_ENDIF(); \ 810 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \810 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 811 811 IEM_MC_END(); \ 812 812 } void(0) … … 843 843 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 844 844 845 IEM_MC_ADVANCE_ RIP_AND_FINISH();845 IEM_MC_ADVANCE_PC_AND_FINISH(); 846 846 IEM_MC_END(); 847 847 } … … 869 869 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 870 870 871 IEM_MC_ADVANCE_ RIP_AND_FINISH();871 IEM_MC_ADVANCE_PC_AND_FINISH(); 872 872 IEM_MC_END(); 873 873 } … … 905 905 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 906 906 907 IEM_MC_ADVANCE_ RIP_AND_FINISH();907 IEM_MC_ADVANCE_PC_AND_FINISH(); 908 908 IEM_MC_END(); 909 909 } … … 931 931 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 932 932 933 IEM_MC_ADVANCE_ RIP_AND_FINISH();933 IEM_MC_ADVANCE_PC_AND_FINISH(); 934 934 IEM_MC_END(); 935 935 } … … 967 967 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 968 968 969 IEM_MC_ADVANCE_ RIP_AND_FINISH();969 IEM_MC_ADVANCE_PC_AND_FINISH(); 970 970 IEM_MC_END(); 971 971 } … … 993 993 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 994 994 995 IEM_MC_ADVANCE_ RIP_AND_FINISH();995 IEM_MC_ADVANCE_PC_AND_FINISH(); 996 996 IEM_MC_END(); 997 997 } … … 1025 1025 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 1026 1026 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 1027 IEM_MC_ADVANCE_ RIP_AND_FINISH();1027 IEM_MC_ADVANCE_PC_AND_FINISH(); 1028 1028 IEM_MC_END(); 1029 1029 } … … 1053 1053 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, puDst, puSrc); 1054 1054 1055 IEM_MC_ADVANCE_ RIP_AND_FINISH();1055 IEM_MC_ADVANCE_PC_AND_FINISH(); 1056 1056 IEM_MC_END(); 1057 1057 } … … 1089 1089 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 1090 1090 1091 IEM_MC_ADVANCE_ RIP_AND_FINISH();1091 IEM_MC_ADVANCE_PC_AND_FINISH(); 1092 1092 IEM_MC_END(); 1093 1093 } … … 1115 1115 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 1116 1116 1117 IEM_MC_ADVANCE_ RIP_AND_FINISH();1117 IEM_MC_ADVANCE_PC_AND_FINISH(); 1118 1118 IEM_MC_END(); 1119 1119 } … … 2010 2010 /* Currently a NOP. */ 2011 2011 IEM_MC_NOREF(GCPtrEffSrc); 2012 IEM_MC_ADVANCE_ RIP_AND_FINISH();2012 IEM_MC_ADVANCE_PC_AND_FINISH(); 2013 2013 IEM_MC_END(); 2014 2014 } … … 2026 2026 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 2027 2027 IEM_MC_FPU_FROM_MMX_MODE(); 2028 IEM_MC_ADVANCE_ RIP_AND_FINISH();2028 IEM_MC_ADVANCE_PC_AND_FINISH(); 2029 2029 IEM_MC_END(); 2030 2030 } … … 2075 2075 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2076 2076 IEM_GET_MODRM_RM(pVCpu, bRm)); 2077 IEM_MC_ADVANCE_ RIP_AND_FINISH();2077 IEM_MC_ADVANCE_PC_AND_FINISH(); 2078 2078 IEM_MC_END(); 2079 2079 } … … 2095 2095 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2096 2096 2097 IEM_MC_ADVANCE_ RIP_AND_FINISH();2097 IEM_MC_ADVANCE_PC_AND_FINISH(); 2098 2098 IEM_MC_END(); 2099 2099 } … … 2126 2126 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 2127 2127 IEM_GET_MODRM_RM(pVCpu, bRm)); 2128 IEM_MC_ADVANCE_ RIP_AND_FINISH();2128 IEM_MC_ADVANCE_PC_AND_FINISH(); 2129 2129 IEM_MC_END(); 2130 2130 } … … 2146 2146 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2147 2147 2148 IEM_MC_ADVANCE_ RIP_AND_FINISH();2148 IEM_MC_ADVANCE_PC_AND_FINISH(); 2149 2149 IEM_MC_END(); 2150 2150 } … … 2179 2179 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, uSrc); 2180 2180 2181 IEM_MC_ADVANCE_ RIP_AND_FINISH();2181 IEM_MC_ADVANCE_PC_AND_FINISH(); 2182 2182 IEM_MC_END(); 2183 2183 } … … 2199 2199 IEM_MC_STORE_XREG_U32_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2200 2200 2201 IEM_MC_ADVANCE_ RIP_AND_FINISH();2201 IEM_MC_ADVANCE_PC_AND_FINISH(); 2202 2202 IEM_MC_END(); 2203 2203 } … … 2232 2232 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc); 2233 2233 2234 IEM_MC_ADVANCE_ RIP_AND_FINISH();2234 IEM_MC_ADVANCE_PC_AND_FINISH(); 2235 2235 IEM_MC_END(); 2236 2236 } … … 2252 2252 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2253 2253 2254 IEM_MC_ADVANCE_ RIP_AND_FINISH();2254 IEM_MC_ADVANCE_PC_AND_FINISH(); 2255 2255 IEM_MC_END(); 2256 2256 } … … 2282 2282 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 2283 2283 IEM_GET_MODRM_REG(pVCpu, bRm)); 2284 IEM_MC_ADVANCE_ RIP_AND_FINISH();2284 IEM_MC_ADVANCE_PC_AND_FINISH(); 2285 2285 IEM_MC_END(); 2286 2286 } … … 2302 2302 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2303 2303 2304 IEM_MC_ADVANCE_ RIP_AND_FINISH();2304 IEM_MC_ADVANCE_PC_AND_FINISH(); 2305 2305 IEM_MC_END(); 2306 2306 } … … 2332 2332 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 2333 2333 IEM_GET_MODRM_REG(pVCpu, bRm)); 2334 IEM_MC_ADVANCE_ RIP_AND_FINISH();2334 IEM_MC_ADVANCE_PC_AND_FINISH(); 2335 2335 IEM_MC_END(); 2336 2336 } … … 2352 2352 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2353 2353 2354 IEM_MC_ADVANCE_ RIP_AND_FINISH();2354 IEM_MC_ADVANCE_PC_AND_FINISH(); 2355 2355 IEM_MC_END(); 2356 2356 } … … 2385 2385 IEM_MC_STORE_XREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), 0 /*a_iDword*/, uSrc); 2386 2386 2387 IEM_MC_ADVANCE_ RIP_AND_FINISH();2387 IEM_MC_ADVANCE_PC_AND_FINISH(); 2388 2388 IEM_MC_END(); 2389 2389 } … … 2405 2405 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2406 2406 2407 IEM_MC_ADVANCE_ RIP_AND_FINISH();2407 IEM_MC_ADVANCE_PC_AND_FINISH(); 2408 2408 IEM_MC_END(); 2409 2409 } … … 2438 2438 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), 0 /* a_iQword*/, uSrc); 2439 2439 2440 IEM_MC_ADVANCE_ RIP_AND_FINISH();2440 IEM_MC_ADVANCE_PC_AND_FINISH(); 2441 2441 IEM_MC_END(); 2442 2442 } … … 2458 2458 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2459 2459 2460 IEM_MC_ADVANCE_ RIP_AND_FINISH();2460 IEM_MC_ADVANCE_PC_AND_FINISH(); 2461 2461 IEM_MC_END(); 2462 2462 } … … 2490 2490 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc); 2491 2491 2492 IEM_MC_ADVANCE_ RIP_AND_FINISH();2492 IEM_MC_ADVANCE_PC_AND_FINISH(); 2493 2493 IEM_MC_END(); 2494 2494 } … … 2521 2521 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc); 2522 2522 2523 IEM_MC_ADVANCE_ RIP_AND_FINISH();2523 IEM_MC_ADVANCE_PC_AND_FINISH(); 2524 2524 IEM_MC_END(); 2525 2525 } … … 2556 2556 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /* a_iQword*/, uSrc); 2557 2557 2558 IEM_MC_ADVANCE_ RIP_AND_FINISH();2558 IEM_MC_ADVANCE_PC_AND_FINISH(); 2559 2559 IEM_MC_END(); 2560 2560 } … … 2606 2606 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2); 2607 2607 2608 IEM_MC_ADVANCE_ RIP_AND_FINISH();2608 IEM_MC_ADVANCE_PC_AND_FINISH(); 2609 2609 IEM_MC_END(); 2610 2610 } … … 2629 2629 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 2); 2630 2630 2631 IEM_MC_ADVANCE_ RIP_AND_FINISH();2631 IEM_MC_ADVANCE_PC_AND_FINISH(); 2632 2632 IEM_MC_END(); 2633 2633 } … … 2664 2664 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc); 2665 2665 2666 IEM_MC_ADVANCE_ RIP_AND_FINISH();2666 IEM_MC_ADVANCE_PC_AND_FINISH(); 2667 2667 IEM_MC_END(); 2668 2668 } … … 2685 2685 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /* a_iQword*/, uSrc); 2686 2686 2687 IEM_MC_ADVANCE_ RIP_AND_FINISH();2687 IEM_MC_ADVANCE_PC_AND_FINISH(); 2688 2688 IEM_MC_END(); 2689 2689 } … … 2720 2720 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2721 2721 2722 IEM_MC_ADVANCE_ RIP_AND_FINISH();2722 IEM_MC_ADVANCE_PC_AND_FINISH(); 2723 2723 IEM_MC_END(); 2724 2724 } … … 2768 2768 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2769 2769 2770 IEM_MC_ADVANCE_ RIP_AND_FINISH();2770 IEM_MC_ADVANCE_PC_AND_FINISH(); 2771 2771 IEM_MC_END(); 2772 2772 } … … 2910 2910 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQword*/, uSrc); 2911 2911 2912 IEM_MC_ADVANCE_ RIP_AND_FINISH();2912 IEM_MC_ADVANCE_PC_AND_FINISH(); 2913 2913 IEM_MC_END(); 2914 2914 } … … 2941 2941 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQword*/, uSrc); 2942 2942 2943 IEM_MC_ADVANCE_ RIP_AND_FINISH();2943 IEM_MC_ADVANCE_PC_AND_FINISH(); 2944 2944 IEM_MC_END(); 2945 2945 } … … 2976 2976 IEM_MC_STORE_XREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 1 /*a_iQword*/, uSrc); 2977 2977 2978 IEM_MC_ADVANCE_ RIP_AND_FINISH();2978 IEM_MC_ADVANCE_PC_AND_FINISH(); 2979 2979 IEM_MC_END(); 2980 2980 } … … 3026 3026 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3); 3027 3027 3028 IEM_MC_ADVANCE_ RIP_AND_FINISH();3028 IEM_MC_ADVANCE_PC_AND_FINISH(); 3029 3029 IEM_MC_END(); 3030 3030 } … … 3049 3049 IEM_MC_STORE_XREG_U32_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3, uSrc, 3); 3050 3050 3051 IEM_MC_ADVANCE_ RIP_AND_FINISH();3051 IEM_MC_ADVANCE_PC_AND_FINISH(); 3052 3052 IEM_MC_END(); 3053 3053 } … … 3095 3095 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3096 3096 3097 IEM_MC_ADVANCE_ RIP_AND_FINISH();3097 IEM_MC_ADVANCE_PC_AND_FINISH(); 3098 3098 IEM_MC_END(); 3099 3099 } … … 3143 3143 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3144 3144 3145 IEM_MC_ADVANCE_ RIP_AND_FINISH();3145 IEM_MC_ADVANCE_PC_AND_FINISH(); 3146 3146 IEM_MC_END(); 3147 3147 } … … 3209 3209 /* Currently a NOP. */ 3210 3210 IEM_MC_NOREF(GCPtrEffSrc); 3211 IEM_MC_ADVANCE_ RIP_AND_FINISH();3211 IEM_MC_ADVANCE_PC_AND_FINISH(); 3212 3212 IEM_MC_END(); 3213 3213 } … … 3226 3226 IEM_MC_BEGIN(0, 0); 3227 3227 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 3228 IEM_MC_ADVANCE_ RIP_AND_FINISH();3228 IEM_MC_ADVANCE_PC_AND_FINISH(); 3229 3229 IEM_MC_END(); 3230 3230 } … … 3237 3237 /* Currently a NOP. */ 3238 3238 IEM_MC_NOREF(GCPtrEffSrc); 3239 IEM_MC_ADVANCE_ RIP_AND_FINISH();3239 IEM_MC_ADVANCE_PC_AND_FINISH(); 3240 3240 IEM_MC_END(); 3241 3241 } … … 3399 3399 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3400 3400 IEM_GET_MODRM_RM(pVCpu, bRm)); 3401 IEM_MC_ADVANCE_ RIP_AND_FINISH();3401 IEM_MC_ADVANCE_PC_AND_FINISH(); 3402 3402 IEM_MC_END(); 3403 3403 } … … 3419 3419 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 3420 3420 3421 IEM_MC_ADVANCE_ RIP_AND_FINISH();3421 IEM_MC_ADVANCE_PC_AND_FINISH(); 3422 3422 IEM_MC_END(); 3423 3423 } … … 3448 3448 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 3449 3449 IEM_GET_MODRM_RM(pVCpu, bRm)); 3450 IEM_MC_ADVANCE_ RIP_AND_FINISH();3450 IEM_MC_ADVANCE_PC_AND_FINISH(); 3451 3451 IEM_MC_END(); 3452 3452 } … … 3468 3468 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 3469 3469 3470 IEM_MC_ADVANCE_ RIP_AND_FINISH();3470 IEM_MC_ADVANCE_PC_AND_FINISH(); 3471 3471 IEM_MC_END(); 3472 3472 } … … 3500 3500 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 3501 3501 IEM_GET_MODRM_REG(pVCpu, bRm)); 3502 IEM_MC_ADVANCE_ RIP_AND_FINISH();3502 IEM_MC_ADVANCE_PC_AND_FINISH(); 3503 3503 IEM_MC_END(); 3504 3504 } … … 3520 3520 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3521 3521 3522 IEM_MC_ADVANCE_ RIP_AND_FINISH();3522 IEM_MC_ADVANCE_PC_AND_FINISH(); 3523 3523 IEM_MC_END(); 3524 3524 } … … 3549 3549 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 3550 3550 IEM_GET_MODRM_REG(pVCpu, bRm)); 3551 IEM_MC_ADVANCE_ RIP_AND_FINISH();3551 IEM_MC_ADVANCE_PC_AND_FINISH(); 3552 3552 IEM_MC_END(); 3553 3553 } … … 3569 3569 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3570 3570 3571 IEM_MC_ADVANCE_ RIP_AND_FINISH();3571 IEM_MC_ADVANCE_PC_AND_FINISH(); 3572 3572 IEM_MC_END(); 3573 3573 } … … 3604 3604 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 3605 3605 3606 IEM_MC_ADVANCE_ RIP_AND_FINISH();3606 IEM_MC_ADVANCE_PC_AND_FINISH(); 3607 3607 IEM_MC_END(); 3608 3608 } … … 3630 3630 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 3631 3631 3632 IEM_MC_ADVANCE_ RIP_AND_FINISH();3632 IEM_MC_ADVANCE_PC_AND_FINISH(); 3633 3633 IEM_MC_END(); 3634 3634 } … … 3661 3661 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 3662 3662 3663 IEM_MC_ADVANCE_ RIP_AND_FINISH();3663 IEM_MC_ADVANCE_PC_AND_FINISH(); 3664 3664 IEM_MC_END(); 3665 3665 } … … 3687 3687 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 3688 3688 3689 IEM_MC_ADVANCE_ RIP_AND_FINISH();3689 IEM_MC_ADVANCE_PC_AND_FINISH(); 3690 3690 IEM_MC_END(); 3691 3691 } … … 3717 3717 IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst); 3718 3718 3719 IEM_MC_ADVANCE_ RIP_AND_FINISH();3719 IEM_MC_ADVANCE_PC_AND_FINISH(); 3720 3720 IEM_MC_END(); 3721 3721 } … … 3739 3739 IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst); 3740 3740 3741 IEM_MC_ADVANCE_ RIP_AND_FINISH();3741 IEM_MC_ADVANCE_PC_AND_FINISH(); 3742 3742 IEM_MC_END(); 3743 3743 } … … 3761 3761 IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst); 3762 3762 3763 IEM_MC_ADVANCE_ RIP_AND_FINISH();3763 IEM_MC_ADVANCE_PC_AND_FINISH(); 3764 3764 IEM_MC_END(); 3765 3765 } … … 3783 3783 IEM_MC_STORE_XREG_R32(IEM_GET_MODRM_REG(pVCpu, bRm), r32Dst); 3784 3784 3785 IEM_MC_ADVANCE_ RIP_AND_FINISH();3785 IEM_MC_ADVANCE_PC_AND_FINISH(); 3786 3786 IEM_MC_END(); 3787 3787 } … … 3814 3814 IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst); 3815 3815 3816 IEM_MC_ADVANCE_ RIP_AND_FINISH();3816 IEM_MC_ADVANCE_PC_AND_FINISH(); 3817 3817 IEM_MC_END(); 3818 3818 } … … 3836 3836 IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst); 3837 3837 3838 IEM_MC_ADVANCE_ RIP_AND_FINISH();3838 IEM_MC_ADVANCE_PC_AND_FINISH(); 3839 3839 IEM_MC_END(); 3840 3840 } … … 3858 3858 IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst); 3859 3859 3860 IEM_MC_ADVANCE_ RIP_AND_FINISH();3860 IEM_MC_ADVANCE_PC_AND_FINISH(); 3861 3861 IEM_MC_END(); 3862 3862 } … … 3880 3880 IEM_MC_STORE_XREG_R64(IEM_GET_MODRM_REG(pVCpu, bRm), r64Dst); 3881 3881 3882 IEM_MC_ADVANCE_ RIP_AND_FINISH();3882 IEM_MC_ADVANCE_PC_AND_FINISH(); 3883 3883 IEM_MC_END(); 3884 3884 } … … 3918 3918 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3919 3919 3920 IEM_MC_ADVANCE_ RIP_AND_FINISH();3920 IEM_MC_ADVANCE_PC_AND_FINISH(); 3921 3921 IEM_MC_END(); 3922 3922 } … … 3957 3957 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 3958 3958 3959 IEM_MC_ADVANCE_ RIP_AND_FINISH();3959 IEM_MC_ADVANCE_PC_AND_FINISH(); 3960 3960 IEM_MC_END(); 3961 3961 } … … 3993 3993 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 3994 3994 3995 IEM_MC_ADVANCE_ RIP_AND_FINISH();3995 IEM_MC_ADVANCE_PC_AND_FINISH(); 3996 3996 IEM_MC_END(); 3997 3997 } … … 4019 4019 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4020 4020 4021 IEM_MC_ADVANCE_ RIP_AND_FINISH();4021 IEM_MC_ADVANCE_PC_AND_FINISH(); 4022 4022 IEM_MC_END(); 4023 4023 } … … 4050 4050 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4051 4051 4052 IEM_MC_ADVANCE_ RIP_AND_FINISH();4052 IEM_MC_ADVANCE_PC_AND_FINISH(); 4053 4053 IEM_MC_END(); 4054 4054 } … … 4077 4077 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4078 4078 4079 IEM_MC_ADVANCE_ RIP_AND_FINISH();4079 IEM_MC_ADVANCE_PC_AND_FINISH(); 4080 4080 IEM_MC_END(); 4081 4081 } … … 4107 4107 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4108 4108 4109 IEM_MC_ADVANCE_ RIP_AND_FINISH();4109 IEM_MC_ADVANCE_PC_AND_FINISH(); 4110 4110 IEM_MC_END(); 4111 4111 } … … 4129 4129 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4130 4130 4131 IEM_MC_ADVANCE_ RIP_AND_FINISH();4131 IEM_MC_ADVANCE_PC_AND_FINISH(); 4132 4132 IEM_MC_END(); 4133 4133 } … … 4151 4151 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4152 4152 4153 IEM_MC_ADVANCE_ RIP_AND_FINISH();4153 IEM_MC_ADVANCE_PC_AND_FINISH(); 4154 4154 IEM_MC_END(); 4155 4155 } … … 4173 4173 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4174 4174 4175 IEM_MC_ADVANCE_ RIP_AND_FINISH();4175 IEM_MC_ADVANCE_PC_AND_FINISH(); 4176 4176 IEM_MC_END(); 4177 4177 } … … 4204 4204 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4205 4205 4206 IEM_MC_ADVANCE_ RIP_AND_FINISH();4206 IEM_MC_ADVANCE_PC_AND_FINISH(); 4207 4207 IEM_MC_END(); 4208 4208 } … … 4226 4226 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4227 4227 4228 IEM_MC_ADVANCE_ RIP_AND_FINISH();4228 IEM_MC_ADVANCE_PC_AND_FINISH(); 4229 4229 IEM_MC_END(); 4230 4230 } … … 4248 4248 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4249 4249 4250 IEM_MC_ADVANCE_ RIP_AND_FINISH();4250 IEM_MC_ADVANCE_PC_AND_FINISH(); 4251 4251 IEM_MC_END(); 4252 4252 } … … 4270 4270 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4271 4271 4272 IEM_MC_ADVANCE_ RIP_AND_FINISH();4272 IEM_MC_ADVANCE_PC_AND_FINISH(); 4273 4273 IEM_MC_END(); 4274 4274 } … … 4303 4303 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4304 4304 4305 IEM_MC_ADVANCE_ RIP_AND_FINISH();4305 IEM_MC_ADVANCE_PC_AND_FINISH(); 4306 4306 IEM_MC_END(); 4307 4307 } … … 4329 4329 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4330 4330 4331 IEM_MC_ADVANCE_ RIP_AND_FINISH();4331 IEM_MC_ADVANCE_PC_AND_FINISH(); 4332 4332 IEM_MC_END(); 4333 4333 } … … 4361 4361 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4362 4362 4363 IEM_MC_ADVANCE_ RIP_AND_FINISH();4363 IEM_MC_ADVANCE_PC_AND_FINISH(); 4364 4364 IEM_MC_END(); 4365 4365 } … … 4388 4388 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Dst); 4389 4389 4390 IEM_MC_ADVANCE_ RIP_AND_FINISH();4390 IEM_MC_ADVANCE_PC_AND_FINISH(); 4391 4391 IEM_MC_END(); 4392 4392 } … … 4418 4418 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4419 4419 4420 IEM_MC_ADVANCE_ RIP_AND_FINISH();4420 IEM_MC_ADVANCE_PC_AND_FINISH(); 4421 4421 IEM_MC_END(); 4422 4422 } … … 4440 4440 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4441 4441 4442 IEM_MC_ADVANCE_ RIP_AND_FINISH();4442 IEM_MC_ADVANCE_PC_AND_FINISH(); 4443 4443 IEM_MC_END(); 4444 4444 } … … 4462 4462 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4463 4463 4464 IEM_MC_ADVANCE_ RIP_AND_FINISH();4464 IEM_MC_ADVANCE_PC_AND_FINISH(); 4465 4465 IEM_MC_END(); 4466 4466 } … … 4484 4484 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4485 4485 4486 IEM_MC_ADVANCE_ RIP_AND_FINISH();4486 IEM_MC_ADVANCE_PC_AND_FINISH(); 4487 4487 IEM_MC_END(); 4488 4488 } … … 4515 4515 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4516 4516 4517 IEM_MC_ADVANCE_ RIP_AND_FINISH();4517 IEM_MC_ADVANCE_PC_AND_FINISH(); 4518 4518 IEM_MC_END(); 4519 4519 } … … 4537 4537 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); 4538 4538 4539 IEM_MC_ADVANCE_ RIP_AND_FINISH();4539 IEM_MC_ADVANCE_PC_AND_FINISH(); 4540 4540 IEM_MC_END(); 4541 4541 } … … 4559 4559 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4560 4560 4561 IEM_MC_ADVANCE_ RIP_AND_FINISH();4561 IEM_MC_ADVANCE_PC_AND_FINISH(); 4562 4562 IEM_MC_END(); 4563 4563 } … … 4581 4581 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); 4582 4582 4583 IEM_MC_ADVANCE_ RIP_AND_FINISH();4583 IEM_MC_ADVANCE_PC_AND_FINISH(); 4584 4584 IEM_MC_END(); 4585 4585 } … … 4617 4617 IEM_MC_COMMIT_EFLAGS(fEFlags); 4618 4618 4619 IEM_MC_ADVANCE_ RIP_AND_FINISH();4619 IEM_MC_ADVANCE_PC_AND_FINISH(); 4620 4620 IEM_MC_END(); 4621 4621 } … … 4643 4643 IEM_MC_COMMIT_EFLAGS(fEFlags); 4644 4644 4645 IEM_MC_ADVANCE_ RIP_AND_FINISH();4645 IEM_MC_ADVANCE_PC_AND_FINISH(); 4646 4646 IEM_MC_END(); 4647 4647 } … … 4678 4678 IEM_MC_COMMIT_EFLAGS(fEFlags); 4679 4679 4680 IEM_MC_ADVANCE_ RIP_AND_FINISH();4680 IEM_MC_ADVANCE_PC_AND_FINISH(); 4681 4681 IEM_MC_END(); 4682 4682 } … … 4704 4704 IEM_MC_COMMIT_EFLAGS(fEFlags); 4705 4705 4706 IEM_MC_ADVANCE_ RIP_AND_FINISH();4706 IEM_MC_ADVANCE_PC_AND_FINISH(); 4707 4707 IEM_MC_END(); 4708 4708 } … … 4743 4743 IEM_MC_COMMIT_EFLAGS(fEFlags); 4744 4744 4745 IEM_MC_ADVANCE_ RIP_AND_FINISH();4745 IEM_MC_ADVANCE_PC_AND_FINISH(); 4746 4746 IEM_MC_END(); 4747 4747 } … … 4769 4769 IEM_MC_COMMIT_EFLAGS(fEFlags); 4770 4770 4771 IEM_MC_ADVANCE_ RIP_AND_FINISH();4771 IEM_MC_ADVANCE_PC_AND_FINISH(); 4772 4772 IEM_MC_END(); 4773 4773 } … … 4804 4804 IEM_MC_COMMIT_EFLAGS(fEFlags); 4805 4805 4806 IEM_MC_ADVANCE_ RIP_AND_FINISH();4806 IEM_MC_ADVANCE_PC_AND_FINISH(); 4807 4807 IEM_MC_END(); 4808 4808 } … … 4830 4830 IEM_MC_COMMIT_EFLAGS(fEFlags); 4831 4831 4832 IEM_MC_ADVANCE_ RIP_AND_FINISH();4832 IEM_MC_ADVANCE_PC_AND_FINISH(); 4833 4833 IEM_MC_END(); 4834 4834 } … … 4956 4956 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp); \ 4957 4957 } IEM_MC_ENDIF(); \ 4958 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4958 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4959 4959 IEM_MC_END(); \ 4960 4960 break; \ … … 4970 4970 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 4971 4971 } IEM_MC_ENDIF(); \ 4972 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4972 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4973 4973 IEM_MC_END(); \ 4974 4974 break; \ … … 4982 4982 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); \ 4983 4983 } IEM_MC_ENDIF(); \ 4984 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4984 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4985 4985 IEM_MC_END(); \ 4986 4986 break; \ … … 5003 5003 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Tmp); \ 5004 5004 } IEM_MC_ENDIF(); \ 5005 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5005 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5006 5006 IEM_MC_END(); \ 5007 5007 break; \ … … 5019 5019 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 5020 5020 } IEM_MC_ENDIF(); \ 5021 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5021 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5022 5022 IEM_MC_END(); \ 5023 5023 break; \ … … 5033 5033 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); \ 5034 5034 } IEM_MC_ENDIF(); \ 5035 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5035 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5036 5036 IEM_MC_END(); \ 5037 5037 break; \ … … 5240 5240 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movmskps_u128, pu8Dst, puSrc); 5241 5241 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 5242 IEM_MC_ADVANCE_ RIP_AND_FINISH();5242 IEM_MC_ADVANCE_PC_AND_FINISH(); 5243 5243 IEM_MC_END(); 5244 5244 } … … 5269 5269 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_movmskpd_u128, pu8Dst, puSrc); 5270 5270 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 5271 IEM_MC_ADVANCE_ RIP_AND_FINISH();5271 IEM_MC_ADVANCE_PC_AND_FINISH(); 5272 5272 IEM_MC_END(); 5273 5273 } … … 5524 5524 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 5525 5525 5526 IEM_MC_ADVANCE_ RIP_AND_FINISH();5526 IEM_MC_ADVANCE_PC_AND_FINISH(); 5527 5527 IEM_MC_END(); 5528 5528 } … … 5548 5548 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), SseRes); 5549 5549 5550 IEM_MC_ADVANCE_ RIP_AND_FINISH();5550 IEM_MC_ADVANCE_PC_AND_FINISH(); 5551 5551 IEM_MC_END(); 5552 5552 } … … 6036 6036 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Tmp); 6037 6037 6038 IEM_MC_ADVANCE_ RIP_AND_FINISH();6038 IEM_MC_ADVANCE_PC_AND_FINISH(); 6039 6039 IEM_MC_END(); 6040 6040 } … … 6055 6055 IEM_MC_FPU_TO_MMX_MODE(); 6056 6056 6057 IEM_MC_ADVANCE_ RIP_AND_FINISH();6057 IEM_MC_ADVANCE_PC_AND_FINISH(); 6058 6058 IEM_MC_END(); 6059 6059 } … … 6088 6088 IEM_MC_STORE_MREG_U32_ZX_U64(IEM_GET_MODRM_REG_8(bRm), u32Tmp); 6089 6089 6090 IEM_MC_ADVANCE_ RIP_AND_FINISH();6090 IEM_MC_ADVANCE_PC_AND_FINISH(); 6091 6091 IEM_MC_END(); 6092 6092 } … … 6107 6107 IEM_MC_FPU_TO_MMX_MODE(); 6108 6108 6109 IEM_MC_ADVANCE_ RIP_AND_FINISH();6109 IEM_MC_ADVANCE_PC_AND_FINISH(); 6110 6110 IEM_MC_END(); 6111 6111 } … … 6142 6142 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); 6143 6143 6144 IEM_MC_ADVANCE_ RIP_AND_FINISH();6144 IEM_MC_ADVANCE_PC_AND_FINISH(); 6145 6145 IEM_MC_END(); 6146 6146 } … … 6160 6160 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); 6161 6161 6162 IEM_MC_ADVANCE_ RIP_AND_FINISH();6162 IEM_MC_ADVANCE_PC_AND_FINISH(); 6163 6163 IEM_MC_END(); 6164 6164 } … … 6192 6192 IEM_MC_STORE_XREG_U32_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp); 6193 6193 6194 IEM_MC_ADVANCE_ RIP_AND_FINISH();6194 IEM_MC_ADVANCE_PC_AND_FINISH(); 6195 6195 IEM_MC_END(); 6196 6196 } … … 6210 6210 IEM_MC_STORE_XREG_U32_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp); 6211 6211 6212 IEM_MC_ADVANCE_ RIP_AND_FINISH();6212 IEM_MC_ADVANCE_PC_AND_FINISH(); 6213 6213 IEM_MC_END(); 6214 6214 } … … 6248 6248 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Tmp); 6249 6249 6250 IEM_MC_ADVANCE_ RIP_AND_FINISH();6250 IEM_MC_ADVANCE_PC_AND_FINISH(); 6251 6251 IEM_MC_END(); 6252 6252 } … … 6270 6270 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), u64Tmp); 6271 6271 6272 IEM_MC_ADVANCE_ RIP_AND_FINISH();6272 IEM_MC_ADVANCE_PC_AND_FINISH(); 6273 6273 IEM_MC_END(); 6274 6274 } … … 6301 6301 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 6302 6302 IEM_GET_MODRM_RM(pVCpu, bRm)); 6303 IEM_MC_ADVANCE_ RIP_AND_FINISH();6303 IEM_MC_ADVANCE_PC_AND_FINISH(); 6304 6304 IEM_MC_END(); 6305 6305 } … … 6321 6321 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 6322 6322 6323 IEM_MC_ADVANCE_ RIP_AND_FINISH();6323 IEM_MC_ADVANCE_PC_AND_FINISH(); 6324 6324 IEM_MC_END(); 6325 6325 } … … 6350 6350 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), 6351 6351 IEM_GET_MODRM_RM(pVCpu, bRm)); 6352 IEM_MC_ADVANCE_ RIP_AND_FINISH();6352 IEM_MC_ADVANCE_PC_AND_FINISH(); 6353 6353 IEM_MC_END(); 6354 6354 } … … 6369 6369 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 6370 6370 6371 IEM_MC_ADVANCE_ RIP_AND_FINISH();6371 IEM_MC_ADVANCE_PC_AND_FINISH(); 6372 6372 IEM_MC_END(); 6373 6373 } … … 6400 6400 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 6401 6401 6402 IEM_MC_ADVANCE_ RIP_AND_FINISH();6402 IEM_MC_ADVANCE_PC_AND_FINISH(); 6403 6403 IEM_MC_END(); 6404 6404 } … … 6428 6428 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 6429 6429 6430 IEM_MC_ADVANCE_ RIP_AND_FINISH();6430 IEM_MC_ADVANCE_PC_AND_FINISH(); 6431 6431 IEM_MC_END(); 6432 6432 } … … 6462 6462 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 6463 6463 IEM_MC_CALL_VOID_AIMPL_3(pfnWorker, puDst, puSrc, bImmArg); 6464 IEM_MC_ADVANCE_ RIP_AND_FINISH();6464 IEM_MC_ADVANCE_PC_AND_FINISH(); 6465 6465 IEM_MC_END(); 6466 6466 } … … 6487 6487 IEM_MC_CALL_VOID_AIMPL_3(pfnWorker, puDst, puSrc, bImmArg); 6488 6488 6489 IEM_MC_ADVANCE_ RIP_AND_FINISH();6489 IEM_MC_ADVANCE_PC_AND_FINISH(); 6490 6490 IEM_MC_END(); 6491 6491 } … … 6549 6549 IEM_MC_MODIFIED_MREG_BY_REF(pDst); 6550 6550 6551 IEM_MC_ADVANCE_ RIP_AND_FINISH();6551 IEM_MC_ADVANCE_PC_AND_FINISH(); 6552 6552 IEM_MC_END(); 6553 6553 } … … 6592 6592 IEM_MC_REF_XREG_U128(pDst, IEM_GET_MODRM_RM(pVCpu, bRm)); 6593 6593 IEM_MC_CALL_VOID_AIMPL_2(pfnU128, pDst, bShiftArg); 6594 IEM_MC_ADVANCE_ RIP_AND_FINISH();6594 IEM_MC_ADVANCE_PC_AND_FINISH(); 6595 6595 IEM_MC_END(); 6596 6596 } … … 6629 6629 IEM_MC_CALL_VOID_AIMPL_2(RT_CONCAT3(iemAImpl_,a_Ins,_imm_u128), pDst, bShiftArg); \ 6630 6630 } IEM_MC_NATIVE_ENDIF(); \ 6631 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6631 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6632 6632 IEM_MC_END(); \ 6633 6633 } \ … … 6939 6939 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 6940 6940 IEM_MC_FPU_FROM_MMX_MODE(); 6941 IEM_MC_ADVANCE_ RIP_AND_FINISH();6941 IEM_MC_ADVANCE_PC_AND_FINISH(); 6942 6942 IEM_MC_END(); 6943 6943 } … … 7194 7194 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp); 7195 7195 7196 IEM_MC_ADVANCE_ RIP_AND_FINISH();7196 IEM_MC_ADVANCE_PC_AND_FINISH(); 7197 7197 IEM_MC_END(); 7198 7198 } … … 7213 7213 IEM_MC_FPU_TO_MMX_MODE(); 7214 7214 7215 IEM_MC_ADVANCE_ RIP_AND_FINISH();7215 IEM_MC_ADVANCE_PC_AND_FINISH(); 7216 7216 IEM_MC_END(); 7217 7217 } … … 7246 7246 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp); 7247 7247 7248 IEM_MC_ADVANCE_ RIP_AND_FINISH();7248 IEM_MC_ADVANCE_PC_AND_FINISH(); 7249 7249 IEM_MC_END(); 7250 7250 } … … 7265 7265 IEM_MC_FPU_TO_MMX_MODE(); 7266 7266 7267 IEM_MC_ADVANCE_ RIP_AND_FINISH();7267 IEM_MC_ADVANCE_PC_AND_FINISH(); 7268 7268 IEM_MC_END(); 7269 7269 } … … 7301 7301 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp); 7302 7302 7303 IEM_MC_ADVANCE_ RIP_AND_FINISH();7303 IEM_MC_ADVANCE_PC_AND_FINISH(); 7304 7304 IEM_MC_END(); 7305 7305 } … … 7319 7319 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp); 7320 7320 7321 IEM_MC_ADVANCE_ RIP_AND_FINISH();7321 IEM_MC_ADVANCE_PC_AND_FINISH(); 7322 7322 IEM_MC_END(); 7323 7323 } … … 7351 7351 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp); 7352 7352 7353 IEM_MC_ADVANCE_ RIP_AND_FINISH();7353 IEM_MC_ADVANCE_PC_AND_FINISH(); 7354 7354 IEM_MC_END(); 7355 7355 } … … 7369 7369 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp); 7370 7370 7371 IEM_MC_ADVANCE_ RIP_AND_FINISH();7371 IEM_MC_ADVANCE_PC_AND_FINISH(); 7372 7372 IEM_MC_END(); 7373 7373 } … … 7403 7403 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 7404 7404 7405 IEM_MC_ADVANCE_ RIP_AND_FINISH();7405 IEM_MC_ADVANCE_PC_AND_FINISH(); 7406 7406 IEM_MC_END(); 7407 7407 } … … 7423 7423 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 7424 7424 7425 IEM_MC_ADVANCE_ RIP_AND_FINISH();7425 IEM_MC_ADVANCE_PC_AND_FINISH(); 7426 7426 IEM_MC_END(); 7427 7427 } … … 7453 7453 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_RM_8(bRm), u64Tmp); 7454 7454 7455 IEM_MC_ADVANCE_ RIP_AND_FINISH();7455 IEM_MC_ADVANCE_PC_AND_FINISH(); 7456 7456 IEM_MC_END(); 7457 7457 } … … 7474 7474 IEM_MC_FPU_TO_MMX_MODE(); 7475 7475 7476 IEM_MC_ADVANCE_ RIP_AND_FINISH();7476 IEM_MC_ADVANCE_PC_AND_FINISH(); 7477 7477 IEM_MC_END(); 7478 7478 } … … 7495 7495 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 7496 7496 IEM_GET_MODRM_REG(pVCpu, bRm)); 7497 IEM_MC_ADVANCE_ RIP_AND_FINISH();7497 IEM_MC_ADVANCE_PC_AND_FINISH(); 7498 7498 IEM_MC_END(); 7499 7499 } … … 7515 7515 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp); 7516 7516 7517 IEM_MC_ADVANCE_ RIP_AND_FINISH();7517 IEM_MC_ADVANCE_PC_AND_FINISH(); 7518 7518 IEM_MC_END(); 7519 7519 } … … 7536 7536 IEM_MC_COPY_XREG_U128(IEM_GET_MODRM_RM(pVCpu, bRm), 7537 7537 IEM_GET_MODRM_REG(pVCpu, bRm)); 7538 IEM_MC_ADVANCE_ RIP_AND_FINISH();7538 IEM_MC_ADVANCE_PC_AND_FINISH(); 7539 7539 IEM_MC_END(); 7540 7540 } … … 7556 7556 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp); 7557 7557 7558 IEM_MC_ADVANCE_ RIP_AND_FINISH();7558 IEM_MC_ADVANCE_PC_AND_FINISH(); 7559 7559 IEM_MC_END(); 7560 7560 } … … 7581 7581 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7582 7582 } IEM_MC_ELSE() { 7583 IEM_MC_ADVANCE_ RIP_AND_FINISH();7583 IEM_MC_ADVANCE_PC_AND_FINISH(); 7584 7584 } IEM_MC_ENDIF(); 7585 7585 IEM_MC_END(); … … 7593 7593 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7594 7594 } IEM_MC_ELSE() { 7595 IEM_MC_ADVANCE_ RIP_AND_FINISH();7595 IEM_MC_ADVANCE_PC_AND_FINISH(); 7596 7596 } IEM_MC_ENDIF(); 7597 7597 IEM_MC_END(); … … 7615 7615 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7616 7616 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) { 7617 IEM_MC_ADVANCE_ RIP_AND_FINISH();7617 IEM_MC_ADVANCE_PC_AND_FINISH(); 7618 7618 } IEM_MC_ELSE() { 7619 7619 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7627 7627 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7628 7628 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) { 7629 IEM_MC_ADVANCE_ RIP_AND_FINISH();7629 IEM_MC_ADVANCE_PC_AND_FINISH(); 7630 7630 } IEM_MC_ELSE() { 7631 7631 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 7653 7653 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7654 7654 } IEM_MC_ELSE() { 7655 IEM_MC_ADVANCE_ RIP_AND_FINISH();7655 IEM_MC_ADVANCE_PC_AND_FINISH(); 7656 7656 } IEM_MC_ENDIF(); 7657 7657 IEM_MC_END(); … … 7665 7665 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7666 7666 } IEM_MC_ELSE() { 7667 IEM_MC_ADVANCE_ RIP_AND_FINISH();7667 IEM_MC_ADVANCE_PC_AND_FINISH(); 7668 7668 } IEM_MC_ENDIF(); 7669 7669 IEM_MC_END(); … … 7687 7687 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7688 7688 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) { 7689 IEM_MC_ADVANCE_ RIP_AND_FINISH();7689 IEM_MC_ADVANCE_PC_AND_FINISH(); 7690 7690 } IEM_MC_ELSE() { 7691 7691 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7699 7699 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7700 7700 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) { 7701 IEM_MC_ADVANCE_ RIP_AND_FINISH();7701 IEM_MC_ADVANCE_PC_AND_FINISH(); 7702 7702 } IEM_MC_ELSE() { 7703 7703 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 7725 7725 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7726 7726 } IEM_MC_ELSE() { 7727 IEM_MC_ADVANCE_ RIP_AND_FINISH();7727 IEM_MC_ADVANCE_PC_AND_FINISH(); 7728 7728 } IEM_MC_ENDIF(); 7729 7729 IEM_MC_END(); … … 7737 7737 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7738 7738 } IEM_MC_ELSE() { 7739 IEM_MC_ADVANCE_ RIP_AND_FINISH();7739 IEM_MC_ADVANCE_PC_AND_FINISH(); 7740 7740 } IEM_MC_ENDIF(); 7741 7741 IEM_MC_END(); … … 7759 7759 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7760 7760 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) { 7761 IEM_MC_ADVANCE_ RIP_AND_FINISH();7761 IEM_MC_ADVANCE_PC_AND_FINISH(); 7762 7762 } IEM_MC_ELSE() { 7763 7763 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7771 7771 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7772 7772 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) { 7773 IEM_MC_ADVANCE_ RIP_AND_FINISH();7773 IEM_MC_ADVANCE_PC_AND_FINISH(); 7774 7774 } IEM_MC_ELSE() { 7775 7775 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 7797 7797 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7798 7798 } IEM_MC_ELSE() { 7799 IEM_MC_ADVANCE_ RIP_AND_FINISH();7799 IEM_MC_ADVANCE_PC_AND_FINISH(); 7800 7800 } IEM_MC_ENDIF(); 7801 7801 IEM_MC_END(); … … 7809 7809 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7810 7810 } IEM_MC_ELSE() { 7811 IEM_MC_ADVANCE_ RIP_AND_FINISH();7811 IEM_MC_ADVANCE_PC_AND_FINISH(); 7812 7812 } IEM_MC_ENDIF(); 7813 7813 IEM_MC_END(); … … 7831 7831 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7832 7832 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7833 IEM_MC_ADVANCE_ RIP_AND_FINISH();7833 IEM_MC_ADVANCE_PC_AND_FINISH(); 7834 7834 } IEM_MC_ELSE() { 7835 7835 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7843 7843 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7844 7844 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 7845 IEM_MC_ADVANCE_ RIP_AND_FINISH();7845 IEM_MC_ADVANCE_PC_AND_FINISH(); 7846 7846 } IEM_MC_ELSE() { 7847 7847 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 7869 7869 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7870 7870 } IEM_MC_ELSE() { 7871 IEM_MC_ADVANCE_ RIP_AND_FINISH();7871 IEM_MC_ADVANCE_PC_AND_FINISH(); 7872 7872 } IEM_MC_ENDIF(); 7873 7873 IEM_MC_END(); … … 7881 7881 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7882 7882 } IEM_MC_ELSE() { 7883 IEM_MC_ADVANCE_ RIP_AND_FINISH();7883 IEM_MC_ADVANCE_PC_AND_FINISH(); 7884 7884 } IEM_MC_ENDIF(); 7885 7885 IEM_MC_END(); … … 7903 7903 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7904 7904 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) { 7905 IEM_MC_ADVANCE_ RIP_AND_FINISH();7905 IEM_MC_ADVANCE_PC_AND_FINISH(); 7906 7906 } IEM_MC_ELSE() { 7907 7907 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7915 7915 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7916 7916 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) { 7917 IEM_MC_ADVANCE_ RIP_AND_FINISH();7917 IEM_MC_ADVANCE_PC_AND_FINISH(); 7918 7918 } IEM_MC_ELSE() { 7919 7919 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 7941 7941 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 7942 7942 } IEM_MC_ELSE() { 7943 IEM_MC_ADVANCE_ RIP_AND_FINISH();7943 IEM_MC_ADVANCE_PC_AND_FINISH(); 7944 7944 } IEM_MC_ENDIF(); 7945 7945 IEM_MC_END(); … … 7953 7953 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 7954 7954 } IEM_MC_ELSE() { 7955 IEM_MC_ADVANCE_ RIP_AND_FINISH();7955 IEM_MC_ADVANCE_PC_AND_FINISH(); 7956 7956 } IEM_MC_ENDIF(); 7957 7957 IEM_MC_END(); … … 7975 7975 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7976 7976 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) { 7977 IEM_MC_ADVANCE_ RIP_AND_FINISH();7977 IEM_MC_ADVANCE_PC_AND_FINISH(); 7978 7978 } IEM_MC_ELSE() { 7979 7979 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 7987 7987 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 7988 7988 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) { 7989 IEM_MC_ADVANCE_ RIP_AND_FINISH();7989 IEM_MC_ADVANCE_PC_AND_FINISH(); 7990 7990 } IEM_MC_ELSE() { 7991 7991 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 8013 8013 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 8014 8014 } IEM_MC_ELSE() { 8015 IEM_MC_ADVANCE_ RIP_AND_FINISH();8015 IEM_MC_ADVANCE_PC_AND_FINISH(); 8016 8016 } IEM_MC_ENDIF(); 8017 8017 IEM_MC_END(); … … 8025 8025 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 8026 8026 } IEM_MC_ELSE() { 8027 IEM_MC_ADVANCE_ RIP_AND_FINISH();8027 IEM_MC_ADVANCE_PC_AND_FINISH(); 8028 8028 } IEM_MC_ENDIF(); 8029 8029 IEM_MC_END(); … … 8047 8047 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8048 8048 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8049 IEM_MC_ADVANCE_ RIP_AND_FINISH();8049 IEM_MC_ADVANCE_PC_AND_FINISH(); 8050 8050 } IEM_MC_ELSE() { 8051 8051 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 8059 8059 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8060 8060 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 8061 IEM_MC_ADVANCE_ RIP_AND_FINISH();8061 IEM_MC_ADVANCE_PC_AND_FINISH(); 8062 8062 } IEM_MC_ELSE() { 8063 8063 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 8085 8085 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); 8086 8086 } IEM_MC_ELSE() { 8087 IEM_MC_ADVANCE_ RIP_AND_FINISH();8087 IEM_MC_ADVANCE_PC_AND_FINISH(); 8088 8088 } IEM_MC_ENDIF(); 8089 8089 IEM_MC_END(); … … 8097 8097 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); 8098 8098 } IEM_MC_ELSE() { 8099 IEM_MC_ADVANCE_ RIP_AND_FINISH();8099 IEM_MC_ADVANCE_PC_AND_FINISH(); 8100 8100 } IEM_MC_ENDIF(); 8101 8101 IEM_MC_END(); … … 8119 8119 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8120 8120 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8121 IEM_MC_ADVANCE_ RIP_AND_FINISH();8121 IEM_MC_ADVANCE_PC_AND_FINISH(); 8122 8122 } IEM_MC_ELSE() { 8123 8123 IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm); … … 8131 8131 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8132 8132 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 8133 IEM_MC_ADVANCE_ RIP_AND_FINISH();8133 IEM_MC_ADVANCE_PC_AND_FINISH(); 8134 8134 } IEM_MC_ELSE() { 8135 8135 IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm); … … 8163 8163 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8164 8164 } IEM_MC_ENDIF(); 8165 IEM_MC_ADVANCE_ RIP_AND_FINISH();8165 IEM_MC_ADVANCE_PC_AND_FINISH(); 8166 8166 IEM_MC_END(); 8167 8167 } … … 8178 8178 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8179 8179 } IEM_MC_ENDIF(); 8180 IEM_MC_ADVANCE_ RIP_AND_FINISH();8180 IEM_MC_ADVANCE_PC_AND_FINISH(); 8181 8181 IEM_MC_END(); 8182 8182 } … … 8207 8207 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8208 8208 } IEM_MC_ENDIF(); 8209 IEM_MC_ADVANCE_ RIP_AND_FINISH();8209 IEM_MC_ADVANCE_PC_AND_FINISH(); 8210 8210 IEM_MC_END(); 8211 8211 } … … 8222 8222 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8223 8223 } IEM_MC_ENDIF(); 8224 IEM_MC_ADVANCE_ RIP_AND_FINISH();8224 IEM_MC_ADVANCE_PC_AND_FINISH(); 8225 8225 IEM_MC_END(); 8226 8226 } … … 8251 8251 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8252 8252 } IEM_MC_ENDIF(); 8253 IEM_MC_ADVANCE_ RIP_AND_FINISH();8253 IEM_MC_ADVANCE_PC_AND_FINISH(); 8254 8254 IEM_MC_END(); 8255 8255 } … … 8266 8266 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8267 8267 } IEM_MC_ENDIF(); 8268 IEM_MC_ADVANCE_ RIP_AND_FINISH();8268 IEM_MC_ADVANCE_PC_AND_FINISH(); 8269 8269 IEM_MC_END(); 8270 8270 } … … 8295 8295 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8296 8296 } IEM_MC_ENDIF(); 8297 IEM_MC_ADVANCE_ RIP_AND_FINISH();8297 IEM_MC_ADVANCE_PC_AND_FINISH(); 8298 8298 IEM_MC_END(); 8299 8299 } … … 8310 8310 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8311 8311 } IEM_MC_ENDIF(); 8312 IEM_MC_ADVANCE_ RIP_AND_FINISH();8312 IEM_MC_ADVANCE_PC_AND_FINISH(); 8313 8313 IEM_MC_END(); 8314 8314 } … … 8339 8339 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8340 8340 } IEM_MC_ENDIF(); 8341 IEM_MC_ADVANCE_ RIP_AND_FINISH();8341 IEM_MC_ADVANCE_PC_AND_FINISH(); 8342 8342 IEM_MC_END(); 8343 8343 } … … 8354 8354 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8355 8355 } IEM_MC_ENDIF(); 8356 IEM_MC_ADVANCE_ RIP_AND_FINISH();8356 IEM_MC_ADVANCE_PC_AND_FINISH(); 8357 8357 IEM_MC_END(); 8358 8358 } … … 8383 8383 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8384 8384 } IEM_MC_ENDIF(); 8385 IEM_MC_ADVANCE_ RIP_AND_FINISH();8385 IEM_MC_ADVANCE_PC_AND_FINISH(); 8386 8386 IEM_MC_END(); 8387 8387 } … … 8398 8398 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8399 8399 } IEM_MC_ENDIF(); 8400 IEM_MC_ADVANCE_ RIP_AND_FINISH();8400 IEM_MC_ADVANCE_PC_AND_FINISH(); 8401 8401 IEM_MC_END(); 8402 8402 } … … 8427 8427 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8428 8428 } IEM_MC_ENDIF(); 8429 IEM_MC_ADVANCE_ RIP_AND_FINISH();8429 IEM_MC_ADVANCE_PC_AND_FINISH(); 8430 8430 IEM_MC_END(); 8431 8431 } … … 8442 8442 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8443 8443 } IEM_MC_ENDIF(); 8444 IEM_MC_ADVANCE_ RIP_AND_FINISH();8444 IEM_MC_ADVANCE_PC_AND_FINISH(); 8445 8445 IEM_MC_END(); 8446 8446 } … … 8471 8471 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8472 8472 } IEM_MC_ENDIF(); 8473 IEM_MC_ADVANCE_ RIP_AND_FINISH();8473 IEM_MC_ADVANCE_PC_AND_FINISH(); 8474 8474 IEM_MC_END(); 8475 8475 } … … 8486 8486 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8487 8487 } IEM_MC_ENDIF(); 8488 IEM_MC_ADVANCE_ RIP_AND_FINISH();8488 IEM_MC_ADVANCE_PC_AND_FINISH(); 8489 8489 IEM_MC_END(); 8490 8490 } … … 8515 8515 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8516 8516 } IEM_MC_ENDIF(); 8517 IEM_MC_ADVANCE_ RIP_AND_FINISH();8517 IEM_MC_ADVANCE_PC_AND_FINISH(); 8518 8518 IEM_MC_END(); 8519 8519 } … … 8530 8530 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8531 8531 } IEM_MC_ENDIF(); 8532 IEM_MC_ADVANCE_ RIP_AND_FINISH();8532 IEM_MC_ADVANCE_PC_AND_FINISH(); 8533 8533 IEM_MC_END(); 8534 8534 } … … 8559 8559 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8560 8560 } IEM_MC_ENDIF(); 8561 IEM_MC_ADVANCE_ RIP_AND_FINISH();8561 IEM_MC_ADVANCE_PC_AND_FINISH(); 8562 8562 IEM_MC_END(); 8563 8563 } … … 8574 8574 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8575 8575 } IEM_MC_ENDIF(); 8576 IEM_MC_ADVANCE_ RIP_AND_FINISH();8576 IEM_MC_ADVANCE_PC_AND_FINISH(); 8577 8577 IEM_MC_END(); 8578 8578 } … … 8603 8603 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8604 8604 } IEM_MC_ENDIF(); 8605 IEM_MC_ADVANCE_ RIP_AND_FINISH();8605 IEM_MC_ADVANCE_PC_AND_FINISH(); 8606 8606 IEM_MC_END(); 8607 8607 } … … 8618 8618 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8619 8619 } IEM_MC_ENDIF(); 8620 IEM_MC_ADVANCE_ RIP_AND_FINISH();8620 IEM_MC_ADVANCE_PC_AND_FINISH(); 8621 8621 IEM_MC_END(); 8622 8622 } … … 8647 8647 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8648 8648 } IEM_MC_ENDIF(); 8649 IEM_MC_ADVANCE_ RIP_AND_FINISH();8649 IEM_MC_ADVANCE_PC_AND_FINISH(); 8650 8650 IEM_MC_END(); 8651 8651 } … … 8662 8662 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8663 8663 } IEM_MC_ENDIF(); 8664 IEM_MC_ADVANCE_ RIP_AND_FINISH();8664 IEM_MC_ADVANCE_PC_AND_FINISH(); 8665 8665 IEM_MC_END(); 8666 8666 } … … 8691 8691 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8692 8692 } IEM_MC_ENDIF(); 8693 IEM_MC_ADVANCE_ RIP_AND_FINISH();8693 IEM_MC_ADVANCE_PC_AND_FINISH(); 8694 8694 IEM_MC_END(); 8695 8695 } … … 8706 8706 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8707 8707 } IEM_MC_ENDIF(); 8708 IEM_MC_ADVANCE_ RIP_AND_FINISH();8708 IEM_MC_ADVANCE_PC_AND_FINISH(); 8709 8709 IEM_MC_END(); 8710 8710 } … … 8735 8735 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8736 8736 } IEM_MC_ENDIF(); 8737 IEM_MC_ADVANCE_ RIP_AND_FINISH();8737 IEM_MC_ADVANCE_PC_AND_FINISH(); 8738 8738 IEM_MC_END(); 8739 8739 } … … 8750 8750 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8751 8751 } IEM_MC_ENDIF(); 8752 IEM_MC_ADVANCE_ RIP_AND_FINISH();8752 IEM_MC_ADVANCE_PC_AND_FINISH(); 8753 8753 IEM_MC_END(); 8754 8754 } … … 8779 8779 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 0); 8780 8780 } IEM_MC_ENDIF(); 8781 IEM_MC_ADVANCE_ RIP_AND_FINISH();8781 IEM_MC_ADVANCE_PC_AND_FINISH(); 8782 8782 IEM_MC_END(); 8783 8783 } … … 8794 8794 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0); 8795 8795 } IEM_MC_ENDIF(); 8796 IEM_MC_ADVANCE_ RIP_AND_FINISH();8796 IEM_MC_ADVANCE_PC_AND_FINISH(); 8797 8797 IEM_MC_END(); 8798 8798 } … … 8823 8823 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), 1); 8824 8824 } IEM_MC_ENDIF(); 8825 IEM_MC_ADVANCE_ RIP_AND_FINISH();8825 IEM_MC_ADVANCE_PC_AND_FINISH(); 8826 8826 IEM_MC_END(); 8827 8827 } … … 8838 8838 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, 1); 8839 8839 } IEM_MC_ENDIF(); 8840 IEM_MC_ADVANCE_ RIP_AND_FINISH();8840 IEM_MC_ADVANCE_PC_AND_FINISH(); 8841 8841 IEM_MC_END(); 8842 8842 } … … 8913 8913 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8914 8914 \ 8915 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8915 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8916 8916 IEM_MC_END(); \ 8917 8917 break; \ … … 8931 8931 \ 8932 8932 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 8933 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8933 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8934 8934 IEM_MC_END(); \ 8935 8935 break; \ … … 8948 8948 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8949 8949 \ 8950 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8950 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8951 8951 IEM_MC_END(); \ 8952 8952 break; \ … … 8986 8986 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 8987 8987 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8988 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8988 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8989 8989 IEM_MC_END(); \ 8990 8990 break; \ … … 9013 9013 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9014 9014 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9015 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9015 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9016 9016 IEM_MC_END(); \ 9017 9017 break; \ … … 9040 9040 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9041 9041 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9042 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9042 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9043 9043 IEM_MC_END(); \ 9044 9044 break; \ … … 9077 9077 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 9078 9078 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9079 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9079 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9080 9080 IEM_MC_END(); \ 9081 9081 break; \ … … 9104 9104 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 9105 9105 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9106 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9106 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9107 9107 IEM_MC_END(); \ 9108 9108 break; \ … … 9131 9131 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 9132 9132 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9133 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9133 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9134 9134 IEM_MC_END(); \ 9135 9135 break; \ … … 9164 9164 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9165 9165 \ 9166 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9166 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9167 9167 IEM_MC_END(); \ 9168 9168 break; \ … … 9181 9181 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9182 9182 \ 9183 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9183 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9184 9184 IEM_MC_END(); \ 9185 9185 break; \ … … 9198 9198 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9199 9199 \ 9200 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9200 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9201 9201 IEM_MC_END(); \ 9202 9202 break; \ … … 9236 9236 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 9237 9237 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9238 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9238 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9239 9239 IEM_MC_END(); \ 9240 9240 break; \ … … 9263 9263 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 9264 9264 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9265 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9265 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9266 9266 IEM_MC_END(); \ 9267 9267 break; \ … … 9290 9290 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 9291 9291 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9292 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9292 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9293 9293 IEM_MC_END(); \ 9294 9294 break; \ … … 9347 9347 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9348 9348 \ 9349 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9349 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9350 9350 IEM_MC_END(); \ 9351 9351 break; \ … … 9365 9365 \ 9366 9366 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9367 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9367 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9368 9368 IEM_MC_END(); \ 9369 9369 break; \ … … 9382 9382 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9383 9383 \ 9384 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9384 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9385 9385 IEM_MC_END(); \ 9386 9386 break; \ … … 9413 9413 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9414 9414 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9415 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9415 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9416 9416 IEM_MC_END(); \ 9417 9417 break; \ … … 9437 9437 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9438 9438 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9439 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9439 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9440 9440 IEM_MC_END(); \ 9441 9441 break; \ … … 9462 9462 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9463 9463 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9464 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9464 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9465 9465 IEM_MC_END(); \ 9466 9466 break; \ … … 9498 9498 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU16, pu16Dst, u16Src, cShiftArg, pEFlags); \ 9499 9499 \ 9500 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9500 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9501 9501 IEM_MC_END(); \ 9502 9502 break; \ … … 9517 9517 \ 9518 9518 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9519 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9519 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9520 9520 IEM_MC_END(); \ 9521 9521 break; \ … … 9535 9535 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnNormalU64, pu64Dst, u64Src, cShiftArg, pEFlags); \ 9536 9536 \ 9537 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9537 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9538 9538 IEM_MC_END(); \ 9539 9539 break; \ … … 9564 9564 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9565 9565 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9566 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9566 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9567 9567 IEM_MC_END(); \ 9568 9568 break; \ … … 9586 9586 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9587 9587 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9588 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9588 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9589 9589 IEM_MC_END(); \ 9590 9590 break; \ … … 9608 9608 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9609 9609 IEM_MC_COMMIT_EFLAGS(EFlags); \ 9610 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9610 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9611 9611 IEM_MC_END(); \ 9612 9612 break; \ … … 9946 9946 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence); 9947 9947 #endif 9948 IEM_MC_ADVANCE_ RIP_AND_FINISH();9948 IEM_MC_ADVANCE_PC_AND_FINISH(); 9949 9949 IEM_MC_END(); 9950 9950 } … … 9966 9966 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence); 9967 9967 #endif 9968 IEM_MC_ADVANCE_ RIP_AND_FINISH();9968 IEM_MC_ADVANCE_PC_AND_FINISH(); 9969 9969 IEM_MC_END(); 9970 9970 } … … 9986 9986 IEM_MC_CALL_VOID_AIMPL_0(iemAImpl_alt_mem_fence); 9987 9987 #endif 9988 IEM_MC_ADVANCE_ RIP_AND_FINISH();9988 IEM_MC_ADVANCE_PC_AND_FINISH(); 9989 9989 IEM_MC_END(); 9990 9990 } … … 10003 10003 IEM_MC_FETCH_SREG_BASE_U64(u64Dst, X86_SREG_FS); 10004 10004 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Dst); 10005 IEM_MC_ADVANCE_ RIP_AND_FINISH();10005 IEM_MC_ADVANCE_PC_AND_FINISH(); 10006 10006 IEM_MC_END(); 10007 10007 } … … 10014 10014 IEM_MC_FETCH_SREG_BASE_U32(u32Dst, X86_SREG_FS); 10015 10015 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Dst); 10016 IEM_MC_ADVANCE_ RIP_AND_FINISH();10016 IEM_MC_ADVANCE_PC_AND_FINISH(); 10017 10017 IEM_MC_END(); 10018 10018 } … … 10032 10032 IEM_MC_FETCH_SREG_BASE_U64(u64Dst, X86_SREG_GS); 10033 10033 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Dst); 10034 IEM_MC_ADVANCE_ RIP_AND_FINISH();10034 IEM_MC_ADVANCE_PC_AND_FINISH(); 10035 10035 IEM_MC_END(); 10036 10036 } … … 10043 10043 IEM_MC_FETCH_SREG_BASE_U32(u32Dst, X86_SREG_GS); 10044 10044 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Dst); 10045 IEM_MC_ADVANCE_ RIP_AND_FINISH();10045 IEM_MC_ADVANCE_PC_AND_FINISH(); 10046 10046 IEM_MC_END(); 10047 10047 } … … 10062 10062 IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(u64Dst); 10063 10063 IEM_MC_STORE_SREG_BASE_U64(X86_SREG_FS, u64Dst); 10064 IEM_MC_ADVANCE_ RIP_AND_FINISH();10064 IEM_MC_ADVANCE_PC_AND_FINISH(); 10065 10065 IEM_MC_END(); 10066 10066 } … … 10073 10073 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 10074 10074 IEM_MC_STORE_SREG_BASE_U64(X86_SREG_FS, u32Dst); 10075 IEM_MC_ADVANCE_ RIP_AND_FINISH();10075 IEM_MC_ADVANCE_PC_AND_FINISH(); 10076 10076 IEM_MC_END(); 10077 10077 } … … 10092 10092 IEM_MC_MAYBE_RAISE_NON_CANONICAL_ADDR_GP0(u64Dst); 10093 10093 IEM_MC_STORE_SREG_BASE_U64(X86_SREG_GS, u64Dst); 10094 IEM_MC_ADVANCE_ RIP_AND_FINISH();10094 IEM_MC_ADVANCE_PC_AND_FINISH(); 10095 10095 IEM_MC_END(); 10096 10096 } … … 10103 10103 IEM_MC_FETCH_GREG_U32(u32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 10104 10104 IEM_MC_STORE_SREG_BASE_U64(X86_SREG_GS, u32Dst); 10105 IEM_MC_ADVANCE_ RIP_AND_FINISH();10105 IEM_MC_ADVANCE_PC_AND_FINISH(); 10106 10106 IEM_MC_END(); 10107 10107 } … … 10198 10198 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u8, pu8Dst, pu8Al, u8Src, pEFlags); 10199 10199 10200 IEM_MC_ADVANCE_ RIP_AND_FINISH();10200 IEM_MC_ADVANCE_PC_AND_FINISH(); 10201 10201 IEM_MC_END(); 10202 10202 } … … 10226 10226 IEM_MC_COMMIT_EFLAGS(EFlags); \ 10227 10227 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Al); \ 10228 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10228 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10229 10229 IEM_MC_END() 10230 10230 … … 10268 10268 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u16, pu16Dst, pu16Ax, u16Src, pEFlags); 10269 10269 10270 IEM_MC_ADVANCE_ RIP_AND_FINISH();10270 IEM_MC_ADVANCE_PC_AND_FINISH(); 10271 10271 IEM_MC_END(); 10272 10272 break; … … 10292 10292 } IEM_MC_ENDIF(); 10293 10293 10294 IEM_MC_ADVANCE_ RIP_AND_FINISH();10294 IEM_MC_ADVANCE_PC_AND_FINISH(); 10295 10295 IEM_MC_END(); 10296 10296 break; … … 10310 10310 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpxchg_u64, pu64Dst, pu64Rax, u64Src, pEFlags); 10311 10311 10312 IEM_MC_ADVANCE_ RIP_AND_FINISH();10312 IEM_MC_ADVANCE_PC_AND_FINISH(); 10313 10313 IEM_MC_END(); 10314 10314 break; … … 10347 10347 IEM_MC_COMMIT_EFLAGS(EFlags); \ 10348 10348 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Ax); \ 10349 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10349 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10350 10350 IEM_MC_END(); \ 10351 10351 break; \ … … 10378 10378 } IEM_MC_ENDIF(); \ 10379 10379 \ 10380 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10380 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10381 10381 IEM_MC_END(); \ 10382 10382 break; \ … … 10406 10406 IEM_MC_COMMIT_EFLAGS(EFlags); \ 10407 10407 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Rax); \ 10408 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10408 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10409 10409 IEM_MC_END(); \ 10410 10410 break; \ … … 10497 10497 IEM_MC_FETCH_GREG_U8_ZX_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 10498 10498 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 10499 IEM_MC_ADVANCE_ RIP_AND_FINISH();10499 IEM_MC_ADVANCE_PC_AND_FINISH(); 10500 10500 IEM_MC_END(); 10501 10501 break; … … 10507 10507 IEM_MC_FETCH_GREG_U8_ZX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 10508 10508 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 10509 IEM_MC_ADVANCE_ RIP_AND_FINISH();10509 IEM_MC_ADVANCE_PC_AND_FINISH(); 10510 10510 IEM_MC_END(); 10511 10511 break; … … 10517 10517 IEM_MC_FETCH_GREG_U8_ZX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 10518 10518 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 10519 IEM_MC_ADVANCE_ RIP_AND_FINISH();10519 IEM_MC_ADVANCE_PC_AND_FINISH(); 10520 10520 IEM_MC_END(); 10521 10521 break; … … 10539 10539 IEM_MC_FETCH_MEM_U8_ZX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 10540 10540 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 10541 IEM_MC_ADVANCE_ RIP_AND_FINISH();10541 IEM_MC_ADVANCE_PC_AND_FINISH(); 10542 10542 IEM_MC_END(); 10543 10543 break; … … 10551 10551 IEM_MC_FETCH_MEM_U8_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 10552 10552 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 10553 IEM_MC_ADVANCE_ RIP_AND_FINISH();10553 IEM_MC_ADVANCE_PC_AND_FINISH(); 10554 10554 IEM_MC_END(); 10555 10555 break; … … 10563 10563 IEM_MC_FETCH_MEM_U8_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 10564 10564 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 10565 IEM_MC_ADVANCE_ RIP_AND_FINISH();10565 IEM_MC_ADVANCE_PC_AND_FINISH(); 10566 10566 IEM_MC_END(); 10567 10567 break; … … 10600 10600 IEM_MC_FETCH_GREG_U16_ZX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 10601 10601 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 10602 IEM_MC_ADVANCE_ RIP_AND_FINISH();10602 IEM_MC_ADVANCE_PC_AND_FINISH(); 10603 10603 IEM_MC_END(); 10604 10604 } … … 10610 10610 IEM_MC_FETCH_GREG_U16_ZX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 10611 10611 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 10612 IEM_MC_ADVANCE_ RIP_AND_FINISH();10612 IEM_MC_ADVANCE_PC_AND_FINISH(); 10613 10613 IEM_MC_END(); 10614 10614 } … … 10628 10628 IEM_MC_FETCH_MEM_U16_ZX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 10629 10629 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 10630 IEM_MC_ADVANCE_ RIP_AND_FINISH();10630 IEM_MC_ADVANCE_PC_AND_FINISH(); 10631 10631 IEM_MC_END(); 10632 10632 } … … 10640 10640 IEM_MC_FETCH_MEM_U16_ZX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 10641 10641 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 10642 IEM_MC_ADVANCE_ RIP_AND_FINISH();10642 IEM_MC_ADVANCE_PC_AND_FINISH(); 10643 10643 IEM_MC_END(); 10644 10644 } … … 10716 10716 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10717 10717 \ 10718 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10718 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10719 10719 IEM_MC_END(); \ 10720 10720 break; \ … … 10731 10731 \ 10732 10732 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 10733 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10733 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10734 10734 IEM_MC_END(); \ 10735 10735 break; \ … … 10745 10745 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10746 10746 \ 10747 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10747 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10748 10748 IEM_MC_END(); \ 10749 10749 break; \ … … 10778 10778 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10779 10779 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10780 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10780 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10781 10781 IEM_MC_END(); \ 10782 10782 break; \ … … 10800 10800 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10801 10801 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10802 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10802 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10803 10803 IEM_MC_END(); \ 10804 10804 break; \ … … 10822 10822 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10823 10823 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10824 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10824 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10825 10825 IEM_MC_END(); \ 10826 10826 break; \ … … 10854 10854 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 10855 10855 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10856 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10856 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10857 10857 IEM_MC_END(); \ 10858 10858 break; \ … … 10876 10876 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 10877 10877 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10878 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10878 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10879 10879 IEM_MC_END(); \ 10880 10880 break; \ … … 10898 10898 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 10899 10899 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10900 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10900 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10901 10901 IEM_MC_END(); \ 10902 10902 break; \ … … 10929 10929 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10930 10930 \ 10931 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10931 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10932 10932 IEM_MC_END(); \ 10933 10933 break; \ … … 10943 10943 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10944 10944 \ 10945 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10945 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10946 10946 IEM_MC_END(); \ 10947 10947 break; \ … … 10957 10957 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10958 10958 \ 10959 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10959 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10960 10960 IEM_MC_END(); \ 10961 10961 break; \ … … 10990 10990 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 10991 10991 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10992 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10992 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10993 10993 IEM_MC_END(); \ 10994 10994 break; \ … … 11012 11012 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 11013 11013 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11014 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11014 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11015 11015 IEM_MC_END(); \ 11016 11016 break; \ … … 11034 11034 IEM_MC_MEM_COMMIT_AND_UNMAP_RO(bUnmapInfo); \ 11035 11035 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11036 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11036 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11037 11037 IEM_MC_END(); \ 11038 11038 break; \ … … 11171 11171 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11172 11172 \ 11173 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11173 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11174 11174 IEM_MC_END(); \ 11175 11175 break; \ … … 11189 11189 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 11190 11190 } IEM_MC_ENDIF(); \ 11191 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11191 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11192 11192 IEM_MC_END(); \ 11193 11193 break; \ … … 11205 11205 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11206 11206 \ 11207 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11207 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11208 11208 IEM_MC_END(); \ 11209 11209 break; \ … … 11233 11233 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11234 11234 \ 11235 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11235 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11236 11236 IEM_MC_END(); \ 11237 11237 break; \ … … 11254 11254 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 11255 11255 } IEM_MC_ENDIF(); \ 11256 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11256 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11257 11257 IEM_MC_END(); \ 11258 11258 break; \ … … 11272 11272 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 11273 11273 \ 11274 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11274 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11275 11275 IEM_MC_END(); \ 11276 11276 break; \ … … 11413 11413 IEM_MC_FETCH_GREG_U8_SX_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 11414 11414 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 11415 IEM_MC_ADVANCE_ RIP_AND_FINISH();11415 IEM_MC_ADVANCE_PC_AND_FINISH(); 11416 11416 IEM_MC_END(); 11417 11417 break; … … 11423 11423 IEM_MC_FETCH_GREG_U8_SX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 11424 11424 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 11425 IEM_MC_ADVANCE_ RIP_AND_FINISH();11425 IEM_MC_ADVANCE_PC_AND_FINISH(); 11426 11426 IEM_MC_END(); 11427 11427 break; … … 11433 11433 IEM_MC_FETCH_GREG_U8_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 11434 11434 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 11435 IEM_MC_ADVANCE_ RIP_AND_FINISH();11435 IEM_MC_ADVANCE_PC_AND_FINISH(); 11436 11436 IEM_MC_END(); 11437 11437 break; … … 11455 11455 IEM_MC_FETCH_MEM_U8_SX_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11456 11456 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 11457 IEM_MC_ADVANCE_ RIP_AND_FINISH();11457 IEM_MC_ADVANCE_PC_AND_FINISH(); 11458 11458 IEM_MC_END(); 11459 11459 break; … … 11467 11467 IEM_MC_FETCH_MEM_U8_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11468 11468 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 11469 IEM_MC_ADVANCE_ RIP_AND_FINISH();11469 IEM_MC_ADVANCE_PC_AND_FINISH(); 11470 11470 IEM_MC_END(); 11471 11471 break; … … 11479 11479 IEM_MC_FETCH_MEM_U8_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11480 11480 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 11481 IEM_MC_ADVANCE_ RIP_AND_FINISH();11481 IEM_MC_ADVANCE_PC_AND_FINISH(); 11482 11482 IEM_MC_END(); 11483 11483 break; … … 11512 11512 IEM_MC_FETCH_GREG_U16_SX_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 11513 11513 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 11514 IEM_MC_ADVANCE_ RIP_AND_FINISH();11514 IEM_MC_ADVANCE_PC_AND_FINISH(); 11515 11515 IEM_MC_END(); 11516 11516 } … … 11522 11522 IEM_MC_FETCH_GREG_U16_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 11523 11523 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 11524 IEM_MC_ADVANCE_ RIP_AND_FINISH();11524 IEM_MC_ADVANCE_PC_AND_FINISH(); 11525 11525 IEM_MC_END(); 11526 11526 } … … 11540 11540 IEM_MC_FETCH_MEM_U16_SX_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11541 11541 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 11542 IEM_MC_ADVANCE_ RIP_AND_FINISH();11542 IEM_MC_ADVANCE_PC_AND_FINISH(); 11543 11543 IEM_MC_END(); 11544 11544 } … … 11552 11552 IEM_MC_FETCH_MEM_U16_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 11553 11553 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 11554 IEM_MC_ADVANCE_ RIP_AND_FINISH();11554 IEM_MC_ADVANCE_PC_AND_FINISH(); 11555 11555 IEM_MC_END(); 11556 11556 } … … 11585 11585 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u8, pu8Dst, pu8Reg, pEFlags); 11586 11586 11587 IEM_MC_ADVANCE_ RIP_AND_FINISH();11587 IEM_MC_ADVANCE_PC_AND_FINISH(); 11588 11588 IEM_MC_END(); 11589 11589 } … … 11613 11613 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11614 11614 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), u8RegCopy); \ 11615 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11615 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11616 11616 IEM_MC_END() 11617 11617 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK) || (pVCpu->iem.s.fExec & IEM_F_X86_DISREGARD_LOCK)) … … 11656 11656 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u16, pu16Dst, pu16Reg, pEFlags); 11657 11657 11658 IEM_MC_ADVANCE_ RIP_AND_FINISH();11658 IEM_MC_ADVANCE_PC_AND_FINISH(); 11659 11659 IEM_MC_END(); 11660 11660 break; … … 11674 11674 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); 11675 11675 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 11676 IEM_MC_ADVANCE_ RIP_AND_FINISH();11676 IEM_MC_ADVANCE_PC_AND_FINISH(); 11677 11677 IEM_MC_END(); 11678 11678 break; … … 11690 11690 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_xadd_u64, pu64Dst, pu64Reg, pEFlags); 11691 11691 11692 IEM_MC_ADVANCE_ RIP_AND_FINISH();11692 IEM_MC_ADVANCE_PC_AND_FINISH(); 11693 11693 IEM_MC_END(); 11694 11694 break; … … 11726 11726 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11727 11727 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16RegCopy); \ 11728 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11728 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11729 11729 IEM_MC_END(); \ 11730 11730 break; \ … … 11750 11750 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11751 11751 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32RegCopy); \ 11752 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11752 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11753 11753 IEM_MC_END(); \ 11754 11754 break; \ … … 11774 11774 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11775 11775 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64RegCopy); \ 11776 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \11776 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 11777 11777 IEM_MC_END(); \ 11778 11778 break; \ … … 11819 11819 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11820 11820 11821 IEM_MC_ADVANCE_ RIP_AND_FINISH();11821 IEM_MC_ADVANCE_PC_AND_FINISH(); 11822 11822 IEM_MC_END(); 11823 11823 } … … 11845 11845 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11846 11846 11847 IEM_MC_ADVANCE_ RIP_AND_FINISH();11847 IEM_MC_ADVANCE_PC_AND_FINISH(); 11848 11848 IEM_MC_END(); 11849 11849 } … … 11876 11876 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11877 11877 11878 IEM_MC_ADVANCE_ RIP_AND_FINISH();11878 IEM_MC_ADVANCE_PC_AND_FINISH(); 11879 11879 IEM_MC_END(); 11880 11880 } … … 11902 11902 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11903 11903 11904 IEM_MC_ADVANCE_ RIP_AND_FINISH();11904 IEM_MC_ADVANCE_PC_AND_FINISH(); 11905 11905 IEM_MC_END(); 11906 11906 } … … 11933 11933 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 11934 11934 11935 IEM_MC_ADVANCE_ RIP_AND_FINISH();11935 IEM_MC_ADVANCE_PC_AND_FINISH(); 11936 11936 IEM_MC_END(); 11937 11937 } … … 11960 11960 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 11961 11961 11962 IEM_MC_ADVANCE_ RIP_AND_FINISH();11962 IEM_MC_ADVANCE_PC_AND_FINISH(); 11963 11963 IEM_MC_END(); 11964 11964 } … … 11991 11991 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst); 11992 11992 11993 IEM_MC_ADVANCE_ RIP_AND_FINISH();11993 IEM_MC_ADVANCE_PC_AND_FINISH(); 11994 11994 IEM_MC_END(); 11995 11995 } … … 12018 12018 IEM_MC_STORE_XREG_XMM_U64(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iQword*/, Dst); 12019 12019 12020 IEM_MC_ADVANCE_ RIP_AND_FINISH();12020 IEM_MC_ADVANCE_PC_AND_FINISH(); 12021 12021 IEM_MC_END(); 12022 12022 } … … 12046 12046 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 12047 12047 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value); 12048 IEM_MC_ADVANCE_ RIP_AND_FINISH();12048 IEM_MC_ADVANCE_PC_AND_FINISH(); 12049 12049 IEM_MC_END(); 12050 12050 break; … … 12060 12060 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 12061 12061 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value); 12062 IEM_MC_ADVANCE_ RIP_AND_FINISH();12062 IEM_MC_ADVANCE_PC_AND_FINISH(); 12063 12063 IEM_MC_END(); 12064 12064 break; … … 12103 12103 IEM_MC_STORE_MREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue); 12104 12104 12105 IEM_MC_ADVANCE_ RIP_AND_FINISH();12105 IEM_MC_ADVANCE_PC_AND_FINISH(); 12106 12106 IEM_MC_END(); 12107 12107 } … … 12125 12125 IEM_MC_STORE_MREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue); 12126 12126 12127 IEM_MC_ADVANCE_ RIP_AND_FINISH();12127 IEM_MC_ADVANCE_PC_AND_FINISH(); 12128 12128 IEM_MC_END(); 12129 12129 } … … 12151 12151 IEM_MC_FETCH_GREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm)); 12152 12152 IEM_MC_STORE_XREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue); 12153 IEM_MC_ADVANCE_ RIP_AND_FINISH();12153 IEM_MC_ADVANCE_PC_AND_FINISH(); 12154 12154 IEM_MC_END(); 12155 12155 } … … 12171 12171 IEM_MC_FETCH_MEM_U16(uValue, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 12172 12172 IEM_MC_STORE_XREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue); 12173 IEM_MC_ADVANCE_ RIP_AND_FINISH();12173 IEM_MC_ADVANCE_PC_AND_FINISH(); 12174 12174 IEM_MC_END(); 12175 12175 } … … 12200 12200 IEM_MC_FETCH_MREG_U16(uValue, IEM_GET_MODRM_RM_8(bRm), bImm & 3); 12201 12201 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue); 12202 IEM_MC_ADVANCE_ RIP_AND_FINISH();12202 IEM_MC_ADVANCE_PC_AND_FINISH(); 12203 12203 IEM_MC_END(); 12204 12204 } … … 12227 12227 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm), bImm & 7); 12228 12228 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue); 12229 IEM_MC_ADVANCE_ RIP_AND_FINISH();12229 IEM_MC_ADVANCE_PC_AND_FINISH(); 12230 12230 IEM_MC_END(); 12231 12231 } … … 12261 12261 IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 12262 12262 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_shufps_u128, pDst, pSrc, bImmArg); 12263 IEM_MC_ADVANCE_ RIP_AND_FINISH();12263 IEM_MC_ADVANCE_PC_AND_FINISH(); 12264 12264 IEM_MC_END(); 12265 12265 } … … 12286 12286 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_shufps_u128, pDst, pSrc, bImmArg); 12287 12287 12288 IEM_MC_ADVANCE_ RIP_AND_FINISH();12288 IEM_MC_ADVANCE_PC_AND_FINISH(); 12289 12289 IEM_MC_END(); 12290 12290 } … … 12313 12313 IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 12314 12314 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_shufpd_u128, pDst, pSrc, bImmArg); 12315 IEM_MC_ADVANCE_ RIP_AND_FINISH();12315 IEM_MC_ADVANCE_PC_AND_FINISH(); 12316 12316 IEM_MC_END(); 12317 12317 } … … 12338 12338 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_shufpd_u128, pDst, pSrc, bImmArg); 12339 12339 12340 IEM_MC_ADVANCE_ RIP_AND_FINISH();12340 IEM_MC_ADVANCE_PC_AND_FINISH(); 12341 12341 IEM_MC_END(); 12342 12342 } … … 12384 12384 IEM_MC_STORE_GREG_PAIR_U32(X86_GREG_xAX, X86_GREG_xDX, u64EaxEdx); \ 12385 12385 } IEM_MC_ENDIF(); \ 12386 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \12386 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 12387 12387 \ 12388 12388 IEM_MC_END() … … 12442 12442 IEM_MC_STORE_GREG_PAIR_U64(X86_GREG_xAX, X86_GREG_xDX, u128RaxRdx); \ 12443 12443 } IEM_MC_ENDIF(); \ 12444 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \12444 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 12445 12445 IEM_MC_END() 12446 12446 … … 12715 12715 IEM_MC_REF_GREG_U32(pu32Dst, iReg); /* Don't clear the high dword! */ 12716 12716 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u16, pu32Dst); 12717 IEM_MC_ADVANCE_ RIP_AND_FINISH();12717 IEM_MC_ADVANCE_PC_AND_FINISH(); 12718 12718 IEM_MC_END(); 12719 12719 break; … … 12726 12726 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u32, pu32Dst); 12727 12727 IEM_MC_CLEAR_HIGH_GREG_U64(iReg); 12728 IEM_MC_ADVANCE_ RIP_AND_FINISH();12728 IEM_MC_ADVANCE_PC_AND_FINISH(); 12729 12729 IEM_MC_END(); 12730 12730 break; … … 12736 12736 IEM_MC_REF_GREG_U64(pu64Dst, iReg); 12737 12737 IEM_MC_CALL_VOID_AIMPL_1(iemAImpl_bswap_u64, pu64Dst); 12738 IEM_MC_ADVANCE_ RIP_AND_FINISH();12738 IEM_MC_ADVANCE_PC_AND_FINISH(); 12739 12739 IEM_MC_END(); 12740 12740 break; … … 12966 12966 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_RM(pVCpu, bRm), uSrc); 12967 12967 12968 IEM_MC_ADVANCE_ RIP_AND_FINISH();12968 IEM_MC_ADVANCE_PC_AND_FINISH(); 12969 12969 IEM_MC_END(); 12970 12970 } … … 12986 12986 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 12987 12987 12988 IEM_MC_ADVANCE_ RIP_AND_FINISH();12988 IEM_MC_ADVANCE_PC_AND_FINISH(); 12989 12989 IEM_MC_END(); 12990 12990 } … … 13021 13021 IEM_MC_STORE_XREG_U64_ZX_U128(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 13022 13022 13023 IEM_MC_ADVANCE_ RIP_AND_FINISH();13023 IEM_MC_ADVANCE_PC_AND_FINISH(); 13024 13024 IEM_MC_END(); 13025 13025 } … … 13073 13073 IEM_MC_STORE_MREG_U64(IEM_GET_MODRM_REG_8(bRm), uSrc); 13074 13074 13075 IEM_MC_ADVANCE_ RIP_AND_FINISH();13075 IEM_MC_ADVANCE_PC_AND_FINISH(); 13076 13076 IEM_MC_END(); 13077 13077 } … … 13113 13113 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u64, puDst, puSrc); 13114 13114 13115 IEM_MC_ADVANCE_ RIP_AND_FINISH();13115 IEM_MC_ADVANCE_PC_AND_FINISH(); 13116 13116 IEM_MC_END(); 13117 13117 } … … 13145 13145 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc); 13146 13146 } IEM_MC_NATIVE_ENDIF(); 13147 IEM_MC_ADVANCE_ RIP_AND_FINISH();13147 IEM_MC_ADVANCE_PC_AND_FINISH(); 13148 13148 IEM_MC_END(); 13149 13149 } … … 13479 13479 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 13480 13480 13481 IEM_MC_ADVANCE_ RIP_AND_FINISH();13481 IEM_MC_ADVANCE_PC_AND_FINISH(); 13482 13482 IEM_MC_END(); 13483 13483 } … … 13525 13525 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 13526 13526 13527 IEM_MC_ADVANCE_ RIP_AND_FINISH();13527 IEM_MC_ADVANCE_PC_AND_FINISH(); 13528 13528 IEM_MC_END(); 13529 13529 } … … 13735 13735 IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 13736 13736 13737 IEM_MC_ADVANCE_ RIP_AND_FINISH();13737 IEM_MC_ADVANCE_PC_AND_FINISH(); 13738 13738 IEM_MC_END(); 13739 13739 } … … 13875 13875 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, u64EffAddr, u64Mem); 13876 13876 13877 IEM_MC_ADVANCE_ RIP_AND_FINISH();13877 IEM_MC_ADVANCE_PC_AND_FINISH(); 13878 13878 IEM_MC_END(); 13879 13879 } … … 13913 13913 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, u64EffAddr, u128Mem); 13914 13914 13915 IEM_MC_ADVANCE_ RIP_AND_FINISH();13915 IEM_MC_ADVANCE_PC_AND_FINISH(); 13916 13916 IEM_MC_END(); 13917 13917 } -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstVexMap1-x86.cpp.h
r108204 r108267 66 66 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2); 67 67 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 68 IEM_MC_ADVANCE_ RIP_AND_FINISH();68 IEM_MC_ADVANCE_PC_AND_FINISH(); 69 69 IEM_MC_END(); 70 70 } … … 85 85 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 86 86 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 87 IEM_MC_ADVANCE_ RIP_AND_FINISH();87 IEM_MC_ADVANCE_PC_AND_FINISH(); 88 88 IEM_MC_END(); 89 89 } … … 113 113 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2); 114 114 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 115 IEM_MC_ADVANCE_ RIP_AND_FINISH();115 IEM_MC_ADVANCE_PC_AND_FINISH(); 116 116 IEM_MC_END(); 117 117 } … … 136 136 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 137 137 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 138 IEM_MC_ADVANCE_ RIP_AND_FINISH();138 IEM_MC_ADVANCE_PC_AND_FINISH(); 139 139 IEM_MC_END(); 140 140 } … … 175 175 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 176 176 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 177 IEM_MC_ADVANCE_ RIP_AND_FINISH();177 IEM_MC_ADVANCE_PC_AND_FINISH(); 178 178 IEM_MC_END(); 179 179 } … … 200 200 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 201 201 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 202 IEM_MC_ADVANCE_ RIP_AND_FINISH();202 IEM_MC_ADVANCE_PC_AND_FINISH(); 203 203 IEM_MC_END(); 204 204 } … … 238 238 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 239 239 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 240 IEM_MC_ADVANCE_ RIP_AND_FINISH();240 IEM_MC_ADVANCE_PC_AND_FINISH(); 241 241 IEM_MC_END(); 242 242 } … … 263 263 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 264 264 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 265 IEM_MC_ADVANCE_ RIP_AND_FINISH();265 IEM_MC_ADVANCE_PC_AND_FINISH(); 266 266 IEM_MC_END(); 267 267 } … … 302 302 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc1, puSrc2); 303 303 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 304 IEM_MC_ADVANCE_ RIP_AND_FINISH();304 IEM_MC_ADVANCE_PC_AND_FINISH(); 305 305 IEM_MC_END(); 306 306 } … … 319 319 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc1, puSrc2); 320 320 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 321 IEM_MC_ADVANCE_ RIP_AND_FINISH();321 IEM_MC_ADVANCE_PC_AND_FINISH(); 322 322 IEM_MC_END(); 323 323 } … … 349 349 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 350 350 351 IEM_MC_ADVANCE_ RIP_AND_FINISH();351 IEM_MC_ADVANCE_PC_AND_FINISH(); 352 352 IEM_MC_END(); 353 353 } … … 372 372 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 373 373 374 IEM_MC_ADVANCE_ RIP_AND_FINISH();374 IEM_MC_ADVANCE_PC_AND_FINISH(); 375 375 IEM_MC_END(); 376 376 } … … 441 441 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU256, puDst, puSrc); 442 442 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 443 IEM_MC_ADVANCE_ RIP_AND_FINISH();443 IEM_MC_ADVANCE_PC_AND_FINISH(); 444 444 IEM_MC_END(); 445 445 } … … 456 456 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnU128, puDst, puSrc); 457 457 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 458 IEM_MC_ADVANCE_ RIP_AND_FINISH();458 IEM_MC_ADVANCE_PC_AND_FINISH(); 459 459 IEM_MC_END(); 460 460 } … … 483 483 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 484 484 485 IEM_MC_ADVANCE_ RIP_AND_FINISH();485 IEM_MC_ADVANCE_PC_AND_FINISH(); 486 486 IEM_MC_END(); 487 487 } … … 504 504 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 505 505 506 IEM_MC_ADVANCE_ RIP_AND_FINISH();506 IEM_MC_ADVANCE_PC_AND_FINISH(); 507 507 IEM_MC_END(); 508 508 } … … 540 540 IEM_MC_CALL_AVX_AIMPL_2(pImpl->pfnU256, puDst, puSrc); 541 541 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 542 IEM_MC_ADVANCE_ RIP_AND_FINISH();542 IEM_MC_ADVANCE_PC_AND_FINISH(); 543 543 IEM_MC_END(); 544 544 } … … 557 557 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 558 558 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 559 IEM_MC_ADVANCE_ RIP_AND_FINISH();559 IEM_MC_ADVANCE_PC_AND_FINISH(); 560 560 IEM_MC_END(); 561 561 } … … 582 582 IEM_MC_CALL_AVX_AIMPL_2(pImpl->pfnU256, puDst, puSrc); 583 583 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 584 IEM_MC_ADVANCE_ RIP_AND_FINISH();584 IEM_MC_ADVANCE_PC_AND_FINISH(); 585 585 IEM_MC_END(); 586 586 } … … 602 602 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 603 603 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 604 IEM_MC_ADVANCE_ RIP_AND_FINISH();604 IEM_MC_ADVANCE_PC_AND_FINISH(); 605 605 IEM_MC_END(); 606 606 } … … 664 664 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 665 665 IEM_GET_MODRM_RM(pVCpu, bRm)); 666 IEM_MC_ADVANCE_ RIP_AND_FINISH();666 IEM_MC_ADVANCE_PC_AND_FINISH(); 667 667 IEM_MC_END(); 668 668 } … … 684 684 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 685 685 686 IEM_MC_ADVANCE_ RIP_AND_FINISH();686 IEM_MC_ADVANCE_PC_AND_FINISH(); 687 687 IEM_MC_END(); 688 688 } … … 704 704 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 705 705 706 IEM_MC_ADVANCE_ RIP_AND_FINISH();706 IEM_MC_ADVANCE_PC_AND_FINISH(); 707 707 IEM_MC_END(); 708 708 } … … 739 739 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 740 740 IEM_GET_MODRM_RM(pVCpu, bRm)); 741 IEM_MC_ADVANCE_ RIP_AND_FINISH();741 IEM_MC_ADVANCE_PC_AND_FINISH(); 742 742 IEM_MC_END(); 743 743 } … … 759 759 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 760 760 761 IEM_MC_ADVANCE_ RIP_AND_FINISH();761 IEM_MC_ADVANCE_PC_AND_FINISH(); 762 762 IEM_MC_END(); 763 763 } … … 779 779 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 780 780 781 IEM_MC_ADVANCE_ RIP_AND_FINISH();781 IEM_MC_ADVANCE_PC_AND_FINISH(); 782 782 IEM_MC_END(); 783 783 } … … 812 812 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/, 813 813 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/); 814 IEM_MC_ADVANCE_ RIP_AND_FINISH();814 IEM_MC_ADVANCE_PC_AND_FINISH(); 815 815 IEM_MC_END(); 816 816 } … … 842 842 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 843 843 844 IEM_MC_ADVANCE_ RIP_AND_FINISH();844 IEM_MC_ADVANCE_PC_AND_FINISH(); 845 845 IEM_MC_END(); 846 846 } … … 876 876 IEM_GET_MODRM_RM(pVCpu, bRm) /*U32*/, 877 877 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/); 878 IEM_MC_ADVANCE_ RIP_AND_FINISH();878 IEM_MC_ADVANCE_PC_AND_FINISH(); 879 879 IEM_MC_END(); 880 880 } … … 906 906 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 907 907 908 IEM_MC_ADVANCE_ RIP_AND_FINISH();908 IEM_MC_ADVANCE_PC_AND_FINISH(); 909 909 IEM_MC_END(); 910 910 } … … 941 941 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 942 942 IEM_GET_MODRM_REG(pVCpu, bRm)); 943 IEM_MC_ADVANCE_ RIP_AND_FINISH();943 IEM_MC_ADVANCE_PC_AND_FINISH(); 944 944 IEM_MC_END(); 945 945 } … … 961 961 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 962 962 963 IEM_MC_ADVANCE_ RIP_AND_FINISH();963 IEM_MC_ADVANCE_PC_AND_FINISH(); 964 964 IEM_MC_END(); 965 965 } … … 981 981 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 982 982 983 IEM_MC_ADVANCE_ RIP_AND_FINISH();983 IEM_MC_ADVANCE_PC_AND_FINISH(); 984 984 IEM_MC_END(); 985 985 } … … 1016 1016 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 1017 1017 IEM_GET_MODRM_REG(pVCpu, bRm)); 1018 IEM_MC_ADVANCE_ RIP_AND_FINISH();1018 IEM_MC_ADVANCE_PC_AND_FINISH(); 1019 1019 IEM_MC_END(); 1020 1020 } … … 1036 1036 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1037 1037 1038 IEM_MC_ADVANCE_ RIP_AND_FINISH();1038 IEM_MC_ADVANCE_PC_AND_FINISH(); 1039 1039 IEM_MC_END(); 1040 1040 } … … 1056 1056 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1057 1057 1058 IEM_MC_ADVANCE_ RIP_AND_FINISH();1058 IEM_MC_ADVANCE_PC_AND_FINISH(); 1059 1059 IEM_MC_END(); 1060 1060 } … … 1089 1089 IEM_GET_MODRM_REG(pVCpu, bRm), 1090 1090 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/); 1091 IEM_MC_ADVANCE_ RIP_AND_FINISH();1091 IEM_MC_ADVANCE_PC_AND_FINISH(); 1092 1092 IEM_MC_END(); 1093 1093 } … … 1119 1119 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1120 1120 1121 IEM_MC_ADVANCE_ RIP_AND_FINISH();1121 IEM_MC_ADVANCE_PC_AND_FINISH(); 1122 1122 IEM_MC_END(); 1123 1123 } … … 1153 1153 IEM_GET_MODRM_REG(pVCpu, bRm), 1154 1154 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hss*/); 1155 IEM_MC_ADVANCE_ RIP_AND_FINISH();1155 IEM_MC_ADVANCE_PC_AND_FINISH(); 1156 1156 IEM_MC_END(); 1157 1157 } … … 1183 1183 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1184 1184 1185 IEM_MC_ADVANCE_ RIP_AND_FINISH();1185 IEM_MC_ADVANCE_PC_AND_FINISH(); 1186 1186 IEM_MC_END(); 1187 1187 } … … 1217 1217 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/); 1218 1218 1219 IEM_MC_ADVANCE_ RIP_AND_FINISH();1219 IEM_MC_ADVANCE_PC_AND_FINISH(); 1220 1220 IEM_MC_END(); 1221 1221 } … … 1252 1252 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/); 1253 1253 1254 IEM_MC_ADVANCE_ RIP_AND_FINISH();1254 IEM_MC_ADVANCE_PC_AND_FINISH(); 1255 1255 IEM_MC_END(); 1256 1256 } … … 1291 1291 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/); 1292 1292 1293 IEM_MC_ADVANCE_ RIP_AND_FINISH();1293 IEM_MC_ADVANCE_PC_AND_FINISH(); 1294 1294 IEM_MC_END(); 1295 1295 } … … 1348 1348 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1349 1349 1350 IEM_MC_ADVANCE_ RIP_AND_FINISH();1350 IEM_MC_ADVANCE_PC_AND_FINISH(); 1351 1351 IEM_MC_END(); 1352 1352 } … … 1370 1370 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1371 1371 1372 IEM_MC_ADVANCE_ RIP_AND_FINISH();1372 IEM_MC_ADVANCE_PC_AND_FINISH(); 1373 1373 IEM_MC_END(); 1374 1374 } … … 1397 1397 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1398 1398 1399 IEM_MC_ADVANCE_ RIP_AND_FINISH();1399 IEM_MC_ADVANCE_PC_AND_FINISH(); 1400 1400 IEM_MC_END(); 1401 1401 } … … 1422 1422 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1423 1423 1424 IEM_MC_ADVANCE_ RIP_AND_FINISH();1424 IEM_MC_ADVANCE_PC_AND_FINISH(); 1425 1425 IEM_MC_END(); 1426 1426 } … … 1463 1463 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1464 1464 1465 IEM_MC_ADVANCE_ RIP_AND_FINISH();1465 IEM_MC_ADVANCE_PC_AND_FINISH(); 1466 1466 IEM_MC_END(); 1467 1467 } … … 1484 1484 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1485 1485 1486 IEM_MC_ADVANCE_ RIP_AND_FINISH();1486 IEM_MC_ADVANCE_PC_AND_FINISH(); 1487 1487 IEM_MC_END(); 1488 1488 } … … 1509 1509 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1510 1510 1511 IEM_MC_ADVANCE_ RIP_AND_FINISH();1511 IEM_MC_ADVANCE_PC_AND_FINISH(); 1512 1512 IEM_MC_END(); 1513 1513 } … … 1531 1531 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1532 1532 1533 IEM_MC_ADVANCE_ RIP_AND_FINISH();1533 IEM_MC_ADVANCE_PC_AND_FINISH(); 1534 1534 IEM_MC_END(); 1535 1535 } … … 1567 1567 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1568 1568 1569 IEM_MC_ADVANCE_ RIP_AND_FINISH();1569 IEM_MC_ADVANCE_PC_AND_FINISH(); 1570 1570 IEM_MC_END(); 1571 1571 } … … 1614 1614 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1615 1615 1616 IEM_MC_ADVANCE_ RIP_AND_FINISH();1616 IEM_MC_ADVANCE_PC_AND_FINISH(); 1617 1617 IEM_MC_END(); 1618 1618 } … … 1703 1703 IEM_GET_EFFECTIVE_VVVV(pVCpu) /*Hq*/); 1704 1704 1705 IEM_MC_ADVANCE_ RIP_AND_FINISH();1705 IEM_MC_ADVANCE_PC_AND_FINISH(); 1706 1706 IEM_MC_END(); 1707 1707 } … … 1734 1734 uSrc); 1735 1735 1736 IEM_MC_ADVANCE_ RIP_AND_FINISH();1736 IEM_MC_ADVANCE_PC_AND_FINISH(); 1737 1737 IEM_MC_END(); 1738 1738 } … … 1769 1769 uSrc); 1770 1770 1771 IEM_MC_ADVANCE_ RIP_AND_FINISH();1771 IEM_MC_ADVANCE_PC_AND_FINISH(); 1772 1772 IEM_MC_END(); 1773 1773 } … … 1822 1822 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1823 1823 1824 IEM_MC_ADVANCE_ RIP_AND_FINISH();1824 IEM_MC_ADVANCE_PC_AND_FINISH(); 1825 1825 IEM_MC_END(); 1826 1826 } … … 1844 1844 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1845 1845 1846 IEM_MC_ADVANCE_ RIP_AND_FINISH();1846 IEM_MC_ADVANCE_PC_AND_FINISH(); 1847 1847 IEM_MC_END(); 1848 1848 } … … 1871 1871 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1872 1872 1873 IEM_MC_ADVANCE_ RIP_AND_FINISH();1873 IEM_MC_ADVANCE_PC_AND_FINISH(); 1874 1874 IEM_MC_END(); 1875 1875 } … … 1896 1896 IEM_MC_CLEAR_ZREG_256_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 1897 1897 1898 IEM_MC_ADVANCE_ RIP_AND_FINISH();1898 IEM_MC_ADVANCE_PC_AND_FINISH(); 1899 1899 IEM_MC_END(); 1900 1900 } … … 1933 1933 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1934 1934 1935 IEM_MC_ADVANCE_ RIP_AND_FINISH();1935 IEM_MC_ADVANCE_PC_AND_FINISH(); 1936 1936 IEM_MC_END(); 1937 1937 } … … 1979 1979 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1980 1980 1981 IEM_MC_ADVANCE_ RIP_AND_FINISH();1981 IEM_MC_ADVANCE_PC_AND_FINISH(); 1982 1982 IEM_MC_END(); 1983 1983 } … … 2051 2051 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 2052 2052 IEM_GET_MODRM_RM(pVCpu, bRm)); 2053 IEM_MC_ADVANCE_ RIP_AND_FINISH();2053 IEM_MC_ADVANCE_PC_AND_FINISH(); 2054 2054 IEM_MC_END(); 2055 2055 } … … 2073 2073 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2074 2074 2075 IEM_MC_ADVANCE_ RIP_AND_FINISH();2075 IEM_MC_ADVANCE_PC_AND_FINISH(); 2076 2076 IEM_MC_END(); 2077 2077 } … … 2090 2090 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2091 2091 2092 IEM_MC_ADVANCE_ RIP_AND_FINISH();2092 IEM_MC_ADVANCE_PC_AND_FINISH(); 2093 2093 IEM_MC_END(); 2094 2094 } … … 2128 2128 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 2129 2129 IEM_GET_MODRM_RM(pVCpu, bRm)); 2130 IEM_MC_ADVANCE_ RIP_AND_FINISH();2130 IEM_MC_ADVANCE_PC_AND_FINISH(); 2131 2131 IEM_MC_END(); 2132 2132 } … … 2150 2150 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2151 2151 2152 IEM_MC_ADVANCE_ RIP_AND_FINISH();2152 IEM_MC_ADVANCE_PC_AND_FINISH(); 2153 2153 IEM_MC_END(); 2154 2154 } … … 2167 2167 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2168 2168 2169 IEM_MC_ADVANCE_ RIP_AND_FINISH();2169 IEM_MC_ADVANCE_PC_AND_FINISH(); 2170 2170 IEM_MC_END(); 2171 2171 } … … 2224 2224 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 2225 2225 IEM_GET_MODRM_REG(pVCpu, bRm)); 2226 IEM_MC_ADVANCE_ RIP_AND_FINISH();2226 IEM_MC_ADVANCE_PC_AND_FINISH(); 2227 2227 IEM_MC_END(); 2228 2228 } … … 2246 2246 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2247 2247 2248 IEM_MC_ADVANCE_ RIP_AND_FINISH();2248 IEM_MC_ADVANCE_PC_AND_FINISH(); 2249 2249 IEM_MC_END(); 2250 2250 } … … 2263 2263 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2264 2264 2265 IEM_MC_ADVANCE_ RIP_AND_FINISH();2265 IEM_MC_ADVANCE_PC_AND_FINISH(); 2266 2266 IEM_MC_END(); 2267 2267 } … … 2300 2300 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 2301 2301 IEM_GET_MODRM_REG(pVCpu, bRm)); 2302 IEM_MC_ADVANCE_ RIP_AND_FINISH();2302 IEM_MC_ADVANCE_PC_AND_FINISH(); 2303 2303 IEM_MC_END(); 2304 2304 } … … 2322 2322 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2323 2323 2324 IEM_MC_ADVANCE_ RIP_AND_FINISH();2324 IEM_MC_ADVANCE_PC_AND_FINISH(); 2325 2325 IEM_MC_END(); 2326 2326 } … … 2339 2339 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2340 2340 2341 IEM_MC_ADVANCE_ RIP_AND_FINISH();2341 IEM_MC_ADVANCE_PC_AND_FINISH(); 2342 2342 IEM_MC_END(); 2343 2343 } … … 2397 2397 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2398 2398 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2399 IEM_MC_ADVANCE_ RIP_AND_FINISH();2399 IEM_MC_ADVANCE_PC_AND_FINISH(); 2400 2400 IEM_MC_END(); 2401 2401 } … … 2421 2421 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2422 2422 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2423 IEM_MC_ADVANCE_ RIP_AND_FINISH();2423 IEM_MC_ADVANCE_PC_AND_FINISH(); 2424 2424 IEM_MC_END(); 2425 2425 } … … 2445 2445 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2446 2446 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2447 IEM_MC_ADVANCE_ RIP_AND_FINISH();2447 IEM_MC_ADVANCE_PC_AND_FINISH(); 2448 2448 IEM_MC_END(); 2449 2449 } … … 2469 2469 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2470 2470 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2471 IEM_MC_ADVANCE_ RIP_AND_FINISH();2471 IEM_MC_ADVANCE_PC_AND_FINISH(); 2472 2472 IEM_MC_END(); 2473 2473 } … … 2502 2502 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2503 2503 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2504 IEM_MC_ADVANCE_ RIP_AND_FINISH();2504 IEM_MC_ADVANCE_PC_AND_FINISH(); 2505 2505 IEM_MC_END(); 2506 2506 } … … 2526 2526 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2527 2527 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2528 IEM_MC_ADVANCE_ RIP_AND_FINISH();2528 IEM_MC_ADVANCE_PC_AND_FINISH(); 2529 2529 IEM_MC_END(); 2530 2530 } … … 2550 2550 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2551 2551 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2552 IEM_MC_ADVANCE_ RIP_AND_FINISH();2552 IEM_MC_ADVANCE_PC_AND_FINISH(); 2553 2553 IEM_MC_END(); 2554 2554 } … … 2574 2574 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2575 2575 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2576 IEM_MC_ADVANCE_ RIP_AND_FINISH();2576 IEM_MC_ADVANCE_PC_AND_FINISH(); 2577 2577 IEM_MC_END(); 2578 2578 } … … 2616 2616 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2617 2617 2618 IEM_MC_ADVANCE_ RIP_AND_FINISH();2618 IEM_MC_ADVANCE_PC_AND_FINISH(); 2619 2619 IEM_MC_END(); 2620 2620 } … … 2633 2633 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2634 2634 2635 IEM_MC_ADVANCE_ RIP_AND_FINISH();2635 IEM_MC_ADVANCE_PC_AND_FINISH(); 2636 2636 IEM_MC_END(); 2637 2637 } … … 2677 2677 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2678 2678 2679 IEM_MC_ADVANCE_ RIP_AND_FINISH();2679 IEM_MC_ADVANCE_PC_AND_FINISH(); 2680 2680 IEM_MC_END(); 2681 2681 } … … 2694 2694 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 2695 2695 2696 IEM_MC_ADVANCE_ RIP_AND_FINISH();2696 IEM_MC_ADVANCE_PC_AND_FINISH(); 2697 2697 IEM_MC_END(); 2698 2698 } … … 2748 2748 pi64Dst, pr32Src); \ 2749 2749 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); \ 2750 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2750 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2751 2751 IEM_MC_END(); \ 2752 2752 } \ … … 2770 2770 pi64Dst, pr32Src); \ 2771 2771 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); \ 2772 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2772 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2773 2773 IEM_MC_END(); \ 2774 2774 } \ … … 2792 2792 pi32Dst, pr32Src); \ 2793 2793 IEM_MC_STORE_GREG_I32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); \ 2794 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2794 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2795 2795 IEM_MC_END(); \ 2796 2796 } \ … … 2814 2814 pi32Dst, pr32Src); \ 2815 2815 IEM_MC_STORE_GREG_I32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); \ 2816 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2816 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2817 2817 IEM_MC_END(); \ 2818 2818 } \ … … 2842 2842 pi64Dst, pr64Src); \ 2843 2843 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); \ 2844 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2844 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2845 2845 IEM_MC_END(); \ 2846 2846 } \ … … 2864 2864 pi64Dst, pr64Src); \ 2865 2865 IEM_MC_STORE_GREG_I64(IEM_GET_MODRM_REG(pVCpu, bRm), i64Dst); \ 2866 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2866 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2867 2867 IEM_MC_END(); \ 2868 2868 } \ … … 2886 2886 pi32Dst, pr64Src); \ 2887 2887 IEM_MC_STORE_GREG_I32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); \ 2888 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2888 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2889 2889 IEM_MC_END(); \ 2890 2890 } \ … … 2908 2908 pi32Dst, pr64Src); \ 2909 2909 IEM_MC_STORE_GREG_I32(IEM_GET_MODRM_REG(pVCpu, bRm), i32Dst); \ 2910 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2910 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2911 2911 IEM_MC_END(); \ 2912 2912 } \ … … 2982 2982 IEM_MC_COMMIT_EFLAGS(fEFlags); 2983 2983 2984 IEM_MC_ADVANCE_ RIP_AND_FINISH();2984 IEM_MC_ADVANCE_PC_AND_FINISH(); 2985 2985 IEM_MC_END(); 2986 2986 } … … 3009 3009 IEM_MC_COMMIT_EFLAGS(fEFlags); 3010 3010 3011 IEM_MC_ADVANCE_ RIP_AND_FINISH();3011 IEM_MC_ADVANCE_PC_AND_FINISH(); 3012 3012 IEM_MC_END(); 3013 3013 } … … 3045 3045 IEM_MC_COMMIT_EFLAGS(fEFlags); 3046 3046 3047 IEM_MC_ADVANCE_ RIP_AND_FINISH();3047 IEM_MC_ADVANCE_PC_AND_FINISH(); 3048 3048 IEM_MC_END(); 3049 3049 } … … 3072 3072 IEM_MC_COMMIT_EFLAGS(fEFlags); 3073 3073 3074 IEM_MC_ADVANCE_ RIP_AND_FINISH();3074 IEM_MC_ADVANCE_PC_AND_FINISH(); 3075 3075 IEM_MC_END(); 3076 3076 } … … 3111 3111 IEM_MC_COMMIT_EFLAGS(fEFlags); 3112 3112 3113 IEM_MC_ADVANCE_ RIP_AND_FINISH();3113 IEM_MC_ADVANCE_PC_AND_FINISH(); 3114 3114 IEM_MC_END(); 3115 3115 } … … 3138 3138 IEM_MC_COMMIT_EFLAGS(fEFlags); 3139 3139 3140 IEM_MC_ADVANCE_ RIP_AND_FINISH();3140 IEM_MC_ADVANCE_PC_AND_FINISH(); 3141 3141 IEM_MC_END(); 3142 3142 } … … 3174 3174 IEM_MC_COMMIT_EFLAGS(fEFlags); 3175 3175 3176 IEM_MC_ADVANCE_ RIP_AND_FINISH();3176 IEM_MC_ADVANCE_PC_AND_FINISH(); 3177 3177 IEM_MC_END(); 3178 3178 } … … 3201 3201 IEM_MC_COMMIT_EFLAGS(fEFlags); 3202 3202 3203 IEM_MC_ADVANCE_ RIP_AND_FINISH();3203 IEM_MC_ADVANCE_PC_AND_FINISH(); 3204 3204 IEM_MC_END(); 3205 3205 } … … 3267 3267 pu8Dst, puSrc); 3268 3268 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 3269 IEM_MC_ADVANCE_ RIP_AND_FINISH();3269 IEM_MC_ADVANCE_PC_AND_FINISH(); 3270 3270 IEM_MC_END(); 3271 3271 } … … 3285 3285 pu8Dst, puSrc); 3286 3286 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 3287 IEM_MC_ADVANCE_ RIP_AND_FINISH();3287 IEM_MC_ADVANCE_PC_AND_FINISH(); 3288 3288 IEM_MC_END(); 3289 3289 } … … 3318 3318 pu8Dst, puSrc); 3319 3319 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 3320 IEM_MC_ADVANCE_ RIP_AND_FINISH();3320 IEM_MC_ADVANCE_PC_AND_FINISH(); 3321 3321 IEM_MC_END(); 3322 3322 } … … 3336 3336 pu8Dst, puSrc); 3337 3337 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u8Dst); 3338 IEM_MC_ADVANCE_ RIP_AND_FINISH();3338 IEM_MC_ADVANCE_PC_AND_FINISH(); 3339 3339 IEM_MC_END(); 3340 3340 } … … 3618 3618 puDst, puSrc); 3619 3619 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3620 IEM_MC_ADVANCE_ RIP_AND_FINISH();3620 IEM_MC_ADVANCE_PC_AND_FINISH(); 3621 3621 IEM_MC_END(); 3622 3622 } … … 3638 3638 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3639 3639 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 3640 IEM_MC_ADVANCE_ RIP_AND_FINISH();3640 IEM_MC_ADVANCE_PC_AND_FINISH(); 3641 3641 IEM_MC_END(); 3642 3642 } … … 3666 3666 puDst, puSrc); 3667 3667 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3668 IEM_MC_ADVANCE_ RIP_AND_FINISH();3668 IEM_MC_ADVANCE_PC_AND_FINISH(); 3669 3669 IEM_MC_END(); 3670 3670 } … … 3689 3689 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3690 3690 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 3691 IEM_MC_ADVANCE_ RIP_AND_FINISH();3691 IEM_MC_ADVANCE_PC_AND_FINISH(); 3692 3692 IEM_MC_END(); 3693 3693 } … … 3724 3724 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3725 3725 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 3726 IEM_MC_ADVANCE_ RIP_AND_FINISH();3726 IEM_MC_ADVANCE_PC_AND_FINISH(); 3727 3727 IEM_MC_END(); 3728 3728 } … … 3744 3744 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3745 3745 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 3746 IEM_MC_ADVANCE_ RIP_AND_FINISH();3746 IEM_MC_ADVANCE_PC_AND_FINISH(); 3747 3747 IEM_MC_END(); 3748 3748 } … … 3773 3773 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3774 3774 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 3775 IEM_MC_ADVANCE_ RIP_AND_FINISH();3775 IEM_MC_ADVANCE_PC_AND_FINISH(); 3776 3776 IEM_MC_END(); 3777 3777 } … … 3796 3796 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 3797 3797 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 3798 IEM_MC_ADVANCE_ RIP_AND_FINISH();3798 IEM_MC_ADVANCE_PC_AND_FINISH(); 3799 3799 IEM_MC_END(); 3800 3800 } … … 4138 4138 // IEM_MC_REF_XREG_U128_CONST(pSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 4139 4139 // IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc); 4140 // IEM_MC_ADVANCE_ RIP_AND_FINISH();4140 // IEM_MC_ADVANCE_PC_AND_FINISH(); 4141 4141 // IEM_MC_END(); 4142 4142 // } … … 4161 4161 // IEM_MC_CALL_SSE_AIMPL_2(pImpl->pfnU128, pDst, pSrc); 4162 4162 // 4163 // IEM_MC_ADVANCE_ RIP_AND_FINISH();4163 // IEM_MC_ADVANCE_PC_AND_FINISH(); 4164 4164 // IEM_MC_END(); 4165 4165 // } … … 4290 4290 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); 4291 4291 4292 IEM_MC_ADVANCE_ RIP_AND_FINISH();4292 IEM_MC_ADVANCE_PC_AND_FINISH(); 4293 4293 IEM_MC_END(); 4294 4294 } … … 4308 4308 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u64Tmp); 4309 4309 4310 IEM_MC_ADVANCE_ RIP_AND_FINISH();4310 IEM_MC_ADVANCE_PC_AND_FINISH(); 4311 4311 IEM_MC_END(); 4312 4312 } … … 4340 4340 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp); 4341 4341 4342 IEM_MC_ADVANCE_ RIP_AND_FINISH();4342 IEM_MC_ADVANCE_PC_AND_FINISH(); 4343 4343 IEM_MC_END(); 4344 4344 } … … 4358 4358 IEM_MC_STORE_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u32Tmp); 4359 4359 4360 IEM_MC_ADVANCE_ RIP_AND_FINISH();4360 IEM_MC_ADVANCE_PC_AND_FINISH(); 4361 4361 IEM_MC_END(); 4362 4362 } … … 4400 4400 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 4401 4401 IEM_GET_MODRM_RM(pVCpu, bRm)); 4402 IEM_MC_ADVANCE_ RIP_AND_FINISH();4402 IEM_MC_ADVANCE_PC_AND_FINISH(); 4403 4403 IEM_MC_END(); 4404 4404 } … … 4420 4420 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 4421 4421 4422 IEM_MC_ADVANCE_ RIP_AND_FINISH();4422 IEM_MC_ADVANCE_PC_AND_FINISH(); 4423 4423 IEM_MC_END(); 4424 4424 } … … 4440 4440 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp); 4441 4441 4442 IEM_MC_ADVANCE_ RIP_AND_FINISH();4442 IEM_MC_ADVANCE_PC_AND_FINISH(); 4443 4443 IEM_MC_END(); 4444 4444 } … … 4475 4475 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 4476 4476 IEM_GET_MODRM_RM(pVCpu, bRm)); 4477 IEM_MC_ADVANCE_ RIP_AND_FINISH();4477 IEM_MC_ADVANCE_PC_AND_FINISH(); 4478 4478 IEM_MC_END(); 4479 4479 } … … 4495 4495 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 4496 4496 4497 IEM_MC_ADVANCE_ RIP_AND_FINISH();4497 IEM_MC_ADVANCE_PC_AND_FINISH(); 4498 4498 IEM_MC_END(); 4499 4499 } … … 4515 4515 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp); 4516 4516 4517 IEM_MC_ADVANCE_ RIP_AND_FINISH();4517 IEM_MC_ADVANCE_PC_AND_FINISH(); 4518 4518 IEM_MC_END(); 4519 4519 } … … 4554 4554 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg); 4555 4555 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 4556 IEM_MC_ADVANCE_ RIP_AND_FINISH();4556 IEM_MC_ADVANCE_PC_AND_FINISH(); 4557 4557 IEM_MC_END(); 4558 4558 } … … 4570 4570 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 4571 4571 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 4572 IEM_MC_ADVANCE_ RIP_AND_FINISH();4572 IEM_MC_ADVANCE_PC_AND_FINISH(); 4573 4573 IEM_MC_END(); 4574 4574 } … … 4599 4599 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 4600 4600 4601 IEM_MC_ADVANCE_ RIP_AND_FINISH();4601 IEM_MC_ADVANCE_PC_AND_FINISH(); 4602 4602 IEM_MC_END(); 4603 4603 } … … 4622 4622 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 4623 4623 4624 IEM_MC_ADVANCE_ RIP_AND_FINISH();4624 IEM_MC_ADVANCE_PC_AND_FINISH(); 4625 4625 IEM_MC_END(); 4626 4626 } … … 4684 4684 IEM_MC_CALL_VOID_AIMPL_3(pfnU128, puDst, puSrc, bImmArg); 4685 4685 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_EFFECTIVE_VVVV(pVCpu)); 4686 IEM_MC_ADVANCE_ RIP_AND_FINISH();4686 IEM_MC_ADVANCE_PC_AND_FINISH(); 4687 4687 IEM_MC_END(); 4688 4688 } … … 4712 4712 IEM_MC_CALL_VOID_AIMPL_3(pfnU256, puDst, puSrc, bImmArg); 4713 4713 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_EFFECTIVE_VVVV(pVCpu), uDst); 4714 IEM_MC_ADVANCE_ RIP_AND_FINISH();4714 IEM_MC_ADVANCE_PC_AND_FINISH(); 4715 4715 IEM_MC_END(); 4716 4716 } … … 5069 5069 } 5070 5070 5071 IEM_MC_ADVANCE_ RIP_AND_FINISH();5071 IEM_MC_ADVANCE_PC_AND_FINISH(); 5072 5072 IEM_MC_END(); 5073 5073 } … … 5106 5106 } 5107 5107 5108 IEM_MC_ADVANCE_ RIP_AND_FINISH();5108 IEM_MC_ADVANCE_PC_AND_FINISH(); 5109 5109 IEM_MC_END(); 5110 5110 } … … 5216 5216 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Tmp); 5217 5217 5218 IEM_MC_ADVANCE_ RIP_AND_FINISH();5218 IEM_MC_ADVANCE_PC_AND_FINISH(); 5219 5219 IEM_MC_END(); 5220 5220 } … … 5234 5234 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u64Tmp); 5235 5235 5236 IEM_MC_ADVANCE_ RIP_AND_FINISH();5236 IEM_MC_ADVANCE_PC_AND_FINISH(); 5237 5237 IEM_MC_END(); 5238 5238 } … … 5266 5266 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Tmp); 5267 5267 5268 IEM_MC_ADVANCE_ RIP_AND_FINISH();5268 IEM_MC_ADVANCE_PC_AND_FINISH(); 5269 5269 IEM_MC_END(); 5270 5270 } … … 5284 5284 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u32Tmp); 5285 5285 5286 IEM_MC_ADVANCE_ RIP_AND_FINISH();5286 IEM_MC_ADVANCE_PC_AND_FINISH(); 5287 5287 IEM_MC_END(); 5288 5288 } … … 5317 5317 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), 5318 5318 IEM_GET_MODRM_RM(pVCpu, bRm)); 5319 IEM_MC_ADVANCE_ RIP_AND_FINISH();5319 IEM_MC_ADVANCE_PC_AND_FINISH(); 5320 5320 IEM_MC_END(); 5321 5321 } … … 5337 5337 IEM_MC_STORE_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 5338 5338 5339 IEM_MC_ADVANCE_ RIP_AND_FINISH();5339 IEM_MC_ADVANCE_PC_AND_FINISH(); 5340 5340 IEM_MC_END(); 5341 5341 } … … 5377 5377 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 5378 5378 IEM_GET_MODRM_REG(pVCpu, bRm)); 5379 IEM_MC_ADVANCE_ RIP_AND_FINISH();5379 IEM_MC_ADVANCE_PC_AND_FINISH(); 5380 5380 IEM_MC_END(); 5381 5381 } … … 5397 5397 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp); 5398 5398 5399 IEM_MC_ADVANCE_ RIP_AND_FINISH();5399 IEM_MC_ADVANCE_PC_AND_FINISH(); 5400 5400 IEM_MC_END(); 5401 5401 } … … 5417 5417 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp); 5418 5418 5419 IEM_MC_ADVANCE_ RIP_AND_FINISH();5419 IEM_MC_ADVANCE_PC_AND_FINISH(); 5420 5420 IEM_MC_END(); 5421 5421 } … … 5453 5453 IEM_MC_COPY_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 5454 5454 IEM_GET_MODRM_REG(pVCpu, bRm)); 5455 IEM_MC_ADVANCE_ RIP_AND_FINISH();5455 IEM_MC_ADVANCE_PC_AND_FINISH(); 5456 5456 IEM_MC_END(); 5457 5457 } … … 5473 5473 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u128Tmp); 5474 5474 5475 IEM_MC_ADVANCE_ RIP_AND_FINISH();5475 IEM_MC_ADVANCE_PC_AND_FINISH(); 5476 5476 IEM_MC_END(); 5477 5477 } … … 5493 5493 IEM_MC_STORE_MEM_U256_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, u256Tmp); 5494 5494 5495 IEM_MC_ADVANCE_ RIP_AND_FINISH();5495 IEM_MC_ADVANCE_PC_AND_FINISH(); 5496 5496 IEM_MC_END(); 5497 5497 } … … 5736 5736 puDst, puSrc, bImmArg); \ 5737 5737 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 5738 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5738 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5739 5739 IEM_MC_END(); \ 5740 5740 } \ … … 5758 5758 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 5759 5759 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 5760 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5760 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5761 5761 IEM_MC_END(); \ 5762 5762 } \ … … 5787 5787 puDst, puSrc, bImmArg); \ 5788 5788 IEM_MC_STORE_YREG_YMM_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 5789 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5789 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5790 5790 IEM_MC_END(); \ 5791 5791 } \ … … 5811 5811 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 5812 5812 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 5813 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5813 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5814 5814 IEM_MC_END(); \ 5815 5815 } \ … … 5860 5860 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 5861 5861 5862 IEM_MC_ADVANCE_ RIP_AND_FINISH();5862 IEM_MC_ADVANCE_PC_AND_FINISH(); 5863 5863 IEM_MC_END(); 5864 5864 } … … 5888 5888 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 5889 5889 5890 IEM_MC_ADVANCE_ RIP_AND_FINISH();5890 IEM_MC_ADVANCE_PC_AND_FINISH(); 5891 5891 IEM_MC_END(); 5892 5892 } … … 5920 5920 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 5921 5921 5922 IEM_MC_ADVANCE_ RIP_AND_FINISH();5922 IEM_MC_ADVANCE_PC_AND_FINISH(); 5923 5923 IEM_MC_END(); 5924 5924 } … … 5948 5948 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 5949 5949 5950 IEM_MC_ADVANCE_ RIP_AND_FINISH();5950 IEM_MC_ADVANCE_PC_AND_FINISH(); 5951 5951 IEM_MC_END(); 5952 5952 } … … 5985 5985 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 5986 5986 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue); 5987 IEM_MC_ADVANCE_ RIP_AND_FINISH();5987 IEM_MC_ADVANCE_PC_AND_FINISH(); 5988 5988 IEM_MC_END(); 5989 5989 } … … 6008 6008 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 6009 6009 IEM_MC_STORE_XREG_U16( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7, uValue); 6010 IEM_MC_ADVANCE_ RIP_AND_FINISH();6010 IEM_MC_ADVANCE_PC_AND_FINISH(); 6011 6011 IEM_MC_END(); 6012 6012 } … … 6038 6038 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_RM(pVCpu, bRm), bImm & 7); 6039 6039 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uValue); 6040 IEM_MC_ADVANCE_ RIP_AND_FINISH();6040 IEM_MC_ADVANCE_PC_AND_FINISH(); 6041 6041 IEM_MC_END(); 6042 6042 } … … 6077 6077 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \ 6078 6078 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 6079 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6079 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6080 6080 IEM_MC_END(); \ 6081 6081 } \ … … 6097 6097 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \ 6098 6098 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \ 6099 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6099 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6100 6100 IEM_MC_END(); \ 6101 6101 } \ … … 6127 6127 iemAImpl_ ## a_Instr ## _u256_fallback), puDst, puSrc1, puSrc2, bImmArg); \ 6128 6128 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 6129 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6129 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6130 6130 IEM_MC_END(); \ 6131 6131 } \ … … 6150 6150 iemAImpl_ ## a_Instr ## _u128_fallback), puDst, puSrc1, puSrc2, bImmArg); \ 6151 6151 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \ 6152 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6152 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6153 6153 IEM_MC_END(); \ 6154 6154 } \ … … 6311 6311 IEM_MC_COPY_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_RM(pVCpu, bRm), 6312 6312 IEM_GET_MODRM_REG(pVCpu, bRm)); 6313 IEM_MC_ADVANCE_ RIP_AND_FINISH();6313 IEM_MC_ADVANCE_PC_AND_FINISH(); 6314 6314 IEM_MC_END(); 6315 6315 } … … 6331 6331 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 6332 6332 6333 IEM_MC_ADVANCE_ RIP_AND_FINISH();6333 IEM_MC_ADVANCE_PC_AND_FINISH(); 6334 6334 IEM_MC_END(); 6335 6335 } … … 6364 6364 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAvx2, iemAImpl_vpmovmskb_u256, 6365 6365 iemAImpl_vpmovmskb_u256_fallback), puDst, puSrc); 6366 IEM_MC_ADVANCE_ RIP_AND_FINISH();6366 IEM_MC_ADVANCE_PC_AND_FINISH(); 6367 6367 IEM_MC_END(); 6368 6368 } … … 6378 6378 IEM_MC_REF_XREG_U128_CONST(puSrc, IEM_GET_MODRM_RM(pVCpu, bRm)); 6379 6379 IEM_MC_CALL_VOID_AIMPL_2(iemAImpl_pmovmskb_u128, puDst, puSrc); 6380 IEM_MC_ADVANCE_ RIP_AND_FINISH();6380 IEM_MC_ADVANCE_PC_AND_FINISH(); 6381 6381 IEM_MC_END(); 6382 6382 } … … 6625 6625 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6626 6626 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6627 IEM_MC_ADVANCE_ RIP_AND_FINISH();6627 IEM_MC_ADVANCE_PC_AND_FINISH(); 6628 6628 IEM_MC_END(); 6629 6629 } … … 6645 6645 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6646 6646 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6647 IEM_MC_ADVANCE_ RIP_AND_FINISH();6647 IEM_MC_ADVANCE_PC_AND_FINISH(); 6648 6648 IEM_MC_END(); 6649 6649 } … … 6674 6674 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6675 6675 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6676 IEM_MC_ADVANCE_ RIP_AND_FINISH();6676 IEM_MC_ADVANCE_PC_AND_FINISH(); 6677 6677 IEM_MC_END(); 6678 6678 } … … 6697 6697 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6698 6698 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 6699 IEM_MC_ADVANCE_ RIP_AND_FINISH();6699 IEM_MC_ADVANCE_PC_AND_FINISH(); 6700 6700 IEM_MC_END(); 6701 6701 } … … 6730 6730 puDst, puSrc); 6731 6731 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6732 IEM_MC_ADVANCE_ RIP_AND_FINISH();6732 IEM_MC_ADVANCE_PC_AND_FINISH(); 6733 6733 IEM_MC_END(); 6734 6734 } … … 6750 6750 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6751 6751 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 6752 IEM_MC_ADVANCE_ RIP_AND_FINISH();6752 IEM_MC_ADVANCE_PC_AND_FINISH(); 6753 6753 IEM_MC_END(); 6754 6754 } … … 6778 6778 puDst, puSrc); 6779 6779 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6780 IEM_MC_ADVANCE_ RIP_AND_FINISH();6780 IEM_MC_ADVANCE_PC_AND_FINISH(); 6781 6781 IEM_MC_END(); 6782 6782 } … … 6801 6801 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6802 6802 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 6803 IEM_MC_ADVANCE_ RIP_AND_FINISH();6803 IEM_MC_ADVANCE_PC_AND_FINISH(); 6804 6804 IEM_MC_END(); 6805 6805 } … … 6836 6836 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6837 6837 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6838 IEM_MC_ADVANCE_ RIP_AND_FINISH();6838 IEM_MC_ADVANCE_PC_AND_FINISH(); 6839 6839 IEM_MC_END(); 6840 6840 } … … 6856 6856 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6857 6857 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6858 IEM_MC_ADVANCE_ RIP_AND_FINISH();6858 IEM_MC_ADVANCE_PC_AND_FINISH(); 6859 6859 IEM_MC_END(); 6860 6860 } … … 6885 6885 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6886 6886 IEM_MC_CLEAR_YREG_128_UP(IEM_GET_MODRM_REG(pVCpu, bRm)); 6887 IEM_MC_ADVANCE_ RIP_AND_FINISH();6887 IEM_MC_ADVANCE_PC_AND_FINISH(); 6888 6888 IEM_MC_END(); 6889 6889 } … … 6908 6908 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 6909 6909 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 6910 IEM_MC_ADVANCE_ RIP_AND_FINISH();6910 IEM_MC_ADVANCE_PC_AND_FINISH(); 6911 6911 IEM_MC_END(); 6912 6912 } … … 6951 6951 IEM_MC_STORE_MEM_U128_ALIGN_SSE(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 6952 6952 6953 IEM_MC_ADVANCE_ RIP_AND_FINISH();6953 IEM_MC_ADVANCE_PC_AND_FINISH(); 6954 6954 IEM_MC_END(); 6955 6955 } … … 6971 6971 IEM_MC_STORE_MEM_U256_ALIGN_AVX(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 6972 6972 6973 IEM_MC_ADVANCE_ RIP_AND_FINISH();6973 IEM_MC_ADVANCE_PC_AND_FINISH(); 6974 6974 IEM_MC_END(); 6975 6975 } … … 7149 7149 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp); 7150 7150 7151 IEM_MC_ADVANCE_ RIP_AND_FINISH();7151 IEM_MC_ADVANCE_PC_AND_FINISH(); 7152 7152 IEM_MC_END(); 7153 7153 } … … 7169 7169 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp); 7170 7170 7171 IEM_MC_ADVANCE_ RIP_AND_FINISH();7171 IEM_MC_ADVANCE_PC_AND_FINISH(); 7172 7172 IEM_MC_END(); 7173 7173 } … … 7278 7278 IEM_MC_STORE_MEM_U128(pVCpu->iem.s.iEffSeg, u64EffAddr, u128Mem); 7279 7279 7280 IEM_MC_ADVANCE_ RIP_AND_FINISH();7280 IEM_MC_ADVANCE_PC_AND_FINISH(); 7281 7281 IEM_MC_END(); 7282 7282 } -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstVexMap2-x86.cpp.h
r108204 r108267 62 62 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 63 63 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 64 IEM_MC_ADVANCE_ RIP_AND_FINISH();64 IEM_MC_ADVANCE_PC_AND_FINISH(); 65 65 IEM_MC_END(); 66 66 } … … 88 88 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 89 89 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 90 IEM_MC_ADVANCE_ RIP_AND_FINISH();90 IEM_MC_ADVANCE_PC_AND_FINISH(); 91 91 IEM_MC_END(); 92 92 } … … 298 298 iemAImpl_ ## a_Instr ## _u256_fallback), \ 299 299 puSrc1, puSrc2, pEFlags); \ 300 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \300 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 301 301 IEM_MC_END(); \ 302 302 } \ … … 316 316 iemAImpl_ ## a_Instr ## _u128_fallback), \ 317 317 puSrc1, puSrc2, pEFlags); \ 318 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \318 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 319 319 IEM_MC_END(); \ 320 320 } \ … … 344 344 iemAImpl_ ## a_Instr ## _u256_fallback), \ 345 345 puSrc1, puSrc2, pEFlags); \ 346 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \346 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 347 347 IEM_MC_END(); \ 348 348 } \ … … 365 365 iemAImpl_ ## a_Instr ## _u128_fallback), \ 366 366 puSrc1, puSrc2, pEFlags); \ 367 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \367 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 368 368 IEM_MC_END(); \ 369 369 } \ … … 448 448 puDst, puSrc1, puSrc2); 449 449 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 450 IEM_MC_ADVANCE_ RIP_AND_FINISH();450 IEM_MC_ADVANCE_PC_AND_FINISH(); 451 451 IEM_MC_END(); 452 452 } … … 473 473 puDst, puSrc1, puSrc2); 474 474 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 475 IEM_MC_ADVANCE_ RIP_AND_FINISH();475 IEM_MC_ADVANCE_PC_AND_FINISH(); 476 476 IEM_MC_END(); 477 477 } … … 512 512 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAvx, iemAImpl_vptest_u256, iemAImpl_vptest_u256_fallback), 513 513 puSrc1, puSrc2, pEFlags); 514 IEM_MC_ADVANCE_ RIP_AND_FINISH();514 IEM_MC_ADVANCE_PC_AND_FINISH(); 515 515 IEM_MC_END(); 516 516 } … … 528 528 IEM_MC_REF_EFLAGS(pEFlags); 529 529 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags); 530 IEM_MC_ADVANCE_ RIP_AND_FINISH();530 IEM_MC_ADVANCE_PC_AND_FINISH(); 531 531 IEM_MC_END(); 532 532 } … … 558 558 puSrc1, puSrc2, pEFlags); 559 559 560 IEM_MC_ADVANCE_ RIP_AND_FINISH();560 IEM_MC_ADVANCE_PC_AND_FINISH(); 561 561 IEM_MC_END(); 562 562 } … … 580 580 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_ptest_u128, puSrc1, puSrc2, pEFlags); 581 581 582 IEM_MC_ADVANCE_ RIP_AND_FINISH();582 IEM_MC_ADVANCE_PC_AND_FINISH(); 583 583 IEM_MC_END(); 584 584 } … … 612 612 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 613 613 614 IEM_MC_ADVANCE_ RIP_AND_FINISH();614 IEM_MC_ADVANCE_PC_AND_FINISH(); 615 615 IEM_MC_END(); 616 616 } … … 626 626 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 627 627 628 IEM_MC_ADVANCE_ RIP_AND_FINISH();628 IEM_MC_ADVANCE_PC_AND_FINISH(); 629 629 IEM_MC_END(); 630 630 } … … 649 649 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 650 650 651 IEM_MC_ADVANCE_ RIP_AND_FINISH();651 IEM_MC_ADVANCE_PC_AND_FINISH(); 652 652 IEM_MC_END(); 653 653 } … … 666 666 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 667 667 668 IEM_MC_ADVANCE_ RIP_AND_FINISH();668 IEM_MC_ADVANCE_PC_AND_FINISH(); 669 669 IEM_MC_END(); 670 670 } … … 698 698 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 699 699 700 IEM_MC_ADVANCE_ RIP_AND_FINISH();700 IEM_MC_ADVANCE_PC_AND_FINISH(); 701 701 IEM_MC_END(); 702 702 } … … 712 712 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 713 713 714 IEM_MC_ADVANCE_ RIP_AND_FINISH();714 IEM_MC_ADVANCE_PC_AND_FINISH(); 715 715 IEM_MC_END(); 716 716 } … … 733 733 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 734 734 735 IEM_MC_ADVANCE_ RIP_AND_FINISH();735 IEM_MC_ADVANCE_PC_AND_FINISH(); 736 736 IEM_MC_END(); 737 737 } … … 771 771 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 772 772 773 IEM_MC_ADVANCE_ RIP_AND_FINISH();773 IEM_MC_ADVANCE_PC_AND_FINISH(); 774 774 IEM_MC_END(); 775 775 } … … 840 840 puDst, puSrc); \ 841 841 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 842 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \842 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 843 843 IEM_MC_END(); \ 844 844 } \ … … 857 857 puDst, uSrc); \ 858 858 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \ 859 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \859 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 860 860 IEM_MC_END(); \ 861 861 } \ … … 883 883 puDst, puSrc); \ 884 884 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); \ 885 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \885 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 886 886 IEM_MC_END(); \ 887 887 } \ … … 902 902 puDst, uSrc); \ 903 903 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); \ 904 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \904 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 905 905 IEM_MC_END(); \ 906 906 } \ … … 1017 1017 IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1018 1018 1019 IEM_MC_ADVANCE_ RIP_AND_FINISH();1019 IEM_MC_ADVANCE_PC_AND_FINISH(); 1020 1020 IEM_MC_END(); 1021 1021 } … … 1048 1048 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1049 1049 1050 IEM_MC_ADVANCE_ RIP_AND_FINISH();1050 IEM_MC_ADVANCE_PC_AND_FINISH(); 1051 1051 IEM_MC_END(); 1052 1052 } … … 1383 1383 puDst, puSrc1, puSrc2); 1384 1384 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1385 IEM_MC_ADVANCE_ RIP_AND_FINISH();1385 IEM_MC_ADVANCE_PC_AND_FINISH(); 1386 1386 IEM_MC_END(); 1387 1387 } … … 1408 1408 puDst, puSrc1, puSrc2); 1409 1409 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1410 IEM_MC_ADVANCE_ RIP_AND_FINISH();1410 IEM_MC_ADVANCE_PC_AND_FINISH(); 1411 1411 IEM_MC_END(); 1412 1412 } … … 1525 1525 puDst, puSrc); 1526 1526 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1527 IEM_MC_ADVANCE_ RIP_AND_FINISH();1527 IEM_MC_ADVANCE_PC_AND_FINISH(); 1528 1528 IEM_MC_END(); 1529 1529 } … … 1550 1550 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1551 1551 1552 IEM_MC_ADVANCE_ RIP_AND_FINISH();1552 IEM_MC_ADVANCE_PC_AND_FINISH(); 1553 1553 IEM_MC_END(); 1554 1554 } … … 1653 1653 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1654 1654 1655 IEM_MC_ADVANCE_ RIP_AND_FINISH();1655 IEM_MC_ADVANCE_PC_AND_FINISH(); 1656 1656 IEM_MC_END(); 1657 1657 } … … 1667 1667 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1668 1668 1669 IEM_MC_ADVANCE_ RIP_AND_FINISH();1669 IEM_MC_ADVANCE_PC_AND_FINISH(); 1670 1670 IEM_MC_END(); 1671 1671 } … … 1690 1690 IEM_MC_BROADCAST_YREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1691 1691 1692 IEM_MC_ADVANCE_ RIP_AND_FINISH();1692 IEM_MC_ADVANCE_PC_AND_FINISH(); 1693 1693 IEM_MC_END(); 1694 1694 } … … 1707 1707 IEM_MC_BROADCAST_XREG_U32_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1708 1708 1709 IEM_MC_ADVANCE_ RIP_AND_FINISH();1709 IEM_MC_ADVANCE_PC_AND_FINISH(); 1710 1710 IEM_MC_END(); 1711 1711 } … … 1736 1736 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1737 1737 1738 IEM_MC_ADVANCE_ RIP_AND_FINISH();1738 IEM_MC_ADVANCE_PC_AND_FINISH(); 1739 1739 IEM_MC_END(); 1740 1740 } … … 1750 1750 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1751 1751 1752 IEM_MC_ADVANCE_ RIP_AND_FINISH();1752 IEM_MC_ADVANCE_PC_AND_FINISH(); 1753 1753 IEM_MC_END(); 1754 1754 } … … 1773 1773 IEM_MC_BROADCAST_YREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1774 1774 1775 IEM_MC_ADVANCE_ RIP_AND_FINISH();1775 IEM_MC_ADVANCE_PC_AND_FINISH(); 1776 1776 IEM_MC_END(); 1777 1777 } … … 1790 1790 IEM_MC_BROADCAST_XREG_U64_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1791 1791 1792 IEM_MC_ADVANCE_ RIP_AND_FINISH();1792 IEM_MC_ADVANCE_PC_AND_FINISH(); 1793 1793 IEM_MC_END(); 1794 1794 } … … 1826 1826 IEM_MC_BROADCAST_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1827 1827 1828 IEM_MC_ADVANCE_ RIP_AND_FINISH();1828 IEM_MC_ADVANCE_PC_AND_FINISH(); 1829 1829 IEM_MC_END(); 1830 1830 } … … 1887 1887 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1888 1888 1889 IEM_MC_ADVANCE_ RIP_AND_FINISH();1889 IEM_MC_ADVANCE_PC_AND_FINISH(); 1890 1890 IEM_MC_END(); 1891 1891 } … … 1901 1901 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1902 1902 1903 IEM_MC_ADVANCE_ RIP_AND_FINISH();1903 IEM_MC_ADVANCE_PC_AND_FINISH(); 1904 1904 IEM_MC_END(); 1905 1905 } … … 1924 1924 IEM_MC_BROADCAST_YREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1925 1925 1926 IEM_MC_ADVANCE_ RIP_AND_FINISH();1926 IEM_MC_ADVANCE_PC_AND_FINISH(); 1927 1927 IEM_MC_END(); 1928 1928 } … … 1941 1941 IEM_MC_BROADCAST_XREG_U8_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1942 1942 1943 IEM_MC_ADVANCE_ RIP_AND_FINISH();1943 IEM_MC_ADVANCE_PC_AND_FINISH(); 1944 1944 IEM_MC_END(); 1945 1945 } … … 1970 1970 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1971 1971 1972 IEM_MC_ADVANCE_ RIP_AND_FINISH();1972 IEM_MC_ADVANCE_PC_AND_FINISH(); 1973 1973 IEM_MC_END(); 1974 1974 } … … 1984 1984 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 1985 1985 1986 IEM_MC_ADVANCE_ RIP_AND_FINISH();1986 IEM_MC_ADVANCE_PC_AND_FINISH(); 1987 1987 IEM_MC_END(); 1988 1988 } … … 2007 2007 IEM_MC_BROADCAST_YREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2008 2008 2009 IEM_MC_ADVANCE_ RIP_AND_FINISH();2009 IEM_MC_ADVANCE_PC_AND_FINISH(); 2010 2010 IEM_MC_END(); 2011 2011 } … … 2024 2024 IEM_MC_BROADCAST_XREG_U16_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uSrc); 2025 2025 2026 IEM_MC_ADVANCE_ RIP_AND_FINISH();2026 IEM_MC_ADVANCE_PC_AND_FINISH(); 2027 2027 IEM_MC_END(); 2028 2028 } … … 2515 2515 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback), puDst, puSrc); 2516 2516 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2517 IEM_MC_ADVANCE_ RIP_AND_FINISH();2517 IEM_MC_ADVANCE_PC_AND_FINISH(); 2518 2518 IEM_MC_END(); 2519 2519 } … … 2538 2538 IEM_MC_CALL_VOID_AIMPL_2(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaesimc_u128, iemAImpl_vaesimc_u128_fallback), puDst, puSrc); 2539 2539 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2540 IEM_MC_ADVANCE_ RIP_AND_FINISH();2540 IEM_MC_ADVANCE_PC_AND_FINISH(); 2541 2541 IEM_MC_END(); 2542 2542 } … … 2641 2641 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback), 2642 2642 pDst, uSrc1, uSrc2, pEFlags); 2643 IEM_MC_ADVANCE_ RIP_AND_FINISH();2643 IEM_MC_ADVANCE_PC_AND_FINISH(); 2644 2644 IEM_MC_END(); 2645 2645 } … … 2659 2659 pDst, uSrc1, uSrc2, pEFlags); 2660 2660 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 2661 IEM_MC_ADVANCE_ RIP_AND_FINISH();2661 IEM_MC_ADVANCE_PC_AND_FINISH(); 2662 2662 IEM_MC_END(); 2663 2663 } … … 2684 2684 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi1, iemAImpl_andn_u64, iemAImpl_andn_u64_fallback), 2685 2685 pDst, uSrc1, uSrc2, pEFlags); 2686 IEM_MC_ADVANCE_ RIP_AND_FINISH();2686 IEM_MC_ADVANCE_PC_AND_FINISH(); 2687 2687 IEM_MC_END(); 2688 2688 } … … 2704 2704 pDst, uSrc1, uSrc2, pEFlags); 2705 2705 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 2706 IEM_MC_ADVANCE_ RIP_AND_FINISH();2706 IEM_MC_ADVANCE_PC_AND_FINISH(); 2707 2707 IEM_MC_END(); 2708 2708 } … … 2742 2742 iemAImpl_ ## a_Instr ## _u64_fallback), fEFlagsIn, pDst, uSrc); \ 2743 2743 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2744 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2744 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2745 2745 IEM_MC_END(); \ 2746 2746 } \ … … 2759 2759 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \ 2760 2760 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2761 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2761 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2762 2762 IEM_MC_END(); \ 2763 2763 } \ … … 2784 2784 iemAImpl_ ## a_Instr ## _u64_fallback), fEFlagsIn, pDst, uSrc); \ 2785 2785 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2786 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2786 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2787 2787 IEM_MC_END(); \ 2788 2788 } \ … … 2804 2804 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); \ 2805 2805 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2806 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2806 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2807 2807 IEM_MC_END(); \ 2808 2808 } \ … … 2914 2914 iemAImpl_ ## a_Instr ## _u64_fallback), \ 2915 2915 pDst, uSrc1, uSrc2, pEFlags); \ 2916 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2916 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2917 2917 IEM_MC_END(); \ 2918 2918 } \ … … 2933 2933 pDst, uSrc1, uSrc2, pEFlags); \ 2934 2934 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 2935 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2935 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2936 2936 IEM_MC_END(); \ 2937 2937 } \ … … 2959 2959 iemAImpl_ ## a_Instr ## _u64_fallback), \ 2960 2960 pDst, uSrc1, uSrc2, pEFlags); \ 2961 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2961 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2962 2962 IEM_MC_END(); \ 2963 2963 } \ … … 2980 2980 pDst, uSrc1, uSrc2, pEFlags); \ 2981 2981 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 2982 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2982 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2983 2983 IEM_MC_END(); \ 2984 2984 } \ … … 3007 3007 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \ 3008 3008 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \ 3009 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3009 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3010 3010 IEM_MC_END(); \ 3011 3011 } \ … … 3023 3023 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \ 3024 3024 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 3025 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3025 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3026 3026 IEM_MC_END(); \ 3027 3027 } \ … … 3046 3046 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(a_fFeatureMember, iemAImpl_ ## a_Instr ## _u64, \ 3047 3047 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \ 3048 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3048 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3049 3049 IEM_MC_END(); \ 3050 3050 } \ … … 3064 3064 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \ 3065 3065 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 3066 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3066 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3067 3067 IEM_MC_END(); \ 3068 3068 } \ … … 3108 3108 iemAImpl_ ## a_Instr ## _u64, \ 3109 3109 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \ 3110 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3110 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3111 3111 IEM_MC_END(); \ 3112 3112 } \ … … 3125 3125 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \ 3126 3126 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 3127 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3127 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3128 3128 IEM_MC_END(); \ 3129 3129 } \ … … 3149 3149 iemAImpl_ ## a_Instr ## _u64, \ 3150 3150 iemAImpl_ ## a_Instr ## _u64_fallback), pDst, uSrc1, uSrc2); \ 3151 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3151 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3152 3152 IEM_MC_END(); \ 3153 3153 } \ … … 3168 3168 iemAImpl_ ## a_Instr ## _u32_fallback), pDst, uSrc1, uSrc2); \ 3169 3169 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); \ 3170 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \3170 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 3171 3171 IEM_MC_END(); \ 3172 3172 } \ … … 3225 3225 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback), 3226 3226 pDst1, pDst2, uSrc1, uSrc2); 3227 IEM_MC_ADVANCE_ RIP_AND_FINISH();3227 IEM_MC_ADVANCE_PC_AND_FINISH(); 3228 3228 IEM_MC_END(); 3229 3229 } … … 3244 3244 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); 3245 3245 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 3246 IEM_MC_ADVANCE_ RIP_AND_FINISH();3246 IEM_MC_ADVANCE_PC_AND_FINISH(); 3247 3247 IEM_MC_END(); 3248 3248 } … … 3269 3269 IEM_MC_CALL_VOID_AIMPL_4(IEM_SELECT_HOST_OR_FALLBACK(fBmi2, iemAImpl_mulx_u64, iemAImpl_mulx_u64_fallback), 3270 3270 pDst1, pDst2, uSrc1, uSrc2); 3271 IEM_MC_ADVANCE_ RIP_AND_FINISH();3271 IEM_MC_ADVANCE_PC_AND_FINISH(); 3272 3272 IEM_MC_END(); 3273 3273 } … … 3290 3290 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_EFFECTIVE_VVVV(pVCpu)); 3291 3291 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 3292 IEM_MC_ADVANCE_ RIP_AND_FINISH();3292 IEM_MC_ADVANCE_PC_AND_FINISH(); 3293 3293 IEM_MC_END(); 3294 3294 } -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstVexMap3-x86.cpp.h
r108204 r108267 70 70 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg); 71 71 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 72 IEM_MC_ADVANCE_ RIP_AND_FINISH();72 IEM_MC_ADVANCE_PC_AND_FINISH(); 73 73 IEM_MC_END(); 74 74 } … … 89 89 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg); 90 90 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 91 IEM_MC_ADVANCE_ RIP_AND_FINISH();91 IEM_MC_ADVANCE_PC_AND_FINISH(); 92 92 IEM_MC_END(); 93 93 } … … 121 121 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 122 122 123 IEM_MC_ADVANCE_ RIP_AND_FINISH();123 IEM_MC_ADVANCE_PC_AND_FINISH(); 124 124 IEM_MC_END(); 125 125 } … … 146 146 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 147 147 148 IEM_MC_ADVANCE_ RIP_AND_FINISH();148 IEM_MC_ADVANCE_PC_AND_FINISH(); 149 149 IEM_MC_END(); 150 150 } … … 183 183 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg); 184 184 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 185 IEM_MC_ADVANCE_ RIP_AND_FINISH();185 IEM_MC_ADVANCE_PC_AND_FINISH(); 186 186 IEM_MC_END(); 187 187 } … … 200 200 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 201 201 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 202 IEM_MC_ADVANCE_ RIP_AND_FINISH();202 IEM_MC_ADVANCE_PC_AND_FINISH(); 203 203 IEM_MC_END(); 204 204 } … … 226 226 IEM_MC_CALL_AVX_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg); 227 227 IEM_MC_STORE_YREG_YMM_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 228 IEM_MC_ADVANCE_ RIP_AND_FINISH();228 IEM_MC_ADVANCE_PC_AND_FINISH(); 229 229 IEM_MC_END(); 230 230 } … … 247 247 IEM_MC_STORE_XREG_XMM( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 248 248 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 249 IEM_MC_ADVANCE_ RIP_AND_FINISH();249 IEM_MC_ADVANCE_PC_AND_FINISH(); 250 250 IEM_MC_END(); 251 251 } … … 286 286 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU256, puDst, puSrc, bImmArg); 287 287 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 288 IEM_MC_ADVANCE_ RIP_AND_FINISH();288 IEM_MC_ADVANCE_PC_AND_FINISH(); 289 289 IEM_MC_END(); 290 290 } … … 302 302 IEM_MC_CALL_VOID_AIMPL_3(pImpl->pfnU128, puDst, puSrc, bImmArg); 303 303 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 304 IEM_MC_ADVANCE_ RIP_AND_FINISH();304 IEM_MC_ADVANCE_PC_AND_FINISH(); 305 305 IEM_MC_END(); 306 306 } … … 331 331 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 332 332 333 IEM_MC_ADVANCE_ RIP_AND_FINISH();333 IEM_MC_ADVANCE_PC_AND_FINISH(); 334 334 IEM_MC_END(); 335 335 } … … 354 354 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 355 355 356 IEM_MC_ADVANCE_ RIP_AND_FINISH();356 IEM_MC_ADVANCE_PC_AND_FINISH(); 357 357 IEM_MC_END(); 358 358 } … … 396 396 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, bImmArg); 397 397 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 398 IEM_MC_ADVANCE_ RIP_AND_FINISH();398 IEM_MC_ADVANCE_PC_AND_FINISH(); 399 399 IEM_MC_END(); 400 400 } … … 414 414 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, bImmArg); 415 415 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 416 IEM_MC_ADVANCE_ RIP_AND_FINISH();416 IEM_MC_ADVANCE_PC_AND_FINISH(); 417 417 IEM_MC_END(); 418 418 } … … 446 446 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 447 447 448 IEM_MC_ADVANCE_ RIP_AND_FINISH();448 IEM_MC_ADVANCE_PC_AND_FINISH(); 449 449 IEM_MC_END(); 450 450 } … … 471 471 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 472 472 473 IEM_MC_ADVANCE_ RIP_AND_FINISH();473 IEM_MC_ADVANCE_PC_AND_FINISH(); 474 474 IEM_MC_END(); 475 475 } … … 501 501 puDst, puSrc, bImmArg); 502 502 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 503 IEM_MC_ADVANCE_ RIP_AND_FINISH();503 IEM_MC_ADVANCE_PC_AND_FINISH(); 504 504 IEM_MC_END(); 505 505 } … … 526 526 puDst, puSrc, bImmArg); 527 527 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 528 IEM_MC_ADVANCE_ RIP_AND_FINISH();528 IEM_MC_ADVANCE_PC_AND_FINISH(); 529 529 IEM_MC_END(); 530 530 } … … 555 555 puDst, puSrc, bImmArg); 556 556 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 557 IEM_MC_ADVANCE_ RIP_AND_FINISH();557 IEM_MC_ADVANCE_PC_AND_FINISH(); 558 558 IEM_MC_END(); 559 559 } … … 580 580 puDst, puSrc, bImmArg); 581 581 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 582 IEM_MC_ADVANCE_ RIP_AND_FINISH();582 IEM_MC_ADVANCE_PC_AND_FINISH(); 583 583 IEM_MC_END(); 584 584 } … … 646 646 puDst, puSrc1, puSrc2, bImmArg); 647 647 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 648 IEM_MC_ADVANCE_ RIP_AND_FINISH();648 IEM_MC_ADVANCE_PC_AND_FINISH(); 649 649 IEM_MC_END(); 650 650 } … … 676 676 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 677 677 678 IEM_MC_ADVANCE_ RIP_AND_FINISH();678 IEM_MC_ADVANCE_PC_AND_FINISH(); 679 679 IEM_MC_END(); 680 680 } … … 728 728 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 729 729 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 730 IEM_MC_ADVANCE_ RIP_AND_FINISH();730 IEM_MC_ADVANCE_PC_AND_FINISH(); 731 731 IEM_MC_END(); 732 732 } … … 754 754 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 755 755 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 756 IEM_MC_ADVANCE_ RIP_AND_FINISH();756 IEM_MC_ADVANCE_PC_AND_FINISH(); 757 757 IEM_MC_END(); 758 758 } … … 785 785 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 786 786 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 787 IEM_MC_ADVANCE_ RIP_AND_FINISH();787 IEM_MC_ADVANCE_PC_AND_FINISH(); 788 788 IEM_MC_END(); 789 789 } … … 811 811 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 812 812 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 813 IEM_MC_ADVANCE_ RIP_AND_FINISH();813 IEM_MC_ADVANCE_PC_AND_FINISH(); 814 814 IEM_MC_END(); 815 815 } … … 885 885 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/); 886 886 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 887 IEM_MC_ADVANCE_ RIP_AND_FINISH();887 IEM_MC_ADVANCE_PC_AND_FINISH(); 888 888 IEM_MC_END(); 889 889 } … … 905 905 IEM_MC_FETCH_XREG_U8(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15 /*a_iByte*/); 906 906 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 907 IEM_MC_ADVANCE_ RIP_AND_FINISH();907 IEM_MC_ADVANCE_PC_AND_FINISH(); 908 908 IEM_MC_END(); 909 909 } … … 932 932 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7); 933 933 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 934 IEM_MC_ADVANCE_ RIP_AND_FINISH();934 IEM_MC_ADVANCE_PC_AND_FINISH(); 935 935 IEM_MC_END(); 936 936 } … … 952 952 IEM_MC_FETCH_XREG_U16(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 7); 953 953 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 954 IEM_MC_ADVANCE_ RIP_AND_FINISH();954 IEM_MC_ADVANCE_PC_AND_FINISH(); 955 955 IEM_MC_END(); 956 956 } … … 980 980 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1); 981 981 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 982 IEM_MC_ADVANCE_ RIP_AND_FINISH();982 IEM_MC_ADVANCE_PC_AND_FINISH(); 983 983 IEM_MC_END(); 984 984 } … … 1000 1000 IEM_MC_FETCH_XREG_U64(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1); 1001 1001 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 1002 IEM_MC_ADVANCE_ RIP_AND_FINISH();1002 IEM_MC_ADVANCE_PC_AND_FINISH(); 1003 1003 IEM_MC_END(); 1004 1004 } … … 1025 1025 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3); 1026 1026 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), uValue); 1027 IEM_MC_ADVANCE_ RIP_AND_FINISH();1027 IEM_MC_ADVANCE_PC_AND_FINISH(); 1028 1028 IEM_MC_END(); 1029 1029 } … … 1045 1045 IEM_MC_FETCH_XREG_U32(uValue, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3); 1046 1046 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uValue); 1047 IEM_MC_ADVANCE_ RIP_AND_FINISH();1047 IEM_MC_ADVANCE_PC_AND_FINISH(); 1048 1048 IEM_MC_END(); 1049 1049 } … … 1072 1072 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 1073 1073 IEM_MC_STORE_GREG_U32( IEM_GET_MODRM_RM(pVCpu, bRm), uSrc); 1074 IEM_MC_ADVANCE_ RIP_AND_FINISH();1074 IEM_MC_ADVANCE_PC_AND_FINISH(); 1075 1075 IEM_MC_END(); 1076 1076 } … … 1092 1092 IEM_MC_FETCH_XREG_U32(uSrc, IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3 /*a_iDword*/); 1093 1093 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uSrc); 1094 IEM_MC_ADVANCE_ RIP_AND_FINISH();1094 IEM_MC_ADVANCE_PC_AND_FINISH(); 1095 1095 IEM_MC_END(); 1096 1096 } … … 1120 1120 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc); 1121 1121 1122 IEM_MC_ADVANCE_ RIP_AND_FINISH();1122 IEM_MC_ADVANCE_PC_AND_FINISH(); 1123 1123 IEM_MC_END(); 1124 1124 } … … 1142 1142 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc); 1143 1143 1144 IEM_MC_ADVANCE_ RIP_AND_FINISH();1144 IEM_MC_ADVANCE_PC_AND_FINISH(); 1145 1145 IEM_MC_END(); 1146 1146 } … … 1169 1169 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst); 1170 1170 1171 IEM_MC_ADVANCE_ RIP_AND_FINISH();1171 IEM_MC_ADVANCE_PC_AND_FINISH(); 1172 1172 IEM_MC_END(); 1173 1173 } … … 1190 1190 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst); 1191 1191 1192 IEM_MC_ADVANCE_ RIP_AND_FINISH();1192 IEM_MC_ADVANCE_PC_AND_FINISH(); 1193 1193 IEM_MC_END(); 1194 1194 } … … 1228 1228 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1229 1229 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue); 1230 IEM_MC_ADVANCE_ RIP_AND_FINISH();1230 IEM_MC_ADVANCE_PC_AND_FINISH(); 1231 1231 IEM_MC_END(); 1232 1232 } … … 1251 1251 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1252 1252 IEM_MC_STORE_XREG_U8( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 15, uValue); 1253 IEM_MC_ADVANCE_ RIP_AND_FINISH();1253 IEM_MC_ADVANCE_PC_AND_FINISH(); 1254 1254 IEM_MC_END(); 1255 1255 } … … 1281 1281 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc2); 1282 1282 IEM_MC_CLEAR_XREG_U32_MASK( IEM_GET_MODRM_REG(pVCpu, bRm), bImm); 1283 IEM_MC_ADVANCE_ RIP_AND_FINISH();1283 IEM_MC_ADVANCE_PC_AND_FINISH(); 1284 1284 IEM_MC_END(); 1285 1285 } … … 1305 1305 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), (bImm >> 4) & 3, uSrc2); 1306 1306 IEM_MC_CLEAR_XREG_U32_MASK( IEM_GET_MODRM_REG(pVCpu, bRm), bImm); 1307 IEM_MC_ADVANCE_ RIP_AND_FINISH();1307 IEM_MC_ADVANCE_PC_AND_FINISH(); 1308 1308 IEM_MC_END(); 1309 1309 } … … 1336 1336 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1337 1337 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue); 1338 IEM_MC_ADVANCE_ RIP_AND_FINISH();1338 IEM_MC_ADVANCE_PC_AND_FINISH(); 1339 1339 IEM_MC_END(); 1340 1340 } … … 1359 1359 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1360 1360 IEM_MC_STORE_XREG_U64( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uValue); 1361 IEM_MC_ADVANCE_ RIP_AND_FINISH();1361 IEM_MC_ADVANCE_PC_AND_FINISH(); 1362 1362 IEM_MC_END(); 1363 1363 } … … 1384 1384 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1385 1385 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue); 1386 IEM_MC_ADVANCE_ RIP_AND_FINISH();1386 IEM_MC_ADVANCE_PC_AND_FINISH(); 1387 1387 IEM_MC_END(); 1388 1388 } … … 1407 1407 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), uSrc1); 1408 1408 IEM_MC_STORE_XREG_U32( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 3, uValue); 1409 IEM_MC_ADVANCE_ RIP_AND_FINISH();1409 IEM_MC_ADVANCE_PC_AND_FINISH(); 1410 1410 IEM_MC_END(); 1411 1411 } … … 1461 1461 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc); 1462 1462 1463 IEM_MC_ADVANCE_ RIP_AND_FINISH();1463 IEM_MC_ADVANCE_PC_AND_FINISH(); 1464 1464 IEM_MC_END(); 1465 1465 } … … 1483 1483 IEM_MC_STORE_YREG_U128( IEM_GET_MODRM_REG(pVCpu, bRm), bImm & 1, uSrc); 1484 1484 1485 IEM_MC_ADVANCE_ RIP_AND_FINISH();1485 IEM_MC_ADVANCE_PC_AND_FINISH(); 1486 1486 IEM_MC_END(); 1487 1487 } … … 1510 1510 IEM_MC_STORE_XREG_U128( IEM_GET_MODRM_RM(pVCpu, bRm), uDst); 1511 1511 1512 IEM_MC_ADVANCE_ RIP_AND_FINISH();1512 IEM_MC_ADVANCE_PC_AND_FINISH(); 1513 1513 IEM_MC_END(); 1514 1514 } … … 1531 1531 IEM_MC_STORE_MEM_U128_NO_AC(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, uDst); 1532 1532 1533 IEM_MC_ADVANCE_ RIP_AND_FINISH();1533 IEM_MC_ADVANCE_PC_AND_FINISH(); 1534 1534 IEM_MC_END(); 1535 1535 } … … 1571 1571 puDst, puSrc, bImmArg); 1572 1572 IEM_MC_STORE_YREG_YMM_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1573 IEM_MC_ADVANCE_ RIP_AND_FINISH();1573 IEM_MC_ADVANCE_PC_AND_FINISH(); 1574 1574 IEM_MC_END(); 1575 1575 } … … 1591 1591 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1592 1592 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1593 IEM_MC_ADVANCE_ RIP_AND_FINISH();1593 IEM_MC_ADVANCE_PC_AND_FINISH(); 1594 1594 IEM_MC_END(); 1595 1595 } … … 1619 1619 puDst, puSrc, bImmArg); 1620 1620 IEM_MC_STORE_YREG_YMM_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1621 IEM_MC_ADVANCE_ RIP_AND_FINISH();1621 IEM_MC_ADVANCE_PC_AND_FINISH(); 1622 1622 IEM_MC_END(); 1623 1623 } … … 1642 1642 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1643 1643 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1644 IEM_MC_ADVANCE_ RIP_AND_FINISH();1644 IEM_MC_ADVANCE_PC_AND_FINISH(); 1645 1645 IEM_MC_END(); 1646 1646 } … … 1674 1674 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1675 1675 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1676 IEM_MC_ADVANCE_ RIP_AND_FINISH();1676 IEM_MC_ADVANCE_PC_AND_FINISH(); 1677 1677 IEM_MC_END(); 1678 1678 } … … 1700 1700 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1701 1701 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1702 IEM_MC_ADVANCE_ RIP_AND_FINISH();1702 IEM_MC_ADVANCE_PC_AND_FINISH(); 1703 1703 IEM_MC_END(); 1704 1704 } … … 1743 1743 puDst, puSrc1, puSrc2, bImmArg); 1744 1744 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1745 IEM_MC_ADVANCE_ RIP_AND_FINISH();1745 IEM_MC_ADVANCE_PC_AND_FINISH(); 1746 1746 IEM_MC_END(); 1747 1747 } … … 1772 1772 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1773 1773 1774 IEM_MC_ADVANCE_ RIP_AND_FINISH();1774 IEM_MC_ADVANCE_PC_AND_FINISH(); 1775 1775 IEM_MC_END(); 1776 1776 } … … 1808 1808 puDst, puSrc1, puSrc2, bImmArg); 1809 1809 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1810 IEM_MC_ADVANCE_ RIP_AND_FINISH();1810 IEM_MC_ADVANCE_PC_AND_FINISH(); 1811 1811 IEM_MC_END(); 1812 1812 } … … 1838 1838 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1839 1839 1840 IEM_MC_ADVANCE_ RIP_AND_FINISH();1840 IEM_MC_ADVANCE_PC_AND_FINISH(); 1841 1841 IEM_MC_END(); 1842 1842 } … … 1887 1887 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU256, puDst, puSrc1, puSrc2, puSrc3); 1888 1888 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1889 IEM_MC_ADVANCE_ RIP_AND_FINISH();1889 IEM_MC_ADVANCE_PC_AND_FINISH(); 1890 1890 IEM_MC_END(); 1891 1891 } … … 1906 1906 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3); 1907 1907 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1908 IEM_MC_ADVANCE_ RIP_AND_FINISH();1908 IEM_MC_ADVANCE_PC_AND_FINISH(); 1909 1909 IEM_MC_END(); 1910 1910 } … … 1940 1940 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 1941 1941 1942 IEM_MC_ADVANCE_ RIP_AND_FINISH();1942 IEM_MC_ADVANCE_PC_AND_FINISH(); 1943 1943 IEM_MC_END(); 1944 1944 } … … 1966 1966 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 1967 1967 1968 IEM_MC_ADVANCE_ RIP_AND_FINISH();1968 IEM_MC_ADVANCE_PC_AND_FINISH(); 1969 1969 IEM_MC_END(); 1970 1970 } … … 2035 2035 2036 2036 IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2037 IEM_MC_ADVANCE_ RIP_AND_FINISH();2037 IEM_MC_ADVANCE_PC_AND_FINISH(); 2038 2038 IEM_MC_END(); 2039 2039 } … … 2054 2054 IEM_MC_CALL_VOID_AIMPL_4(pImpl->pfnU128, puDst, puSrc1, puSrc2, puSrc3); 2055 2055 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2056 IEM_MC_ADVANCE_ RIP_AND_FINISH();2056 IEM_MC_ADVANCE_PC_AND_FINISH(); 2057 2057 IEM_MC_END(); 2058 2058 } … … 2093 2093 2094 2094 IEM_MC_STORE_YREG_U256_ZX_VLMAX( IEM_GET_MODRM_REG(pVCpu, bRm), uDst); 2095 IEM_MC_ADVANCE_ RIP_AND_FINISH();2095 IEM_MC_ADVANCE_PC_AND_FINISH(); 2096 2096 IEM_MC_END(); 2097 2097 } … … 2120 2120 IEM_MC_CLEAR_YREG_128_UP( IEM_GET_MODRM_REG(pVCpu, bRm)); 2121 2121 2122 IEM_MC_ADVANCE_ RIP_AND_FINISH();2122 IEM_MC_ADVANCE_PC_AND_FINISH(); 2123 2123 IEM_MC_END(); 2124 2124 } … … 2201 2201 iemAImpl_vpcmpestrm_u128_fallback), 2202 2202 puDst, pEFlags, pSrc, bImmArg); 2203 IEM_MC_ADVANCE_ RIP_AND_FINISH();2203 IEM_MC_ADVANCE_PC_AND_FINISH(); 2204 2204 IEM_MC_END(); 2205 2205 } … … 2231 2231 iemAImpl_vpcmpestrm_u128_fallback), 2232 2232 puDst, pEFlags, pSrc, bImmArg); 2233 IEM_MC_ADVANCE_ RIP_AND_FINISH();2233 IEM_MC_ADVANCE_PC_AND_FINISH(); 2234 2234 IEM_MC_END(); 2235 2235 } … … 2259 2259 iemAImpl_vpcmpestrm_u128_fallback), 2260 2260 puDst, pEFlags, pSrc, bImmArg); 2261 IEM_MC_ADVANCE_ RIP_AND_FINISH();2261 IEM_MC_ADVANCE_PC_AND_FINISH(); 2262 2262 IEM_MC_END(); 2263 2263 } … … 2289 2289 iemAImpl_vpcmpestrm_u128_fallback), 2290 2290 puDst, pEFlags, pSrc, bImmArg); 2291 IEM_MC_ADVANCE_ RIP_AND_FINISH();2291 IEM_MC_ADVANCE_PC_AND_FINISH(); 2292 2292 IEM_MC_END(); 2293 2293 } … … 2333 2333 pu32Ecx, pEFlags, pSrc, bImmArg); 2334 2334 /** @todo testcase: High dword of RCX cleared? */ 2335 IEM_MC_ADVANCE_ RIP_AND_FINISH();2335 IEM_MC_ADVANCE_PC_AND_FINISH(); 2336 2336 IEM_MC_END(); 2337 2337 } … … 2365 2365 pu32Ecx, pEFlags, pSrc, bImmArg); 2366 2366 /** @todo testcase: High dword of RCX cleared? */ 2367 IEM_MC_ADVANCE_ RIP_AND_FINISH();2367 IEM_MC_ADVANCE_PC_AND_FINISH(); 2368 2368 IEM_MC_END(); 2369 2369 } … … 2395 2395 pu32Ecx, pEFlags, pSrc, bImmArg); 2396 2396 /** @todo testcase: High dword of RCX cleared? */ 2397 IEM_MC_ADVANCE_ RIP_AND_FINISH();2397 IEM_MC_ADVANCE_PC_AND_FINISH(); 2398 2398 IEM_MC_END(); 2399 2399 } … … 2427 2427 pu32Ecx, pEFlags, pSrc, bImmArg); 2428 2428 /** @todo testcase: High dword of RCX cleared? */ 2429 IEM_MC_ADVANCE_ RIP_AND_FINISH();2429 IEM_MC_ADVANCE_PC_AND_FINISH(); 2430 2430 IEM_MC_END(); 2431 2431 } … … 2467 2467 iemAImpl_vpcmpistrm_u128_fallback), 2468 2468 puDst, pEFlags, pSrc, bImmArg); 2469 IEM_MC_ADVANCE_ RIP_AND_FINISH();2469 IEM_MC_ADVANCE_PC_AND_FINISH(); 2470 2470 IEM_MC_END(); 2471 2471 } … … 2496 2496 iemAImpl_vpcmpistrm_u128_fallback), 2497 2497 puDst, pEFlags, pSrc, bImmArg); 2498 IEM_MC_ADVANCE_ RIP_AND_FINISH();2498 IEM_MC_ADVANCE_PC_AND_FINISH(); 2499 2499 IEM_MC_END(); 2500 2500 } … … 2539 2539 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX); 2540 2540 2541 IEM_MC_ADVANCE_ RIP_AND_FINISH();2541 IEM_MC_ADVANCE_PC_AND_FINISH(); 2542 2542 IEM_MC_END(); 2543 2543 } … … 2572 2572 IEM_MC_STORE_GREG_U32(X86_GREG_xCX, u32Ecx); 2573 2573 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xCX); 2574 IEM_MC_ADVANCE_ RIP_AND_FINISH();2574 IEM_MC_ADVANCE_PC_AND_FINISH(); 2575 2575 IEM_MC_END(); 2576 2576 } … … 2683 2683 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback), 2684 2684 puDst, puSrc, bImmArg); 2685 IEM_MC_ADVANCE_ RIP_AND_FINISH();2685 IEM_MC_ADVANCE_PC_AND_FINISH(); 2686 2686 IEM_MC_END(); 2687 2687 } … … 2707 2707 IEM_MC_CALL_VOID_AIMPL_3(IEM_SELECT_HOST_OR_FALLBACK(fAesNi, iemAImpl_vaeskeygenassist_u128, iemAImpl_vaeskeygenassist_u128_fallback), 2708 2708 puDst, puSrc, bImmArg); 2709 IEM_MC_ADVANCE_ RIP_AND_FINISH();2709 IEM_MC_ADVANCE_PC_AND_FINISH(); 2710 2710 IEM_MC_END(); 2711 2711 } … … 2739 2739 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); 2740 2740 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2); 2741 IEM_MC_ADVANCE_ RIP_AND_FINISH();2741 IEM_MC_ADVANCE_PC_AND_FINISH(); 2742 2742 IEM_MC_END(); 2743 2743 } … … 2753 2753 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2); 2754 2754 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 2755 IEM_MC_ADVANCE_ RIP_AND_FINISH();2755 IEM_MC_ADVANCE_PC_AND_FINISH(); 2756 2756 IEM_MC_END(); 2757 2757 } … … 2775 2775 IEM_MC_REF_GREG_U64(pDst, IEM_GET_MODRM_REG(pVCpu, bRm)); 2776 2776 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u64, pDst, uSrc1, uSrc2); 2777 IEM_MC_ADVANCE_ RIP_AND_FINISH();2777 IEM_MC_ADVANCE_PC_AND_FINISH(); 2778 2778 IEM_MC_END(); 2779 2779 } … … 2792 2792 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_rorx_u32, pDst, uSrc1, uSrc2); 2793 2793 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm)); 2794 IEM_MC_ADVANCE_ RIP_AND_FINISH();2794 IEM_MC_ADVANCE_PC_AND_FINISH(); 2795 2795 IEM_MC_END(); 2796 2796 } -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veLiveness-x86.h
r108204 r108267 311 311 312 312 /* We don't track RIP (PC) liveness. */ 313 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_NO_FLAGS()314 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_NO_FLAGS()315 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_NO_FLAGS()316 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_WITH_FLAGS()317 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_WITH_FLAGS()318 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal)IEM_LIVENESS_PC_WITH_FLAGS()313 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_NO_FLAGS() 314 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_NO_FLAGS() 315 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_NO_FLAGS() 316 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_WITH_FLAGS() 317 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_WITH_FLAGS() 318 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) IEM_LIVENESS_PC_WITH_FLAGS() 319 319 320 320 #define IEM_MC_REL_JMP_S8_AND_FINISH_THREADED_PC16(a_i8, a_cbInstr, a_rcNormal) IEM_LIVENESS_PC16_JMP_NO_FLAGS() -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllN8veRecompFuncs-x86.h
r108204 r108267 402 402 403 403 /********************************************************************************************************************************* 404 * Emitters for advancing PC/RIP/EIP/IP (IEM_MC_ADVANCE_ RIP_AND_FINISH_XXX)*404 * Emitters for advancing PC/RIP/EIP/IP (IEM_MC_ADVANCE_PC_AND_FINISH_XXX) * 405 405 *********************************************************************************************************************************/ 406 406 407 /** Emits the flags check for IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS407 /** Emits the flags check for IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64_WITH_FLAGS 408 408 * and the other _WITH_FLAGS MCs, see iemRegFinishClearingRF. */ 409 409 DECL_INLINE_THROW(uint32_t) … … 570 570 571 571 572 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \572 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \ 573 573 off = iemNativeEmitAddToRip64AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 574 574 off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal, false /*a_fIsJump*/>(pReNative, off, pCallEntry, 0) 575 575 576 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \576 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 577 577 off = iemNativeEmitAddToRip64AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 578 578 off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \ … … 616 616 617 617 618 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \618 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \ 619 619 off = iemNativeEmitAddToEip32AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 620 620 off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal, false /*a_fIsJump*/>(pReNative, off, pCallEntry, 0) 621 621 622 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \622 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 623 623 off = iemNativeEmitAddToEip32AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 624 624 off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \ … … 662 662 663 663 664 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \664 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \ 665 665 off = iemNativeEmitAddToIp16AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 666 666 off = iemNativeEmitFinishInstructionWithStatus<a_rcNormal, false /*a_fIsJump*/>(pReNative, off, pCallEntry, 0) 667 667 668 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \668 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 669 669 off = iemNativeEmitAddToIp16AndFinishingNoFlags(pReNative, off, (a_cbInstr)); \ 670 670 off = iemNativeEmitFinishInstructionFlagsCheck(pReNative, off); \ -
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllThrdFuncs-x86.cpp
r108260 r108267 82 82 *********************************************************************************************************************************/ 83 83 84 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param84 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 85 85 * and only used when we're in 16-bit code on a pre-386 CPU. */ 86 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \86 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16(a_cbInstr, a_rcNormal) \ 87 87 return iemRegAddToIp16AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal) 88 88 89 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param89 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 90 90 * and used for 16-bit and 32-bit code on 386 and later CPUs. */ 91 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \91 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32(a_cbInstr, a_rcNormal) \ 92 92 return iemRegAddToEip32AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal) 93 93 94 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param94 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 95 95 * and only used when we're in 64-bit code. */ 96 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \96 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64(a_cbInstr, a_rcNormal) \ 97 97 return iemRegAddToRip64AndFinishingNoFlags(pVCpu, a_cbInstr, a_rcNormal) 98 98 99 99 100 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param100 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 101 101 * and only used when we're in 16-bit code on a pre-386 CPU and we need to 102 102 * check and clear flags. */ 103 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \103 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC16_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 104 104 return iemRegAddToIp16AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal) 105 105 106 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param106 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 107 107 * and used for 16-bit and 32-bit code on 386 and later CPUs and we need to 108 108 * check and clear flags. */ 109 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \109 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC32_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 110 110 return iemRegAddToEip32AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal) 111 111 112 /** Variant of IEM_MC_ADVANCE_ RIP_AND_FINISH with instruction length as param112 /** Variant of IEM_MC_ADVANCE_PC_AND_FINISH with instruction length as param 113 113 * and only used when we're in 64-bit code and we need to check and clear 114 114 * flags. */ 115 #define IEM_MC_ADVANCE_ RIP_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \115 #define IEM_MC_ADVANCE_PC_AND_FINISH_THREADED_PC64_WITH_FLAGS(a_cbInstr, a_rcNormal) \ 116 116 return iemRegAddToRip64AndFinishingClearingRF(pVCpu, a_cbInstr, a_rcNormal) 117 117 118 #undef IEM_MC_ADVANCE_ RIP_AND_FINISH118 #undef IEM_MC_ADVANCE_PC_AND_FINISH 119 119 120 120 -
trunk/src/VBox/VMM/include/IEMMc.h
r107218 r108267 61 61 /** Advances RIP, finishes the instruction and returns. 62 62 * This may include raising debug exceptions and such. */ 63 #define IEM_MC_ADVANCE_ RIP_AND_FINISH()return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu))63 #define IEM_MC_ADVANCE_PC_AND_FINISH() return iemRegAddToRipAndFinishingClearingRF(pVCpu, IEM_GET_INSTR_LEN(pVCpu)) 64 64 /** Sets RIP (may trigger \#GP), finishes the instruction and returns. */ 65 65 #define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) \ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r108204 r108267 604 604 #define IEM_MC_NO_NATIVE_RECOMPILE() ((void)0) 605 605 606 #define IEM_MC_ADVANCE_ RIP_AND_FINISH()do { (void)fMcBegin; return VINF_SUCCESS; } while (0)606 #define IEM_MC_ADVANCE_PC_AND_FINISH() do { (void)fMcBegin; return VINF_SUCCESS; } while (0) 607 607 #define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8) do { (void)fMcBegin; CHK_TYPE(int8_t, a_i8); return VINF_SUCCESS; } while (0) 608 608 #define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16) do { (void)fMcBegin; CHK_TYPE(int16_t, a_i16); return VINF_SUCCESS; } while (0)
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