Changeset 108267 in vbox for trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstOneByte-x86.cpp.h
- Timestamp:
- Feb 17, 2025 9:20:49 PM (5 weeks ago)
- svn:sync-xref-src-repo-rev:
- 167592
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/target-x86/IEMAllInstOneByte-x86.cpp.h
r108204 r108267 75 75 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 76 76 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 77 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \77 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 78 78 IEM_MC_END(); \ 79 79 } ((void)0) … … 107 107 IEM_MC_COMMIT_EFLAGS_OPT(fEFlagsRet); \ 108 108 } IEM_MC_NATIVE_ENDIF(); \ 109 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \109 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 110 110 IEM_MC_END(); \ 111 111 } \ … … 132 132 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 133 133 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 134 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \134 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 135 135 IEM_MC_END(); \ 136 136 } \ … … 152 152 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bMapInfoDst); \ 153 153 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 154 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \154 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 155 155 IEM_MC_END(); \ 156 156 } \ … … 185 185 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 186 186 } IEM_MC_NATIVE_ENDIF(); \ 187 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \187 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 188 188 IEM_MC_END(); \ 189 189 } \ … … 218 218 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 219 219 } IEM_MC_NATIVE_ENDIF(); \ 220 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \220 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 221 221 IEM_MC_END(); \ 222 222 } \ … … 258 258 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 259 259 } IEM_MC_NATIVE_ENDIF(); \ 260 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \260 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 261 261 IEM_MC_END(); \ 262 262 } \ … … 286 286 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 287 287 } IEM_MC_NATIVE_ENDIF(); \ 288 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \288 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 289 289 IEM_MC_END(); \ 290 290 } \ … … 317 317 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 318 318 } IEM_MC_NATIVE_ENDIF(); \ 319 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \319 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 320 320 IEM_MC_END(); \ 321 321 } \ … … 344 344 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 345 345 } IEM_MC_NATIVE_ENDIF(); \ 346 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \346 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 347 347 IEM_MC_END(); \ 348 348 } \ … … 381 381 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 382 382 } IEM_MC_NATIVE_ENDIF(); \ 383 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \383 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 384 384 IEM_MC_END(); \ 385 385 break; \ … … 405 405 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 406 406 } IEM_MC_NATIVE_ENDIF(); \ 407 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \407 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 408 408 IEM_MC_END(); \ 409 409 break; \ … … 428 428 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 429 429 } IEM_MC_NATIVE_ENDIF(); \ 430 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \430 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 431 431 IEM_MC_END(); \ 432 432 break; \ … … 460 460 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 461 461 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 462 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \462 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 463 463 IEM_MC_END(); \ 464 464 break; \ … … 480 480 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 481 481 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 482 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \482 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 483 483 IEM_MC_END(); \ 484 484 break; \ … … 500 500 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 501 501 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 502 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \502 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 503 503 IEM_MC_END(); \ 504 504 break; \ … … 530 530 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 531 531 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 532 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \532 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 533 533 IEM_MC_END(); \ 534 534 break; \ … … 550 550 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo /* CMP,TEST */); \ 551 551 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 552 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \552 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 553 553 IEM_MC_END(); \ 554 554 break; \ … … 570 570 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 571 571 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 572 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \572 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 573 573 IEM_MC_END(); \ 574 574 break; \ … … 610 610 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 611 611 } IEM_MC_NATIVE_ENDIF(); \ 612 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \612 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 613 613 IEM_MC_END(); \ 614 614 break; \ … … 632 632 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 633 633 } IEM_MC_NATIVE_ENDIF(); \ 634 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \634 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 635 635 IEM_MC_END(); \ 636 636 break; \ … … 654 654 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 655 655 } IEM_MC_NATIVE_ENDIF(); \ 656 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \656 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 657 657 IEM_MC_END(); \ 658 658 break; \ … … 694 694 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 695 695 } IEM_MC_NATIVE_ENDIF(); \ 696 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \696 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 697 697 IEM_MC_END(); \ 698 698 break; \ … … 722 722 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 723 723 } IEM_MC_NATIVE_ENDIF(); \ 724 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \724 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 725 725 IEM_MC_END(); \ 726 726 break; \ … … 750 750 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 751 751 } IEM_MC_NATIVE_ENDIF(); \ 752 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \752 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 753 753 IEM_MC_END(); \ 754 754 break; \ … … 790 790 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 791 791 } IEM_MC_NATIVE_ENDIF(); \ 792 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \792 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 793 793 IEM_MC_END() 794 794 … … 821 821 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 822 822 } IEM_MC_NATIVE_ENDIF(); \ 823 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \823 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 824 824 IEM_MC_END(); \ 825 825 } \ … … 847 847 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 848 848 } IEM_MC_NATIVE_ENDIF(); \ 849 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \849 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 850 850 IEM_MC_END(); \ 851 851 } \ … … 872 872 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 873 873 } IEM_MC_NATIVE_ENDIF(); \ 874 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \874 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 875 875 IEM_MC_END(); \ 876 876 } \ … … 907 907 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 908 908 } IEM_MC_NATIVE_ENDIF(); \ 909 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \909 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 910 910 IEM_MC_END(); \ 911 911 } \ … … 931 931 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 932 932 } IEM_MC_NATIVE_ENDIF(); \ 933 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \933 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 934 934 IEM_MC_END(); \ 935 935 } \ … … 955 955 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 956 956 } IEM_MC_NATIVE_ENDIF(); \ 957 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \957 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 958 958 IEM_MC_END(); \ 959 959 } \ … … 1627 1627 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1628 1628 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1629 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1629 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1630 1630 IEM_MC_END(); \ 1631 1631 break; \ … … 1639 1639 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1640 1640 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1641 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1641 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1642 1642 IEM_MC_END(); \ 1643 1643 break; \ … … 1651 1651 IEM_MC_OR_LOCAL_U32(fEFlags, X86_EFL_PF | X86_EFL_ZF); \ 1652 1652 IEM_MC_COMMIT_EFLAGS(fEFlags); \ 1653 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1653 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1654 1654 IEM_MC_END(); \ 1655 1655 break; \ … … 1965 1965 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 1966 1966 } IEM_MC_NATIVE_ENDIF(); \ 1967 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1967 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1968 1968 IEM_MC_END(); \ 1969 1969 break; \ … … 1987 1987 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 1988 1988 } IEM_MC_NATIVE_ENDIF(); \ 1989 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \1989 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 1990 1990 IEM_MC_END(); \ 1991 1991 break; \ … … 2009 2009 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2010 2010 } IEM_MC_NATIVE_ENDIF(); \ 2011 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2011 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2012 2012 IEM_MC_END(); \ 2013 2013 break; \ … … 2043 2043 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2044 2044 } IEM_MC_NATIVE_ENDIF(); \ 2045 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2045 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2046 2046 IEM_MC_END(); \ 2047 2047 break; \ … … 2067 2067 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2068 2068 } IEM_MC_NATIVE_ENDIF(); \ 2069 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2069 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2070 2070 IEM_MC_END(); \ 2071 2071 break; \ … … 2091 2091 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 2092 2092 } IEM_MC_NATIVE_ENDIF(); \ 2093 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2093 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2094 2094 IEM_MC_END(); \ 2095 2095 break; \ … … 2254 2254 IEM_MC_REF_EFLAGS(pEFlags); \ 2255 2255 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 2256 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2256 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2257 2257 IEM_MC_END(); \ 2258 2258 break; \ … … 2267 2267 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 2268 2268 IEM_MC_CLEAR_HIGH_GREG_U64(a_iReg); \ 2269 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \2269 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 2270 2270 IEM_MC_END(); \ 2271 2271 break; \ … … 2695 2695 IEM_MC_FETCH_GREG_U16(u16Value, iReg); 2696 2696 IEM_MC_PUSH_U16(u16Value); 2697 IEM_MC_ADVANCE_ RIP_AND_FINISH();2697 IEM_MC_ADVANCE_PC_AND_FINISH(); 2698 2698 IEM_MC_END(); 2699 2699 break; … … 2705 2705 IEM_MC_FETCH_GREG_U32(u32Value, iReg); 2706 2706 IEM_MC_PUSH_U32(u32Value); 2707 IEM_MC_ADVANCE_ RIP_AND_FINISH();2707 IEM_MC_ADVANCE_PC_AND_FINISH(); 2708 2708 IEM_MC_END(); 2709 2709 break; … … 2715 2715 IEM_MC_FETCH_GREG_U64(u64Value, iReg); 2716 2716 IEM_MC_PUSH_U64(u64Value); 2717 IEM_MC_ADVANCE_ RIP_AND_FINISH();2717 IEM_MC_ADVANCE_PC_AND_FINISH(); 2718 2718 IEM_MC_END(); 2719 2719 break; … … 2780 2780 IEM_MC_SUB_LOCAL_U16(u16Value, 2); 2781 2781 IEM_MC_PUSH_U16(u16Value); 2782 IEM_MC_ADVANCE_ RIP_AND_FINISH();2782 IEM_MC_ADVANCE_PC_AND_FINISH(); 2783 2783 IEM_MC_END(); 2784 2784 } … … 2833 2833 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2834 2834 IEM_MC_POP_GREG_U16(iReg); 2835 IEM_MC_ADVANCE_ RIP_AND_FINISH();2835 IEM_MC_ADVANCE_PC_AND_FINISH(); 2836 2836 IEM_MC_END(); 2837 2837 break; … … 2841 2841 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2842 2842 IEM_MC_POP_GREG_U32(iReg); 2843 IEM_MC_ADVANCE_ RIP_AND_FINISH();2843 IEM_MC_ADVANCE_PC_AND_FINISH(); 2844 2844 IEM_MC_END(); 2845 2845 break; … … 2849 2849 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 2850 2850 IEM_MC_POP_GREG_U64(iReg); 2851 IEM_MC_ADVANCE_ RIP_AND_FINISH();2851 IEM_MC_ADVANCE_PC_AND_FINISH(); 2852 2852 IEM_MC_END(); 2853 2853 break; … … 3158 3158 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3159 3159 3160 IEM_MC_ADVANCE_ RIP_AND_FINISH();3160 IEM_MC_ADVANCE_PC_AND_FINISH(); 3161 3161 IEM_MC_END(); 3162 3162 } … … 3179 3179 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); 3180 3180 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3181 IEM_MC_ADVANCE_ RIP_AND_FINISH();3181 IEM_MC_ADVANCE_PC_AND_FINISH(); 3182 3182 IEM_MC_END(); 3183 3183 } … … 3210 3210 IEM_MC_FETCH_GREG_U32_SX_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 3211 3211 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 3212 IEM_MC_ADVANCE_ RIP_AND_FINISH();3212 IEM_MC_ADVANCE_PC_AND_FINISH(); 3213 3213 IEM_MC_END(); 3214 3214 } … … 3225 3225 IEM_MC_FETCH_MEM_U32_SX_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 3226 3226 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 3227 IEM_MC_ADVANCE_ RIP_AND_FINISH();3227 IEM_MC_ADVANCE_PC_AND_FINISH(); 3228 3228 IEM_MC_END(); 3229 3229 } … … 3341 3341 IEM_MC_LOCAL_CONST(uint16_t, u16Value, u16Imm); 3342 3342 IEM_MC_PUSH_U16(u16Value); 3343 IEM_MC_ADVANCE_ RIP_AND_FINISH();3343 IEM_MC_ADVANCE_PC_AND_FINISH(); 3344 3344 IEM_MC_END(); 3345 3345 break; … … 3351 3351 IEM_MC_LOCAL_CONST(uint32_t, u32Value, u32Imm); 3352 3352 IEM_MC_PUSH_U32(u32Value); 3353 IEM_MC_ADVANCE_ RIP_AND_FINISH();3353 IEM_MC_ADVANCE_PC_AND_FINISH(); 3354 3354 IEM_MC_END(); 3355 3355 break; … … 3361 3361 IEM_MC_LOCAL_CONST(uint64_t, u64Value, u64Imm); 3362 3362 IEM_MC_PUSH_U64(u64Value); 3363 IEM_MC_ADVANCE_ RIP_AND_FINISH();3363 IEM_MC_ADVANCE_PC_AND_FINISH(); 3364 3364 IEM_MC_END(); 3365 3365 break; … … 3402 3402 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3403 3403 3404 IEM_MC_ADVANCE_ RIP_AND_FINISH();3404 IEM_MC_ADVANCE_PC_AND_FINISH(); 3405 3405 IEM_MC_END(); 3406 3406 } … … 3425 3425 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3426 3426 3427 IEM_MC_ADVANCE_ RIP_AND_FINISH();3427 IEM_MC_ADVANCE_PC_AND_FINISH(); 3428 3428 IEM_MC_END(); 3429 3429 } … … 3450 3450 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3451 3451 3452 IEM_MC_ADVANCE_ RIP_AND_FINISH();3452 IEM_MC_ADVANCE_PC_AND_FINISH(); 3453 3453 IEM_MC_END(); 3454 3454 } … … 3473 3473 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3474 3474 3475 IEM_MC_ADVANCE_ RIP_AND_FINISH();3475 IEM_MC_ADVANCE_PC_AND_FINISH(); 3476 3476 IEM_MC_END(); 3477 3477 } … … 3498 3498 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3499 3499 3500 IEM_MC_ADVANCE_ RIP_AND_FINISH();3500 IEM_MC_ADVANCE_PC_AND_FINISH(); 3501 3501 IEM_MC_END(); 3502 3502 } … … 3521 3521 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3522 3522 3523 IEM_MC_ADVANCE_ RIP_AND_FINISH();3523 IEM_MC_ADVANCE_PC_AND_FINISH(); 3524 3524 IEM_MC_END(); 3525 3525 } … … 3549 3549 IEM_MC_LOCAL_CONST(uint16_t, uValue, (int16_t)i8Imm); 3550 3550 IEM_MC_PUSH_U16(uValue); 3551 IEM_MC_ADVANCE_ RIP_AND_FINISH();3551 IEM_MC_ADVANCE_PC_AND_FINISH(); 3552 3552 IEM_MC_END(); 3553 3553 break; … … 3557 3557 IEM_MC_LOCAL_CONST(uint32_t, uValue, (int32_t)i8Imm); 3558 3558 IEM_MC_PUSH_U32(uValue); 3559 IEM_MC_ADVANCE_ RIP_AND_FINISH();3559 IEM_MC_ADVANCE_PC_AND_FINISH(); 3560 3560 IEM_MC_END(); 3561 3561 break; … … 3565 3565 IEM_MC_LOCAL_CONST(uint64_t, uValue, (int64_t)i8Imm); 3566 3566 IEM_MC_PUSH_U64(uValue); 3567 IEM_MC_ADVANCE_ RIP_AND_FINISH();3567 IEM_MC_ADVANCE_PC_AND_FINISH(); 3568 3568 IEM_MC_END(); 3569 3569 break; … … 3606 3606 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3607 3607 3608 IEM_MC_ADVANCE_ RIP_AND_FINISH();3608 IEM_MC_ADVANCE_PC_AND_FINISH(); 3609 3609 IEM_MC_END(); 3610 3610 } … … 3630 3630 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3631 3631 3632 IEM_MC_ADVANCE_ RIP_AND_FINISH();3632 IEM_MC_ADVANCE_PC_AND_FINISH(); 3633 3633 IEM_MC_END(); 3634 3634 } … … 3655 3655 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3656 3656 3657 IEM_MC_ADVANCE_ RIP_AND_FINISH();3657 IEM_MC_ADVANCE_PC_AND_FINISH(); 3658 3658 IEM_MC_END(); 3659 3659 } … … 3678 3678 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3679 3679 3680 IEM_MC_ADVANCE_ RIP_AND_FINISH();3680 IEM_MC_ADVANCE_PC_AND_FINISH(); 3681 3681 IEM_MC_END(); 3682 3682 } … … 3703 3703 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3704 3704 3705 IEM_MC_ADVANCE_ RIP_AND_FINISH();3705 IEM_MC_ADVANCE_PC_AND_FINISH(); 3706 3706 IEM_MC_END(); 3707 3707 } … … 3726 3726 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 3727 3727 3728 IEM_MC_ADVANCE_ RIP_AND_FINISH();3728 IEM_MC_ADVANCE_PC_AND_FINISH(); 3729 3729 IEM_MC_END(); 3730 3730 } … … 4074 4074 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4075 4075 } IEM_MC_ELSE() { 4076 IEM_MC_ADVANCE_ RIP_AND_FINISH();4076 IEM_MC_ADVANCE_PC_AND_FINISH(); 4077 4077 } IEM_MC_ENDIF(); 4078 4078 IEM_MC_END(); … … 4093 4093 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4094 4094 IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) { 4095 IEM_MC_ADVANCE_ RIP_AND_FINISH();4095 IEM_MC_ADVANCE_PC_AND_FINISH(); 4096 4096 } IEM_MC_ELSE() { 4097 4097 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4115 4115 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4116 4116 } IEM_MC_ELSE() { 4117 IEM_MC_ADVANCE_ RIP_AND_FINISH();4117 IEM_MC_ADVANCE_PC_AND_FINISH(); 4118 4118 } IEM_MC_ENDIF(); 4119 4119 IEM_MC_END(); … … 4134 4134 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4135 4135 IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) { 4136 IEM_MC_ADVANCE_ RIP_AND_FINISH();4136 IEM_MC_ADVANCE_PC_AND_FINISH(); 4137 4137 } IEM_MC_ELSE() { 4138 4138 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4157 4157 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4158 4158 } IEM_MC_ELSE() { 4159 IEM_MC_ADVANCE_ RIP_AND_FINISH();4159 IEM_MC_ADVANCE_PC_AND_FINISH(); 4160 4160 } IEM_MC_ENDIF(); 4161 4161 IEM_MC_END(); … … 4176 4176 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4177 4177 IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) { 4178 IEM_MC_ADVANCE_ RIP_AND_FINISH();4178 IEM_MC_ADVANCE_PC_AND_FINISH(); 4179 4179 } IEM_MC_ELSE() { 4180 4180 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4199 4199 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4200 4200 } IEM_MC_ELSE() { 4201 IEM_MC_ADVANCE_ RIP_AND_FINISH();4201 IEM_MC_ADVANCE_PC_AND_FINISH(); 4202 4202 } IEM_MC_ENDIF(); 4203 4203 IEM_MC_END(); … … 4218 4218 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4219 4219 IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) { 4220 IEM_MC_ADVANCE_ RIP_AND_FINISH();4220 IEM_MC_ADVANCE_PC_AND_FINISH(); 4221 4221 } IEM_MC_ELSE() { 4222 4222 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4241 4241 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4242 4242 } IEM_MC_ELSE() { 4243 IEM_MC_ADVANCE_ RIP_AND_FINISH();4243 IEM_MC_ADVANCE_PC_AND_FINISH(); 4244 4244 } IEM_MC_ENDIF(); 4245 4245 IEM_MC_END(); … … 4260 4260 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4261 4261 IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) { 4262 IEM_MC_ADVANCE_ RIP_AND_FINISH();4262 IEM_MC_ADVANCE_PC_AND_FINISH(); 4263 4263 } IEM_MC_ELSE() { 4264 4264 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4283 4283 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4284 4284 } IEM_MC_ELSE() { 4285 IEM_MC_ADVANCE_ RIP_AND_FINISH();4285 IEM_MC_ADVANCE_PC_AND_FINISH(); 4286 4286 } IEM_MC_ENDIF(); 4287 4287 IEM_MC_END(); … … 4302 4302 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4303 4303 IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) { 4304 IEM_MC_ADVANCE_ RIP_AND_FINISH();4304 IEM_MC_ADVANCE_PC_AND_FINISH(); 4305 4305 } IEM_MC_ELSE() { 4306 4306 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4325 4325 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4326 4326 } IEM_MC_ELSE() { 4327 IEM_MC_ADVANCE_ RIP_AND_FINISH();4327 IEM_MC_ADVANCE_PC_AND_FINISH(); 4328 4328 } IEM_MC_ENDIF(); 4329 4329 IEM_MC_END(); … … 4344 4344 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4345 4345 IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) { 4346 IEM_MC_ADVANCE_ RIP_AND_FINISH();4346 IEM_MC_ADVANCE_PC_AND_FINISH(); 4347 4347 } IEM_MC_ELSE() { 4348 4348 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4367 4367 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); 4368 4368 } IEM_MC_ELSE() { 4369 IEM_MC_ADVANCE_ RIP_AND_FINISH();4369 IEM_MC_ADVANCE_PC_AND_FINISH(); 4370 4370 } IEM_MC_ENDIF(); 4371 4371 IEM_MC_END(); … … 4386 4386 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4387 4387 IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) { 4388 IEM_MC_ADVANCE_ RIP_AND_FINISH();4388 IEM_MC_ADVANCE_PC_AND_FINISH(); 4389 4389 } IEM_MC_ELSE() { 4390 4390 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 4420 4420 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4421 4421 } IEM_MC_NATIVE_ENDIF(); \ 4422 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4422 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4423 4423 IEM_MC_END(); \ 4424 4424 } \ … … 4443 4443 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4444 4444 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4445 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4445 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4446 4446 IEM_MC_END(); \ 4447 4447 } \ … … 4463 4463 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4464 4464 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4465 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4465 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4466 4466 IEM_MC_END(); \ 4467 4467 } \ … … 4490 4490 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4491 4491 } IEM_MC_NATIVE_ENDIF(); \ 4492 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4492 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4493 4493 IEM_MC_END(); \ 4494 4494 } \ … … 4519 4519 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4520 4520 } IEM_MC_NATIVE_ENDIF(); \ 4521 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4521 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4522 4522 IEM_MC_END(); \ 4523 4523 } \ … … 4679 4679 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4680 4680 } IEM_MC_NATIVE_ENDIF(); \ 4681 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4681 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4682 4682 IEM_MC_END(); \ 4683 4683 break; \ … … 4706 4706 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4707 4707 } IEM_MC_NATIVE_ENDIF(); \ 4708 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4708 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4709 4709 IEM_MC_END(); \ 4710 4710 break; \ … … 4732 4732 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4733 4733 } IEM_MC_NATIVE_ENDIF(); \ 4734 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4734 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4735 4735 IEM_MC_END(); \ 4736 4736 break; \ … … 4766 4766 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4767 4767 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4768 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4768 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4769 4769 IEM_MC_END(); \ 4770 4770 break; \ … … 4790 4790 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4791 4791 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4792 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4792 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4793 4793 IEM_MC_END(); \ 4794 4794 break; \ … … 4815 4815 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 4816 4816 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4817 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4817 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4818 4818 IEM_MC_END(); \ 4819 4819 break; \ … … 4846 4846 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4847 4847 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4848 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4848 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4849 4849 IEM_MC_END(); \ 4850 4850 break; \ … … 4870 4870 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4871 4871 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4872 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4872 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4873 4873 IEM_MC_END(); \ 4874 4874 break; \ … … 4894 4894 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 4895 4895 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4896 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4896 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4897 4897 IEM_MC_END(); \ 4898 4898 break; \ … … 4932 4932 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4933 4933 } IEM_MC_NATIVE_ENDIF(); \ 4934 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4934 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4935 4935 IEM_MC_END(); \ 4936 4936 break; \ … … 4957 4957 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4958 4958 } IEM_MC_NATIVE_ENDIF(); \ 4959 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4959 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4960 4960 IEM_MC_END(); \ 4961 4961 break; \ … … 4982 4982 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 4983 4983 } IEM_MC_NATIVE_ENDIF(); \ 4984 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \4984 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 4985 4985 IEM_MC_END(); \ 4986 4986 break; \ … … 5020 5020 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5021 5021 } IEM_MC_NATIVE_ENDIF(); \ 5022 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5022 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5023 5023 IEM_MC_END(); \ 5024 5024 break; \ … … 5048 5048 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5049 5049 } IEM_MC_NATIVE_ENDIF(); \ 5050 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5050 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5051 5051 IEM_MC_END(); \ 5052 5052 break; \ … … 5076 5076 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5077 5077 } IEM_MC_NATIVE_ENDIF(); \ 5078 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5078 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5079 5079 IEM_MC_END(); \ 5080 5080 break; \ … … 5254 5254 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5255 5255 } IEM_MC_NATIVE_ENDIF(); \ 5256 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5256 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5257 5257 IEM_MC_END(); \ 5258 5258 break; \ … … 5278 5278 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5279 5279 } IEM_MC_NATIVE_ENDIF(); \ 5280 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5280 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5281 5281 IEM_MC_END(); \ 5282 5282 break; \ … … 5301 5301 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5302 5302 } IEM_MC_NATIVE_ENDIF(); \ 5303 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5303 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5304 5304 IEM_MC_END(); \ 5305 5305 break; \ … … 5335 5335 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5336 5336 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5337 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5337 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5338 5338 IEM_MC_END(); \ 5339 5339 break; \ … … 5357 5357 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5358 5358 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5359 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5359 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5360 5360 IEM_MC_END(); \ 5361 5361 break; \ … … 5379 5379 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 5380 5380 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5381 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5381 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5382 5382 IEM_MC_END(); \ 5383 5383 break; \ … … 5408 5408 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5409 5409 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5410 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5410 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5411 5411 IEM_MC_END(); \ 5412 5412 break; \ … … 5430 5430 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5431 5431 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5432 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5432 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5433 5433 IEM_MC_END(); \ 5434 5434 break; \ … … 5452 5452 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 5453 5453 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5454 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5454 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5455 5455 IEM_MC_END(); \ 5456 5456 break; \ … … 5489 5489 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5490 5490 } IEM_MC_NATIVE_ENDIF(); \ 5491 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5491 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5492 5492 IEM_MC_END(); \ 5493 5493 break; \ … … 5510 5510 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5511 5511 } IEM_MC_NATIVE_ENDIF(); \ 5512 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5512 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5513 5513 IEM_MC_END(); \ 5514 5514 break; \ … … 5531 5531 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5532 5532 } IEM_MC_NATIVE_ENDIF(); \ 5533 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5533 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5534 5534 IEM_MC_END(); \ 5535 5535 break; \ … … 5569 5569 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5570 5570 } IEM_MC_NATIVE_ENDIF(); \ 5571 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5571 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5572 5572 IEM_MC_END(); \ 5573 5573 break; \ … … 5595 5595 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5596 5596 } IEM_MC_NATIVE_ENDIF(); \ 5597 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5597 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5598 5598 IEM_MC_END(); \ 5599 5599 break; \ … … 5621 5621 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 5622 5622 } IEM_MC_NATIVE_ENDIF(); \ 5623 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5623 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5624 5624 IEM_MC_END(); \ 5625 5625 break; \ … … 5789 5789 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5790 5790 } IEM_MC_NATIVE_ENDIF(); 5791 IEM_MC_ADVANCE_ RIP_AND_FINISH();5791 IEM_MC_ADVANCE_PC_AND_FINISH(); 5792 5792 IEM_MC_END(); 5793 5793 } … … 5833 5833 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5834 5834 } IEM_MC_NATIVE_ENDIF(); 5835 IEM_MC_ADVANCE_ RIP_AND_FINISH();5835 IEM_MC_ADVANCE_PC_AND_FINISH(); 5836 5836 IEM_MC_END(); 5837 5837 break; … … 5853 5853 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5854 5854 } IEM_MC_NATIVE_ENDIF(); 5855 IEM_MC_ADVANCE_ RIP_AND_FINISH();5855 IEM_MC_ADVANCE_PC_AND_FINISH(); 5856 5856 IEM_MC_END(); 5857 5857 break; … … 5873 5873 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); 5874 5874 } IEM_MC_NATIVE_ENDIF(); 5875 IEM_MC_ADVANCE_ RIP_AND_FINISH();5875 IEM_MC_ADVANCE_PC_AND_FINISH(); 5876 5876 IEM_MC_END(); 5877 5877 break; … … 5908 5908 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5909 5909 5910 IEM_MC_ADVANCE_ RIP_AND_FINISH();5910 IEM_MC_ADVANCE_PC_AND_FINISH(); 5911 5911 IEM_MC_END(); 5912 5912 } … … 5932 5932 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 5933 5933 \ 5934 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \5934 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 5935 5935 IEM_MC_END() 5936 5936 … … 5973 5973 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5974 5974 5975 IEM_MC_ADVANCE_ RIP_AND_FINISH();5975 IEM_MC_ADVANCE_PC_AND_FINISH(); 5976 5976 IEM_MC_END(); 5977 5977 break; … … 5988 5988 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 5989 5989 5990 IEM_MC_ADVANCE_ RIP_AND_FINISH();5990 IEM_MC_ADVANCE_PC_AND_FINISH(); 5991 5991 IEM_MC_END(); 5992 5992 break; … … 6003 6003 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uTmp2); 6004 6004 6005 IEM_MC_ADVANCE_ RIP_AND_FINISH();6005 IEM_MC_ADVANCE_PC_AND_FINISH(); 6006 6006 IEM_MC_END(); 6007 6007 break; … … 6035 6035 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6036 6036 \ 6037 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6037 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6038 6038 IEM_MC_END(); \ 6039 6039 break; \ … … 6055 6055 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6056 6056 \ 6057 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6057 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6058 6058 IEM_MC_END(); \ 6059 6059 break; \ … … 6075 6075 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), uTmpReg); \ 6076 6076 \ 6077 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \6077 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 6078 6078 IEM_MC_END(); \ 6079 6079 break; \ … … 6114 6114 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6115 6115 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_RM(pVCpu, bRm), u8Value); 6116 IEM_MC_ADVANCE_ RIP_AND_FINISH();6116 IEM_MC_ADVANCE_PC_AND_FINISH(); 6117 6117 IEM_MC_END(); 6118 6118 } … … 6129 6129 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6130 6130 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Value); 6131 IEM_MC_ADVANCE_ RIP_AND_FINISH();6131 IEM_MC_ADVANCE_PC_AND_FINISH(); 6132 6132 IEM_MC_END(); 6133 6133 } … … 6157 6157 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6158 6158 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, bRm), u16Value); 6159 IEM_MC_ADVANCE_ RIP_AND_FINISH();6159 IEM_MC_ADVANCE_PC_AND_FINISH(); 6160 6160 IEM_MC_END(); 6161 6161 break; … … 6167 6167 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6168 6168 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Value); 6169 IEM_MC_ADVANCE_ RIP_AND_FINISH();6169 IEM_MC_ADVANCE_PC_AND_FINISH(); 6170 6170 IEM_MC_END(); 6171 6171 break; … … 6177 6177 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6178 6178 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Value); 6179 IEM_MC_ADVANCE_ RIP_AND_FINISH();6179 IEM_MC_ADVANCE_PC_AND_FINISH(); 6180 6180 IEM_MC_END(); 6181 6181 break; … … 6199 6199 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6200 6200 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value); 6201 IEM_MC_ADVANCE_ RIP_AND_FINISH();6201 IEM_MC_ADVANCE_PC_AND_FINISH(); 6202 6202 IEM_MC_END(); 6203 6203 break; … … 6211 6211 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6212 6212 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Value); 6213 IEM_MC_ADVANCE_ RIP_AND_FINISH();6213 IEM_MC_ADVANCE_PC_AND_FINISH(); 6214 6214 IEM_MC_END(); 6215 6215 break; … … 6223 6223 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_REG(pVCpu, bRm)); 6224 6224 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Value); 6225 IEM_MC_ADVANCE_ RIP_AND_FINISH();6225 IEM_MC_ADVANCE_PC_AND_FINISH(); 6226 6226 IEM_MC_END(); 6227 6227 break; … … 6252 6252 IEM_MC_FETCH_GREG_U8(u8Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6253 6253 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), u8Value); 6254 IEM_MC_ADVANCE_ RIP_AND_FINISH();6254 IEM_MC_ADVANCE_PC_AND_FINISH(); 6255 6255 IEM_MC_END(); 6256 6256 } … … 6267 6267 IEM_MC_FETCH_MEM_U8(u8Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6268 6268 IEM_MC_STORE_GREG_U8(IEM_GET_MODRM_REG(pVCpu, bRm), u8Value); 6269 IEM_MC_ADVANCE_ RIP_AND_FINISH();6269 IEM_MC_ADVANCE_PC_AND_FINISH(); 6270 6270 IEM_MC_END(); 6271 6271 } … … 6295 6295 IEM_MC_FETCH_GREG_U16(u16Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6296 6296 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 6297 IEM_MC_ADVANCE_ RIP_AND_FINISH();6297 IEM_MC_ADVANCE_PC_AND_FINISH(); 6298 6298 IEM_MC_END(); 6299 6299 break; … … 6305 6305 IEM_MC_FETCH_GREG_U32(u32Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6306 6306 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 6307 IEM_MC_ADVANCE_ RIP_AND_FINISH();6307 IEM_MC_ADVANCE_PC_AND_FINISH(); 6308 6308 IEM_MC_END(); 6309 6309 break; … … 6315 6315 IEM_MC_FETCH_GREG_U64(u64Value, IEM_GET_MODRM_RM(pVCpu, bRm)); 6316 6316 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 6317 IEM_MC_ADVANCE_ RIP_AND_FINISH();6317 IEM_MC_ADVANCE_PC_AND_FINISH(); 6318 6318 IEM_MC_END(); 6319 6319 break; … … 6337 6337 IEM_MC_FETCH_MEM_U16(u16Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6338 6338 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Value); 6339 IEM_MC_ADVANCE_ RIP_AND_FINISH();6339 IEM_MC_ADVANCE_PC_AND_FINISH(); 6340 6340 IEM_MC_END(); 6341 6341 break; … … 6349 6349 IEM_MC_FETCH_MEM_U32(u32Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6350 6350 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Value); 6351 IEM_MC_ADVANCE_ RIP_AND_FINISH();6351 IEM_MC_ADVANCE_PC_AND_FINISH(); 6352 6352 IEM_MC_END(); 6353 6353 break; … … 6361 6361 IEM_MC_FETCH_MEM_U64(u64Value, pVCpu->iem.s.iEffSeg, GCPtrEffDst); 6362 6362 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), u64Value); 6363 IEM_MC_ADVANCE_ RIP_AND_FINISH();6363 IEM_MC_ADVANCE_PC_AND_FINISH(); 6364 6364 IEM_MC_END(); 6365 6365 break; … … 6416 6416 IEM_MC_FETCH_SREG_U16(u16Value, iSegReg); 6417 6417 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_RM(pVCpu, bRm), u16Value); 6418 IEM_MC_ADVANCE_ RIP_AND_FINISH();6418 IEM_MC_ADVANCE_PC_AND_FINISH(); 6419 6419 IEM_MC_END(); 6420 6420 break; … … 6426 6426 IEM_MC_FETCH_SREG_ZX_U32(u32Value, iSegReg); 6427 6427 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_RM(pVCpu, bRm), u32Value); 6428 IEM_MC_ADVANCE_ RIP_AND_FINISH();6428 IEM_MC_ADVANCE_PC_AND_FINISH(); 6429 6429 IEM_MC_END(); 6430 6430 break; … … 6436 6436 IEM_MC_FETCH_SREG_ZX_U64(u64Value, iSegReg); 6437 6437 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm), u64Value); 6438 IEM_MC_ADVANCE_ RIP_AND_FINISH();6438 IEM_MC_ADVANCE_PC_AND_FINISH(); 6439 6439 IEM_MC_END(); 6440 6440 break; … … 6459 6459 IEM_MC_FETCH_SREG_U16(u16Value, iSegReg); 6460 6460 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Value); 6461 IEM_MC_ADVANCE_ RIP_AND_FINISH();6461 IEM_MC_ADVANCE_PC_AND_FINISH(); 6462 6462 IEM_MC_END(); 6463 6463 } … … 6490 6490 IEM_MC_ASSIGN_TO_SMALLER(u16Cast, GCPtrEffSrc); 6491 6491 IEM_MC_STORE_GREG_U16(IEM_GET_MODRM_REG(pVCpu, bRm), u16Cast); 6492 IEM_MC_ADVANCE_ RIP_AND_FINISH();6492 IEM_MC_ADVANCE_PC_AND_FINISH(); 6493 6493 IEM_MC_END(); 6494 6494 break; … … 6505 6505 IEM_MC_ASSIGN_TO_SMALLER(u32Cast, GCPtrEffSrc); 6506 6506 IEM_MC_STORE_GREG_U32(IEM_GET_MODRM_REG(pVCpu, bRm), u32Cast); 6507 IEM_MC_ADVANCE_ RIP_AND_FINISH();6507 IEM_MC_ADVANCE_PC_AND_FINISH(); 6508 6508 IEM_MC_END(); 6509 6509 break; … … 6515 6515 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 6516 6516 IEM_MC_STORE_GREG_U64(IEM_GET_MODRM_REG(pVCpu, bRm), GCPtrEffSrc); 6517 IEM_MC_ADVANCE_ RIP_AND_FINISH();6517 IEM_MC_ADVANCE_PC_AND_FINISH(); 6518 6518 IEM_MC_END(); 6519 6519 break; … … 6855 6855 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp1); 6856 6856 IEM_MC_STORE_GREG_U16(iReg, u16Tmp2); 6857 IEM_MC_ADVANCE_ RIP_AND_FINISH();6857 IEM_MC_ADVANCE_PC_AND_FINISH(); 6858 6858 IEM_MC_END(); 6859 6859 break; … … 6868 6868 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp1); 6869 6869 IEM_MC_STORE_GREG_U32(iReg, u32Tmp2); 6870 IEM_MC_ADVANCE_ RIP_AND_FINISH();6870 IEM_MC_ADVANCE_PC_AND_FINISH(); 6871 6871 IEM_MC_END(); 6872 6872 break; … … 6881 6881 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp1); 6882 6882 IEM_MC_STORE_GREG_U64(iReg, u64Tmp2); 6883 IEM_MC_ADVANCE_ RIP_AND_FINISH();6883 IEM_MC_ADVANCE_PC_AND_FINISH(); 6884 6884 IEM_MC_END(); 6885 6885 break; … … 6923 6923 IEM_MC_BEGIN(0, 0); 6924 6924 IEMOP_HLP_DONE_DECODING(); 6925 IEM_MC_ADVANCE_ RIP_AND_FINISH();6925 IEM_MC_ADVANCE_PC_AND_FINISH(); 6926 6926 IEM_MC_END(); 6927 6927 } … … 7014 7014 IEM_MC_AND_GREG_U16(X86_GREG_xAX, UINT16_C(0x00ff)); 7015 7015 } IEM_MC_ENDIF(); 7016 IEM_MC_ADVANCE_ RIP_AND_FINISH();7016 IEM_MC_ADVANCE_PC_AND_FINISH(); 7017 7017 IEM_MC_END(); 7018 7018 break; … … 7027 7027 IEM_MC_AND_GREG_U32(X86_GREG_xAX, UINT32_C(0x0000ffff)); 7028 7028 } IEM_MC_ENDIF(); 7029 IEM_MC_ADVANCE_ RIP_AND_FINISH();7029 IEM_MC_ADVANCE_PC_AND_FINISH(); 7030 7030 IEM_MC_END(); 7031 7031 break; … … 7040 7040 IEM_MC_AND_GREG_U64(X86_GREG_xAX, UINT64_C(0x00000000ffffffff)); 7041 7041 } IEM_MC_ENDIF(); 7042 IEM_MC_ADVANCE_ RIP_AND_FINISH();7042 IEM_MC_ADVANCE_PC_AND_FINISH(); 7043 7043 IEM_MC_END(); 7044 7044 break; … … 7065 7065 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xDX, 0); 7066 7066 } IEM_MC_ENDIF(); 7067 IEM_MC_ADVANCE_ RIP_AND_FINISH();7067 IEM_MC_ADVANCE_PC_AND_FINISH(); 7068 7068 IEM_MC_END(); 7069 7069 break; … … 7078 7078 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xDX, 0); 7079 7079 } IEM_MC_ENDIF(); 7080 IEM_MC_ADVANCE_ RIP_AND_FINISH();7080 IEM_MC_ADVANCE_PC_AND_FINISH(); 7081 7081 IEM_MC_END(); 7082 7082 break; … … 7091 7091 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xDX, 0); 7092 7092 } IEM_MC_ENDIF(); 7093 IEM_MC_ADVANCE_ RIP_AND_FINISH();7093 IEM_MC_ADVANCE_PC_AND_FINISH(); 7094 7094 IEM_MC_END(); 7095 7095 break; … … 7131 7131 IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE(); 7132 7132 IEM_MC_MAYBE_RAISE_FPU_XCPT(); 7133 IEM_MC_ADVANCE_ RIP_AND_FINISH();7133 IEM_MC_ADVANCE_PC_AND_FINISH(); 7134 7134 IEM_MC_END(); 7135 7135 } … … 7184 7184 IEM_MC_OR_2LOCS_U32(EFlags, u32Flags); 7185 7185 IEM_MC_COMMIT_EFLAGS(EFlags); 7186 IEM_MC_ADVANCE_ RIP_AND_FINISH();7186 IEM_MC_ADVANCE_PC_AND_FINISH(); 7187 7187 IEM_MC_END(); 7188 7188 } … … 7204 7204 IEM_MC_FETCH_EFLAGS_U8(u8Flags); 7205 7205 IEM_MC_STORE_GREG_U8(X86_GREG_xSP/*=AH*/, u8Flags); 7206 IEM_MC_ADVANCE_ RIP_AND_FINISH();7206 IEM_MC_ADVANCE_PC_AND_FINISH(); 7207 7207 IEM_MC_END(); 7208 7208 } … … 7254 7254 IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7255 7255 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 7256 IEM_MC_ADVANCE_ RIP_AND_FINISH();7256 IEM_MC_ADVANCE_PC_AND_FINISH(); 7257 7257 IEM_MC_END(); 7258 7258 } … … 7283 7283 IEM_MC_FETCH_MEM_U16(u16Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7284 7284 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp); 7285 IEM_MC_ADVANCE_ RIP_AND_FINISH();7285 IEM_MC_ADVANCE_PC_AND_FINISH(); 7286 7286 IEM_MC_END(); 7287 7287 break; … … 7294 7294 IEM_MC_FETCH_MEM_U32(u32Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7295 7295 IEM_MC_STORE_GREG_U32(X86_GREG_xAX, u32Tmp); 7296 IEM_MC_ADVANCE_ RIP_AND_FINISH();7296 IEM_MC_ADVANCE_PC_AND_FINISH(); 7297 7297 IEM_MC_END(); 7298 7298 break; … … 7305 7305 IEM_MC_FETCH_MEM_U64(u64Tmp, pVCpu->iem.s.iEffSeg, GCPtrMemOff); 7306 7306 IEM_MC_STORE_GREG_U64(X86_GREG_xAX, u64Tmp); 7307 IEM_MC_ADVANCE_ RIP_AND_FINISH();7307 IEM_MC_ADVANCE_PC_AND_FINISH(); 7308 7308 IEM_MC_END(); 7309 7309 break; … … 7335 7335 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7336 7336 IEM_MC_STORE_MEM_U8(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u8Tmp); 7337 IEM_MC_ADVANCE_ RIP_AND_FINISH();7337 IEM_MC_ADVANCE_PC_AND_FINISH(); 7338 7338 IEM_MC_END(); 7339 7339 } … … 7364 7364 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7365 7365 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u16Tmp); 7366 IEM_MC_ADVANCE_ RIP_AND_FINISH();7366 IEM_MC_ADVANCE_PC_AND_FINISH(); 7367 7367 IEM_MC_END(); 7368 7368 break; … … 7375 7375 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7376 7376 IEM_MC_STORE_MEM_U32(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u32Tmp); 7377 IEM_MC_ADVANCE_ RIP_AND_FINISH();7377 IEM_MC_ADVANCE_PC_AND_FINISH(); 7378 7378 IEM_MC_END(); 7379 7379 break; … … 7386 7386 IEM_MC_LOCAL_CONST(RTGCPTR, GCPtrMemOff, GCPtrMemOffDecode); 7387 7387 IEM_MC_STORE_MEM_U64(pVCpu->iem.s.iEffSeg, GCPtrMemOff, u64Tmp); 7388 IEM_MC_ADVANCE_ RIP_AND_FINISH();7388 IEM_MC_ADVANCE_PC_AND_FINISH(); 7389 7389 IEM_MC_END(); 7390 7390 break; … … 7411 7411 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 7412 7412 } IEM_MC_ENDIF(); \ 7413 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7413 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7414 7414 IEM_MC_END() \ 7415 7415 … … 7619 7619 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 7620 7620 } IEM_MC_ENDIF(); \ 7621 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7621 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7622 7622 IEM_MC_END() \ 7623 7623 … … 7942 7942 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 7943 7943 } IEM_MC_ENDIF(); \ 7944 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \7944 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 7945 7945 IEM_MC_END() \ 7946 7946 … … 8123 8123 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xSI, ValBits / 8); \ 8124 8124 } IEM_MC_ENDIF(); \ 8125 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8125 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8126 8126 IEM_MC_END() \ 8127 8127 … … 8324 8324 IEM_MC_ADD_GREG_U##AddrBits(X86_GREG_xDI, ValBits / 8); \ 8325 8325 } IEM_MC_ENDIF(); \ 8326 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8326 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8327 8327 IEM_MC_END(); 8328 8328 … … 8594 8594 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8595 8595 IEM_MC_STORE_GREG_U8_CONST(iFixedReg, u8Imm); 8596 IEM_MC_ADVANCE_ RIP_AND_FINISH();8596 IEM_MC_ADVANCE_PC_AND_FINISH(); 8597 8597 IEM_MC_END(); 8598 8598 } … … 8691 8691 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8692 8692 IEM_MC_STORE_GREG_U16_CONST(iFixedReg, u16Imm); 8693 IEM_MC_ADVANCE_ RIP_AND_FINISH();8693 IEM_MC_ADVANCE_PC_AND_FINISH(); 8694 8694 IEM_MC_END(); 8695 8695 break; … … 8700 8700 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8701 8701 IEM_MC_STORE_GREG_U32_CONST(iFixedReg, u32Imm); 8702 IEM_MC_ADVANCE_ RIP_AND_FINISH();8702 IEM_MC_ADVANCE_PC_AND_FINISH(); 8703 8703 IEM_MC_END(); 8704 8704 break; … … 8709 8709 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 8710 8710 IEM_MC_STORE_GREG_U64_CONST(iFixedReg, u64Imm); 8711 IEM_MC_ADVANCE_ RIP_AND_FINISH();8711 IEM_MC_ADVANCE_PC_AND_FINISH(); 8712 8712 IEM_MC_END(); 8713 8713 break; … … 8821 8821 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 8822 8822 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8823 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8823 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8824 8824 IEM_MC_END(); \ 8825 8825 } \ … … 8844 8844 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 8845 8845 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8846 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8846 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8847 8847 IEM_MC_END(); \ 8848 8848 } (void)0 … … 8969 8969 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, cShiftArg); \ 8970 8970 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8971 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8971 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8972 8972 IEM_MC_END(); \ 8973 8973 break; \ … … 8983 8983 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 8984 8984 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8985 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8985 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8986 8986 IEM_MC_END(); \ 8987 8987 break; \ … … 8996 8996 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, cShiftArg); \ 8997 8997 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 8998 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \8998 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 8999 8999 IEM_MC_END(); \ 9000 9000 break; \ … … 9026 9026 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9027 9027 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9028 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9028 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9029 9029 IEM_MC_END(); \ 9030 9030 break; \ … … 9048 9048 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9049 9049 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9050 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9050 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9051 9051 IEM_MC_END(); \ 9052 9052 break; \ … … 9070 9070 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9071 9071 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9072 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9072 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9073 9073 IEM_MC_END(); \ 9074 9074 break; \ … … 9378 9378 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9379 9379 IEM_MC_STORE_GREG_U8_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u8Imm); 9380 IEM_MC_ADVANCE_ RIP_AND_FINISH();9380 IEM_MC_ADVANCE_PC_AND_FINISH(); 9381 9381 IEM_MC_END(); 9382 9382 } … … 9390 9390 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9391 9391 IEM_MC_STORE_MEM_U8_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u8Imm); 9392 IEM_MC_ADVANCE_ RIP_AND_FINISH();9392 IEM_MC_ADVANCE_PC_AND_FINISH(); 9393 9393 IEM_MC_END(); 9394 9394 } … … 9416 9416 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9417 9417 IEM_MC_STORE_GREG_U16_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u16Imm); 9418 IEM_MC_ADVANCE_ RIP_AND_FINISH();9418 IEM_MC_ADVANCE_PC_AND_FINISH(); 9419 9419 IEM_MC_END(); 9420 9420 break; … … 9425 9425 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9426 9426 IEM_MC_STORE_GREG_U32_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u32Imm); 9427 IEM_MC_ADVANCE_ RIP_AND_FINISH();9427 IEM_MC_ADVANCE_PC_AND_FINISH(); 9428 9428 IEM_MC_END(); 9429 9429 break; … … 9434 9434 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9435 9435 IEM_MC_STORE_GREG_U64_CONST(IEM_GET_MODRM_RM(pVCpu, bRm), u64Imm); 9436 IEM_MC_ADVANCE_ RIP_AND_FINISH();9436 IEM_MC_ADVANCE_PC_AND_FINISH(); 9437 9437 IEM_MC_END(); 9438 9438 break; … … 9453 9453 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9454 9454 IEM_MC_STORE_MEM_U16_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Imm); 9455 IEM_MC_ADVANCE_ RIP_AND_FINISH();9455 IEM_MC_ADVANCE_PC_AND_FINISH(); 9456 9456 IEM_MC_END(); 9457 9457 break; … … 9464 9464 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9465 9465 IEM_MC_STORE_MEM_U32_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u32Imm); 9466 IEM_MC_ADVANCE_ RIP_AND_FINISH();9466 IEM_MC_ADVANCE_PC_AND_FINISH(); 9467 9467 IEM_MC_END(); 9468 9468 break; … … 9475 9475 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 9476 9476 IEM_MC_STORE_MEM_U64_CONST(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u64Imm); 9477 IEM_MC_ADVANCE_ RIP_AND_FINISH();9477 IEM_MC_ADVANCE_PC_AND_FINISH(); 9478 9478 IEM_MC_END(); 9479 9479 break; … … 9680 9680 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 9681 9681 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9682 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9682 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9683 9683 IEM_MC_END(); \ 9684 9684 } \ … … 9701 9701 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9702 9702 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9703 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9703 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9704 9704 IEM_MC_END(); \ 9705 9705 } (void)0 … … 9817 9817 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU16, fEFlagsIn, pu16Dst, cShiftArg); \ 9818 9818 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9819 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9819 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9820 9820 IEM_MC_END(); \ 9821 9821 break; \ … … 9831 9831 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 9832 9832 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9833 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9833 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9834 9834 IEM_MC_END(); \ 9835 9835 break; \ … … 9844 9844 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU64, fEFlagsIn, pu64Dst, cShiftArg); \ 9845 9845 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9846 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9846 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9847 9847 IEM_MC_END(); \ 9848 9848 break; \ … … 9872 9872 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9873 9873 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9874 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9874 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9875 9875 IEM_MC_END(); \ 9876 9876 break; \ … … 9892 9892 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9893 9893 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9894 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9894 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9895 9895 IEM_MC_END(); \ 9896 9896 break; \ … … 9912 9912 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 9913 9913 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 9914 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \9914 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 9915 9915 IEM_MC_END(); \ 9916 9916 break; \ … … 10049 10049 IEM_MC_CALL_AIMPL_3(uint32_t, fEFlagsRet, pImpl->pfnNormalU8, fEFlagsIn, pu8Dst, cShiftArg); \ 10050 10050 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10051 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10051 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10052 10052 IEM_MC_END(); \ 10053 10053 } \ … … 10072 10072 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10073 10073 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10074 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10074 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10075 10075 IEM_MC_END(); \ 10076 10076 } (void)0 … … 10200 10200 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10201 10201 } IEM_MC_NATIVE_ENDIF(); \ 10202 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10202 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10203 10203 IEM_MC_END(); \ 10204 10204 break; \ … … 10226 10226 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10227 10227 } IEM_MC_NATIVE_ENDIF(); \ 10228 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10228 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10229 10229 IEM_MC_END(); \ 10230 10230 break; \ … … 10251 10251 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10252 10252 } IEM_MC_NATIVE_ENDIF(); \ 10253 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10253 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10254 10254 IEM_MC_END(); \ 10255 10255 break; \ … … 10280 10280 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10281 10281 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10282 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10282 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10283 10283 IEM_MC_END(); \ 10284 10284 break; \ … … 10301 10301 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10302 10302 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10303 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10303 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10304 10304 IEM_MC_END(); \ 10305 10305 break; \ … … 10322 10322 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 10323 10323 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 10324 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \10324 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 10325 10325 IEM_MC_END(); \ 10326 10326 break; \ … … 10486 10486 IEM_MC_STORE_GREG_U8_CONST(X86_GREG_xAX, 0x00); 10487 10487 } IEM_MC_ENDIF(); 10488 IEM_MC_ADVANCE_ RIP_AND_FINISH();10488 IEM_MC_ADVANCE_PC_AND_FINISH(); 10489 10489 IEM_MC_END(); 10490 10490 } … … 10508 10508 IEM_MC_FETCH_MEM16_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u16Addr); 10509 10509 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10510 IEM_MC_ADVANCE_ RIP_AND_FINISH();10510 IEM_MC_ADVANCE_PC_AND_FINISH(); 10511 10511 IEM_MC_END(); 10512 10512 break; … … 10521 10521 IEM_MC_FETCH_MEM32_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u32Addr); 10522 10522 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10523 IEM_MC_ADVANCE_ RIP_AND_FINISH();10523 IEM_MC_ADVANCE_PC_AND_FINISH(); 10524 10524 IEM_MC_END(); 10525 10525 break; … … 10534 10534 IEM_MC_FETCH_MEM_U8(u8Tmp, pVCpu->iem.s.iEffSeg, u64Addr); 10535 10535 IEM_MC_STORE_GREG_U8(X86_GREG_xAX, u8Tmp); 10536 IEM_MC_ADVANCE_ RIP_AND_FINISH();10536 IEM_MC_ADVANCE_PC_AND_FINISH(); 10537 10537 IEM_MC_END(); 10538 10538 break; … … 10568 10568 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 10569 10569 } IEM_MC_ENDIF(); 10570 IEM_MC_ADVANCE_ RIP_AND_FINISH();10570 IEM_MC_ADVANCE_PC_AND_FINISH(); 10571 10571 10572 10572 IEM_MC_END(); … … 10599 10599 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 10600 10600 } IEM_MC_ENDIF(); 10601 IEM_MC_ADVANCE_ RIP_AND_FINISH();10601 IEM_MC_ADVANCE_PC_AND_FINISH(); 10602 10602 10603 10603 IEM_MC_END(); … … 10630 10630 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 10631 10631 } IEM_MC_ENDIF(); 10632 IEM_MC_ADVANCE_ RIP_AND_FINISH();10632 IEM_MC_ADVANCE_PC_AND_FINISH(); 10633 10633 10634 10634 IEM_MC_END(); … … 10731 10731 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 10732 10732 } IEM_MC_ENDIF(); 10733 IEM_MC_ADVANCE_ RIP_AND_FINISH();10733 IEM_MC_ADVANCE_PC_AND_FINISH(); 10734 10734 10735 10735 IEM_MC_END(); … … 10780 10780 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10781 10781 } IEM_MC_ENDIF(); 10782 IEM_MC_ADVANCE_ RIP_AND_FINISH();10782 IEM_MC_ADVANCE_PC_AND_FINISH(); 10783 10783 10784 10784 IEM_MC_END(); … … 10813 10813 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10814 10814 } IEM_MC_ENDIF(); 10815 IEM_MC_ADVANCE_ RIP_AND_FINISH();10815 IEM_MC_ADVANCE_PC_AND_FINISH(); 10816 10816 10817 10817 IEM_MC_END(); … … 10918 10918 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 10919 10919 } IEM_MC_ENDIF(); 10920 IEM_MC_ADVANCE_ RIP_AND_FINISH();10920 IEM_MC_ADVANCE_PC_AND_FINISH(); 10921 10921 10922 10922 IEM_MC_END(); … … 10957 10957 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 10958 10958 } IEM_MC_ENDIF(); 10959 IEM_MC_ADVANCE_ RIP_AND_FINISH();10959 IEM_MC_ADVANCE_PC_AND_FINISH(); 10960 10960 10961 10961 IEM_MC_END(); … … 10996 10996 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 10997 10997 } IEM_MC_ENDIF(); 10998 IEM_MC_ADVANCE_ RIP_AND_FINISH();10998 IEM_MC_ADVANCE_PC_AND_FINISH(); 10999 10999 11000 11000 IEM_MC_END(); … … 11076 11076 IEM_MC_FETCH_FCW(u16Fcw); 11077 11077 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Fcw); 11078 IEM_MC_ADVANCE_ RIP_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */11078 IEM_MC_ADVANCE_PC_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */ 11079 11079 IEM_MC_END(); 11080 11080 } … … 11093 11093 * intel optimizations. Investigate. */ 11094 11094 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 11095 IEM_MC_ADVANCE_ RIP_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */11095 IEM_MC_ADVANCE_PC_AND_FINISH(); /* C0-C3 are documented as undefined, we leave them unmodified. */ 11096 11096 IEM_MC_END(); 11097 11097 } … … 11119 11119 } IEM_MC_ENDIF(); 11120 11120 11121 IEM_MC_ADVANCE_ RIP_AND_FINISH();11121 IEM_MC_ADVANCE_PC_AND_FINISH(); 11122 11122 IEM_MC_END(); 11123 11123 } … … 11149 11149 } IEM_MC_ENDIF(); 11150 11150 11151 IEM_MC_ADVANCE_ RIP_AND_FINISH();11151 IEM_MC_ADVANCE_PC_AND_FINISH(); 11152 11152 IEM_MC_END(); 11153 11153 } … … 11176 11176 } IEM_MC_ENDIF(); 11177 11177 11178 IEM_MC_ADVANCE_ RIP_AND_FINISH();11178 IEM_MC_ADVANCE_PC_AND_FINISH(); 11179 11179 IEM_MC_END(); 11180 11180 } … … 11196 11196 } IEM_MC_ENDIF(); 11197 11197 11198 IEM_MC_ADVANCE_ RIP_AND_FINISH();11198 IEM_MC_ADVANCE_PC_AND_FINISH(); 11199 11199 IEM_MC_END(); 11200 11200 } … … 11225 11225 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11226 11226 } IEM_MC_ENDIF(); 11227 IEM_MC_ADVANCE_ RIP_AND_FINISH();11227 IEM_MC_ADVANCE_PC_AND_FINISH(); 11228 11228 11229 11229 IEM_MC_END(); … … 11266 11266 IEM_MC_FPU_STACK_UNDERFLOW(UINT8_MAX, pVCpu->iem.s.uFpuOpcode); 11267 11267 } IEM_MC_ENDIF(); 11268 IEM_MC_ADVANCE_ RIP_AND_FINISH();11268 IEM_MC_ADVANCE_PC_AND_FINISH(); 11269 11269 11270 11270 IEM_MC_END(); … … 11288 11288 IEM_MC_CALL_FPU_AIMPL_2(iemAImpl_fxam_r80, pu16Fsw, pr80Value); 11289 11289 IEM_MC_UPDATE_FSW(u16Fsw, pVCpu->iem.s.uFpuOpcode); 11290 IEM_MC_ADVANCE_ RIP_AND_FINISH();11290 IEM_MC_ADVANCE_PC_AND_FINISH(); 11291 11291 11292 11292 IEM_MC_END(); … … 11315 11315 IEM_MC_FPU_STACK_PUSH_OVERFLOW(pVCpu->iem.s.uFpuOpcode); 11316 11316 } IEM_MC_ENDIF(); 11317 IEM_MC_ADVANCE_ RIP_AND_FINISH();11317 IEM_MC_ADVANCE_PC_AND_FINISH(); 11318 11318 11319 11319 IEM_MC_END(); … … 11416 11416 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP(IEM_GET_MODRM_RM_8(bRm), pVCpu->iem.s.uFpuOpcode); 11417 11417 } IEM_MC_ENDIF(); 11418 IEM_MC_ADVANCE_ RIP_AND_FINISH();11418 IEM_MC_ADVANCE_PC_AND_FINISH(); 11419 11419 11420 11420 IEM_MC_END(); … … 11453 11453 IEM_MC_FPU_STACK_PUSH_UNDERFLOW_TWO(pVCpu->iem.s.uFpuOpcode); 11454 11454 } IEM_MC_ENDIF(); 11455 IEM_MC_ADVANCE_ RIP_AND_FINISH();11455 IEM_MC_ADVANCE_PC_AND_FINISH(); 11456 11456 11457 11457 IEM_MC_END(); … … 11508 11508 IEM_MC_UPDATE_FSW_CONST(0, pVCpu->iem.s.uFpuOpcode); 11509 11509 11510 IEM_MC_ADVANCE_ RIP_AND_FINISH();11510 IEM_MC_ADVANCE_PC_AND_FINISH(); 11511 11511 IEM_MC_END(); 11512 11512 } … … 11530 11530 IEM_MC_UPDATE_FSW_CONST(0, pVCpu->iem.s.uFpuOpcode); 11531 11531 11532 IEM_MC_ADVANCE_ RIP_AND_FINISH();11532 IEM_MC_ADVANCE_PC_AND_FINISH(); 11533 11533 IEM_MC_END(); 11534 11534 } … … 11703 11703 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11704 11704 } IEM_MC_ENDIF(); 11705 IEM_MC_ADVANCE_ RIP_AND_FINISH();11705 IEM_MC_ADVANCE_PC_AND_FINISH(); 11706 11706 11707 11707 IEM_MC_END(); … … 11729 11729 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11730 11730 } IEM_MC_ENDIF(); 11731 IEM_MC_ADVANCE_ RIP_AND_FINISH();11731 IEM_MC_ADVANCE_PC_AND_FINISH(); 11732 11732 11733 11733 IEM_MC_END(); … … 11755 11755 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11756 11756 } IEM_MC_ENDIF(); 11757 IEM_MC_ADVANCE_ RIP_AND_FINISH();11757 IEM_MC_ADVANCE_PC_AND_FINISH(); 11758 11758 11759 11759 IEM_MC_END(); … … 11781 11781 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11782 11782 } IEM_MC_ENDIF(); 11783 IEM_MC_ADVANCE_ RIP_AND_FINISH();11783 IEM_MC_ADVANCE_PC_AND_FINISH(); 11784 11784 11785 11785 IEM_MC_END(); … … 11812 11812 IEM_MC_FPU_STACK_UNDERFLOW_THEN_POP_POP(pVCpu->iem.s.uFpuOpcode); 11813 11813 } IEM_MC_ENDIF(); 11814 IEM_MC_ADVANCE_ RIP_AND_FINISH();11814 IEM_MC_ADVANCE_PC_AND_FINISH(); 11815 11815 11816 11816 IEM_MC_END(); … … 11857 11857 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 11858 11858 } IEM_MC_ENDIF(); 11859 IEM_MC_ADVANCE_ RIP_AND_FINISH();11859 IEM_MC_ADVANCE_PC_AND_FINISH(); 11860 11860 11861 11861 IEM_MC_END(); … … 11906 11906 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 11907 11907 } IEM_MC_ENDIF(); 11908 IEM_MC_ADVANCE_ RIP_AND_FINISH();11908 IEM_MC_ADVANCE_PC_AND_FINISH(); 11909 11909 11910 11910 IEM_MC_END(); … … 11939 11939 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 11940 11940 } IEM_MC_ENDIF(); 11941 IEM_MC_ADVANCE_ RIP_AND_FINISH();11941 IEM_MC_ADVANCE_PC_AND_FINISH(); 11942 11942 11943 11943 IEM_MC_END(); … … 12046 12046 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12047 12047 } IEM_MC_ENDIF(); 12048 IEM_MC_ADVANCE_ RIP_AND_FINISH();12048 IEM_MC_ADVANCE_PC_AND_FINISH(); 12049 12049 12050 12050 IEM_MC_END(); … … 12085 12085 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12086 12086 } IEM_MC_ENDIF(); 12087 IEM_MC_ADVANCE_ RIP_AND_FINISH();12087 IEM_MC_ADVANCE_PC_AND_FINISH(); 12088 12088 12089 12089 IEM_MC_END(); … … 12124 12124 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12125 12125 } IEM_MC_ENDIF(); 12126 IEM_MC_ADVANCE_ RIP_AND_FINISH();12126 IEM_MC_ADVANCE_PC_AND_FINISH(); 12127 12127 12128 12128 IEM_MC_END(); … … 12163 12163 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12164 12164 } IEM_MC_ENDIF(); 12165 IEM_MC_ADVANCE_ RIP_AND_FINISH();12165 IEM_MC_ADVANCE_PC_AND_FINISH(); 12166 12166 12167 12167 IEM_MC_END(); … … 12195 12195 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12196 12196 } IEM_MC_ENDIF(); 12197 IEM_MC_ADVANCE_ RIP_AND_FINISH();12197 IEM_MC_ADVANCE_PC_AND_FINISH(); 12198 12198 12199 12199 IEM_MC_END(); … … 12234 12234 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12235 12235 } IEM_MC_ENDIF(); 12236 IEM_MC_ADVANCE_ RIP_AND_FINISH();12236 IEM_MC_ADVANCE_PC_AND_FINISH(); 12237 12237 12238 12238 IEM_MC_END(); … … 12260 12260 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12261 12261 } IEM_MC_ENDIF(); 12262 IEM_MC_ADVANCE_ RIP_AND_FINISH();12262 IEM_MC_ADVANCE_PC_AND_FINISH(); 12263 12263 12264 12264 IEM_MC_END(); … … 12286 12286 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12287 12287 } IEM_MC_ENDIF(); 12288 IEM_MC_ADVANCE_ RIP_AND_FINISH();12288 IEM_MC_ADVANCE_PC_AND_FINISH(); 12289 12289 12290 12290 IEM_MC_END(); … … 12312 12312 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12313 12313 } IEM_MC_ENDIF(); 12314 IEM_MC_ADVANCE_ RIP_AND_FINISH();12314 IEM_MC_ADVANCE_PC_AND_FINISH(); 12315 12315 12316 12316 IEM_MC_END(); … … 12338 12338 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 12339 12339 } IEM_MC_ENDIF(); 12340 IEM_MC_ADVANCE_ RIP_AND_FINISH();12340 IEM_MC_ADVANCE_PC_AND_FINISH(); 12341 12341 12342 12342 IEM_MC_END(); … … 12351 12351 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12352 12352 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12353 IEM_MC_ADVANCE_ RIP_AND_FINISH();12353 IEM_MC_ADVANCE_PC_AND_FINISH(); 12354 12354 IEM_MC_END(); 12355 12355 } … … 12363 12363 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12364 12364 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12365 IEM_MC_ADVANCE_ RIP_AND_FINISH();12365 IEM_MC_ADVANCE_PC_AND_FINISH(); 12366 12366 IEM_MC_END(); 12367 12367 } … … 12377 12377 IEM_MC_ACTUALIZE_FPU_STATE_FOR_CHANGE(); 12378 12378 IEM_MC_CLEAR_FSW_EX(); 12379 IEM_MC_ADVANCE_ RIP_AND_FINISH();12379 IEM_MC_ADVANCE_PC_AND_FINISH(); 12380 12380 IEM_MC_END(); 12381 12381 } … … 12399 12399 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12400 12400 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12401 IEM_MC_ADVANCE_ RIP_AND_FINISH();12401 IEM_MC_ADVANCE_PC_AND_FINISH(); 12402 12402 IEM_MC_END(); 12403 12403 } … … 12412 12412 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12413 12413 IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE(); 12414 IEM_MC_ADVANCE_ RIP_AND_FINISH();12414 IEM_MC_ADVANCE_PC_AND_FINISH(); 12415 12415 IEM_MC_END(); 12416 12416 return VINF_SUCCESS; … … 12520 12520 IEM_MC_FPU_STACK_UNDERFLOW(IEM_GET_MODRM_RM_8(bRm), pVCpu->iem.s.uFpuOpcode); 12521 12521 } IEM_MC_ENDIF(); 12522 IEM_MC_ADVANCE_ RIP_AND_FINISH();12522 IEM_MC_ADVANCE_PC_AND_FINISH(); 12523 12523 12524 12524 IEM_MC_END(); … … 12604 12604 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(0, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12605 12605 } IEM_MC_ENDIF(); 12606 IEM_MC_ADVANCE_ RIP_AND_FINISH();12606 IEM_MC_ADVANCE_PC_AND_FINISH(); 12607 12607 12608 12608 IEM_MC_END(); … … 12653 12653 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12654 12654 } IEM_MC_ENDIF(); 12655 IEM_MC_ADVANCE_ RIP_AND_FINISH();12655 IEM_MC_ADVANCE_PC_AND_FINISH(); 12656 12656 12657 12657 IEM_MC_END(); … … 12686 12686 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12687 12687 } IEM_MC_ENDIF(); 12688 IEM_MC_ADVANCE_ RIP_AND_FINISH();12688 IEM_MC_ADVANCE_PC_AND_FINISH(); 12689 12689 12690 12690 IEM_MC_END(); … … 12790 12790 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 12791 12791 } IEM_MC_ENDIF(); 12792 IEM_MC_ADVANCE_ RIP_AND_FINISH();12792 IEM_MC_ADVANCE_PC_AND_FINISH(); 12793 12793 12794 12794 IEM_MC_END(); … … 12829 12829 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12830 12830 } IEM_MC_ENDIF(); 12831 IEM_MC_ADVANCE_ RIP_AND_FINISH();12831 IEM_MC_ADVANCE_PC_AND_FINISH(); 12832 12832 12833 12833 IEM_MC_END(); … … 12868 12868 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12869 12869 } IEM_MC_ENDIF(); 12870 IEM_MC_ADVANCE_ RIP_AND_FINISH();12870 IEM_MC_ADVANCE_PC_AND_FINISH(); 12871 12871 12872 12872 IEM_MC_END(); … … 12909 12909 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 12910 12910 } IEM_MC_ENDIF(); 12911 IEM_MC_ADVANCE_ RIP_AND_FINISH();12911 IEM_MC_ADVANCE_PC_AND_FINISH(); 12912 12912 12913 12913 IEM_MC_END(); … … 12970 12970 IEM_MC_FETCH_FSW(u16Tmp); 12971 12971 IEM_MC_STORE_MEM_U16(pVCpu->iem.s.iEffSeg, GCPtrEffDst, u16Tmp); 12972 IEM_MC_ADVANCE_ RIP_AND_FINISH();12972 IEM_MC_ADVANCE_PC_AND_FINISH(); 12973 12973 12974 12974 /** @todo Debug / drop a hint to the verifier that things may differ … … 12995 12995 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 12996 12996 12997 IEM_MC_ADVANCE_ RIP_AND_FINISH();12997 IEM_MC_ADVANCE_PC_AND_FINISH(); 12998 12998 IEM_MC_END(); 12999 12999 } … … 13019 13019 } IEM_MC_ENDIF(); 13020 13020 13021 IEM_MC_ADVANCE_ RIP_AND_FINISH();13021 IEM_MC_ADVANCE_PC_AND_FINISH(); 13022 13022 IEM_MC_END(); 13023 13023 } … … 13167 13167 IEM_MC_FPU_STACK_UNDERFLOW(0, pVCpu->iem.s.uFpuOpcode); 13168 13168 } IEM_MC_ENDIF(); 13169 IEM_MC_ADVANCE_ RIP_AND_FINISH();13169 IEM_MC_ADVANCE_PC_AND_FINISH(); 13170 13170 13171 13171 IEM_MC_END(); … … 13216 13216 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13217 13217 } IEM_MC_ENDIF(); 13218 IEM_MC_ADVANCE_ RIP_AND_FINISH();13218 IEM_MC_ADVANCE_PC_AND_FINISH(); 13219 13219 13220 13220 IEM_MC_END(); … … 13249 13249 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13250 13250 } IEM_MC_ENDIF(); 13251 IEM_MC_ADVANCE_ RIP_AND_FINISH();13251 IEM_MC_ADVANCE_PC_AND_FINISH(); 13252 13252 13253 13253 IEM_MC_END(); … … 13345 13345 IEM_MC_UPDATE_FPU_OPCODE_IP(pVCpu->iem.s.uFpuOpcode); 13346 13346 13347 IEM_MC_ADVANCE_ RIP_AND_FINISH();13347 IEM_MC_ADVANCE_PC_AND_FINISH(); 13348 13348 IEM_MC_END(); 13349 13349 } … … 13361 13361 IEM_MC_FETCH_FSW(u16Tmp); 13362 13362 IEM_MC_STORE_GREG_U16(X86_GREG_xAX, u16Tmp); 13363 IEM_MC_ADVANCE_ RIP_AND_FINISH();13363 IEM_MC_ADVANCE_PC_AND_FINISH(); 13364 13364 IEM_MC_END(); 13365 13365 } … … 13412 13412 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13413 13413 } IEM_MC_ENDIF(); 13414 IEM_MC_ADVANCE_ RIP_AND_FINISH();13414 IEM_MC_ADVANCE_PC_AND_FINISH(); 13415 13415 13416 13416 IEM_MC_END(); … … 13451 13451 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13452 13452 } IEM_MC_ENDIF(); 13453 IEM_MC_ADVANCE_ RIP_AND_FINISH();13453 IEM_MC_ADVANCE_PC_AND_FINISH(); 13454 13454 13455 13455 IEM_MC_END(); … … 13490 13490 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13491 13491 } IEM_MC_ENDIF(); 13492 IEM_MC_ADVANCE_ RIP_AND_FINISH();13492 IEM_MC_ADVANCE_PC_AND_FINISH(); 13493 13493 13494 13494 IEM_MC_END(); … … 13529 13529 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13530 13530 } IEM_MC_ENDIF(); 13531 IEM_MC_ADVANCE_ RIP_AND_FINISH();13531 IEM_MC_ADVANCE_PC_AND_FINISH(); 13532 13532 13533 13533 IEM_MC_END(); … … 13561 13561 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13562 13562 } IEM_MC_ENDIF(); 13563 IEM_MC_ADVANCE_ RIP_AND_FINISH();13563 IEM_MC_ADVANCE_PC_AND_FINISH(); 13564 13564 13565 13565 IEM_MC_END(); … … 13593 13593 IEM_MC_FPU_STACK_PUSH_OVERFLOW_MEM_OP(pVCpu->iem.s.iEffSeg, GCPtrEffSrc, pVCpu->iem.s.uFpuOpcode); 13594 13594 } IEM_MC_ENDIF(); 13595 IEM_MC_ADVANCE_ RIP_AND_FINISH();13595 IEM_MC_ADVANCE_PC_AND_FINISH(); 13596 13596 13597 13597 IEM_MC_END(); … … 13632 13632 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13633 13633 } IEM_MC_ENDIF(); 13634 IEM_MC_ADVANCE_ RIP_AND_FINISH();13634 IEM_MC_ADVANCE_PC_AND_FINISH(); 13635 13635 13636 13636 IEM_MC_END(); … … 13671 13671 IEM_MC_FPU_STACK_UNDERFLOW_MEM_OP_THEN_POP(UINT8_MAX, pVCpu->iem.s.iEffSeg, GCPtrEffDst, pVCpu->iem.s.uFpuOpcode); 13672 13672 } IEM_MC_ENDIF(); 13673 IEM_MC_ADVANCE_ RIP_AND_FINISH();13673 IEM_MC_ADVANCE_PC_AND_FINISH(); 13674 13674 13675 13675 IEM_MC_END(); … … 13739 13739 } IEM_MC_ELSE() { 13740 13740 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 13741 IEM_MC_ADVANCE_ RIP_AND_FINISH();13741 IEM_MC_ADVANCE_PC_AND_FINISH(); 13742 13742 } IEM_MC_ENDIF(); 13743 13743 IEM_MC_END(); … … 13752 13752 } IEM_MC_ELSE() { 13753 13753 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 13754 IEM_MC_ADVANCE_ RIP_AND_FINISH();13754 IEM_MC_ADVANCE_PC_AND_FINISH(); 13755 13755 } IEM_MC_ENDIF(); 13756 13756 IEM_MC_END(); … … 13765 13765 } IEM_MC_ELSE() { 13766 13766 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 13767 IEM_MC_ADVANCE_ RIP_AND_FINISH();13767 IEM_MC_ADVANCE_PC_AND_FINISH(); 13768 13768 } IEM_MC_ENDIF(); 13769 13769 IEM_MC_END(); … … 13795 13795 } IEM_MC_ELSE() { 13796 13796 IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1); 13797 IEM_MC_ADVANCE_ RIP_AND_FINISH();13797 IEM_MC_ADVANCE_PC_AND_FINISH(); 13798 13798 } IEM_MC_ENDIF(); 13799 13799 IEM_MC_END(); … … 13808 13808 } IEM_MC_ELSE() { 13809 13809 IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1); 13810 IEM_MC_ADVANCE_ RIP_AND_FINISH();13810 IEM_MC_ADVANCE_PC_AND_FINISH(); 13811 13811 } IEM_MC_ENDIF(); 13812 13812 IEM_MC_END(); … … 13821 13821 } IEM_MC_ELSE() { 13822 13822 IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1); 13823 IEM_MC_ADVANCE_ RIP_AND_FINISH();13823 IEM_MC_ADVANCE_PC_AND_FINISH(); 13824 13824 } IEM_MC_ENDIF(); 13825 13825 IEM_MC_END(); … … 13856 13856 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13857 13857 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 13858 IEM_MC_ADVANCE_ RIP_AND_FINISH();13858 IEM_MC_ADVANCE_PC_AND_FINISH(); 13859 13859 IEM_MC_END(); 13860 13860 break; … … 13864 13864 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13865 13865 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 13866 IEM_MC_ADVANCE_ RIP_AND_FINISH();13866 IEM_MC_ADVANCE_PC_AND_FINISH(); 13867 13867 IEM_MC_END(); 13868 13868 break; … … 13872 13872 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13873 13873 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 13874 IEM_MC_ADVANCE_ RIP_AND_FINISH();13874 IEM_MC_ADVANCE_PC_AND_FINISH(); 13875 13875 IEM_MC_END(); 13876 13876 break; … … 13890 13890 } IEM_MC_ELSE() { 13891 13891 IEM_MC_STORE_GREG_U16_CONST(X86_GREG_xCX, 0); 13892 IEM_MC_ADVANCE_ RIP_AND_FINISH();13892 IEM_MC_ADVANCE_PC_AND_FINISH(); 13893 13893 } IEM_MC_ENDIF(); 13894 13894 IEM_MC_END(); … … 13903 13903 } IEM_MC_ELSE() { 13904 13904 IEM_MC_STORE_GREG_U32_CONST(X86_GREG_xCX, 0); 13905 IEM_MC_ADVANCE_ RIP_AND_FINISH();13905 IEM_MC_ADVANCE_PC_AND_FINISH(); 13906 13906 } IEM_MC_ENDIF(); 13907 13907 IEM_MC_END(); … … 13916 13916 } IEM_MC_ELSE() { 13917 13917 IEM_MC_STORE_GREG_U64_CONST(X86_GREG_xCX, 0); 13918 IEM_MC_ADVANCE_ RIP_AND_FINISH();13918 IEM_MC_ADVANCE_PC_AND_FINISH(); 13919 13919 } IEM_MC_ENDIF(); 13920 13920 IEM_MC_END(); … … 13941 13941 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13942 13942 IEM_MC_IF_CX_IS_NZ() { 13943 IEM_MC_ADVANCE_ RIP_AND_FINISH();13943 IEM_MC_ADVANCE_PC_AND_FINISH(); 13944 13944 } IEM_MC_ELSE() { 13945 13945 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 13952 13952 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13953 13953 IEM_MC_IF_ECX_IS_NZ() { 13954 IEM_MC_ADVANCE_ RIP_AND_FINISH();13954 IEM_MC_ADVANCE_PC_AND_FINISH(); 13955 13955 } IEM_MC_ELSE() { 13956 13956 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 13963 13963 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 13964 13964 IEM_MC_IF_RCX_IS_NZ() { 13965 IEM_MC_ADVANCE_ RIP_AND_FINISH();13965 IEM_MC_ADVANCE_PC_AND_FINISH(); 13966 13966 } IEM_MC_ELSE() { 13967 13967 IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm); … … 14292 14292 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14293 14293 IEM_MC_FLIP_EFL_BIT(X86_EFL_CF); 14294 IEM_MC_ADVANCE_ RIP_AND_FINISH();14294 IEM_MC_ADVANCE_PC_AND_FINISH(); 14295 14295 IEM_MC_END(); 14296 14296 } … … 14311 14311 IEM_MC_REF_EFLAGS(pEFlags); \ 14312 14312 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU8, pu8Dst, pEFlags); \ 14313 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14313 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14314 14314 IEM_MC_END(); \ 14315 14315 } \ … … 14332 14332 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14333 14333 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14334 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14334 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14335 14335 IEM_MC_END(); \ 14336 14336 } \ … … 14350 14350 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14351 14351 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14352 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14352 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14353 14353 IEM_MC_END(); \ 14354 14354 } \ … … 14376 14376 IEM_MC_REF_EFLAGS(pEFlags); \ 14377 14377 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 14378 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14378 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14379 14379 IEM_MC_END(); \ 14380 14380 break; \ … … 14389 14389 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 14390 14390 IEM_MC_CLEAR_HIGH_GREG_U64(IEM_GET_MODRM_RM(pVCpu, bRm)); \ 14391 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14391 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14392 14392 IEM_MC_END(); \ 14393 14393 break; \ … … 14401 14401 IEM_MC_REF_EFLAGS(pEFlags); \ 14402 14402 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU64, pu64Dst, pEFlags); \ 14403 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14403 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14404 14404 IEM_MC_END(); \ 14405 14405 break; \ … … 14431 14431 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14432 14432 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14433 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14433 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14434 14434 IEM_MC_END(); \ 14435 14435 break; \ … … 14449 14449 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14450 14450 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14451 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14451 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14452 14452 IEM_MC_END(); \ 14453 14453 break; \ … … 14467 14467 IEM_MC_MEM_COMMIT_AND_UNMAP_RW(bUnmapInfo); \ 14468 14468 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14469 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14469 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14470 14470 IEM_MC_END(); \ 14471 14471 break; \ … … 14495 14495 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14496 14496 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14497 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14497 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14498 14498 IEM_MC_END(); \ 14499 14499 break; \ … … 14513 14513 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14514 14514 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14515 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14515 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14516 14516 IEM_MC_END(); \ 14517 14517 break; \ … … 14531 14531 IEM_MC_MEM_COMMIT_AND_UNMAP_ATOMIC(bUnmapInfo); \ 14532 14532 IEM_MC_COMMIT_EFLAGS(EFlags); \ 14533 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14533 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14534 14534 IEM_MC_END(); \ 14535 14535 break; \ … … 14573 14573 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14574 14574 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14575 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14575 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14576 14576 IEM_MC_END(); \ 14577 14577 } \ … … 14593 14593 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14594 14594 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14595 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14595 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14596 14596 IEM_MC_END(); \ 14597 14597 } (void)0 … … 14620 14620 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14621 14621 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14622 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14622 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14623 14623 IEM_MC_END(); \ 14624 14624 break; \ … … 14640 14640 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xAX); \ 14641 14641 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xDX); \ 14642 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14642 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14643 14643 IEM_MC_END(); \ 14644 14644 break; \ … … 14658 14658 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14659 14659 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14660 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14660 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14661 14661 IEM_MC_END(); \ 14662 14662 break; \ … … 14687 14687 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14688 14688 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14689 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14689 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14690 14690 IEM_MC_END(); \ 14691 14691 break; \ … … 14710 14710 IEM_MC_CLEAR_HIGH_GREG_U64(X86_GREG_xDX); \ 14711 14711 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14712 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14712 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14713 14713 IEM_MC_END(); \ 14714 14714 break; \ … … 14731 14731 IEM_MC_RAISE_DIVIDE_ERROR_IF_LOCAL_IS_ZERO(fEFlagsRet); \ 14732 14732 IEM_MC_COMMIT_EFLAGS(fEFlagsRet); \ 14733 IEM_MC_ADVANCE_ RIP_AND_FINISH(); \14733 IEM_MC_ADVANCE_PC_AND_FINISH(); \ 14734 14734 IEM_MC_END(); \ 14735 14735 break; \ … … 14962 14962 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14963 14963 IEM_MC_CLEAR_EFL_BIT(X86_EFL_CF); 14964 IEM_MC_ADVANCE_ RIP_AND_FINISH();14964 IEM_MC_ADVANCE_PC_AND_FINISH(); 14965 14965 IEM_MC_END(); 14966 14966 } … … 14978 14978 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 14979 14979 IEM_MC_SET_EFL_BIT(X86_EFL_CF); 14980 IEM_MC_ADVANCE_ RIP_AND_FINISH();14980 IEM_MC_ADVANCE_PC_AND_FINISH(); 14981 14981 IEM_MC_END(); 14982 14982 } … … 15021 15021 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 15022 15022 IEM_MC_CLEAR_EFL_BIT(X86_EFL_DF); 15023 IEM_MC_ADVANCE_ RIP_AND_FINISH();15023 IEM_MC_ADVANCE_PC_AND_FINISH(); 15024 15024 IEM_MC_END(); 15025 15025 } … … 15037 15037 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 15038 15038 IEM_MC_SET_EFL_BIT(X86_EFL_DF); 15039 IEM_MC_ADVANCE_ RIP_AND_FINISH();15039 IEM_MC_ADVANCE_PC_AND_FINISH(); 15040 15040 IEM_MC_END(); 15041 15041 } … … 15400 15400 IEM_MC_FETCH_MEM_U16(u16Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15401 15401 IEM_MC_PUSH_U16(u16Src); 15402 IEM_MC_ADVANCE_ RIP_AND_FINISH();15402 IEM_MC_ADVANCE_PC_AND_FINISH(); 15403 15403 IEM_MC_END(); 15404 15404 break; … … 15412 15412 IEM_MC_FETCH_MEM_U32(u32Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15413 15413 IEM_MC_PUSH_U32(u32Src); 15414 IEM_MC_ADVANCE_ RIP_AND_FINISH();15414 IEM_MC_ADVANCE_PC_AND_FINISH(); 15415 15415 IEM_MC_END(); 15416 15416 break; … … 15424 15424 IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 15425 15425 IEM_MC_PUSH_U64(u64Src); 15426 IEM_MC_ADVANCE_ RIP_AND_FINISH();15426 IEM_MC_ADVANCE_PC_AND_FINISH(); 15427 15427 IEM_MC_END(); 15428 15428 break;
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