Changeset 108413 in vbox for trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp
- Timestamp:
- Feb 28, 2025 9:12:06 AM (2 months ago)
- svn:sync-xref-src-repo-rev:
- 167783
- File:
-
- 1 edited
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- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp
r107933 r108413 228 228 static FN_HV_GIC_STATE_GET_DATA *g_pfnHvGicStateGetData = NULL; /* Since 15.0 */ 229 229 static FN_HV_GIC_SEND_MSI *g_pfnHvGicSendMsi = NULL; /* Since 15.0 */ 230 static FN_HV_GIC_SET_SPI *g_pfnHvGicSetSpi = NULL; /* Since 15.0*/230 FN_HV_GIC_SET_SPI *g_pfnHvGicSetSpi = NULL; /* Since 15.0, exported for GICR3Nem-darwin.cpp */ 231 231 static FN_HV_GIC_GET_DISTRIBUTOR_REG *g_pfnHvGicGetDistributorReg = NULL; /* Since 15.0 */ 232 232 static FN_HV_GIC_GET_MSI_REG *g_pfnHvGicGetMsiReg = NULL; /* Since 15.0 */ … … 1195 1195 1196 1196 1197 /**1198 * Sets the given SPI inside the in-kernel HvF GIC.1199 *1200 * @returns VBox status code.1201 * @param pVM The VM instance.1202 * @param uIntId The SPI ID to update.1203 * @param fAsserted Flag whether the interrupt is asserted (true) or not (false).1204 */1205 VMM_INT_DECL(int) NEMR3GicSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)1206 {1207 RT_NOREF(pVM);1208 Assert(hv_gic_set_spi);1209 1210 hv_return_t hrc = hv_gic_set_spi(uIntId + GIC_INTID_RANGE_SPI_START, fAsserted);1211 return nemR3DarwinHvSts2Rc(hrc);1212 }1213 1214 1215 /**1216 * Sets the given PPI inside the in-kernel HvF GIC.1217 *1218 * @returns VBox status code.1219 * @param pVCpu The vCPU for which the PPI state is to be updated.1220 * @param uIntId The PPI ID to update.1221 * @param fAsserted Flag whether the interrupt is asserted (true) or not (false).1222 */1223 VMM_INT_DECL(int) NEMR3GicSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)1224 {1225 RT_NOREF(pVCpu, uIntId, fAsserted);1226 1227 /* Should never be called as the PPIs are handled entirely in Hypervisor.framework/AppleHV. */1228 AssertFailed();1229 return VERR_NEM_IPE_9;1230 }1231 1232 1233 /**1234 * Writes a system ICC register inside the in-kernel HvF GIC.1235 *1236 * @returns VBox status code.1237 * @param pVCpu The cross context virtual CPU structure.1238 * @param u32Reg The ICC register.1239 * @param u64Value The value being set.1240 */1241 VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)1242 {1243 hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);1244 hv_return_t const hrc = hv_gic_set_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, u64Value);1245 return nemR3DarwinHvSts2Rc(hrc);1246 }1247 1248 1249 /**1250 * Reads a system ICC register inside the in-kernel HvF GIC.1251 *1252 * @returns VBox status code.1253 * @param pVCpu The cross context virtual CPU structure.1254 * @param u32Reg The ICC register.1255 * @param pu64Value Where to store value.1256 */1257 VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)1258 {1259 hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);1260 hv_return_t const hrc = hv_gic_get_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, pu64Value);1261 return nemR3DarwinHvSts2Rc(hrc);1262 }1263 1264 1265 1197 static int nemR3DarwinGicCreate(PVM pVM) 1266 1198 { … … 1301 1233 return nemR3DarwinHvSts2Rc(hrc); 1302 1234 1303 /* Make sure the device is not instantiated as Hypervisor.framework provides it. */1304 //CFGMR3RemoveNode(pGicDev);1305 1235 return rc; 1306 1236 }
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