VirtualBox

Changeset 108443 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Mar 4, 2025 8:15:22 PM (2 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
167817
Message:

VMM/GIC: bugref:10404 Fixes to the interrupt priority logic which fixes hang during arm64 Windows 11 guest boot.
Other minor cleanups.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/VBox/VMM/VMMR3/GICR3.cpp

    r108439 r108443  
    112112
    113113    pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
    114     pHlp->pfnPrintf(pHlp, "  fIrqGrp0Enabled    = %RTbool\n", pGicCpu->fIrqGrp0Enabled);
    115     pHlp->pfnPrintf(pHlp, "  fIrqGrp1Enabled    = %RTbool\n", pGicCpu->fIrqGrp1Enabled);
     114    pHlp->pfnPrintf(pHlp, "  fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
     115    pHlp->pfnPrintf(pHlp, "  fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
    116116    pHlp->pfnPrintf(pHlp, "  bInterruptPriority = %u\n",      pGicCpu->bInterruptPriority);
    117117    pHlp->pfnPrintf(pHlp, "  bBinaryPointGrp0   = %u\n",      pGicCpu->bBinaryPointGrp0);
     
    167167#endif
    168168
    169     pHlp->pfnPrintf(pHlp, "  fIrqGrp0Enabled    = %RTbool\n", pGicDev->fIrqGrp0Enabled);
    170     pHlp->pfnPrintf(pHlp, "  fIrqGrp1Enabled    = %RTbool\n", pGicDev->fIrqGrp1Enabled);
     169    pHlp->pfnPrintf(pHlp, "  fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
     170    pHlp->pfnPrintf(pHlp, "  fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
    171171}
    172172
     
    223223
    224224    pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
    225     pHlp->pfnPrintf(pHlp, "  fIrqGrp0Enabled    = %RTbool\n", pGicCpu->fIrqGrp0Enabled);
    226     pHlp->pfnPrintf(pHlp, "  fIrqGrp1Enabled    = %RTbool\n", pGicCpu->fIrqGrp1Enabled);
     225    pHlp->pfnPrintf(pHlp, "  fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
     226    pHlp->pfnPrintf(pHlp, "  fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
    227227    pHlp->pfnPrintf(pHlp, "  bInterruptPriority = %u\n",      pGicCpu->bInterruptPriority);
    228228    pHlp->pfnPrintf(pHlp, "  bBinaryPointGrp0   = %u\n",      pGicCpu->bBinaryPointGrp0);
     
    384384    pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSelSupport);
    385385#endif
    386     pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
    387     pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
     386    pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
     387    pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
    388388    pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
    389389    GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrGroup);
     
    417417        pHlp->pfnSSMPutU8(pSSM,              pGicCpu->bBinaryPointGrp0);
    418418        pHlp->pfnSSMPutU8(pSSM,              pGicCpu->bBinaryPointGrp1);
    419         pHlp->pfnSSMPutBool(pSSM,            pGicCpu->fIrqGrp0Enabled);
    420         pHlp->pfnSSMPutBool(pSSM,            pGicCpu->fIrqGrp1Enabled);
     419        pHlp->pfnSSMPutBool(pSSM,            pGicCpu->fIntrGroup0Enabled);
     420        pHlp->pfnSSMPutBool(pSSM,            pGicCpu->fIntrGroup1Enabled);
    421421    }
    422422
     
    531531    pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSelSupport);
    532532#endif
    533     pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIrqGrp0Enabled);
    534     pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIrqGrp1Enabled);
     533    pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
     534    pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
    535535    pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
    536536    GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrGroup);
     
    564564        pHlp->pfnSSMGetU8(pSSM,              &pGicCpu->bBinaryPointGrp0);
    565565        pHlp->pfnSSMGetU8(pSSM,              &pGicCpu->bBinaryPointGrp1);
    566         pHlp->pfnSSMGetBool(pSSM,            &pGicCpu->fIrqGrp0Enabled);
    567         pHlp->pfnSSMGetBool(pSSM,            &pGicCpu->fIrqGrp1Enabled);
     566        pHlp->pfnSSMGetBool(pSSM,            &pGicCpu->fIntrGroup0Enabled);
     567        pHlp->pfnSSMGetBool(pSSM,            &pGicCpu->fIntrGroup1Enabled);
    568568    }
    569569
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette