VirtualBox

Changeset 108589 in vbox


Ignore:
Timestamp:
Mar 18, 2025 10:08:56 AM (2 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
167996
Message:

VMM/IEM: ARM (target) mem & tlb stuff. jiraref:VBP-1598

Location:
trunk/src/VBox/VMM
Files:
6 edited
1 copied

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/Makefile.kmk

    r108434 r108589  
    560560 ifdef VBOX_WITH_IEM_TARGETING_ARM
    561561  VBoxVMMArm_SOURCES += \
    562         VMMAll/IEMAll.cpp
     562        VMMAll/IEMAll.cpp \
     563        VMMAll/IEMAllMem.cpp \
     564        VMMAll/IEMAllTlb.cpp
    563565 else
    564566  VBoxVMMArm_SOURCES += VMMAll/IEMAllStub.cpp

  • trunk/src/VBox/VMM/VMMAll/IEMAllMem.cpp

    r108331 r108589  
    5050#include "IEMInline.h"
    5151#ifdef VBOX_VMM_TARGET_X86
    52 # include "target-x86/IEMInline-x86.h" /* not really required. sigh. */
    5352# include "target-x86/IEMAllTlbInline-x86.h"
    5453#endif
    … …  
    340339        fDataBps         |= iemMemCheckDataBreakpoint(pVM, pVCpu, (GCPtrFirst + (cbMem - 1)) & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK,
    341340                                                      cbSecondPage, fAccess);
     341#ifdef VBOX_VMM_TARGET_X86
    342342        pVCpu->cpum.GstCtx.eflags.uBoth |= fDataBps & (CPUMCTX_DBG_HIT_DRX_MASK | CPUMCTX_DBG_DBGF_MASK);
    343343        if (fDataBps > 1)
    344344            LogEx(LOG_GROUP_IEM, ("iemMemBounceBufferMapCrossPage: Data breakpoint: fDataBps=%#x for %RGv LB %zx; fAccess=%#x cs:rip=%04x:%08RX64\n",
    345345                                  fDataBps, GCPtrFirst, cbMem, fAccess, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
     346#elif defined(VBOX_VMM_TARGET_ARMV8)
     347        AssertFailed(); RT_NOREF(fDataBps); /** @todo ARMv8/IEM: implement data breakpoints. */
     348#else
     349# error "port me"
     350#endif
    346351    }
    347352

  • trunk/src/VBox/VMM/VMMAll/IEMAllTlb.cpp

    r108247 r108589  
    4646#include <iprt/x86.h>
    4747
    48 //#include "IEMInline.h"
    4948#ifdef VBOX_VMM_TARGET_X86
    5049# include "target-x86/IEMAllTlbInline-x86.h"
     50#elif defined(VBOX_VMM_TARGET_ARMV8)
     51# include "target-armv8/IEMAllTlbInline-armv8.h"
    5152#endif
    5253

  • trunk/src/VBox/VMM/VMMAll/target-armv8/IEMAllTlbInline-armv8.h

    r108565 r108589  
    3636
    3737#if defined(IEM_WITH_CODE_TLB) || defined(IEM_WITH_DATA_TLB)
     38
     39#if 0 /** @todo ARMv8: TLB flushing is a lot more complex on arm! */
    3840
    3941/**
    … …  
    412414}
    413415
     416#endif /** @todo ARMv8: TLB flushing is a lot more complex on arm! */
     417
    414418template<bool const a_fDataTlb>
    415419DECLINLINE(void) iemTlbInvalidatePageWorker(PVMCPUCC pVCpu, IEMTLB *pTlb, RTGCPTR GCPtrTag, uintptr_t idxEven) RT_NOEXCEPT
    … …  
    435439    }
    436440
     441#if 0 /** @todo ARMv8: TLB flushing is a lot more complex on arm! */
    437442    /*
    438443     * If there are (or has been) large pages in the TLB, we must check if the
    … …  
    452457            iemTlbInvalidateLargePageWorker<a_fDataTlb, false>(pVCpu, pTlb, GCPtrTag, GCPtrInstrBufPcTag);
    453458    }
     459#endif
    454460}
    455461

  • trunk/src/VBox/VMM/VMMAll/target-x86/IEMInternal-x86.h

    r108368 r108589  
    30043004VBOXSTRICTRC    iemMemApplySegment(PVMCPUCC pVCpu, uint32_t fAccess, uint8_t iSegReg, size_t cbMem, PRTGCPTR pGCPtrMem) RT_NOEXCEPT;
    30053005VBOXSTRICTRC    iemMemMarkSelDescAccessed(PVMCPUCC pVCpu, uint16_t uSel) RT_NOEXCEPT;
    3006 VBOXSTRICTRC    iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess, PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
    30073006
    30083007void            iemOpcodeFlushLight(PVMCPUCC pVCpu, uint8_t cbInstr);

  • trunk/src/VBox/VMM/VMMR3/IEMR3.cpp

    r108369 r108589  
    12401240    if (fFlags & IEMR3INFOTLB_F_CHECK)
    12411241    {
     1242#ifdef VBOX_VMM_TARGET_X86
    12421243        uint32_t const fInvSlotG = (uint32_t)!(uSlot & 1) << X86_PTE_BIT_G;
     1244#endif
    12431245        PGMPTWALKFAST  WalkFast;
    12441246        int rc = PGMGstQueryPageFast(pVCpu, GCPtr, 0 /*fFlags - don't check or modify anything */, &WalkFast);
    … …  
    12481250            {
    12491251                case VERR_PAGE_TABLE_NOT_PRESENT:
     1252#ifdef VBOX_VMM_TARGET_X86
    12501253                    switch ((WalkFast.fFailed & PGM_WALKFAIL_LEVEL_MASK) >> PGM_WALKFAIL_LEVEL_SHIFT)
    12511254                    {
    … …  
    12581261                    }
    12591262                    break;
     1263#else
     1264                    RT_FALL_THRU(); /** @todo  */
     1265#endif
    12601266                default: RTStrPrintf(szTmp, sizeof(szTmp), " stale(rc=%d)", rc); break;
    12611267            }
    12621268        else if (WalkFast.GCPhys != pTlbe->GCPhys)
    12631269            RTStrPrintf(szTmp, sizeof(szTmp), " stale(GCPhys=%RGp)", WalkFast.GCPhys);
     1270#ifdef VBOX_VMM_TARGET_X86
    12641271        else if (   (~WalkFast.fEffective       & (X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D))
    12651272                 == (  (pTlbe->fFlagsAndPhysRev & (  IEMTLBE_F_PT_NO_WRITE | IEMTLBE_F_PT_NO_USER
    … …  
    12991306                        (~WalkFast.fEffective & X86_PTE_A)  == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED) ? ""
    13001307                        : WalkFast.fEffective & X86_PTE_A  ? " accessed-now" : " accessed-no-more");
     1308#elif defined(VBOX_VMM_TARGET_ARMV8)
     1309        else
     1310            RTStrPrintf(szTmp, sizeof(szTmp), " stale(todo)");
     1311#else
     1312# error "port me"
     1313#endif
    13011314    }
    13021315#else
    … …  
    13041317#endif
    13051318
     1319#ifdef VBOX_VMM_TARGET_X86
    13061320    pHlp->pfnPrintf(pHlp, IEMTLB_SLOT_FMT ": %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s%s%s%s/%s%s%s%s/%s %s%s\n",
    13071321                    uSlot,
    … …  
    13311345                    : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired",
    13321346                    pszValid);
     1347#elif defined(VBOX_VMM_TARGET_ARMV8)
     1348    static const char * const s_apszLimAndTopLevelX[] =
     1349    {   /*0bxyz: z=IEMTLBE_F_S2_NO_LIM_WRITE  y=IEMTLBE_F_S2_TL0  x=IEMTLBE_F_S2_TL1 */
     1350        /*0b000:*/ "Lw",
     1351        /*0b001:*/ "",
     1352        /*0b010:*/ "LwTL0",
     1353        /*0b011:*/ "!TL0!",
     1354        /*0b100:*/ "LwTL1",
     1355        /*0b101:*/ "!TL1!",
     1356        /*0b110:*/ "LwTL01", /* See MRO-TL01 */
     1357        /*0b111:*/ "!TL01!",
     1358    };
     1359    static const char * const s_apszSizes[] = { "L3", "L2", "L1", "L0" };
     1360    AssertCompile(((IEMTLBE_F_S2_NO_LIM_WRITE | IEMTLBE_F_S2_TL0 | IEMTLBE_F_S2_TL1) >> IEMTLBE_F_S2_NO_LIM_WRITE_SHIFT) == 7);
     1361    pHlp->pfnPrintf(pHlp, IEMTLB_SLOT_FMT
     1362                    ": %s %#018RX64 -> %RGp / %p / %#05x U%c%c%c%cP%c%c%c%c%c%c/%c%c%c/%s/%c%c%c%c/%c as:%x vm:%x/%s %s%s\n",
     1363                    uSlot,
     1364                    (pTlbe->uTag & IEMTLB_REVISION_MASK) == uTlbRevision ? "valid  "
     1365                    : (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0          ? "empty  "
     1366                                                                         : "expired",
     1367                    GCPtr, /* -> */
     1368                    pTlbe->GCPhys, /* / */ pTlbe->pbMappingR3,
     1369                    /* / */
     1370                    (uint32_t)(pTlbe->fFlagsAndPhysRev & ~(IEMTLBE_F_PHYS_REV | IEMTLBE_F_S1_ASID | IEMTLBE_F_S2_VMID)),
     1371                    /* */
     1372                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_U_NO_READ    ? '-' : 'r',
     1373                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_U_NO_WRITE   ? '-' : 'w',
     1374                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_U_NO_EXEC    ? '-' : 'x',
     1375                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_U_NO_GCS     ? '-' : 's',
     1376                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_P_NO_READ    ? '-' : 'r',
     1377                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_P_NO_WRITE   ? '-' : 'w',
     1378                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_P_NO_EXEC    ? '-' : 'x',
     1379                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_P_NO_GCS     ? '-' : 's',
     1380                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_NO_DIRTY     ? '-' : 'D',
     1381                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_EFF_AMEC         ? 'A' : '-',
     1382                    /* / */
     1383                    !(uSlot & 1)                                         ? '-' : 'G',
     1384                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_S1_NS            ? '-' : 'S',
     1385                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_S1_NSE           ? '-' : 'E',
     1386                    /* / */
     1387                    s_apszLimAndTopLevelX[(pTlbe->fFlagsAndPhysRev >> IEMTLBE_F_S2_NO_LIM_WRITE_SHIFT) & 7],
     1388                    /* / */
     1389                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ       ? '-'  : 'r',
     1390                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE      ? '-'  : 'w',
     1391                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED    ? 'u'  : '-',
     1392                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_CODE_PAGE     ? 'c'  : '-',
     1393                    /* / */
     1394                    pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3     ? 'N'  : 'M',
     1395                    /* */
     1396                    (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_S1_ASID) >> IEMTLBE_F_S1_ASID_SHIFT,
     1397                    /* */
     1398                    (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_S2_VMID) >> IEMTLBE_F_S2_VMID_SHIFT,
     1399                    s_apszSizes[(pTlbe->fFlagsAndPhysRev >> IEMTLBE_F_EFF_SIZE_SHIFT) & 3],
     1400                    /* */
     1401                    (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
     1402                    : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired",
     1403                    pszValid);
     1404#else
     1405# error "port me"
     1406#endif
    13331407}
    13341408

  • trunk/src/VBox/VMM/include/IEMInternal.h

    r108409 r108589  
    426426     *          19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
    427427     *          consumed by PCID and ASID (12 + 6 = 18).
     428     *          Update: Put the PCID + ASID in fFlagsAndPhysRev; that doesn't solve
     429     *          the 57-bit problem, though.
    428430     */
    429431    uint64_t                uTag;
    430432    /** Access flags and physical TLB revision.
    431433     *
     434     * @x86
     435     * @parblock
    432436     * - Bit  0 - page tables   - not executable (X86_PTE_PAE_NX).
    433437     * - Bit  1 - page tables   - not writable (complemented X86_PTE_RW).
    … …  
    437441     * - Bit  5 - page tables   - not accessed (complemented X86_PTE_A).
    438442     * - Bit  6 - page tables   - not dirty (complemented X86_PTE_D).
    439      * - Bit  7 - tlb entry     - pMappingR3 member not valid.
    440      * - Bits 63 thru 8 are used for the physical TLB revision number.
     443     * - Bit  7 - page tables   - large page.
     444     * - Bit  8 - tlb entry     - pMappingR3 member not valid.
     445     * - Bit  9 - phys          - Unassigned memory.
     446     * - Bit 10 - phys          - Code page.
     447     * - Bits 63:11 - phys      - Physical TLB revision number.
    441448     *
    442449     * We're using complemented bit meanings here because it makes it easy to check
    … …  
    447454     * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
    448455     * need to check any PTE flag.
     456     * @endparblock
     457     *
     458     * @arm
     459     * @parblock
     460     * - Bit  0 - stage 1+2       - not unprivileged read accessible.
     461     * - Bit  1 - stage 1+2       - not unprivileged write accessible.
     462     * - Bit  2 - stage 1+2       - not unprivileged execute accessible.
     463     * - Bit  3 - stage 1+2       - not unprivileged guarded control stack accessible.
     464     * - Bit  4 - stage 1+2       - not privileged readable accessible.
     465     * - Bit  5 - stage 1+2       - not privileged writable accessible.
     466     * - Bit  6 - stage 1+2       - not privileged executable accessible.
     467     * - Bit  7 - stage 1+2       - not privileged guarded control stack accessible.
     468     * - Bit  8 - stage 2         - no limited write access (?).
     469     * - Bit  9 - stage 2         - TopLevel0 (?)
     470     * - Bit 10 - stage 2         - TopLevel1 (?)
     471     * - Bit 11 - stage 1+2 leaf  - not dirty.
     472     * - Bit 12 - stage 1+2 leaf  - alternate MECID (AMEC).
     473     * - Bit 13 - pgm phys page   - not directly readable.
     474     * - Bit 14 - pgm phys/virt   - not directly writable.
     475     * - Bit 15 - tlb entry       - pMappingR3 member not valid.
     476     * - Bit 16 - phys            - Unassigned memory.
     477     * - Bit 17 - phys            - Code page.
     478     * - Bit 18 - stage 1 leaf    - NS (not-secure).
     479     * - Bit 19 - stage 1 leaf    - NSE (root).
     480     * - Bits 20:21 - stage 1+2   - Page size.
     481     * - Bits 37:22 - stage 1 reg - Address space ID (ASID).
     482     * - Bits 53:38 - stage 2 reg - Virtual Machine ID (VMID).
     483     * - Bits 63:54 - tlb entry   - physical TLB revision number.
     484     *
     485     * The ASIDs and VMIDs are kept with the physical TLB revision number, so
     486     * there is no extra overhead there.  How the NSE:NS stuff will be handled
     487     * is a question for later.
     488     *
     489     * The above is a preliminary sketch...
     490     * @endparblock
     491     *
     492     * @todo arm64: Not sure if we can combine the stage 1 and 2 AMEC bits,
     493     *       but hope so... Doubt we'll be needing this any time soon.
    449494     */
    450495    uint64_t                fFlagsAndPhysRev;
    … …  
    465510/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
    466511 * @{  */
    467 #define IEMTLBE_F_PT_NO_EXEC        RT_BIT_64(0)  /**< Page tables: Not executable. */
    468 #define IEMTLBE_F_PT_NO_WRITE       RT_BIT_64(1)  /**< Page tables: Not writable. */
    469 #define IEMTLBE_F_PT_NO_USER        RT_BIT_64(2)  /**< Page tables: Not user accessible (supervisor only). */
    470 #define IEMTLBE_F_PG_NO_WRITE       RT_BIT_64(3)  /**< Phys page:   Not writable (access handler, ROM, whatever). */
    471 #define IEMTLBE_F_PG_NO_READ        RT_BIT_64(4)  /**< Phys page:   Not readable (MMIO / access handler, ROM) */
    472 #define IEMTLBE_F_PT_NO_ACCESSED    RT_BIT_64(5)  /**< Phys tables: Not accessed (need to be marked accessed). */
    473 #define IEMTLBE_F_PT_NO_DIRTY       RT_BIT_64(6)  /**< Page tables: Not dirty (needs to be made dirty on write). */
    474 #define IEMTLBE_F_PT_LARGE_PAGE     RT_BIT_64(7)  /**< Page tables: Large 2 or 4 MiB page (for flushing). */
    475 #define IEMTLBE_F_NO_MAPPINGR3      RT_BIT_64(8)  /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
    476 #define IEMTLBE_F_PG_UNASSIGNED     RT_BIT_64(9)  /**< Phys page:   Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
    477 #define IEMTLBE_F_PG_CODE_PAGE      RT_BIT_64(10) /**< Phys page:   Code page. */
    478 #define IEMTLBE_F_PHYS_REV          UINT64_C(0xfffffffffffff800) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     512#if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
     513# define IEMTLBE_F_PT_NO_EXEC       RT_BIT_64(0)  /**< Page tables: Not executable. */
     514# define IEMTLBE_F_PT_NO_WRITE      RT_BIT_64(1)  /**< Page tables: Not writable. */
     515# define IEMTLBE_F_PT_NO_USER       RT_BIT_64(2)  /**< Page tables: Not user accessible (supervisor only). */
     516# define IEMTLBE_F_PG_NO_WRITE      RT_BIT_64(3)  /**< Phys page:   Not writable (access handler, ROM, whatever). */
     517# define IEMTLBE_F_PG_NO_READ       RT_BIT_64(4)  /**< Phys page:   Not readable (MMIO / access handler, ROM) */
     518# define IEMTLBE_F_PT_NO_ACCESSED   RT_BIT_64(5)  /**< Phys tables: Not accessed (need to be marked accessed). */
     519# define IEMTLBE_F_PT_NO_DIRTY      RT_BIT_64(6)  /**< Page tables: Not dirty (needs to be made dirty on write). */
     520# define IEMTLBE_F_PT_LARGE_PAGE    RT_BIT_64(7)  /**< Page tables: Large 2 or 4 MiB page (for flushing). */
     521# define IEMTLBE_F_NO_MAPPINGR3     RT_BIT_64(8)  /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
     522# define IEMTLBE_F_PG_UNASSIGNED    RT_BIT_64(9)  /**< Phys page:   Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
     523# define IEMTLBE_F_PG_CODE_PAGE     RT_BIT_64(10) /**< Phys page:   Code page. */
     524# define IEMTLBE_F_PHYS_REV         UINT64_C(0xfffffffffffff800) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     525#endif
     526#if defined(VBOX_VMM_TARGET_ARMV8) || defined(DOXYGEN_RUNNING)
     527# define IEMTLBE_F_EFF_U_NO_READ      RT_BIT_64(0)  /**< Stage 1+2: No unprivileged read access. */
     528# define IEMTLBE_F_EFF_U_NO_WRITE     RT_BIT_64(1)  /**< Stage 1+2: No unprivileged write access. */
     529# define IEMTLBE_F_EFF_U_NO_EXEC      RT_BIT_64(2)  /**< Stage 1+2: No unprivileged execute access. */
     530# define IEMTLBE_F_EFF_U_NO_GCS       RT_BIT_64(3)  /**< Stage 1+2: No unprivileged guard control stack access. */
     531# define IEMTLBE_F_EFF_P_NO_READ      RT_BIT_64(4)  /**< Stage 1+2: No privileged read access. */
     532# define IEMTLBE_F_EFF_P_NO_WRITE     RT_BIT_64(5)  /**< Stage 1+2: No privileged write access. */
     533# define IEMTLBE_F_EFF_P_NO_EXEC      RT_BIT_64(6)  /**< Stage 1+2: No privileged execute access. */
     534# define IEMTLBE_F_EFF_P_NO_GCS       RT_BIT_64(7)  /**< Stage 1+2: No privileged guard control stack access. */
     535# define IEMTLBE_F_S2_NO_LIM_WRITE    RT_BIT_64(8)  /**< Stage 2:   No limited write access. */
     536# define IEMTLBE_F_S2_NO_LIM_WRITE_SHIFT        8   /**< @see IEMTLBE_F_S2_NO_LIM_WRITE */
     537# define IEMTLBE_F_S2_TL0             RT_BIT_64(9)  /**< Stage 2:   TopLevel0. */
     538# define IEMTLBE_F_S2_TL1             RT_BIT_64(10) /**< Stage 2:   TopLevel1. */
     539# define IEMTLBE_F_EFF_NO_DIRTY       RT_BIT_64(11) /**< Stage 1+2: Not dirty. */
     540# define IEMTLBE_F_EFF_AMEC           RT_BIT_64(12) /**< Stage 1+2: Alternative MECID. */
     541# define IEMTLBE_F_PG_NO_READ         RT_BIT_64(13) /**< Phys page: Not readable (MMIO / access handler, ROM) */
     542# define IEMTLBE_F_PG_NO_WRITE        RT_BIT_64(14) /**< Phys page: Not writable (access handler, ROM, whatever). */
     543# define IEMTLBE_F_NO_MAPPINGR3       RT_BIT_64(15) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
     544# define IEMTLBE_F_PG_UNASSIGNED      RT_BIT_64(16) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
     545# define IEMTLBE_F_PG_CODE_PAGE       RT_BIT_64(17) /**< Phys page: Code page. */
     546# define IEMTLBE_F_S1_NS              RT_BIT_64(18) /**< Stage 1:   Non-secure bit. */
     547# define IEMTLBE_F_S1_NSE             RT_BIT_64(19) /**< Stage 1:   Non-secure extension/whatever bit. */
     548# define IEMTLBE_F_EFF_SIZE_MASK   UINT64(0x300000) /**< Stage 1+2: Page size. @todo may need separate bits for each stage since they may use different page sizes. Or perhaps a single bit suffices? */
     549# define IEMTLBE_F_EFF_SIZE_L3     UINT64(0x000000) /**< Stage 1+2: Smallest page size. */
     550# define IEMTLBE_F_EFF_SIZE_L2     UINT64(0x100000) /**< Stage 1+2: Level 2 block. */
     551# define IEMTLBE_F_EFF_SIZE_L1     UINT64(0x200000) /**< Stage 1+2: Level 1 block. */
     552# define IEMTLBE_F_EFF_SIZE_L0     UINT64(0x300000) /**< Stage 1+2: Level 0 block. */
     553# define IEMTLBE_F_EFF_SIZE_SHIFT             20    /**< @see IEMTLBE_F_EFF_SIZE_MASK */
     554# define IEMTLBE_F_S1_ASID (UINT64_C(0xffff) << 22) /**< Stage 1:   Address space ID (from stage 1 root register). */
     555# define IEMTLBE_F_S1_ASID_SHIFT                22  /**< @see IEMTLBE_F_S1_ASID */
     556# define IEMTLBE_F_S2_VMID (UINT64_C(0xffff) << 38) /**< Stage 2:   Virtual machine ID (from stage 2 root register). */
     557# define IEMTLBE_F_S2_VMID_SHIFT                38  /**< @see IEMTLBE_F_S2_VMID */
     558# ifndef DOXYGEN_RUNNING
     559#  define IEMTLBE_F_PHYS_REV        UINT64_C(0xffc0000000000000) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     560# endif
     561#endif
    479562/** @} */
    480 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE     == IEMTLBE_F_PG_NO_WRITE);
    481 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ      == IEMTLBE_F_PG_NO_READ);
    482 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
    483 AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED   == IEMTLBE_F_PG_UNASSIGNED);
    484 AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE    == IEMTLBE_F_PG_CODE_PAGE);
    485 AssertCompile(PGM_WALKINFO_BIG_PAGE           == IEMTLBE_F_PT_LARGE_PAGE);
    486563/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
    487564#define IEMTLBE_GCPHYS2PTR_MASK     (  PGMIEMGCPHYS2PTR_F_NO_WRITE \
    … …  
    491568                                     | PGMIEMGCPHYS2PTR_F_CODE_PAGE \
    492569                                     | IEMTLBE_F_PHYS_REV )
     570#if defined(VBOX_VMM_TARGET_X86) /// @todo || defined(VBOX_VMM_TARGET_ARMV8)
     571AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE     == IEMTLBE_F_PG_NO_WRITE);
     572AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ      == IEMTLBE_F_PG_NO_READ);
     573AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
     574AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED   == IEMTLBE_F_PG_UNASSIGNED);
     575AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE    == IEMTLBE_F_PG_CODE_PAGE);
     576# ifdef VBOX_VMM_TARGET_X86
     577AssertCompile(PGM_WALKINFO_BIG_PAGE           == IEMTLBE_F_PT_LARGE_PAGE);
     578# endif
     579#endif
    493580
    494581
    … …  
    676763/** IEMTLB::uTlbPhysRev increment.
    677764 * @sa IEMTLBE_F_PHYS_REV */
    678 #define IEMTLB_PHYS_REV_INCR    RT_BIT_64(11)
     765#if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
     766# define IEMTLB_PHYS_REV_INCR   RT_BIT_64(11)
     767#elif defined(VBOX_VMM_TARGET_ARMV8)
     768# define IEMTLB_PHYS_REV_INCR   RT_BIT_64(54)
     769#endif
     770#ifdef IEMTLBE_F_PHYS_REV
    679771AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
     772#endif
    680773
    681774/**
    … …  
    32493342void            iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
    32503343
     3344VBOXSTRICTRC    iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess,
     3345                                                  PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
     3346
    32513347void            iemTlbInvalidateAllPhysicalSlow(PVMCPUCC pVCpu) RT_NOEXCEPT;
    32523348/** @} */
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