VirtualBox

Ignore:
Timestamp:
Mar 18, 2025 10:08:56 AM (2 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
167996
Message:

VMM/IEM: ARM (target) mem & tlb stuff. jiraref:VBP-1598

File:
1 edited

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  • trunk/src/VBox/VMM/include/IEMInternal.h

    r108409 r108589  
    426426     *          19 bits left (64 - 57 + 12 = 19) and they'll almost entire be
    427427     *          consumed by PCID and ASID (12 + 6 = 18).
     428     *          Update: Put the PCID + ASID in fFlagsAndPhysRev; that doesn't solve
     429     *          the 57-bit problem, though.
    428430     */
    429431    uint64_t                uTag;
    430432    /** Access flags and physical TLB revision.
    431433     *
     434     * @x86
     435     * @parblock
    432436     * - Bit  0 - page tables   - not executable (X86_PTE_PAE_NX).
    433437     * - Bit  1 - page tables   - not writable (complemented X86_PTE_RW).
    … …  
    437441     * - Bit  5 - page tables   - not accessed (complemented X86_PTE_A).
    438442     * - Bit  6 - page tables   - not dirty (complemented X86_PTE_D).
    439      * - Bit  7 - tlb entry     - pMappingR3 member not valid.
    440      * - Bits 63 thru 8 are used for the physical TLB revision number.
     443     * - Bit  7 - page tables   - large page.
     444     * - Bit  8 - tlb entry     - pMappingR3 member not valid.
     445     * - Bit  9 - phys          - Unassigned memory.
     446     * - Bit 10 - phys          - Code page.
     447     * - Bits 63:11 - phys      - Physical TLB revision number.
    441448     *
    442449     * We're using complemented bit meanings here because it makes it easy to check
    … …  
    447454     * access would do "TEST fFlags, X86_PTE_US"; and a kernel mode read wouldn't
    448455     * need to check any PTE flag.
     456     * @endparblock
     457     *
     458     * @arm
     459     * @parblock
     460     * - Bit  0 - stage 1+2       - not unprivileged read accessible.
     461     * - Bit  1 - stage 1+2       - not unprivileged write accessible.
     462     * - Bit  2 - stage 1+2       - not unprivileged execute accessible.
     463     * - Bit  3 - stage 1+2       - not unprivileged guarded control stack accessible.
     464     * - Bit  4 - stage 1+2       - not privileged readable accessible.
     465     * - Bit  5 - stage 1+2       - not privileged writable accessible.
     466     * - Bit  6 - stage 1+2       - not privileged executable accessible.
     467     * - Bit  7 - stage 1+2       - not privileged guarded control stack accessible.
     468     * - Bit  8 - stage 2         - no limited write access (?).
     469     * - Bit  9 - stage 2         - TopLevel0 (?)
     470     * - Bit 10 - stage 2         - TopLevel1 (?)
     471     * - Bit 11 - stage 1+2 leaf  - not dirty.
     472     * - Bit 12 - stage 1+2 leaf  - alternate MECID (AMEC).
     473     * - Bit 13 - pgm phys page   - not directly readable.
     474     * - Bit 14 - pgm phys/virt   - not directly writable.
     475     * - Bit 15 - tlb entry       - pMappingR3 member not valid.
     476     * - Bit 16 - phys            - Unassigned memory.
     477     * - Bit 17 - phys            - Code page.
     478     * - Bit 18 - stage 1 leaf    - NS (not-secure).
     479     * - Bit 19 - stage 1 leaf    - NSE (root).
     480     * - Bits 20:21 - stage 1+2   - Page size.
     481     * - Bits 37:22 - stage 1 reg - Address space ID (ASID).
     482     * - Bits 53:38 - stage 2 reg - Virtual Machine ID (VMID).
     483     * - Bits 63:54 - tlb entry   - physical TLB revision number.
     484     *
     485     * The ASIDs and VMIDs are kept with the physical TLB revision number, so
     486     * there is no extra overhead there.  How the NSE:NS stuff will be handled
     487     * is a question for later.
     488     *
     489     * The above is a preliminary sketch...
     490     * @endparblock
     491     *
     492     * @todo arm64: Not sure if we can combine the stage 1 and 2 AMEC bits,
     493     *       but hope so... Doubt we'll be needing this any time soon.
    449494     */
    450495    uint64_t                fFlagsAndPhysRev;
    … …  
    465510/** @name IEMTLBE_F_XXX - TLB entry flags (IEMTLBENTRY::fFlagsAndPhysRev)
    466511 * @{  */
    467 #define IEMTLBE_F_PT_NO_EXEC        RT_BIT_64(0)  /**< Page tables: Not executable. */
    468 #define IEMTLBE_F_PT_NO_WRITE       RT_BIT_64(1)  /**< Page tables: Not writable. */
    469 #define IEMTLBE_F_PT_NO_USER        RT_BIT_64(2)  /**< Page tables: Not user accessible (supervisor only). */
    470 #define IEMTLBE_F_PG_NO_WRITE       RT_BIT_64(3)  /**< Phys page:   Not writable (access handler, ROM, whatever). */
    471 #define IEMTLBE_F_PG_NO_READ        RT_BIT_64(4)  /**< Phys page:   Not readable (MMIO / access handler, ROM) */
    472 #define IEMTLBE_F_PT_NO_ACCESSED    RT_BIT_64(5)  /**< Phys tables: Not accessed (need to be marked accessed). */
    473 #define IEMTLBE_F_PT_NO_DIRTY       RT_BIT_64(6)  /**< Page tables: Not dirty (needs to be made dirty on write). */
    474 #define IEMTLBE_F_PT_LARGE_PAGE     RT_BIT_64(7)  /**< Page tables: Large 2 or 4 MiB page (for flushing). */
    475 #define IEMTLBE_F_NO_MAPPINGR3      RT_BIT_64(8)  /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
    476 #define IEMTLBE_F_PG_UNASSIGNED     RT_BIT_64(9)  /**< Phys page:   Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
    477 #define IEMTLBE_F_PG_CODE_PAGE      RT_BIT_64(10) /**< Phys page:   Code page. */
    478 #define IEMTLBE_F_PHYS_REV          UINT64_C(0xfffffffffffff800) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     512#if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
     513# define IEMTLBE_F_PT_NO_EXEC       RT_BIT_64(0)  /**< Page tables: Not executable. */
     514# define IEMTLBE_F_PT_NO_WRITE      RT_BIT_64(1)  /**< Page tables: Not writable. */
     515# define IEMTLBE_F_PT_NO_USER       RT_BIT_64(2)  /**< Page tables: Not user accessible (supervisor only). */
     516# define IEMTLBE_F_PG_NO_WRITE      RT_BIT_64(3)  /**< Phys page:   Not writable (access handler, ROM, whatever). */
     517# define IEMTLBE_F_PG_NO_READ       RT_BIT_64(4)  /**< Phys page:   Not readable (MMIO / access handler, ROM) */
     518# define IEMTLBE_F_PT_NO_ACCESSED   RT_BIT_64(5)  /**< Phys tables: Not accessed (need to be marked accessed). */
     519# define IEMTLBE_F_PT_NO_DIRTY      RT_BIT_64(6)  /**< Page tables: Not dirty (needs to be made dirty on write). */
     520# define IEMTLBE_F_PT_LARGE_PAGE    RT_BIT_64(7)  /**< Page tables: Large 2 or 4 MiB page (for flushing). */
     521# define IEMTLBE_F_NO_MAPPINGR3     RT_BIT_64(8)  /**< TLB entry:   The IEMTLBENTRY::pMappingR3 member is invalid. */
     522# define IEMTLBE_F_PG_UNASSIGNED    RT_BIT_64(9)  /**< Phys page:   Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
     523# define IEMTLBE_F_PG_CODE_PAGE     RT_BIT_64(10) /**< Phys page:   Code page. */
     524# define IEMTLBE_F_PHYS_REV         UINT64_C(0xfffffffffffff800) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     525#endif
     526#if defined(VBOX_VMM_TARGET_ARMV8) || defined(DOXYGEN_RUNNING)
     527# define IEMTLBE_F_EFF_U_NO_READ      RT_BIT_64(0)  /**< Stage 1+2: No unprivileged read access. */
     528# define IEMTLBE_F_EFF_U_NO_WRITE     RT_BIT_64(1)  /**< Stage 1+2: No unprivileged write access. */
     529# define IEMTLBE_F_EFF_U_NO_EXEC      RT_BIT_64(2)  /**< Stage 1+2: No unprivileged execute access. */
     530# define IEMTLBE_F_EFF_U_NO_GCS       RT_BIT_64(3)  /**< Stage 1+2: No unprivileged guard control stack access. */
     531# define IEMTLBE_F_EFF_P_NO_READ      RT_BIT_64(4)  /**< Stage 1+2: No privileged read access. */
     532# define IEMTLBE_F_EFF_P_NO_WRITE     RT_BIT_64(5)  /**< Stage 1+2: No privileged write access. */
     533# define IEMTLBE_F_EFF_P_NO_EXEC      RT_BIT_64(6)  /**< Stage 1+2: No privileged execute access. */
     534# define IEMTLBE_F_EFF_P_NO_GCS       RT_BIT_64(7)  /**< Stage 1+2: No privileged guard control stack access. */
     535# define IEMTLBE_F_S2_NO_LIM_WRITE    RT_BIT_64(8)  /**< Stage 2:   No limited write access. */
     536# define IEMTLBE_F_S2_NO_LIM_WRITE_SHIFT        8   /**< @see IEMTLBE_F_S2_NO_LIM_WRITE */
     537# define IEMTLBE_F_S2_TL0             RT_BIT_64(9)  /**< Stage 2:   TopLevel0. */
     538# define IEMTLBE_F_S2_TL1             RT_BIT_64(10) /**< Stage 2:   TopLevel1. */
     539# define IEMTLBE_F_EFF_NO_DIRTY       RT_BIT_64(11) /**< Stage 1+2: Not dirty. */
     540# define IEMTLBE_F_EFF_AMEC           RT_BIT_64(12) /**< Stage 1+2: Alternative MECID. */
     541# define IEMTLBE_F_PG_NO_READ         RT_BIT_64(13) /**< Phys page: Not readable (MMIO / access handler, ROM) */
     542# define IEMTLBE_F_PG_NO_WRITE        RT_BIT_64(14) /**< Phys page: Not writable (access handler, ROM, whatever). */
     543# define IEMTLBE_F_NO_MAPPINGR3       RT_BIT_64(15) /**< TLB entry: The IEMTLBENTRY::pMappingR3 member is invalid. */
     544# define IEMTLBE_F_PG_UNASSIGNED      RT_BIT_64(16) /**< Phys page: Unassigned memory (not RAM, ROM, MMIO2 or MMIO). */
     545# define IEMTLBE_F_PG_CODE_PAGE       RT_BIT_64(17) /**< Phys page: Code page. */
     546# define IEMTLBE_F_S1_NS              RT_BIT_64(18) /**< Stage 1:   Non-secure bit. */
     547# define IEMTLBE_F_S1_NSE             RT_BIT_64(19) /**< Stage 1:   Non-secure extension/whatever bit. */
     548# define IEMTLBE_F_EFF_SIZE_MASK   UINT64(0x300000) /**< Stage 1+2: Page size. @todo may need separate bits for each stage since they may use different page sizes. Or perhaps a single bit suffices? */
     549# define IEMTLBE_F_EFF_SIZE_L3     UINT64(0x000000) /**< Stage 1+2: Smallest page size. */
     550# define IEMTLBE_F_EFF_SIZE_L2     UINT64(0x100000) /**< Stage 1+2: Level 2 block. */
     551# define IEMTLBE_F_EFF_SIZE_L1     UINT64(0x200000) /**< Stage 1+2: Level 1 block. */
     552# define IEMTLBE_F_EFF_SIZE_L0     UINT64(0x300000) /**< Stage 1+2: Level 0 block. */
     553# define IEMTLBE_F_EFF_SIZE_SHIFT             20    /**< @see IEMTLBE_F_EFF_SIZE_MASK */
     554# define IEMTLBE_F_S1_ASID (UINT64_C(0xffff) << 22) /**< Stage 1:   Address space ID (from stage 1 root register). */
     555# define IEMTLBE_F_S1_ASID_SHIFT                22  /**< @see IEMTLBE_F_S1_ASID */
     556# define IEMTLBE_F_S2_VMID (UINT64_C(0xffff) << 38) /**< Stage 2:   Virtual machine ID (from stage 2 root register). */
     557# define IEMTLBE_F_S2_VMID_SHIFT                38  /**< @see IEMTLBE_F_S2_VMID */
     558# ifndef DOXYGEN_RUNNING
     559#  define IEMTLBE_F_PHYS_REV        UINT64_C(0xffc0000000000000) /**< Physical revision mask. @sa IEMTLB_PHYS_REV_INCR */
     560# endif
     561#endif
    479562/** @} */
    480 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE     == IEMTLBE_F_PG_NO_WRITE);
    481 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ      == IEMTLBE_F_PG_NO_READ);
    482 AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
    483 AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED   == IEMTLBE_F_PG_UNASSIGNED);
    484 AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE    == IEMTLBE_F_PG_CODE_PAGE);
    485 AssertCompile(PGM_WALKINFO_BIG_PAGE           == IEMTLBE_F_PT_LARGE_PAGE);
    486563/** The bits set by PGMPhysIemGCPhys2PtrNoLock. */
    487564#define IEMTLBE_GCPHYS2PTR_MASK     (  PGMIEMGCPHYS2PTR_F_NO_WRITE \
    … …  
    491568                                     | PGMIEMGCPHYS2PTR_F_CODE_PAGE \
    492569                                     | IEMTLBE_F_PHYS_REV )
     570#if defined(VBOX_VMM_TARGET_X86) /// @todo || defined(VBOX_VMM_TARGET_ARMV8)
     571AssertCompile(PGMIEMGCPHYS2PTR_F_NO_WRITE     == IEMTLBE_F_PG_NO_WRITE);
     572AssertCompile(PGMIEMGCPHYS2PTR_F_NO_READ      == IEMTLBE_F_PG_NO_READ);
     573AssertCompile(PGMIEMGCPHYS2PTR_F_NO_MAPPINGR3 == IEMTLBE_F_NO_MAPPINGR3);
     574AssertCompile(PGMIEMGCPHYS2PTR_F_UNASSIGNED   == IEMTLBE_F_PG_UNASSIGNED);
     575AssertCompile(PGMIEMGCPHYS2PTR_F_CODE_PAGE    == IEMTLBE_F_PG_CODE_PAGE);
     576# ifdef VBOX_VMM_TARGET_X86
     577AssertCompile(PGM_WALKINFO_BIG_PAGE           == IEMTLBE_F_PT_LARGE_PAGE);
     578# endif
     579#endif
    493580
    494581
    … …  
    676763/** IEMTLB::uTlbPhysRev increment.
    677764 * @sa IEMTLBE_F_PHYS_REV */
    678 #define IEMTLB_PHYS_REV_INCR    RT_BIT_64(11)
     765#if defined(VBOX_VMM_TARGET_X86) || defined(DOXYGEN_RUNNING)
     766# define IEMTLB_PHYS_REV_INCR   RT_BIT_64(11)
     767#elif defined(VBOX_VMM_TARGET_ARMV8)
     768# define IEMTLB_PHYS_REV_INCR   RT_BIT_64(54)
     769#endif
     770#ifdef IEMTLBE_F_PHYS_REV
    679771AssertCompile(IEMTLBE_F_PHYS_REV == ~(IEMTLB_PHYS_REV_INCR - 1U));
     772#endif
    680773
    681774/**
    … …  
    32493342void            iemMemRollbackAndUnmapWoSafe(PVMCPUCC pVCpu, uint8_t bUnmapInfo) RT_NOEXCEPT;
    32503343
     3344VBOXSTRICTRC    iemMemPageTranslateAndCheckAccess(PVMCPUCC pVCpu, RTGCPTR GCPtrMem, uint32_t cbAccess, uint32_t fAccess,
     3345                                                  PRTGCPHYS pGCPhysMem) RT_NOEXCEPT;
     3346
    32513347void            iemTlbInvalidateAllPhysicalSlow(PVMCPUCC pVCpu) RT_NOEXCEPT;
    32523348/** @} */
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