Changeset 108794 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm

Timestamp:

Mar 31, 2025 11:31:09 AM (2 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168237

Message:

Devices/EFI/FirmwareNew: Merge edk2-stable202502 from the vendor branch and make it build for the important platforms, bugref:4643

Location:

trunk/src/VBox/Devices/EFI/FirmwareNew

Files:

• . (modified) (1 prop)
• IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm (modified) (3 diffs)

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFsp2Pkg/Library/BaseFspSwitchStackLib/X64/Stack.nasm

@@ -9 +9 @@
 ;
 ;------------------------------------------------------------------------------
-
+    DEFAULT REL
     SECTION .text
 
 %include    "PushPopRegsNasm.inc"
 
+; Page table related bits in CR0/CR4/EFER
+%define CR0_PG_MASK          0x80010000  ; CR0.PG and CR0.WP
+%define CR4_PG_MASK          0x10B0      ; CR4.PSE, CR4.PAE, CR4.PGE and CR4.LA57
+%define EFER_PG_MASK         0x800       ; EFER.NXE
+
 extern ASM_PFX(SwapStack)
+extern ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))
 
 ;------------------------------------------------------------------------------
@@ -56 +62 @@
     cli
     PUSHA_64
+
+    ;
+    ; Allocate 4x8 bytes on the stack.
+    ;
+    sub     rsp, 32
+    lea     rdx, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
+    mov     dl, byte [rdx]
+    cmp     dl, 0
+    jz      SkipPagetableSave
+
+    add     rsp, 32
+    ; Save EFER MSR
+    push   rcx
+    push   rax
+    mov    rcx, 0xC0000080
+    rdmsr
+    shl    rdx, 0x20
+    or     rdx, rax
+    pop    rax
+    pop    rcx
+    push   rdx
+
+    ; Save CR registers
+    mov    rdx, cr4
+    push   rdx
+    mov    rdx, cr3
+    push   rdx
+    mov    rdx, cr0
+    push   rdx
+SkipPagetableSave:
+
     sub     rsp, 16
     sidt    [rsp]
@@ -69 +106 @@
     lidt    [rsp]
     add     rsp, 16
+
+    lea     rax, [ASM_PFX(FeaturePcdGet (PcdFspSaveRestorePageTableEnable))]
+    mov     al, byte [rax]
+    cmp     al, 0
+    jz      SkipPagetableRestore
+    ; [rsp]    stores new cr0
+    ; [rsp+8]  stores new cr3
+    ; [rsp+16] stores new cr4
+    ; [rsp+24] stores new Efer
+    ;
+    ; When new EFER.NXE == 1, the restore flow is: EFER --> CRx
+    ; Otherwise: CRx --> EFER
+    ;
+    ; If NXE bit is changed to 1, change NXE before CR register
+    ; This is because Nx bit in page table entry in new CR3 will be invalid
+    ; if updating CR3 before EFER MSR.
+    ;
+    mov rax, [rsp + 24]
+    bt  rax, 11
+    jnc SkipEferLabel1
+
+    ; Restore EFER MSR
+    mov    ecx, 0xC0000080
+    rdmsr
+    and    eax, ~EFER_PG_MASK
+    mov    ebx, [rsp + 24]
+    and    ebx, EFER_PG_MASK
+    or     eax, ebx
+    wrmsr
+
+SkipEferLabel1:
+
+    mov     rbx, [rsp]
+    mov     rdx, cr0
+    and     rdx, ~CR0_PG_MASK
+    and     rbx, CR0_PG_MASK
+    or      rdx, rbx
+    mov     cr0, rdx
+
+    mov     rbx, [rsp + 8]
+    mov     cr3, rbx
+
+    mov     rbx, [rsp + 16]
+    mov     rdx, cr4
+    and     rdx, ~CR4_PG_MASK
+    and     rbx, CR4_PG_MASK
+    or      rdx, rbx
+    mov     cr4, rdx
+
+    ;
+    ; If NXE bit is changed to 0, change NXE after than CR regiser
+    ;
+    mov rax, [rsp + 24]
+    bt  rax, 11
+    jc  SkipEferLabel2
+
+    ; Restore EFER MSR
+    mov    ecx, 0xC0000080
+    rdmsr
+    and    eax, ~EFER_PG_MASK
+    mov    ebx, [rsp + 24]
+    and    ebx, EFER_PG_MASK
+    or     eax, ebx
+    wrmsr
+
+SkipEferLabel2:
+SkipPagetableRestore:
+    ; pop page table related registers.
+    add     rsp, 32
+
     POPA_64
     popfq