Changeset 108856 in vbox for trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

Timestamp:

Apr 4, 2025 5:36:38 PM (5 weeks ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

168306

Message:

VMM/PGM: Move some code for the ARMv8 page table walking around in order to be able to create standalone testcase, bugref:10388

File:

• trunk/src/VBox/VMM/VMMAll/PGMAll.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

@@ -966 +966 @@
 
 #elif defined(VBOX_VMM_TARGET_ARMV8)
-
-/*
- *
- * Mode criteria:
- *      - MMU enabled/disabled.
- *      - TCR_EL1.TG0 (granule size for TTBR0_EL1).
- *      - TCR_EL1.TG1 (granule size for TTBR1_EL1).
- *      - TCR_EL1.T0SZ (address space size for TTBR0_EL1).
- *      - TCR_EL1.T1SZ (address space size for TTBR1_EL1).
- *      - TCR_EL1.IPS (intermediate physical address size).
- *      - TCR_EL1.TBI0 (ignore top address byte for TTBR0_EL1).
- *      - TCR_EL1.TBI1 (ignore top address byte for TTBR1_EL1).
- *      - TCR_EL1.HPD0 (hierarchical permisson disables for TTBR0_EL1).
- *      - TCR_EL1.HPD1 (hierarchical permisson disables for TTBR1_EL1).
- *      - More ?
- *
- * Other relevant modifiers:
- *      - TCR_EL1.HA - hardware access bit.
- *      - TCR_EL1.HD - hardware dirty bit.
- *      - ++
- *
- * Each privilege EL (1,2,3) has their own TCR_ELx and TTBR[01]_ELx registers,
- * so they should all have their own separate modes.  To make it simpler,
- * why not do a separate mode for TTBR0_ELx and one for TTBR1_ELx.  Top-level
- * functions determins which of the roots to use and call template (C++)
- * functions that takes it from there.  Using the preprocessor function template
- * approach is _not_ desirable here.
- *
- */
-
-/** @todo  Proper ARMv8 guest support for PGM;  The idea is to cache the
- *         configuration register values and lazily reconfigure when they
- *         change. */
 # include "PGMAllGst-armv8.cpp.h"
-
-/**
- * Guest mode data array.
- */
-PGMMODEDATAGST const g_aPgmGuestModeData[PGM_GUEST_MODE_DATA_ARRAY_SIZE] =
-{
-    { UINT32_MAX, NULL, NULL, NULL, NULL, NULL }, /* 0 */
-    {
-        PGM_TYPE_NONE,
-        PGM_CTX(pgm,GstNoneGetPage),
-        PGM_CTX(pgm,GstNoneQueryPageFast),
-        PGM_CTX(pgm,GstNoneModifyPage),
-        PGM_CTX(pgm,GstNoneWalk),
-        PGM_CTX(pgm,GstNoneEnter),
-        PGM_CTX(pgm,GstNoneExit),
-    },
-
-#define PGM_MODE_TYPE_CREATE(a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd) \
-        (2 + (  (a_fEpd ? RT_BIT_32(6) : 0)     \
-              | (a_fTbi ? RT_BIT_32(5) : 0)     \
-              | (a_GranuleSz << 3)              \
-              | (a_InitialLookupLvl << 1)       \
-              | (a_fTtbr0 ? RT_BIT_32(0) : 0) ))
-
-#define PGM_MODE_CREATE_EX(a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd) \
-    { \
-        PGM_MODE_TYPE_CREATE(a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd), \
-        PGM_CTX(pgm,GstGetPage)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd>, \
-        PGM_CTX(pgm,GstQueryPageFast)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd>, \
-        PGM_CTX(pgm,GstModifyPage)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd>, \
-        PGM_CTX(pgm,GstWalk)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd>, \
-        PGM_CTX(pgm,GstEnter)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd>, \
-        PGM_CTX(pgm,GstExit)<a_fTtbr0, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd> \
-    }
-
-#define PGM_MODE_CREATE_TTBR(a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd) \
-    PGM_MODE_CREATE_EX(false, a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd), \
-    PGM_MODE_CREATE_EX(true,  a_InitialLookupLvl, a_GranuleSz, a_fTbi, a_fEpd)
-
-#define PGM_MODE_CREATE_LOOKUP_LVL(a_GranuleSz, a_fTbi, a_fEpd) \
-    PGM_MODE_CREATE_TTBR(0,  a_GranuleSz, a_fTbi, a_fEpd ), \
-    PGM_MODE_CREATE_TTBR(1,  a_GranuleSz, a_fTbi, a_fEpd ), \
-    PGM_MODE_CREATE_TTBR(2,  a_GranuleSz, a_fTbi, a_fEpd ), \
-    PGM_MODE_CREATE_TTBR(3,  a_GranuleSz, a_fTbi, a_fEpd ) /* Invalid */
-
-#define PGM_MODE_CREATE_GRANULE_SZ(a_fTbi, a_fEpd) \
-    PGM_MODE_CREATE_LOOKUP_LVL(ARMV8_TCR_EL1_AARCH64_TG1_INVALID, a_fTbi, a_fEpd), \
-    PGM_MODE_CREATE_LOOKUP_LVL(ARMV8_TCR_EL1_AARCH64_TG1_16KB,    a_fTbi, a_fEpd), \
-    PGM_MODE_CREATE_LOOKUP_LVL(ARMV8_TCR_EL1_AARCH64_TG1_4KB,     a_fTbi, a_fEpd), \
-    PGM_MODE_CREATE_LOOKUP_LVL(ARMV8_TCR_EL1_AARCH64_TG1_64KB,    a_fTbi, a_fEpd)
-
-#define PGM_MODE_CREATE_TBI(a_fEpd) \
-    PGM_MODE_CREATE_GRANULE_SZ(false, a_fEpd), \
-    PGM_MODE_CREATE_GRANULE_SZ(true,  a_fEpd)
-
-    /* Recursive expansion for the win, this will blow up to 128 entries covering all possible modes. */
-    PGM_MODE_CREATE_TBI(false),
-    PGM_MODE_CREATE_TBI(true)
-
-#undef PGM_MODE_CREATE_TBI
-#undef PGM_MODE_CREATE_GRANULE_SZ
-#undef PGM_MODE_CREATE_LOOKUP_LVL
-#undef PGM_MODE_CREATE_TTBR
-#undef PGM_MODE_CREATE_EX
-};
-
 #else
 # error "port me"
@@ -3656 +3557 @@
 #elif defined(VBOX_VMM_TARGET_ARMV8)
 
-template<uint8_t a_offTsz, uint8_t a_offTg, uint8_t a_offTbi, uint8_t a_offEpd, bool a_fTtbr0>
-DECLINLINE(uintptr_t) pgmR3DeduceTypeFromTcr(uint64_t u64RegSctlr, uint64_t u64RegTcr, uint64_t *pfInitialLookupMask)
-{
-    uintptr_t idxNewGst = 0;
-
-    /*
-     * MMU enabled at all?
-     * Technically this is incorrect as we use ARMV8_SCTLR_EL1_M regardless of the EL but the bit is the same
-     * for all exception levels.
-     */
-    if (u64RegSctlr & ARMV8_SCTLR_EL1_M)
-    {
-        uint64_t const u64Tsz = (u64RegTcr >> a_offTsz) & 0x1f;
-        uint64_t const u64Tg  = (u64RegTcr >> a_offTg)  & 0x3;
-        bool     const fTbi   = RT_BOOL(u64RegTcr & RT_BIT_64(a_offTbi));
-        bool     const fEpd   = RT_BOOL(u64RegTcr & RT_BIT_64(a_offEpd));
-
-        /*
-         * From: https://github.com/codingbelief/arm-architecture-reference-manual-for-armv8-a/blob/master/en/chapter_d4/d42_2_controlling_address_translation_stages.md
-         * For all translation stages
-         * The maximum TxSZ value is 39. If TxSZ is programmed to a value larger than 39 then it is IMPLEMENTATION DEFINED whether:
-         *     - The implementation behaves as if the field is programmed to 39 for all purposes other than reading back the value of the field.
-         *     - Any use of the TxSZ value generates a Level 0 Translation fault for the stage of translation at which TxSZ is used.
-         *
-         * For a stage 1 translation
-         * The minimum TxSZ value is 16. If TxSZ is programmed to a value smaller than 16 then it is IMPLEMENTATION DEFINED whether:
-         *     - The implementation behaves as if the field were programmed to 16 for all purposes other than reading back the value of the field.
-         *     - Any use of the TxSZ value generates a stage 1 Level 0 Translation fault.
-         *
-         * We currently choose the former for both.
-         */
-        uint64_t uLookupLvl;
-        if (/*u64Tsz >= 16 &&*/ u64Tsz <= 24)
-        {
-            uLookupLvl = 0;
-            if (u64Tsz >= 16)
-                *pfInitialLookupMask = RT_BIT_64(24 - u64Tsz + 1) - 1;
-            else
-                *pfInitialLookupMask = RT_BIT_64(24 - 16 + 1) - 1;
-        }
-        else if (u64Tsz >= 25 && u64Tsz <= 33)
-        {
-            uLookupLvl = 1;
-            *pfInitialLookupMask = RT_BIT_64(33 - u64Tsz + 1) - 1;
-        }
-        else /*if (u64Tsz >= 34 && u64Tsz <= 39)*/
-        {
-            uLookupLvl = 2;
-            if (u64Tsz <= 39)
-                *pfInitialLookupMask = RT_BIT_64(39 - u64Tsz + 1) - 1;
-            else
-                *pfInitialLookupMask = RT_BIT_64(39 - 39 + 1) - 1;
-        }
-
-        /* Build the index into the PGM mode callback table for the given config. */
-        idxNewGst = PGM_MODE_TYPE_CREATE(a_fTtbr0, uLookupLvl, u64Tg, fTbi, fEpd);
-    }
-    else
-        idxNewGst = PGM_TYPE_NONE;
-
-    return idxNewGst;
-}
-
-
 VMM_INT_DECL(int) PGMChangeMode(PVMCPUCC pVCpu, uint8_t bEl, uint64_t u64RegSctlr, uint64_t u64RegTcr)
 {