Changeset 12612 in vbox for trunk/src/VBox/Devices/PC/DevAPIC.cpp

Timestamp:

Sep 19, 2008 5:58:06 PM (16 years ago)

Author:

vboxsync

Message:

further APIC work

File:

• trunk/src/VBox/Devices/PC/DevAPIC.cpp (modified) (34 diffs)

trunk/src/VBox/Devices/PC/DevAPIC.cpp

@@ -78 +78 @@
 #define IOAPIC_UNLOCK(pThis) (pThis)->CTX_SUFF(pIoApicHlp)->pfnUnlock((pThis)->CTX_SUFF(pDevIns))
 
-/**  @def FIRST_LAPIC
+/**  @def LAPIC_BASE
  * Return address of first LAPIC state. */ 
-#define FIRST_LAPIC(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
-
-#define FOR_EACH_LAPIC(dev, code)                         \
+#define LAPIC_BASE(pThis) ((APICState*)(pThis)->CTX_SUFF(pLapics))
+
+#define foreach_apic(dev, mask, code)                     \
     do {                                                  \
         uint32_t i;                                       \
-        APICState* apic = FIRST_LAPIC(dev);               \
-        for (i=0; i < dev->cCpus; i++)                    \
+        APICState* apic = LAPIC_BASE(dev);                \
+        for (i = 0; i < dev->cCpus; i++)                  \
         {                                                 \
-            code;                                         \
+            if (mask & (1 << (apic->id)))                 \
+            {                                             \
+                code;                                     \
+            }                                             \
             apic++;                                       \
         }                                                 \
@@ -285 +288 @@
 } APICDeviceInfo;
 
-DECLINLINE(APICState*) getLAPIC(APICDeviceInfo* dev)
+DECLINLINE(APICState*) getLapic(APICDeviceInfo* dev)
 {
     uint32_t id = dev->CTX_SUFF(pApicHlp)->pfnGetCpuId(dev->CTX_SUFF(pDevIns));
-    return FIRST_LAPIC(dev) + id;
-}
-
+    return LAPIC_BASE(dev) + id;
+}
+
+
+DECLINLINE(void) cpuSetInterrupt(APICDeviceInfo* dev, uint32_t cpuid)
+{
+    dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns));
+}
+
+DECLINLINE(void) cpuClearInterrupt(APICDeviceInfo* dev, uint32_t cpuid)
+{
+    dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+}
 #endif /* VBOX */
 
@@ -343 +356 @@
     switch (delivery_mode) {
         case APIC_DM_LOWPRI:
-#ifndef VBOX
-            /* XXX: search for focus processor, arbitration */
+        {
+            int d = -1;
+            if (deliver_bitmask)
+                d = ffs_bit(deliver_bitmask);
+            if (d >= 0) 
             {
-                int i, d;
-                d = -1;
-                for(i = 0; i < MAX_APIC_WORDS; i++) {
-                    if (deliver_bitmask[i]) {
-                        d = i * 32 + ffs_bit(deliver_bitmask[i]);
-                        break;
-                    }
-                }
-                if (d >= 0) {
-                    apic_iter = local_apics[d];
-                    if (apic_iter) {
-                        apic_set_irq(apic_iter, vector_num, trigger_mode);
-                    }
-                }
+                APICState* apic = LAPIC_BASE(dev) + d;
+                apic_set_irq(dev, apic, vector_num, trigger_mode);
             }
-#else
-            {
-                int d = -1;
-                if (deliver_bitmask)
-                    d = ffs_bit(deliver_bitmask);
-                if (d >= 0) 
-                {
-                    APICState* apic = FIRST_LAPIC(dev) + d;
-                    apic_set_irq(dev, apic, vector_num, trigger_mode);
-                }
-            }
-#endif
             return;
+        }
         case APIC_DM_FIXED:
             /* XXX: arbitration */
@@ -379 +372 @@
 
         case APIC_DM_SMI:
+            /** @todo: what do we really do with SMI */
+            foreach_apic(dev, deliver_bitmask,
+                         cpuSetInterrupt(dev, apic->id));
+            return;
+
         case APIC_DM_NMI:
-            break;
+            /** @todo: what do we really do with NMI */
+            foreach_apic(dev, deliver_bitmask,
+                         cpuSetInterrupt(dev, apic->id));
+            return;
 
         case APIC_DM_INIT:
             /* normal INIT IPI sent to processors */
 #ifdef VBOX
-            apic_init_ipi (s);
+            foreach_apic(dev, deliver_bitmask,
+                         apic_init_ipi(apic));
 #else
             for (apic_iter = first_local_apic; apic_iter != NULL;
@@ -403 +405 @@
 
 #ifdef VBOX
-    if (deliver_bitmask & (1 << s->id))
-        apic_set_irq (dev, s, vector_num, trigger_mode);
+    foreach_apic(dev, deliver_bitmask,
+                       apic_set_irq (dev, apic, vector_num, trigger_mode));
 #else  /* VBOX */
     for (apic_iter = first_local_apic; apic_iter != NULL;
@@ -435 +437 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     Log(("cpu_set_apic_base: %016RX64\n", val));
 
@@ -447 +449 @@
 
         /* Clear any pending APIC interrupt action flag. */
-        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+        cpuClearInterrupt(dev, s->id);
         dev->CTX_SUFF(pApicHlp)->pfnChangeFeature(pDevIns, false);
     }
@@ -518 +520 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     Log(("apicGetBase: %016llx\n", (uint64_t)s->apicbase));
     return s->apicbase;
@@ -526 +528 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     LogFlow(("apicSetTPR: val=%#x (trp %#x -> %#x)\n", val, s->tpr, (val & 0x0f) << 4));
     apic_update_tpr(dev, s, (val & 0x0f) << 4);
@@ -534 +536 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     Log2(("apicGetTPR: returns %#x\n", s->tpr >> 4));
     return s->tpr >> 4;
@@ -548 +550 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     LogFlow(("apicBusDeliverCallback: s=%p pDevIns=%p u8Dest=%#x u8DestMode=%#x u8DeliveryMode=%#x iVector=%#x u8Polarity=%#x u8TriggerMode=%#x\n",
              s, pDevIns, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode));
@@ -609 +611 @@
     {
         /* Clear any pending APIC interrupt action flag. */
-        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+        cpuClearInterrupt(dev, s->id);
         return false;
     }
@@ -624 +626 @@
     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 #else
-    dev->CTX_SUFF(pApicHlp)->pfnSetInterruptFF(dev->CTX_SUFF(pDevIns));
+    cpuSetInterrupt(dev, s->id);
     return true;
 #endif
@@ -638 +640 @@
     if (!dev)
         return false;
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
 
     irrv = get_highest_priority_int(s->irr);
@@ -665 +667 @@
         Log(("apic_update_tpr: deactivate interrupt that was masked by the TPR update (%x)\n", val));
         STAM_COUNTER_INC(&dev->StatClearedActiveIrq);
-        dev->CTX_SUFF(pApicHlp)->pfnClearInterruptFF(dev->CTX_SUFF(pDevIns));
+        cpuClearInterrupt(dev, s->id);
     }
 }
@@ -700 +702 @@
 #endif /* VBOX */
 {
-#if 0
-    uint32_t mask = 0;
-#ifndef VBOX
-    APICState *apic_iter;
-#endif /* !VBOX */
-
-    if (dest_mode == 0) {
-        if (dest == 0xff)
-            mask = 0xff;
-        else
-            mask = 1 << dest;
-    } else {
-        /* XXX: cluster mode */
-#ifdef VBOX
-        if (dest & s->log_dest)
-            mask |= 1 << s->id;
-#else /* !VBOX */
-        for (apic_iter = first_local_apic; apic_iter != NULL;
-             apic_iter = apic_iter->next_apic) {
-            if (dest & apic_iter->log_dest)
-                mask |= (1 << apic_iter->id);
-        }
-#endif /* !VBOX */
-    }
-
-    return mask;
-#else
     uint32_t mask = 0;
 
@@ -738 +713 @@
     else 
     {
-        APICState *apic = FIRST_LAPIC(dev);
+        APICState *apic = LAPIC_BASE(dev);
         uint32_t i;
         
@@ -763 +738 @@
 
     return mask;
-#endif
 }
 
@@ -850 +824 @@
                 if (level == 0 && trig_mode == 1) {
 #ifdef VBOX
-                    FOR_EACH_LAPIC(dev, 
-                                   if (deliver_bitmask & (1 << apic->id)) 
-                                   {
-                                       apic->arb_id = apic->id;
-                                   });
+                    foreach_apic(dev, deliver_bitmask,
+                                       apic->arb_id = apic->id);
 #else /* !VBOX */
                     for (apic_iter = first_local_apic; apic_iter != NULL;
@@ -878 +849 @@
             }
 #else
-            FOR_EACH_LAPIC(dev, apic_startup(dev, apic, vector_num));
+            foreach_apic(dev, deliver_bitmask,
+                         apic_startup(dev, apic, vector_num));
 #endif /* !VBOX */
             return;
@@ -900 +872 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
 #endif /* VBOX */
     int intno;
@@ -995 +967 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
     dev->pApicHlpR3->pfnLock(pDevIns, VERR_INTERNAL_ERROR);
 #endif /* VBOX */
@@ -1654 +1626 @@
 
 /* LAPIC */
-
-/* LAPICs MMIO is wrong, in SMP there is no relation between memory range and
-   lapic, it's only the CPU that executes this memory access is what matters */
-
 PDMBOTHCBDECL(int) apicMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
 
 #ifdef VBOX_WITH_SMP_GUESTS
-    LogRel(("[SMP] apicMMIORead %p at %ullx\n", pDevIns, (uint64_t)GCPhysAddr));
-#endif
-
-    /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have 
+    LogRel(("[SMP] apicMMIORead at %llx\n", (uint64_t)GCPhysAddr));
+#endif
+
+    /** @todo: add LAPIC range validity checks (different LAPICs can theoretically have 
                different physical addresses, see #3092) */
 
@@ -1715 +1683 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    APICState *s = getLAPIC(dev);
+    APICState *s = getLapic(dev);
+
+#ifdef VBOX_WITH_SMP_GUESTS
+    LogRel(("[SMP] apicMMIOWrite at %llx\n", (uint64_t)GCPhysAddr));
+#endif
 
     /** @todo: add LAPIC range validity checks (multiple LAPICs can theoretically have 
@@ -1752 +1724 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    /* @todo: process all LAPICS */
-    APICState* s = FIRST_LAPIC(dev);
-    apic_save(pSSMHandle, s);
-    /* @todo: save CPU count? */
+
+    /* save all APICs data, @todo: is it correct? */
+    foreach_apic(dev, 0xffffffff, apic_save(pSSMHandle, apic));
+
     return TMR3TimerSave(dev->CTX_SUFF(pTimer), pSSMHandle);
 }
@@ -1765 +1737 @@
 {
     APICDeviceInfo *dev = PDMINS_2_DATA(pDevIns, APICDeviceInfo *);
-    /* @todo: process all LAPICS */
-    APICState* s = FIRST_LAPIC(dev);
-    if (apic_load(pSSMHandle, s, u32Version)) {
-        AssertFailed();
-        return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
-    }
-     /* @todo: restore CPU count? */
+    /* load all APICs data, @todo: is it correct? */
+    foreach_apic(dev, 0xffffffff, 
+                 if (apic_load(pSSMHandle, apic, u32Version))
+                 {
+                      AssertFailed();
+                      return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
+                 }
+                 );
     return TMR3TimerLoad(dev->CTX_SUFF(pTimer), pSSMHandle);
 }
@@ -1786 +1759 @@
 
      /* @todo: process all LAPICS? Or only one? */
-    APICState* s = FIRST_LAPIC(dev);
+    APICState* s = LAPIC_BASE(dev);
 
     apic_init_ipi(s);
@@ -1796 +1769 @@
     dev->pApicHlpR3->pfnChangeFeature(dev->pDevInsR3, true);
     /* Clear any pending APIC interrupt action flag. */
-    dev->pApicHlpR3->pfnClearInterruptFF(pDevIns);
+    cpuClearInterrupt(dev, s->id);
     APIC_UNLOCK(dev);
 }
@@ -1812 +1785 @@
 }
 
-DECLINLINE(void) initAPIC(APICState* apic, uint8_t id)
+DECLINLINE(void) initApicData(APICState* apic, uint8_t id)
 {
     int i;
-    ::memset(apic, 0, sizeof(*apic));
+    memset(apic, 0, sizeof(*apic));
     apic->apicbase  = UINT32_C(0xfee00000) | MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
     for (i = 0; i < APIC_LVT_NB; i++)
@@ -1894 +1867 @@
     for (i = 0; i < cCpus; i++)
     {
-        initAPIC((APICState*)pThis->pLapicsR3+i, i);
+        initApicData((APICState*)pThis->pLapicsR3 + i, i);
     }
 
@@ -1976 +1949 @@
      *        (see IA32_APIC_BASE_MSR)
      */
-    rc = PDMDevHlpMMIORegister(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, pThis,
+    rc = PDMDevHlpMMIORegister(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, pThis,
                                apicMMIOWrite, apicMMIORead, NULL, "APIC Memory");
     if (RT_FAILURE(rc))
@@ -1984 +1957 @@
         pThis->pApicHlpRC = pThis->pApicHlpR3->pfnGetRCHelpers(pDevIns);
 
-        rc = PDMDevHlpMMIORegisterGC(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, 0,
+        rc = PDMDevHlpMMIORegisterGC(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
                                      "apicMMIOWrite", "apicMMIORead", NULL);
         if (RT_FAILURE(rc))
@@ -1993 +1966 @@
         pThis->pApicHlpR0 = pThis->pApicHlpR3->pfnGetR0Helpers(pDevIns);
 
-        rc = PDMDevHlpMMIORegisterR0(pDevIns, FIRST_LAPIC(pThis)->apicbase & ~0xfff, 0x1000, 0,
+        rc = PDMDevHlpMMIORegisterR0(pDevIns, LAPIC_BASE(pThis)->apicbase & ~0xfff, 0x1000, 0,
                                      "apicMMIOWrite", "apicMMIORead", NULL);
         if (RT_FAILURE(rc))
@@ -2080 +2053 @@
 
 #endif /* IN_RING3 */
-
-