Changeset 12657 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Sep 22, 2008 6:29:06 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

36948

Message:

#1865: CPUM. Also added missing aliasing for DR4&5 to the guest DRx setter and getter.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllA.asm (modified) (8 diffs)
• CPUMAllRegs.cpp (modified) (110 diffs)
• EMAll.cpp (modified) (14 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm

@@ -266 +266 @@
 ENDPROC     CPUMLoadFPUAsm
 
+
 ;;
 ; Restores the guest's FPU/XMM state
@@ -285 +286 @@
     ret
 ENDPROC CPUMSaveFPUAsm
+
 
 ;;
@@ -310 +312 @@
     movdqa  xmm6, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6]
     movdqa  xmm7, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7]
-    
+
 %ifdef RT_ARCH_AMD64
     test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
     jz CPUMLoadXMMAsm_done
-    
+
     movdqa  xmm8, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*8]
     movdqa  xmm9, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*9]
@@ -354 +356 @@
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6], xmm6
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7], xmm7
-    
+
 %ifdef RT_ARCH_AMD64
     test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
@@ -367 +369 @@
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*14], xmm14
     movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*15], xmm15
-    
+
 CPUMSaveXMMAsm_done:
 %endif
@@ -396 +398 @@
 ENDPROC   CPUMSetFCW
 
+
 ;;
 ; Get the FPU control word
@@ -408 +411 @@
 
 ;;
-; Set the MXCSR; 
+; Set the MXCSR;
 ;
 ; @param  u32MXCSR    x86:[esp+4] GCC:rdi MSC:rcx     New MXCSR
@@ -428 +431 @@
 ENDPROC   CPUMSetMXCSR
 
+
 ;;
 ; Get the MXCSR

trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

@@ -1 +1 @@
 /* $Id$ */
 /** @file
- * CPUM - CPU Monitor(/Manager) - Gets and Sets.
+ * CPUM - CPU Monitor(/Manager) - Getters and Setters.
  */
 
@@ -38 +38 @@
 
 
-
 /** Disable stack frame pointer generation here. */
 #if defined(_MSC_VER) && !defined(DEBUG)
@@ -58 +57 @@
 CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
 {
-    LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTXALLSUFF(pHyperCore), pCtxCore));
+    LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
     if (!pCtxCore)
     {
@@ -64 +63 @@
         pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
         pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
-        pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
+        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
     }
     else
@@ -70 +69 @@
         pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
         pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
-        pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
+        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
     }
 }
@@ -83 +82 @@
 CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore);
+    return pVM->cpum.s.CTX_SUFF(pHyperCore);
 }
 
@@ -105 +104 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit)
 {
@@ -112 +112 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit)
 {
@@ -119 +120 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3)
 {
@@ -124 +126 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs = SelCS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds = SelDS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelES)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->es = SelES;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
+}
+
 
 CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelFS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs = SelFS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelGS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs = SelGS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss = SelSS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp = u32ESP;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
+}
+
 
 CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32 = Efl;
-    return VINF_SUCCESS;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
+    return VINF_SUCCESS;
+}
+
 
 CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP)
 {
-    pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip = u32EIP;
-}
+    pVM->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
+}
+
 
 CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR)
@@ -175 +187 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR)
 {
     pVM->cpum.s.Hyper.ldtr = SelLDTR;
 }
+
 
 CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0)
@@ -186 +200 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1)
 {
@@ -192 +207 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2)
 {
@@ -198 +214 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3)
 {
@@ -204 +221 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6)
 {
@@ -210 +228 @@
 }
 
+
 CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7)
 {
@@ -219 +238 @@
 CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->cs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ds;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->es;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->es;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->fs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->gs;
+}
+
 
 CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss;
-}
-
-#if 0 /* these are not correct. */
-
-CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr0;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr2;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr3;
-}
-
-CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM)
-{
-    return pVM->cpum.s.Hyper.cr4;
-}
-
-#endif /* not correct */
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ss;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eax;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eax;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ecx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ecx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edx;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edx;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esi;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esi;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edi;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edi;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebp;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebp;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esp;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eip;
+}
+
 
 CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM)
 {
-    return pVM->cpum.s.CTXALLSUFF(pHyperCore)->rip;
-}
+    return pVM->cpum.s.CTX_SUFF(pHyperCore)->rip;
+}
+
 
 CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit)
@@ -333 +345 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit)
 {
@@ -340 +353 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM)
 {
@@ -345 +359 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM)
 {
@@ -350 +365 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM)
 {
@@ -355 +371 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM)
 {
@@ -360 +377 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM)
 {
@@ -365 +383 @@
 }
 
+
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM)
 {
     return pVM->cpum.s.Hyper.dr[6];
 }
+
 
 CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM)
@@ -396 +416 @@
 CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore)
 {
-    /** @todo #1410 requires selectors to be checked. */
+    /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
 
     PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVM->cpum.s.Guest);
@@ -511 +531 @@
                 ASMSetCR0(HyperCR0);
             }
-#ifdef VBOX_STRICT
+# ifdef VBOX_STRICT
             else
             {
@@ -518 +538 @@
                 AssertMsg((HyperCR0 & X86_CR0_EM) == (pVM->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
             }
-#endif
+# endif
         }
         else
@@ -536 +556 @@
         }
     }
-#endif
+#endif /* IN_GC */
 
     /*
@@ -551 +571 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2)
 {
@@ -556 +577 @@
     return VINF_SUCCESS;
 }
+
 
 CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3)
@@ -563 +585 @@
     return VINF_SUCCESS;
 }
+
 
 CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4)
@@ -576 +599 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags)
 {
@@ -582 +606 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip)
 {
@@ -588 +613 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax)
 {
@@ -594 +620 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx)
 {
@@ -600 +627 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx)
 {
@@ -606 +634 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx)
 {
@@ -612 +641 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp)
 {
@@ -618 +648 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp)
 {
@@ -624 +655 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi)
 {
@@ -630 +662 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi)
 {
@@ -636 +669 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss)
 {
@@ -642 +676 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs)
 {
@@ -648 +683 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds)
 {
@@ -654 +690 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es)
 {
@@ -660 +697 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs)
 {
@@ -666 +704 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs)
 {
@@ -672 +711 @@
 }
 
+
 CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val)
 {
@@ -677 +717 @@
 }
 
+
 CPUMDECL(uint64_t)  CPUMGetGuestMsr(PVM pVM, unsigned idMsr)
 {
-    uint64_t val = 0;
+    uint64_t u64 = 0;
 
     switch (idMsr)
     {
-    case MSR_IA32_CR_PAT:
-        val = pVM->cpum.s.Guest.msrPAT;
-        break;
-
-    case MSR_IA32_SYSENTER_CS:
-        val = pVM->cpum.s.Guest.SysEnter.cs;
-        break;
-
-    case MSR_IA32_SYSENTER_EIP:
-        val = pVM->cpum.s.Guest.SysEnter.eip;
-        break;
-
-    case MSR_IA32_SYSENTER_ESP:
-        val = pVM->cpum.s.Guest.SysEnter.esp;
-        break;
-
-    case MSR_K6_EFER:
-        val = pVM->cpum.s.Guest.msrEFER;
-        break;
-
-    case MSR_K8_SF_MASK:
-        val = pVM->cpum.s.Guest.msrSFMASK;
-        break;
-
-    case MSR_K6_STAR:
-        val = pVM->cpum.s.Guest.msrSTAR;
-        break;
-
-    case MSR_K8_LSTAR:
-        val = pVM->cpum.s.Guest.msrLSTAR;
-        break;
-
-    case MSR_K8_CSTAR:
-        val = pVM->cpum.s.Guest.msrCSTAR;
-        break;
-
-    case MSR_K8_KERNEL_GS_BASE:
-        val = pVM->cpum.s.Guest.msrKERNELGSBASE;
-        break;
-
-    /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
-    default:
-        AssertFailed();
-        break;
+        case MSR_IA32_CR_PAT:
+            u64 = pVM->cpum.s.Guest.msrPAT;
+            break;
+
+        case MSR_IA32_SYSENTER_CS:
+            u64 = pVM->cpum.s.Guest.SysEnter.cs;
+            break;
+
+        case MSR_IA32_SYSENTER_EIP:
+            u64 = pVM->cpum.s.Guest.SysEnter.eip;
+            break;
+
+        case MSR_IA32_SYSENTER_ESP:
+            u64 = pVM->cpum.s.Guest.SysEnter.esp;
+            break;
+
+        case MSR_K6_EFER:
+            u64 = pVM->cpum.s.Guest.msrEFER;
+            break;
+
+        case MSR_K8_SF_MASK:
+            u64 = pVM->cpum.s.Guest.msrSFMASK;
+            break;
+
+        case MSR_K6_STAR:
+            u64 = pVM->cpum.s.Guest.msrSTAR;
+            break;
+
+        case MSR_K8_LSTAR:
+            u64 = pVM->cpum.s.Guest.msrLSTAR;
+            break;
+
+        case MSR_K8_CSTAR:
+            u64 = pVM->cpum.s.Guest.msrCSTAR;
+            break;
+
+        case MSR_K8_KERNEL_GS_BASE:
+            u64 = pVM->cpum.s.Guest.msrKERNELGSBASE;
+            break;
+
+        /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
+        default:
+            AssertFailed();
+            break;
     }
-    return val;
-}
+    return u64;
+}
+
 
 CPUMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
@@ -738 +780 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
 {
@@ -743 +786 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM)
 {
@@ -748 +792 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM)
 {
@@ -753 +798 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM)
 {
@@ -758 +804 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM)
 {
@@ -763 +810 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM)
 {
@@ -768 +816 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM)
 {
@@ -773 +822 @@
 }
 
+
 CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM)
 {
@@ -778 +828 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM)
 {
@@ -783 +834 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM)
 {
@@ -788 +840 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM)
 {
@@ -793 +846 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM)
 {
@@ -798 +852 @@
 }
 
+
 CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR)
 {
@@ -803 +858 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM)
 {
@@ -808 +864 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM)
 {
@@ -813 +870 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM)
 {
@@ -818 +876 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM)
 {
@@ -823 +882 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM)
 {
@@ -828 +888 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM)
 {
@@ -833 +894 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM)
 {
@@ -838 +900 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM)
 {
@@ -843 +906 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM)
 {
@@ -848 +912 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM)
 {
@@ -853 +918 @@
 }
 
+
 CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM)
 {
@@ -858 +924 @@
 }
 
+
 CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
 {
@@ -863 +930 @@
 }
 
-//@todo: crx should be an array
+
+///@todo: crx should be an array
 CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue)
 {
@@ -886 +954 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM)
 {
@@ -891 +960 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM)
 {
@@ -896 +966 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM)
 {
@@ -901 +972 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM)
 {
@@ -906 +978 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM)
 {
@@ -911 +984 @@
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM)
 {
@@ -916 +990 @@
 }
 
+
 CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue)
 {
     AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
+    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
+    if (iReg == 4 || iReg == 5)
+        iReg += 2;
     *pValue = pVM->cpum.s.Guest.dr[iReg];
     return VINF_SUCCESS;
 }
 
+
 CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM)
 {
     return pVM->cpum.s.Guest.msrEFER;
 }
+
 
 /**
@@ -957 +1037 @@
 }
 
+
 /**
  * Gets a pointer to the array of standard CPUID leafs.
@@ -971 +1052 @@
 }
 
+
 /**
  * Gets a pointer to the array of extended CPUID leafs.
@@ -982 +1064 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
+}
+
 
 /**
@@ -996 +1079 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
+}
+
 
 /**
@@ -1008 +1092 @@
 CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM)
 {
-    return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
-}
+    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
+}
+
 
 /**
@@ -1023 +1108 @@
 }
 
+
 /**
  * Gets a number of extended CPUID leafs.
@@ -1035 +1121 @@
 }
 
+
 /**
  * Gets a number of centaur CPUID leafs.
@@ -1046 +1133 @@
     return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
 }
+
 
 /**
@@ -1196 +1284 @@
 }
 
+
 /**
  * Queries a CPUID feature bit.
@@ -1220 +1309 @@
     return false;
 }
+
 
 /**
@@ -1272 +1362 @@
 }
 
+
 /**
  * Gets the CPU vendor
@@ -1290 +1381 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1)
 {
@@ -1296 +1388 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2)
 {
@@ -1302 +1395 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3)
 {
@@ -1308 +1402 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6)
 {
@@ -1314 +1409 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7)
 {
@@ -1320 +1416 @@
 }
 
+
 CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value)
 {
     AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
+    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
+    if (iReg == 4 || iReg == 5)
+        iReg += 2;
     pVM->cpum.s.Guest.dr[iReg] = Value;
     return CPUMRecalcHyperDRx(pVM);
@@ -1639 +1739 @@
 
 
-
-
 /**
  * Gets and resets the changed flags (CPUM_CHANGED_*).
@@ -1661 +1759 @@
 }
 
+
 /**
  * Sets the specified changed flags (CPUM_CHANGED_*).
@@ -1670 +1769 @@
     pVM->cpum.s.fChanged |= fChangedFlags;
 }
+
 
 /**
@@ -1706 +1806 @@
 }
 
-
 #ifndef IN_RING3
+
 /**
  * Lazily sync in the FPU/XMM state
@@ -1731 +1831 @@
     return CPUMRestoreHostFPUStateAsm(&pVM->cpum.s);
 }
+
 #endif /* !IN_RING3 */
-
 
 /**
@@ -1756 +1856 @@
 
 
-
 /**
  * Checks if the guest debug state is active
@@ -1768 +1867 @@
 }
 
+
 /**
  * Mark the guest's debug state as inactive
@@ -1774 +1874 @@
  * @param   pVM         VM handle.
  */
-CPUMDECL(void) CPUMDeactivateGuestDebugtate(PVM pVM)
+CPUMDECL(void) CPUMDeactivateGuestDebugState(PVM pVM)
 {
     pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
@@ -1820 +1920 @@
          * not affected by loading a conforming coding segment.
          *
-         * This only seems to apply to AMD-V; in the VT-x case we *do* need to look at SS. (ACP2 regression during install after a far call to ring 2)
+         * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
+         * at SS. (ACP2 regression during install after a far call to ring 2)
          */
         cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
@@ -1862 +1963 @@
     if (!(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
         enmMode = CPUMMODE_REAL;
-    else
-    if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
+    else if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
         enmMode = CPUMMODE_PROTECTED;
     else
@@ -1870 +1970 @@
     return enmMode;
 }
+

trunk/src/VBox/VMM/VMMAll/EMAll.cpp

@@ -298 +298 @@
     if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
         return rc;
-    /* 
-     * The page pool cache may end up here in some cases because it 
-     * flushed one of the shadow mappings used by the trapping 
+    /*
+     * The page pool cache may end up here in some cases because it
+     * flushed one of the shadow mappings used by the trapping
      * instruction and it either flushed the TLB or the CPU reused it.
      */
@@ -319 +319 @@
     if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
         return rc;
-    /* 
-     * The page pool cache may end up here in some cases because it 
-     * flushed one of the shadow mappings used by the trapping 
+    /*
+     * The page pool cache may end up here in some cases because it
+     * flushed one of the shadow mappings used by the trapping
      * instruction and it either flushed the TLB or the CPU reused it.
-     * We want to play safe here, verifying that we've got write 
+     * We want to play safe here, verifying that we've got write
      * access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
      */
@@ -331 +331 @@
     if (RT_FAILURE(rc))
         return rc;
-    if (    !(fFlags & X86_PTE_RW) 
+    if (    !(fFlags & X86_PTE_RW)
         &&  (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
         return VERR_ACCESS_DENIED;
@@ -351 +351 @@
 
 #if defined(VBOX_STRICT) || defined(LOG_ENABLED)
-/** 
+/**
  * Get the mnemonic for the disassembled instruction.
- *  
- * GC/R0 doesn't include the strings in the DIS tables because 
- * of limited space. 
- */ 
+ *
+ * GC/R0 doesn't include the strings in the DIS tables because
+ * of limited space.
+ */
 static const char *emGetMnemonic(PDISCPUSTATE pCpu)
 {
@@ -803 +803 @@
  * LOCK XOR/OR/AND Emulation.
  */
-static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
+static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
                                    uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
 {
@@ -1097 +1097 @@
  * LOCK BTR/C/S Emulation.
  */
-static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
+static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
                                   uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
 {
@@ -1141 +1141 @@
 #ifdef IN_GC
     Assert(TRPMHasTrap(pVM));
-    AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, 
-                    ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault), 
+    AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
+                    ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
                     VERR_EM_INTERPRETER);
 #endif
@@ -1157 +1157 @@
     if (RT_FAILURE(rc))
     {
-        Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n", 
+        Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
              emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
         return VERR_EM_INTERPRETER;
@@ -1395 +1395 @@
     }
     else
-    {    
-        if (!cTransfers) 
+    {
+        if (!cTransfers)
             return VINF_SUCCESS;
 
@@ -1517 +1517 @@
     else
         eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
-    
+
     LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
 
@@ -2043 +2043 @@
         rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
     }
-    else 
+    else
     {
         uint32_t val32;
@@ -2059 +2059 @@
 #ifdef IN_GC
             /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
-            if (    (val    & (X86_CR0_WP | X86_CR0_AM)) 
+            if (    (val    & (X86_CR0_WP | X86_CR0_AM))
                 !=  (oldval & (X86_CR0_WP | X86_CR0_AM)))
                 return VERR_EM_INTERPRETER;
@@ -2200 +2200 @@
         rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
     }
-    else 
+    else
     {
         uint32_t val32;
@@ -2207 +2207 @@
     }
 
-    if (VBOX_SUCCESS(rc))
-    {
-        /* @todo: we don't fail if illegal bits are set/cleared for e.g. dr7 */
+    if (RT_SUCCESS(rc))
+    {
+        /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
         rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
-        if (VBOX_SUCCESS(rc))
+        if (RT_SUCCESS(rc))
             return rc;
         AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));