VirtualBox

Changeset 12657 in vbox


Ignore:
Timestamp:
Sep 22, 2008 6:29:06 PM (17 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
36948
Message:

#1865: CPUM. Also added missing aliasing for DR4&5 to the guest DRx setter and getter.

Location:
trunk
Files:
14 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/cpum.h

    r12603 r12657  
    350350    /** @} */
    351351
    352     /* padding to get 32byte aligned size */
    353 ////    uint32_t        padding[6];
     352#if 0
     353    /*& Padding to align the size on a 64 byte boundrary. */
     354    uint32_t        padding[6];
     355#endif
    354356} CPUMCTX;
    355357#pragma pack()
    … …  
    363365/**
    364366 * Selector hidden registers. (version 1.6)
     367 * @todo move to CPUMInteral.h
    365368 */
    366369typedef struct CPUMSELREGHID_VER1_6
    … …  
    378381/**
    379382 * CPU context. (Version 1.6)
     383 * @todo move to CPUMInteral.h
    380384 */
    381385#pragma pack(1)
    … …  
    582586} CPUMCPUIDFEATURE;
    583587
    584 /*
     588/**
    585589 * CPU Vendor.
    586590 */
    … …  
    688692 * @{  */
    689693
     694
     695CPUMDECL(bool)      CPUMIsGuestIn16BitCode(PVM pVM);
     696CPUMDECL(bool)      CPUMIsGuestIn32BitCode(PVM pVM);
     697CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
     698
    690699/**
    691700 * Tests if the guest is running in real mode or not.
    … …  
    742751    return (pCtx->msrEFER & MSR_K6_EFER_LMA) == MSR_K6_EFER_LMA;
    743752}
    744 
    745 /**
    746  * Tests if the guest is running in 16 bits paged protected or not.
    747  *
    748  * @returns true if in paged protected mode, otherwise false.
    749  * @param   pVM     The VM handle.
    750  */
    751 CPUMDECL(bool) CPUMIsGuestIn16BitCode(PVM pVM);
    752 
    753 /**
    754  * Tests if the guest is running in 32 bits paged protected or not.
    755  *
    756  * @returns true if in paged protected mode, otherwise false.
    757  * @param   pVM     The VM handle.
    758  */
    759 CPUMDECL(bool) CPUMIsGuestIn32BitCode(PVM pVM);
    760753
    761754/**
    … …  
    789782}
    790783
    791 /**
    792  * Gets the CPU vendor
    793  *
    794  * @returns CPU vendor
    795  * @param   pVM     The VM handle.
    796  */
    797 CPUMDECL(CPUMCPUVENDOR) CPUMGetCPUVendor(PVM pVM);
    798 
    799 
    800784/** @} */
    801 
    802785
    803786
    … …  
    868851/** @} */
    869852
    870 CPUMDECL(void) CPUMPushHyper(PVM pVM, uint32_t u32);
    871 
    872 /**
    873  * Sets or resets an alternative hypervisor context core.
    874  *
    875  * This is called when we get a hypervisor trap set switch the context
    876  * core with the trap frame on the stack. It is called again to reset
    877  * back to the default context core when resuming hypervisor execution.
    878  *
    879  * @param   pVM         The VM handle.
    880  * @param   pCtxCore    Pointer to the alternative context core or NULL
    881  *                      to go back to the default context core.
    882  */
    883 CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
    884 
    885 
    886 /**
    887  * Queries the pointer to the internal CPUMCTX structure
    888  *
    889  * @returns VBox status code.
    890  * @param   pVM         Handle to the virtual machine.
    891  * @param   ppCtx       Receives the CPUMCTX pointer when successful.
    892  */
    893 CPUMDECL(int) CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
    894 
    895 /**
    896  * Queries the pointer to the internal CPUMCTX structure for the hypervisor.
    897  *
    898  * @returns VBox status code.
    899  * @param   pVM         Handle to the virtual machine.
    900  * @param   ppCtx       Receives the hyper CPUMCTX pointer when successful.
    901  */
    902 CPUMDECL(int) CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
    903 
    904 
    905 /**
    906  * Gets the pointer to the internal CPUMCTXCORE structure.
    907  * This is only for reading in order to save a few calls.
    908  *
    909  * @param   pVM         Handle to the virtual machine.
    910  */
     853CPUMDECL(void)      CPUMPushHyper(PVM pVM, uint32_t u32);
     854CPUMDECL(void)      CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore);
     855CPUMDECL(int)       CPUMQueryGuestCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
     856CPUMDECL(int)       CPUMQueryHyperCtxPtr(PVM pVM, PCPUMCTX *ppCtx);
    911857CPUMDECL(PCCPUMCTXCORE) CPUMGetGuestCtxCore(PVM pVM);
    912 
    913 /**
    914  * Gets the pointer to the internal CPUMCTXCORE structure for the hypervisor.
    915  * This is only for reading in order to save a few calls.
    916  *
    917  * @param   pVM         Handle to the virtual machine.
    918  */
    919858CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM);
    920 
    921 /**
    922  * Sets the guest context core registers.
    923  *
    924  * @param   pVM         Handle to the virtual machine.
    925  * @param   pCtxCore    The new context core values.
    926  */
    927 CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
    928 
    929 
    930 /**
    931  * Transforms the guest CPU state to raw-ring mode.
    932  *
    933  * This function will change the any of the cs and ss register with DPL=0 to DPL=1.
    934  *
    935  * @returns VBox status. (recompiler failure)
    936  * @param   pVM         VM handle.
    937  * @param   pCtxCore    The context core (for trap usage).
    938  * @see     @ref pg_raw
    939  */
    940 CPUMDECL(int) CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
    941 
    942 /**
    943  * Transforms the guest CPU state from raw-ring mode to correct values.
    944  *
    945  * This function will change any selector registers with DPL=1 to DPL=0.
    946  *
    947  * @returns Adjusted rc.
    948  * @param   pVM         VM handle.
    949  * @param   rc          Raw mode return code
    950  * @param   pCtxCore    The context core (for trap usage).
    951  * @see     @ref pg_raw
    952  */
    953 CPUMDECL(int) CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
    954 
    955 /**
    956  * Gets the EFLAGS while we're in raw-mode.
    957  *
    958  * @returns The eflags.
    959  * @param   pVM         The VM handle.
    960  * @param   pCtxCore    The context core.
    961  */
    962 CPUMDECL(uint32_t) CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
    963 
    964 /**
    965  * Updates the EFLAGS while we're in raw-mode.
    966  *
    967  * @param   pVM         The VM handle.
    968  * @param   pCtxCore    The context core.
    969  * @param   eflags      The new EFLAGS value.
    970  */
    971 CPUMDECL(void) CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
    972 
    973 /**
    974  * Lazily sync in the FPU/XMM state
    975  *
    976  * This function will change any selector registers with DPL=1 to DPL=0.
    977  *
    978  * @returns VBox status code.
    979  * @param   pVM         VM handle.
    980  */
    981 CPUMDECL(int) CPUMHandleLazyFPU(PVM pVM);
    982 
    983 
    984 /**
    985  * Restore host FPU/XMM state
    986  *
    987  * @returns VBox status code.
    988  * @param   pVM         VM handle.
    989  */
    990 CPUMDECL(int) CPUMRestoreHostFPUState(PVM pVM);
     859CPUMDECL(void)      CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore);
     860CPUMDECL(int)       CPUMRawEnter(PVM pVM, PCPUMCTXCORE pCtxCore);
     861CPUMDECL(int)       CPUMRawLeave(PVM pVM, PCPUMCTXCORE pCtxCore, int rc);
     862CPUMDECL(uint32_t)  CPUMRawGetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore);
     863CPUMDECL(void)      CPUMRawSetEFlags(PVM pVM, PCPUMCTXCORE pCtxCore, uint32_t eflags);
     864CPUMDECL(int)       CPUMHandleLazyFPU(PVM pVM);
     865CPUMDECL(int)       CPUMRestoreHostFPUState(PVM pVM);
    991866
    992867/** @name Changed flags
    … …  
    1011886/** @} */
    1012887
    1013 /**
    1014  * Gets and resets the changed flags (CPUM_CHANGED_*).
    1015  *
    1016  * @returns The changed flags.
    1017  * @param   pVM     VM handle.
    1018  */
    1019 CPUMDECL(unsigned) CPUMGetAndClearChangedFlagsREM(PVM pVM);
    1020 
    1021 /**
    1022  * Sets the specified changed flags (CPUM_CHANGED_*).
    1023  *
    1024  * @param   pVM     The VM handle.
    1025  */
    1026 CPUMDECL(void) CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
    1027 
    1028 /**
    1029  * Checks if the CPU supports the FXSAVE and FXRSTOR instruction.
    1030  * @returns true if supported.
    1031  * @returns false if not supported.
    1032  * @param   pVM     The VM handle.
    1033  */
    1034 CPUMDECL(bool) CPUMSupportsFXSR(PVM pVM);
    1035 
    1036 /**
    1037  * Checks if the host OS uses the SYSENTER / SYSEXIT instructions.
    1038  * @returns true if used.
    1039  * @returns false if not used.
    1040  * @param   pVM     The VM handle.
    1041  */
    1042 CPUMDECL(bool) CPUMIsHostUsingSysEnter(PVM pVM);
    1043 
    1044 /**
    1045  * Checks if the host OS uses the SYSCALL / SYSRET instructions.
    1046  * @returns true if used.
    1047  * @returns false if not used.
    1048  * @param   pVM     The VM handle.
    1049  */
    1050 CPUMDECL(bool) CPUMIsHostUsingSysCall(PVM pVM);
    1051 
    1052 /**
    1053  * Checks if we activated the FPU/XMM state of the guest OS
    1054  * @returns true if we did.
    1055  * @returns false if not.
    1056  * @param   pVM     The VM handle.
    1057  */
    1058 CPUMDECL(bool) CPUMIsGuestFPUStateActive(PVM pVM);
    1059 
    1060 /**
    1061  * Deactivate the FPU/XMM state of the guest OS
    1062  * @param   pVM     The VM handle.
    1063  */
    1064 CPUMDECL(void) CPUMDeactivateGuestFPUState(PVM pVM);
    1065 
    1066 /**
    1067  * Checks if the guest debug state is active
    1068  *
    1069  * @returns boolean
    1070  * @param   pVM         VM handle.
    1071  */
    1072 CPUMDECL(bool) CPUMIsGuestDebugStateActive(PVM pVM);
    1073 
    1074 /**
    1075  * Mark the guest's debug state as inactive
    1076  *
    1077  * @returns boolean
    1078  * @param   pVM         VM handle.
    1079  */
    1080 CPUMDECL(void) CPUMDeactivateGuestDebugtate(PVM pVM);
    1081 
    1082 
    1083 /**
    1084  * Checks if the hidden selector registers are valid
    1085  * @returns true if they are.
    1086  * @returns false if not.
    1087  * @param   pVM     The VM handle.
    1088  */
    1089 CPUMDECL(bool) CPUMAreHiddenSelRegsValid(PVM pVM);
    1090 
    1091 /**
    1092  * Checks if the hidden selector registers are valid
    1093  * @param   pVM     The VM handle.
    1094  * @param   fValid  Valid or not
    1095  */
    1096 CPUMDECL(void) CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
    1097 
    1098 /**
    1099  * Get the current privilege level of the guest.
    1100  *
    1101  * @returns cpl
    1102  * @param   pVM         VM Handle.
    1103  * @param   pRegFrame   Trap register frame.
    1104  */
    1105 CPUMDECL(uint32_t) CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
     888CPUMDECL(unsigned)  CPUMGetAndClearChangedFlagsREM(PVM pVM);
     889CPUMDECL(void)      CPUMSetChangedFlags(PVM pVM, uint32_t fChangedFlags);
     890CPUMDECL(bool)      CPUMSupportsFXSR(PVM pVM);
     891CPUMDECL(bool)      CPUMIsHostUsingSysEnter(PVM pVM);
     892CPUMDECL(bool)      CPUMIsHostUsingSysCall(PVM pVM);
     893CPUMDECL(bool)      CPUMIsGuestFPUStateActive(PVM pVM);
     894CPUMDECL(void)      CPUMDeactivateGuestFPUState(PVM pVM);
     895CPUMDECL(bool)      CPUMIsGuestDebugStateActive(PVM pVM);
     896CPUMDECL(void)      CPUMDeactivateGuestDebugState(PVM pVM);
     897CPUMDECL(bool)      CPUMAreHiddenSelRegsValid(PVM pVM);
     898CPUMDECL(void)      CPUMSetHiddenSelRegsValid(PVM pVM, bool fValid);
     899CPUMDECL(uint32_t)  CPUMGetGuestCPL(PVM pVM, PCPUMCTXCORE pCtxCore);
    1106900
    1107901/**
    … …  
    1120914} CPUMMODE;
    1121915
    1122 /**
    1123  * Gets the current guest CPU mode.
    1124  *
    1125  * If paging mode is what you need, check out PGMGetGuestMode().
    1126  *
    1127  * @returns The CPU mode.
    1128  * @param   pVM         The VM handle.
    1129  */
    1130 CPUMDECL(CPUMMODE) CPUMGetGuestMode(PVM pVM);
     916CPUMDECL(CPUMMODE)  CPUMGetGuestMode(PVM pVM);
    1131917
    1132918
    … …  
    1137923 */
    1138924
    1139 /**
    1140  * Initializes the CPUM.
    1141  *
    1142  * @returns VBox status code.
    1143  * @param   pVM         The VM to operate on.
    1144  */
    1145 CPUMR3DECL(int) CPUMR3Init(PVM pVM);
    1146 
    1147 /**
    1148  * Applies relocations to data and code managed by this
    1149  * component. This function will be called at init and
    1150  * whenever the VMM need to relocate it self inside the GC.
    1151  *
    1152  * The CPUM will update the addresses used by the switcher.
    1153  *
    1154  * @param   pVM     The VM.
    1155  */
    1156 CPUMR3DECL(void) CPUMR3Relocate(PVM pVM);
    1157 
    1158 /**
    1159  * Terminates the CPUM.
    1160  *
    1161  * Termination means cleaning up and freeing all resources,
    1162  * the VM it self is at this point powered off or suspended.
    1163  *
    1164  * @returns VBox status code.
    1165  * @param   pVM         The VM to operate on.
    1166  */
    1167 CPUMR3DECL(int) CPUMR3Term(PVM pVM);
    1168 
    1169 /**
    1170  * Resets the CPU.
    1171  *
    1172  * @param   pVM         The VM handle.
    1173  */
    1174 CPUMR3DECL(void) CPUMR3Reset(PVM pVM);
    1175 
    1176 /**
    1177  * Queries the pointer to the internal CPUMCTX structure
    1178  *
    1179  * @returns VBox status code.
    1180  * @param   pVM         Handle to the virtual machine.
    1181  * @param   ppCtx       Receives the CPUMCTX GC pointer when successful.
    1182  */
    1183 CPUMR3DECL(int) CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
    1184 
    1185 
    1186 #ifdef DEBUG
    1187 /**
    1188  * Debug helper - Saves guest context on raw mode entry (for fatal dump)
    1189  *
    1190  * @internal
    1191  */
    1192 CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM);
    1193 #endif
    1194 
    1195 /**
    1196  * API for controlling a few of the CPU features found in CR4.
    1197  *
    1198  * Currently only X86_CR4_TSD is accepted as input.
    1199  *
    1200  * @returns VBox status code.
    1201  *
    1202  * @param   pVM     The VM handle.
    1203  * @param   fOr     The CR4 OR mask.
    1204  * @param   fAnd    The CR4 AND mask.
    1205  */
    1206 CPUMR3DECL(int) CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
     925CPUMR3DECL(int)     CPUMR3Init(PVM pVM);
     926CPUMR3DECL(void)    CPUMR3Relocate(PVM pVM);
     927CPUMR3DECL(int)     CPUMR3Term(PVM pVM);
     928CPUMR3DECL(void)    CPUMR3Reset(PVM pVM);
     929CPUMR3DECL(int)     CPUMR3QueryGuestCtxGCPtr(PVM pVM, RCPTRTYPE(PCPUMCTX) *ppCtx);
     930# ifdef DEBUG
     931CPUMR3DECL(void)    CPUMR3SaveEntryCtx(PVM pVM);
     932# endif
     933CPUMR3DECL(int)     CPUMR3SetCR4Feature(PVM pVM, RTHCUINTREG fOr, RTHCUINTREG fAnd);
    1207934
    1208935/** @} */
    1209 #endif
     936#endif /* IN_RING3 */
    1210937
    1211938#ifdef IN_GC
    … …  
    1227954 *
    1228955 * This function does not return!
    1229  *
    1230  */
    1231 DECLASM(void) CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
    1232 
    1233 /**
    1234  * Performs an iret to V86 code
    1235  * Assumes a trap stack frame has already been setup on the guest's stack!
    1236  *
    1237  * @param   pRegFrame   Original trap/interrupt context
    1238  *
    1239  * This function does not return!
    1240  */
    1241 CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
     956 */
     957DECLASM(void)       CPUMGCCallGuestTrapHandler(PCPUMCTXCORE pRegFrame, uint32_t selCS, RTRCPTR pHandler, uint32_t eflags, uint32_t selSS, RTRCPTR pEsp);
     958CPUMGCDECL(void)    CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
    1242959
    1243960/** @} */
    1244 #endif
     961#endif /* IN_GC */
    1245962
    1246963#ifdef IN_RING0
    … …  
    1249966 * @{
    1250967 */
    1251 
    1252 /**
    1253  * Does Ring-0 CPUM initialization.
    1254  *
    1255  * This is mainly to check that the Host CPU mode is compatible
    1256  * with VBox.
    1257  *
    1258  * @returns VBox status code.
    1259  * @param   pVM         The VM to operate on.
    1260  */
    1261968CPUMR0DECL(int) CPUMR0Init(PVM pVM);
    1262 
    1263 /**
    1264  * Lazily sync in the FPU/XMM state
    1265  *
    1266  * @returns VBox status code.
    1267  * @param   pVM         VM handle.
    1268  * @param   pCtx        CPU context
    1269  */
    1270969CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx);
    1271 
    1272 /**
    1273  * Save guest FPU/XMM state
    1274  *
    1275  * @returns VBox status code.
    1276  * @param   pVM         VM handle.
    1277  * @param   pCtx        CPU context
    1278  */
    1279970CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx);
    1280 
    1281 /**
    1282  * Save guest debug state
    1283  *
    1284  * @returns VBox status code.
    1285  * @param   pVM         VM handle.
    1286  * @param   pCtx        CPU context
    1287  * @param   fDR6        Include DR6 or not
    1288  */
    1289971CPUMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
    1290 
    1291 /**
    1292  * Lazily sync in the debug state
    1293  *
    1294  * @returns VBox status code.
    1295  * @param   pVM         VM handle.
    1296  * @param   pCtx        CPU context
    1297  * @param   fDR6        Include DR6 or not
    1298  */
    1299972CPUMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6);
    1300973
    1301974/** @} */
    1302 #endif
     975#endif /* IN_RING0 */
    1303976
    1304977/** @} */

  • trunk/include/VBox/cpumdis.h

    r8155 r12657  
    4444
    4545#ifdef IN_RING3
    46 
    47 /**
    48  * Disassemble an instruction and return the information in the provided structure.
    49  *
    50  * @returns VBox status code.
    51  * @param   pVM         VM Handle
    52  * @param   pCtx        CPU context
    53  * @param   GCPtrPC     Program counter (relative to CS) to disassemble from.
    54  * @param   pCpu        Disassembly state
    55  * @param   pszPrefix   String prefix for logging (debug only)
    56  *
    57  */
    5846CPUMR3DECL(int) CPUMR3DisasmInstrCPU(PVM pVM, PCPUMCTX pCtx, RTGCPTR GCPtrPC, PDISCPUSTATE pCpu, const char *pszPrefix);
    5947
    6048# ifdef DEBUG
    61 /**
    62  * Disassemble an instruction and dump it to the log
    63  *
    64  * @returns VBox status code.
    65  * @param   pVM         VM Handle
    66  * @param   pCtx        CPU context
    67  * @param   pc          GC instruction pointer
    68  * @param   prefix      String prefix for logging
    69  *
    70  * @deprecated  Use DBGFR3DisasInstrCurrentLog().
    71  */
     49/** @deprecated  Use DBGFR3DisasInstrCurrentLog().  */
    7250CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix);
    73 
    74 /**
    75  * Disassemble an instruction and dump it to the log
    76  *
    77  * @returns VBox status code.
    78  * @param   pVM         VM Handle
    79  * @param   pCtx        CPU context
    80  * @param   pc          GC instruction pointer
    81  * @param   prefix      String prefix for logging
    82  * @param   nrInstructions
    83  *
    84  * @deprecated  Create new DBGFR3Disas function to do this.
    85  */
     51/** @deprecated  Create new DBGFR3Disas function to do this. */
    8652CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions);
    87 
    8853# else
    89 #  define CPUMR3DisasmInstr(pVM, pCtx, pc, prefix)
    90 #  define CPUMR3DisasmBlock(pVM, pCtx, pc, prefix, nrInstructions)
     54/** @deprecated  Use DBGFR3DisasInstrCurrentLog(). */
     55#  define CPUMR3DisasmInstr(pVM, pCtx, pc, prefix)  do {} while (0)
     56/** @deprecated  Create new DBGFR3Disas function to do this. */
     57#  define CPUMR3DisasmBlock(pVM, pCtx, pc, prefix, nrInstructions) do {} while (0)
    9158# endif
    9259

  • trunk/include/VBox/vm.h

    r12579 r12657  
    466466    STAMPROFILEADV      StatSwitcherTSS;
    467467
     468/** @todo Realign everything on 64 byte boundraries to better match the
     469 *        cache-line size. */
    468470    /* padding - the unions must be aligned on 32 bytes boundraries. */
    469     uint32_t            padding[HC_ARCH_BITS == 32 ? 4 : 6];
     471    uint32_t            padding[HC_ARCH_BITS == 32 ? 4+8 : 6];
    470472
    471473    /** CPUM part. */
    … …  
    635637    } rem;
    636638
    637 #if HC_ARCH_BITS == 64
    638639    /** Padding for aligning the cpu array on a 64 byte boundrary. */
    639     uint32_t u32Reserved2[HC_ARCH_BITS == 32 ? 0 : 8];
    640 #endif
     640    uint32_t u32Reserved2[8];
    641641
    642642    /**

  • trunk/include/VBox/vm.mac

    r12545 r12657  
    9393    .StatSwitcherTSS      resb STAMPROFILEADV_size
    9494
    95     alignb 32
     95    alignb 64
    9696    .cpum                 resb 4416
    9797    .vmm                  resb 1024

  • trunk/src/VBox/VMM/CPUM.cpp

    r12600 r12657  
    2828 * There are three CPU contexts, the most important one is the guest one (GC).
    2929 * When running in raw-mode (RC) there is a special hyper context for the VMM
    30  * that floats around inside the guest address space. When running in raw-mode
    31  * or when using 64-bit guests on a 32-bit host, CPUM also maintains a host
    32  * context for saving and restoring registers accross world switches. This latter
    33  * is done in cooperation with the world switcher (@see pg_vmm).
     30 * part that floats around inside the guest address space. When running in
     31 * raw-mode, CPUM also maintains a host context for saving and restoring
     32 * registers accross world switches. This latter is done in cooperation with the
     33 * world switcher (@see pg_vmm).
    3434 */
    3535
    … …  
    6565*******************************************************************************/
    6666/** The saved state version. */
     67#define CPUM_SAVED_STATE_VERSION            8
     68/** The saved state version of 1.6, used for backwards compatability. */
    6769#define CPUM_SAVED_STATE_VERSION_VER1_6     6
    68 #define CPUM_SAVED_STATE_VERSION            8
    6970
    7071
    … …  
    8586/** Pointer to a cpu info dump type. */
    8687typedef CPUMDUMPTYPE *PCPUMDUMPTYPE;
     88
    8789
    8890/*******************************************************************************
    … …  
    119121     * Setup any fixed pointers and offsets.
    120122     */
    121     pVM->cpum.s.offVM = RT_OFFSETOF(VM, cpum);
    122     pVM->cpum.s.pCPUMHC = &pVM->cpum.s;
    123123    pVM->cpum.s.pHyperCoreR3 = CPUMCTX2CORE(&pVM->cpum.s.Hyper);
    124124    pVM->cpum.s.pHyperCoreR0 = VM_R0_ADDR(pVM, CPUMCTX2CORE(&pVM->cpum.s.Hyper));
    … …  
    130130     * Check that the CPU supports the minimum features we require.
    131131     */
    132     /** @todo check the contract! */
    133132    if (!ASMHasCpuId())
    134133    {
    … …  
    510509     * Load CPUID overrides from configuration.
    511510     */
     511    /** @cfgm{CPUM/CPUID/[000000xx|800000xx|c000000x]/[eax|ebx|ecx|edx],32-bit}
     512     * Overloads the CPUID leaf values. */
    512513    PCPUMCPUID  pCpuId = &pCPUM->aGuestCpuIdStd[0];
    513514    uint32_t    cElements = RT_ELEMENTS(pCPUM->aGuestCpuIdStd);
    … …  
    603604     * Switcher pointers.
    604605     */
    605     pVM->cpum.s.pCPUMGC = VM_GUEST_ADDR(pVM, &pVM->cpum.s);
    606     pVM->cpum.s.pHyperCoreGC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
    607     Assert(pVM->cpum.s.pHyperCoreGC != NIL_RTGCPTR);
     606    pVM->cpum.s.pHyperCoreRC = MMHyperCCToRC(pVM, pVM->cpum.s.pHyperCoreR3);
     607    Assert(pVM->cpum.s.pHyperCoreRC != NIL_RTRCPTR);
    608608}
    609609
    … …  
    714714    pCtx->fpu.FCW                   = 0x37f;
    715715
    716     /* Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
     716    /* Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Table 8-1. IA-32 Processor States Following Power-up, Reset, or INIT */
    717717    pCtx->fpu.MXCSR                 = 0x1F80;
    718718
    … …  
    765765}
    766766
     767
    767768/**
    768769 * Load a version 1.6 CPUMCTX structure.
    … …  
    774775static void cpumR3LoadCPUM1_6(PVM pVM, CPUMCTX_VER1_6 *pCpumctx16)
    775776{
    776 #define CPUMCTX16_LOADREG(regname)      pVM->cpum.s.Guest.regname = pCpumctx16->regname;
    777 
    778 #define CPUMCTX16_LOADDRXREG(regname)   pVM->cpum.s.Guest.dr[regname] = pCpumctx16->dr##regname;
    779 
    780 #define CPUMCTX16_LOADHIDREG(regname)                                                   \
    781     pVM->cpum.s.Guest.regname##Hid.u64Base      = pCpumctx16->regname##Hid.u32Base;     \
    782     pVM->cpum.s.Guest.regname##Hid.u32Limit     = pCpumctx16->regname##Hid.u32Limit;    \
    783     pVM->cpum.s.Guest.regname##Hid.Attr         = pCpumctx16->regname##Hid.Attr;
    784 
    785 #define CPUMCTX16_LOADSEGREG(regname)                                                   \
    786     pVM->cpum.s.Guest.regname                   = pCpumctx16->regname;                  \
    787     CPUMCTX16_LOADHIDREG(regname);
    788 
    789     pVM->cpum.s.Guest.fpu               = pCpumctx16->fpu;
     777#define CPUMCTX16_LOADREG(RegName) \
     778        pVM->cpum.s.Guest.RegName = pCpumctx16->RegName;
     779
     780#define CPUMCTX16_LOADDRXREG(RegName) \
     781        pVM->cpum.s.Guest.dr[RegName] = pCpumctx16->dr##RegName;
     782
     783#define CPUMCTX16_LOADHIDREG(RegName) \
     784        pVM->cpum.s.Guest.RegName##Hid.u64Base  = pCpumctx16->RegName##Hid.u32Base; \
     785        pVM->cpum.s.Guest.RegName##Hid.u32Limit = pCpumctx16->RegName##Hid.u32Limit; \
     786        pVM->cpum.s.Guest.RegName##Hid.Attr     = pCpumctx16->RegName##Hid.Attr;
     787
     788#define CPUMCTX16_LOADSEGREG(RegName) \
     789        pVM->cpum.s.Guest.RegName = pCpumctx16->RegName; \
     790        CPUMCTX16_LOADHIDREG(RegName);
     791
     792    pVM->cpum.s.Guest.fpu = pCpumctx16->fpu;
    790793
    791794    CPUMCTX16_LOADREG(rax);
    … …  
    851854    CPUMCTX16_LOADHIDREG(tr);
    852855
     856#undef CPUMCTX16_LOADSEGREG
    853857#undef CPUMCTX16_LOADHIDREG
    854 #undef CPUMCTX16_LOADSEGREG
     858#undef CPUMCTX16_LOADDRXREG
    855859#undef CPUMCTX16_LOADREG
    856860}
     861
    857862
    858863/**
    … …  
    977982     * Format the flags.
    978983     */
    979     static struct
     984    static const struct
    980985    {
    981986        const char *pszSet; const char *pszClear; uint32_t fFlag;
    … …  
    10391044        case CPUMDUMPTYPE_TERSE:
    10401045            if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
    1041             {
    10421046                pHlp->pfnPrintf(pHlp,
    10431047                    "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
    … …  
    10531057                    pszPrefix, (RTSEL)pCtxCore->cs, pszPrefix, (RTSEL)pCtxCore->ss, pszPrefix, (RTSEL)pCtxCore->ds, pszPrefix, (RTSEL)pCtxCore->es,
    10541058                    pszPrefix, (RTSEL)pCtxCore->fs, pszPrefix, (RTSEL)pCtxCore->gs, pszPrefix, efl);
    1055             }
    10561059            else
    10571060                pHlp->pfnPrintf(pHlp,
    … …  
    10671070        case CPUMDUMPTYPE_DEFAULT:
    10681071            if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
    1069             {
    10701072                pHlp->pfnPrintf(pHlp,
    10711073                    "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
    … …  
    10851087                    pszPrefix, pCtx->cr0, pszPrefix, pCtx->cr2, pszPrefix, pCtx->cr3, pszPrefix, pCtx->cr4,
    10861088                    pszPrefix, pCtx->gdtr.pGdt, pCtx->gdtr.cbGdt, pszPrefix, (RTSEL)pCtx->ldtr);
    1087             }
    10881089            else
    10891090                pHlp->pfnPrintf(pHlp,
    … …  
    11031104        case CPUMDUMPTYPE_VERBOSE:
    11041105            if (CPUMIsGuestIn64BitCode(pVM, pCtxCore))
    1105             {
    11061106                pHlp->pfnPrintf(pHlp,
    11071107                    "%srax=%016RX64 %srbx=%016RX64 %srcx=%016RX64 %srdx=%016RX64\n"
    … …  
    11411141                    pszPrefix, (RTSEL)pCtx->tr, pCtx->trHid.u64Base, pCtx->trHid.u32Limit, pCtx->trHid.Attr.u,
    11421142                    pszPrefix, pCtx->SysEnter.cs, pCtx->SysEnter.eip, pCtx->SysEnter.esp);
    1143             }
    11441143            else
    11451144                pHlp->pfnPrintf(pHlp,
    … …  
    11811180                pszPrefix, pCtx->fpu.MXCSR, pszPrefix, pCtx->fpu.MXCSR_MASK);
    11821181
    1183 
    11841182            pHlp->pfnPrintf(pHlp,
    11851183                "MSR:\n"
    … …  
    11981196                pszPrefix, pCtx->msrSFMASK,
    11991197                pszPrefix, pCtx->msrKERNELGSBASE);
    1200 
    12011198            break;
    12021199    }
    … …  
    12761273    cpumR3InfoOne(pVM, &pVM->cpum.s.Guest, CPUMCTX2CORE(&pVM->cpum.s.Guest), pHlp, enmType, "");
    12771274}
     1275
    12781276
    12791277/**
    … …  
    22602258 * @param   pc          GC instruction pointer
    22612259 * @param   prefix      String prefix for logging
     2260 *
    22622261 * @deprecated  Use DBGFR3DisasInstrCurrentLog().
    2263  *
    22642262 */
    22652263CPUMR3DECL(void) CPUMR3DisasmInstr(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix)
    22662264{
    2267     DISCPUSTATE cpu;
    2268 
    2269     CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &cpu, prefix);
    2270 }
     2265    DISCPUSTATE Cpu;
     2266    CPUMR3DisasmInstrCPU(pVM, pCtx, pc, &Cpu, prefix);
     2267}
     2268
    22712269
    22722270/**
    … …  
    22802278 * @param   nrInstructions
    22812279 *
     2280 * @deprecated  Create new DBGFR3Disas function to do this.
    22822281 */
    22832282CPUMR3DECL(void) CPUMR3DisasmBlock(PVM pVM, PCPUMCTX pCtx, RTGCPTR pc, char *prefix, int nrInstructions)
    22842283{
    2285     for(int i=0;i<nrInstructions;i++)
     2284    for (int i = 0; i < nrInstructions; i++)
    22862285    {
    22872286        DISCPUSTATE cpu;
    … …  
    22922291}
    22932292
     2293
     2294/**
     2295 * Debug helper - Saves guest context on raw mode entry (for fatal dump)
     2296 *
     2297 * @internal
     2298 */
     2299CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
     2300{
     2301    pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
     2302}
     2303
    22942304#endif /* DEBUG */
    2295 
    2296 #ifdef DEBUG
    2297 /**
    2298  * Debug helper - Saves guest context on raw mode entry (for fatal dump)
    2299  *
    2300  * @internal
    2301  */
    2302 CPUMR3DECL(void) CPUMR3SaveEntryCtx(PVM pVM)
    2303 {
    2304     pVM->cpum.s.GuestEntry = pVM->cpum.s.Guest;
    2305 }
    2306 #endif /* DEBUG */
    2307 
    23082305
    23092306/**

  • trunk/src/VBox/VMM/CPUMInternal.h

    r10687 r12657  
    8585
    8686/**
    87  * The save host CPU state.
     87 * The saved host CPU state.
    8888 *
    8989 * @remark  The special VBOX_WITH_HYBIRD_32BIT_KERNEL checks here are for the 10.4.x series
    … …  
    189189    CPUMSYSENTER    SysEnter;
    190190
    191     /* padding to get 32byte aligned size */
    192     uint8_t         auPadding[24];
     191    /* padding to get 64byte aligned size */
     192    uint8_t         auPadding[24+32];
    193193
    194194#elif HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL)
    … …  
    236236    /* padding to get 32byte aligned size */
    237237# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
    238     uint8_t         auPadding[16];
     238    uint8_t         auPadding[16+32];
    239239# else
    240     uint8_t         auPadding[8];
     240    uint8_t         auPadding[8+32];
    241241# endif
    242242
    … …  
    244244# error HC_ARCH_BITS not defined
    245245#endif
    246 } CPUMHOSTCTX, *PCPUMHOSTCTX;
    247 
    248 
    249 /**
    250  * Converts a CPUM pointer into a VM pointer.
    251  * @returns Pointer to the VM structure the CPUM is part of.
    252  * @param   pCPUM   Pointer to CPUM instance data.
    253  */
    254 #define CPUM2VM(pCPUM)  ( (PVM)((char*)pCPUM - pCPUM->offVM) )
     246} CPUMHOSTCTX;
     247/** Pointer to the saved host CPU state. */
     248typedef CPUMHOSTCTX *PCPUMHOSTCTX;
    255249
    256250
    … …  
    258252 * CPUM Data (part of VM)
    259253 */
    260 #pragma pack(1)
    261254typedef struct CPUM
    262255{
    263     /** Offset to the VM structure. */
    264     RTUINT          offVM;
    265     /** Pointer to CPU structure in GC. */
    266     RCPTRTYPE(struct CPUM *) pCPUMGC;
    267     /** Pointer to CPU structure in HC. */
    268     R3R0PTRTYPE(struct CPUM *) pCPUMHC;
    269 
    270     /** Force 32byte alignment of the next member. */
    271     uint32_t        padding[4 + (HC_ARCH_BITS == 32)];
    272 
    273256    /**
    274257     * Saved host context. Only valid while inside GC.
    275      * Must be aligned on 16 byte boundrary.
    276      */
    277     CPUMHOSTCTX     Host;
     258     * Aligned on a 64-byte boundrary.
     259     */
     260    CPUMHOSTCTX             Host;
    278261
    279262    /**
    280263     * Hypervisor context.
    281      * Must be aligned on 16 byte boundrary.
    282      */
    283     CPUMCTX         Hyper;
     264     * Aligned on a 64-byte boundrary.
     265     */
     266    CPUMCTX                 Hyper;
    284267
    285268    /**
    286269     * Guest context.
    287      * Must be aligned on 16 byte boundrary.
    288      */
    289     CPUMCTX         Guest;
     270     * Aligned on a 64-byte boundrary.
     271     */
     272    CPUMCTX                 Guest;
    290273
    291274
    … …  
    294277    /** Pointer to the current hypervisor core context - R3Ptr. */
    295278    R0PTRTYPE(PCPUMCTXCORE) pHyperCoreR0;
    296     /** Pointer to the current hypervisor core context - GCPtr. */
    297     RCPTRTYPE(PCPUMCTXCORE) pHyperCoreGC;
     279    /** Pointer to the current hypervisor core context - RCPtr. */
     280    RCPTRTYPE(PCPUMCTXCORE) pHyperCoreRC;
    298281
    299282    /** Use flags.
    300283     * These flags indicates both what is to be used and what have been used.
    301284     */
    302     uint32_t        fUseFlags;
     285    uint32_t                fUseFlags;
    303286
    304287    /** Changed flags.
    … …  
    307290     * See the CPUM_CHANGED_* defines for what we keep track of.
    308291     */
    309     uint32_t        fChanged;
     292    uint32_t                fChanged;
    310293
    311294    /** Hidden selector registers state.
    312295     *  Valid (hw accelerated raw mode) or not (normal raw mode)
    313296     */
    314     uint32_t        fValidHiddenSelRegs;
     297    uint32_t                fValidHiddenSelRegs;
    315298
    316299    /** Host CPU Features - ECX */
    … …  
    321304        /** ecx part */
    322305        X86CPUIDFEATECX     ecx;
    323     }   CPUFeatures;
     306    } CPUFeatures;
    324307    /** Host extended CPU features. */
    325308    struct
    326309    {
    327310        /** edx part */
    328         uint32_t     edx;
     311        uint32_t            edx;
    329312        /** ecx part */
    330         uint32_t     ecx;
    331     }   CPUFeaturesExt;
     313        uint32_t            ecx;
     314    } CPUFeaturesExt;
    332315
    333316    /* CPU manufacturer. */
    … …  
    337320    struct
    338321    {
    339         uint32_t AndMask;
    340         uint32_t OrMask;
     322        uint32_t            AndMask;
     323        uint32_t            OrMask;
    341324    } CR4;
    342325
    … …  
    354337    CPUMCPUID               GuestCpuIdDef;
    355338
     339    /** Align the next member, and thereby the structure, on a 64-byte boundrary. */
     340    uint8_t                 abPadding2[HC_ARCH_BITS == 32 ? 56 : 44];
     341
    356342    /**
    357343     * Guest context on raw mode entry.
    358      * This a debug feature.
    359      */
    360     CPUMCTX         GuestEntry;
    361 } CPUM, *PCPUM;
    362 #pragma pack()
    363 
    364 #ifdef IN_RING3
    365 
    366 #endif
     344     * This a debug feature, see CPUMR3SaveEntryCtx.
     345     */
     346    CPUMCTX                 GuestEntry;
     347} CPUM;
     348/** Pointer to the CPUM instance data residing in the shared VM structure. */
     349typedef CPUM *PCPUM;
    367350
    368351__BEGIN_DECLS
    … …  
    384367
    385368#endif
     369

  • trunk/src/VBox/VMM/CPUMInternal.mac

    r12600 r12657  
    11; $Id$
    22;; @file
    3 ; CPUM - Internal header file.
     3; CPUM - Internal header file (asm).
    44;
    55
    … …  
    3737%define CPUM_HANDLER_CTXCORE_IN_EBP     RT_BIT(31)
    3838
    39 %define VMMGCRET_USED_FPU       040000000h
    40 
    41 %define FPUSTATE_SIZE           512
     39%define VMMGCRET_USED_FPU               040000000h
     40
     41%define FPUSTATE_SIZE                   512
    4242
    4343;; if anyone figures how to do %if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBIRD_32BIT_KERNEL) in
    … …  
    5050
    5151struc CPUM
    52     .offVM          resd           1
    53     .pCPUMGC        RTGCPTR32_RES  1          ; Guest Context pointer
    54     .pCPUMHC        RTHCPTR_RES    1          ; Host Context pointer
    55 
    56 
    5752    ;
    5853    ; Host context state
    5954    ;
    60     alignb 32
    6155    .Host.fpu            resb    FPUSTATE_SIZE
    6256
    … …  
    169163    ;
    170164    ; Hypervisor Context.
    171     ; (Identical to .Host.*)
    172     ;
    173     alignb 32                           ; the padding
     165    ;
     166    alignb 64                           ; the padding
    174167    .Hyper.fpu            resb    FPUSTATE_SIZE
    175168
    … …  
    266259    .Hyper.trHid.Attr         resd    1
    267260
    268     ; padding
    269 ;;;;    .Hyper.padding            resd    6
    270 
    271 
    272261
    273262    ;
    274263    ; Guest context state
    275     ; (Identical to the two above chunks)
    276     ;
    277     alignb 32
     264    ; (Identical to the .Hyper chunk above.)
     265    ;
     266    alignb 64
    278267    .Guest.fpu            resb    FPUSTATE_SIZE
    279268
    … …  
    370359    .Guest.trHid.Attr         resd    1
    371360
    372     ; padding
    373 ;;;;    .Guest.padding            resd    6
    374 
    375 
    376361
    377362    ;
    378363    ; Other stuff.
    379364    ;
    380     alignb 32
     365    alignb 64
    381366    ; hypervisor core context.
    382367    .pHyperCoreR3         RTR3PTR_RES   1
    383368    .pHyperCoreR0         RTR0PTR_RES   1
    384     .pHyperCoreGC         RTGCPTR32_RES 1
     369    .pHyperCoreRC         RTRCPTR_RES  1
    385370    ;...
    386371    .fUseFlags            resd    1
    … …  
    415400    .GuestCpuIdDef        resb    16
    416401
     402    alignb 64
    417403    ; CPUMCTX debug stuff...
    418404    .GuestEntry           resb   1024
    419 
    420405endstruc
    421406

  • trunk/src/VBox/VMM/VMMAll/CPUMAllA.asm

    r10687 r12657  
    266266ENDPROC     CPUMLoadFPUAsm
    267267
     268
    268269;;
    269270; Restores the guest's FPU/XMM state
    … …  
    285286    ret
    286287ENDPROC CPUMSaveFPUAsm
     288
    287289
    288290;;
    … …  
    310312    movdqa  xmm6, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6]
    311313    movdqa  xmm7, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7]
    312    
     314
    313315%ifdef RT_ARCH_AMD64
    314316    test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
    315317    jz CPUMLoadXMMAsm_done
    316    
     318
    317319    movdqa  xmm8, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*8]
    318320    movdqa  xmm9, [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*9]
    … …  
    354356    movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*6], xmm6
    355357    movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*7], xmm7
    356    
     358
    357359%ifdef RT_ARCH_AMD64
    358360    test qword [xDX + CPUMCTX.msrEFER], MSR_K6_EFER_LMA
    … …  
    367369    movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*14], xmm14
    368370    movdqa  [xDX + CPUMCTX.fpu + X86FXSTATE.aXMM + 16*15], xmm15
    369    
     371
    370372CPUMSaveXMMAsm_done:
    371373%endif
    … …  
    396398ENDPROC   CPUMSetFCW
    397399
     400
    398401;;
    399402; Get the FPU control word
    … …  
    408411
    409412;;
    410 ; Set the MXCSR; 
     413; Set the MXCSR;
    411414;
    412415; @param  u32MXCSR    x86:[esp+4] GCC:rdi MSC:rcx     New MXCSR
    … …  
    428431ENDPROC   CPUMSetMXCSR
    429432
     433
    430434;;
    431435; Get the MXCSR

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp

    r12600 r12657  
    11/* $Id$ */
    22/** @file
    3  * CPUM - CPU Monitor(/Manager) - Gets and Sets.
     3 * CPUM - CPU Monitor(/Manager) - Getters and Setters.
    44 */
    55
    … …  
    3838
    3939
    40 
    4140/** Disable stack frame pointer generation here. */
    4241#if defined(_MSC_VER) && !defined(DEBUG)
    … …  
    5857CPUMDECL(void) CPUMHyperSetCtxCore(PVM pVM, PCPUMCTXCORE pCtxCore)
    5958{
    60     LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTXALLSUFF(pHyperCore), pCtxCore));
     59    LogFlow(("CPUMHyperSetCtxCore: %p/%p/%p -> %p\n", pVM->cpum.s.CTX_SUFF(pHyperCore), pCtxCore));
    6160    if (!pCtxCore)
    6261    {
    … …  
    6463        pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))VM_R3_ADDR(pVM, pCtxCore);
    6564        pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))VM_R0_ADDR(pVM, pCtxCore);
    66         pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
     65        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))VM_GUEST_ADDR(pVM, pCtxCore);
    6766    }
    6867    else
    … …  
    7069        pVM->cpum.s.pHyperCoreR3 = (R3PTRTYPE(PCPUMCTXCORE))MMHyperCCToR3(pVM, pCtxCore);
    7170        pVM->cpum.s.pHyperCoreR0 = (R0PTRTYPE(PCPUMCTXCORE))MMHyperCCToR0(pVM, pCtxCore);
    72         pVM->cpum.s.pHyperCoreGC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
     71        pVM->cpum.s.pHyperCoreRC = (RCPTRTYPE(PCPUMCTXCORE))MMHyperCCToRC(pVM, pCtxCore);
    7372    }
    7473}
    … …  
    8382CPUMDECL(PCCPUMCTXCORE) CPUMGetHyperCtxCore(PVM pVM)
    8483{
    85     return pVM->cpum.s.CTXALLSUFF(pHyperCore);
     84    return pVM->cpum.s.CTX_SUFF(pHyperCore);
    8685}
    8786
    … …  
    105104}
    106105
     106
    107107CPUMDECL(void) CPUMSetHyperGDTR(PVM pVM, uint32_t addr, uint16_t limit)
    108108{
    … …  
    112112}
    113113
     114
    114115CPUMDECL(void) CPUMSetHyperIDTR(PVM pVM, uint32_t addr, uint16_t limit)
    115116{
    … …  
    119120}
    120121
     122
    121123CPUMDECL(void) CPUMSetHyperCR3(PVM pVM, uint32_t cr3)
    122124{
    … …  
    124126}
    125127
     128
    126129CPUMDECL(void) CPUMSetHyperCS(PVM pVM, RTSEL SelCS)
    127130{
    128     pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs = SelCS;
    129 }
     131    pVM->cpum.s.CTX_SUFF(pHyperCore)->cs = SelCS;
     132}
     133
    130134
    131135CPUMDECL(void) CPUMSetHyperDS(PVM pVM, RTSEL SelDS)
    132136{
    133     pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds = SelDS;
    134 }
     137    pVM->cpum.s.CTX_SUFF(pHyperCore)->ds = SelDS;
     138}
     139
    135140
    136141CPUMDECL(void) CPUMSetHyperES(PVM pVM, RTSEL SelES)
    137142{
    138     pVM->cpum.s.CTXALLSUFF(pHyperCore)->es = SelES;
    139 }
     143    pVM->cpum.s.CTX_SUFF(pHyperCore)->es = SelES;
     144}
     145
    140146
    141147CPUMDECL(void) CPUMSetHyperFS(PVM pVM, RTSEL SelFS)
    142148{
    143     pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs = SelFS;
    144 }
     149    pVM->cpum.s.CTX_SUFF(pHyperCore)->fs = SelFS;
     150}
     151
    145152
    146153CPUMDECL(void) CPUMSetHyperGS(PVM pVM, RTSEL SelGS)
    147154{
    148     pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs = SelGS;
    149 }
     155    pVM->cpum.s.CTX_SUFF(pHyperCore)->gs = SelGS;
     156}
     157
    150158
    151159CPUMDECL(void) CPUMSetHyperSS(PVM pVM, RTSEL SelSS)
    152160{
    153     pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss = SelSS;
    154 }
     161    pVM->cpum.s.CTX_SUFF(pHyperCore)->ss = SelSS;
     162}
     163
    155164
    156165CPUMDECL(void) CPUMSetHyperESP(PVM pVM, uint32_t u32ESP)
    157166{
    158     pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp = u32ESP;
    159 }
     167    pVM->cpum.s.CTX_SUFF(pHyperCore)->esp = u32ESP;
     168}
     169
    160170
    161171CPUMDECL(int) CPUMSetHyperEFlags(PVM pVM, uint32_t Efl)
    162172{
    163     pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32 = Efl;
    164     return VINF_SUCCESS;
    165 }
     173    pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32 = Efl;
     174    return VINF_SUCCESS;
     175}
     176
    166177
    167178CPUMDECL(void) CPUMSetHyperEIP(PVM pVM, uint32_t u32EIP)
    168179{
    169     pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip = u32EIP;
    170 }
     180    pVM->cpum.s.CTX_SUFF(pHyperCore)->eip = u32EIP;
     181}
     182
    171183
    172184CPUMDECL(void) CPUMSetHyperTR(PVM pVM, RTSEL SelTR)
    … …  
    175187}
    176188
     189
    177190CPUMDECL(void) CPUMSetHyperLDTR(PVM pVM, RTSEL SelLDTR)
    178191{
    179192    pVM->cpum.s.Hyper.ldtr = SelLDTR;
    180193}
     194
    181195
    182196CPUMDECL(void) CPUMSetHyperDR0(PVM pVM, RTGCUINTREG uDr0)
    … …  
    186200}
    187201
     202
    188203CPUMDECL(void) CPUMSetHyperDR1(PVM pVM, RTGCUINTREG uDr1)
    189204{
    … …  
    192207}
    193208
     209
    194210CPUMDECL(void) CPUMSetHyperDR2(PVM pVM, RTGCUINTREG uDr2)
    195211{
    … …  
    198214}
    199215
     216
    200217CPUMDECL(void) CPUMSetHyperDR3(PVM pVM, RTGCUINTREG uDr3)
    201218{
    … …  
    204221}
    205222
     223
    206224CPUMDECL(void) CPUMSetHyperDR6(PVM pVM, RTGCUINTREG uDr6)
    207225{
    … …  
    210228}
    211229
     230
    212231CPUMDECL(void) CPUMSetHyperDR7(PVM pVM, RTGCUINTREG uDr7)
    213232{
    … …  
    219238CPUMDECL(RTSEL) CPUMGetHyperCS(PVM pVM)
    220239{
    221     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->cs;
    222 }
     240    return pVM->cpum.s.CTX_SUFF(pHyperCore)->cs;
     241}
     242
    223243
    224244CPUMDECL(RTSEL) CPUMGetHyperDS(PVM pVM)
    225245{
    226     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ds;
    227 }
     246    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ds;
     247}
     248
    228249
    229250CPUMDECL(RTSEL) CPUMGetHyperES(PVM pVM)
    230251{
    231     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->es;
    232 }
     252    return pVM->cpum.s.CTX_SUFF(pHyperCore)->es;
     253}
     254
    233255
    234256CPUMDECL(RTSEL) CPUMGetHyperFS(PVM pVM)
    235257{
    236     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->fs;
    237 }
     258    return pVM->cpum.s.CTX_SUFF(pHyperCore)->fs;
     259}
     260
    238261
    239262CPUMDECL(RTSEL) CPUMGetHyperGS(PVM pVM)
    240263{
    241     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->gs;
    242 }
     264    return pVM->cpum.s.CTX_SUFF(pHyperCore)->gs;
     265}
     266
    243267
    244268CPUMDECL(RTSEL) CPUMGetHyperSS(PVM pVM)
    245269{
    246     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ss;
    247 }
    248 
    249 #if 0 /* these are not correct. */
    250 
    251 CPUMDECL(uint32_t) CPUMGetHyperCR0(PVM pVM)
    252 {
    253     return pVM->cpum.s.Hyper.cr0;
    254 }
    255 
    256 CPUMDECL(uint32_t) CPUMGetHyperCR2(PVM pVM)
    257 {
    258     return pVM->cpum.s.Hyper.cr2;
    259 }
    260 
    261 CPUMDECL(uint32_t) CPUMGetHyperCR3(PVM pVM)
    262 {
    263     return pVM->cpum.s.Hyper.cr3;
    264 }
    265 
    266 CPUMDECL(uint32_t) CPUMGetHyperCR4(PVM pVM)
    267 {
    268     return pVM->cpum.s.Hyper.cr4;
    269 }
    270 
    271 #endif /* not correct */
     270    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ss;
     271}
     272
    272273
    273274CPUMDECL(uint32_t) CPUMGetHyperEAX(PVM pVM)
    274275{
    275     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eax;
    276 }
     276    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eax;
     277}
     278
    277279
    278280CPUMDECL(uint32_t) CPUMGetHyperEBX(PVM pVM)
    279281{
    280     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebx;
    281 }
     282    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebx;
     283}
     284
    282285
    283286CPUMDECL(uint32_t) CPUMGetHyperECX(PVM pVM)
    284287{
    285     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ecx;
    286 }
     288    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ecx;
     289}
     290
    287291
    288292CPUMDECL(uint32_t) CPUMGetHyperEDX(PVM pVM)
    289293{
    290     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edx;
    291 }
     294    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edx;
     295}
     296
    292297
    293298CPUMDECL(uint32_t) CPUMGetHyperESI(PVM pVM)
    294299{
    295     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esi;
    296 }
     300    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esi;
     301}
     302
    297303
    298304CPUMDECL(uint32_t) CPUMGetHyperEDI(PVM pVM)
    299305{
    300     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->edi;
    301 }
     306    return pVM->cpum.s.CTX_SUFF(pHyperCore)->edi;
     307}
     308
    302309
    303310CPUMDECL(uint32_t) CPUMGetHyperEBP(PVM pVM)
    304311{
    305     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->ebp;
    306 }
     312    return pVM->cpum.s.CTX_SUFF(pHyperCore)->ebp;
     313}
     314
    307315
    308316CPUMDECL(uint32_t) CPUMGetHyperESP(PVM pVM)
    309317{
    310     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->esp;
    311 }
     318    return pVM->cpum.s.CTX_SUFF(pHyperCore)->esp;
     319}
     320
    312321
    313322CPUMDECL(uint32_t) CPUMGetHyperEFlags(PVM pVM)
    314323{
    315     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eflags.u32;
    316 }
     324    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eflags.u32;
     325}
     326
    317327
    318328CPUMDECL(uint32_t) CPUMGetHyperEIP(PVM pVM)
    319329{
    320     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->eip;
    321 }
     330    return pVM->cpum.s.CTX_SUFF(pHyperCore)->eip;
     331}
     332
    322333
    323334CPUMDECL(uint64_t) CPUMGetHyperRIP(PVM pVM)
    324335{
    325     return pVM->cpum.s.CTXALLSUFF(pHyperCore)->rip;
    326 }
     336    return pVM->cpum.s.CTX_SUFF(pHyperCore)->rip;
     337}
     338
    327339
    328340CPUMDECL(uint32_t) CPUMGetHyperIDTR(PVM pVM, uint16_t *pcbLimit)
    … …  
    333345}
    334346
     347
    335348CPUMDECL(uint32_t) CPUMGetHyperGDTR(PVM pVM, uint16_t *pcbLimit)
    336349{
    … …  
    340353}
    341354
     355
    342356CPUMDECL(RTSEL) CPUMGetHyperLDTR(PVM pVM)
    343357{
    … …  
    345359}
    346360
     361
    347362CPUMDECL(RTGCUINTREG) CPUMGetHyperDR0(PVM pVM)
    348363{
    … …  
    350365}
    351366
     367
    352368CPUMDECL(RTGCUINTREG) CPUMGetHyperDR1(PVM pVM)
    353369{
    … …  
    355371}
    356372
     373
    357374CPUMDECL(RTGCUINTREG) CPUMGetHyperDR2(PVM pVM)
    358375{
    … …  
    360377}
    361378
     379
    362380CPUMDECL(RTGCUINTREG) CPUMGetHyperDR3(PVM pVM)
    363381{
    … …  
    365383}
    366384
     385
    367386CPUMDECL(RTGCUINTREG) CPUMGetHyperDR6(PVM pVM)
    368387{
    369388    return pVM->cpum.s.Hyper.dr[6];
    370389}
     390
    371391
    372392CPUMDECL(RTGCUINTREG) CPUMGetHyperDR7(PVM pVM)
    … …  
    396416CPUMDECL(void) CPUMSetGuestCtxCore(PVM pVM, PCCPUMCTXCORE pCtxCore)
    397417{
    398     /** @todo #1410 requires selectors to be checked. */
     418    /** @todo #1410 requires selectors to be checked. (huh? 1410?) */
    399419
    400420    PCPUMCTXCORE pCtxCoreDst = CPUMCTX2CORE(&pVM->cpum.s.Guest);
    … …  
    511531                ASMSetCR0(HyperCR0);
    512532            }
    513 #ifdef VBOX_STRICT
     533# ifdef VBOX_STRICT
    514534            else
    515535            {
    … …  
    518538                AssertMsg((HyperCR0 & X86_CR0_EM) == (pVM->cpum.s.Guest.cr0 & X86_CR0_EM), ("%#x\n", HyperCR0));
    519539            }
    520 #endif
     540# endif
    521541        }
    522542        else
    … …  
    536556        }
    537557    }
    538 #endif
     558#endif /* IN_GC */
    539559
    540560    /*
    … …  
    551571}
    552572
     573
    553574CPUMDECL(int) CPUMSetGuestCR2(PVM pVM, uint64_t cr2)
    554575{
    … …  
    556577    return VINF_SUCCESS;
    557578}
     579
    558580
    559581CPUMDECL(int) CPUMSetGuestCR3(PVM pVM, uint64_t cr3)
    … …  
    563585    return VINF_SUCCESS;
    564586}
     587
    565588
    566589CPUMDECL(int) CPUMSetGuestCR4(PVM pVM, uint64_t cr4)
    … …  
    576599}
    577600
     601
    578602CPUMDECL(int) CPUMSetGuestEFlags(PVM pVM, uint32_t eflags)
    579603{
    … …  
    582606}
    583607
     608
    584609CPUMDECL(int) CPUMSetGuestEIP(PVM pVM, uint32_t eip)
    585610{
    … …  
    588613}
    589614
     615
    590616CPUMDECL(int) CPUMSetGuestEAX(PVM pVM, uint32_t eax)
    591617{
    … …  
    594620}
    595621
     622
    596623CPUMDECL(int) CPUMSetGuestEBX(PVM pVM, uint32_t ebx)
    597624{
    … …  
    600627}
    601628
     629
    602630CPUMDECL(int) CPUMSetGuestECX(PVM pVM, uint32_t ecx)
    603631{
    … …  
    606634}
    607635
     636
    608637CPUMDECL(int) CPUMSetGuestEDX(PVM pVM, uint32_t edx)
    609638{
    … …  
    612641}
    613642
     643
    614644CPUMDECL(int) CPUMSetGuestESP(PVM pVM, uint32_t esp)
    615645{
    … …  
    618648}
    619649
     650
    620651CPUMDECL(int) CPUMSetGuestEBP(PVM pVM, uint32_t ebp)
    621652{
    … …  
    624655}
    625656
     657
    626658CPUMDECL(int) CPUMSetGuestESI(PVM pVM, uint32_t esi)
    627659{
    … …  
    630662}
    631663
     664
    632665CPUMDECL(int) CPUMSetGuestEDI(PVM pVM, uint32_t edi)
    633666{
    … …  
    636669}
    637670
     671
    638672CPUMDECL(int) CPUMSetGuestSS(PVM pVM, uint16_t ss)
    639673{
    … …  
    642676}
    643677
     678
    644679CPUMDECL(int) CPUMSetGuestCS(PVM pVM, uint16_t cs)
    645680{
    … …  
    648683}
    649684
     685
    650686CPUMDECL(int) CPUMSetGuestDS(PVM pVM, uint16_t ds)
    651687{
    … …  
    654690}
    655691
     692
    656693CPUMDECL(int) CPUMSetGuestES(PVM pVM, uint16_t es)
    657694{
    … …  
    660697}
    661698
     699
    662700CPUMDECL(int) CPUMSetGuestFS(PVM pVM, uint16_t fs)
    663701{
    … …  
    666704}
    667705
     706
    668707CPUMDECL(int) CPUMSetGuestGS(PVM pVM, uint16_t gs)
    669708{
    … …  
    672711}
    673712
     713
    674714CPUMDECL(void) CPUMSetGuestEFER(PVM pVM, uint64_t val)
    675715{
    … …  
    677717}
    678718
     719
    679720CPUMDECL(uint64_t)  CPUMGetGuestMsr(PVM pVM, unsigned idMsr)
    680721{
    681     uint64_t val = 0;
     722    uint64_t u64 = 0;
    682723
    683724    switch (idMsr)
    684725    {
    685     case MSR_IA32_CR_PAT:
    686         val = pVM->cpum.s.Guest.msrPAT;
    687         break;
    688 
    689     case MSR_IA32_SYSENTER_CS:
    690         val = pVM->cpum.s.Guest.SysEnter.cs;
    691         break;
    692 
    693     case MSR_IA32_SYSENTER_EIP:
    694         val = pVM->cpum.s.Guest.SysEnter.eip;
    695         break;
    696 
    697     case MSR_IA32_SYSENTER_ESP:
    698         val = pVM->cpum.s.Guest.SysEnter.esp;
    699         break;
    700 
    701     case MSR_K6_EFER:
    702         val = pVM->cpum.s.Guest.msrEFER;
    703         break;
    704 
    705     case MSR_K8_SF_MASK:
    706         val = pVM->cpum.s.Guest.msrSFMASK;
    707         break;
    708 
    709     case MSR_K6_STAR:
    710         val = pVM->cpum.s.Guest.msrSTAR;
    711         break;
    712 
    713     case MSR_K8_LSTAR:
    714         val = pVM->cpum.s.Guest.msrLSTAR;
    715         break;
    716 
    717     case MSR_K8_CSTAR:
    718         val = pVM->cpum.s.Guest.msrCSTAR;
    719         break;
    720 
    721     case MSR_K8_KERNEL_GS_BASE:
    722         val = pVM->cpum.s.Guest.msrKERNELGSBASE;
    723         break;
    724 
    725     /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
    726     default:
    727         AssertFailed();
    728         break;
     726        case MSR_IA32_CR_PAT:
     727            u64 = pVM->cpum.s.Guest.msrPAT;
     728            break;
     729
     730        case MSR_IA32_SYSENTER_CS:
     731            u64 = pVM->cpum.s.Guest.SysEnter.cs;
     732            break;
     733
     734        case MSR_IA32_SYSENTER_EIP:
     735            u64 = pVM->cpum.s.Guest.SysEnter.eip;
     736            break;
     737
     738        case MSR_IA32_SYSENTER_ESP:
     739            u64 = pVM->cpum.s.Guest.SysEnter.esp;
     740            break;
     741
     742        case MSR_K6_EFER:
     743            u64 = pVM->cpum.s.Guest.msrEFER;
     744            break;
     745
     746        case MSR_K8_SF_MASK:
     747            u64 = pVM->cpum.s.Guest.msrSFMASK;
     748            break;
     749
     750        case MSR_K6_STAR:
     751            u64 = pVM->cpum.s.Guest.msrSTAR;
     752            break;
     753
     754        case MSR_K8_LSTAR:
     755            u64 = pVM->cpum.s.Guest.msrLSTAR;
     756            break;
     757
     758        case MSR_K8_CSTAR:
     759            u64 = pVM->cpum.s.Guest.msrCSTAR;
     760            break;
     761
     762        case MSR_K8_KERNEL_GS_BASE:
     763            u64 = pVM->cpum.s.Guest.msrKERNELGSBASE;
     764            break;
     765
     766        /* fs & gs base skipped on purpose as the current context might not be up-to-date. */
     767        default:
     768            AssertFailed();
     769            break;
    729770    }
    730     return val;
    731 }
     771    return u64;
     772}
     773
    732774
    733775CPUMDECL(RTGCPTR) CPUMGetGuestIDTR(PVM pVM, uint16_t *pcbLimit)
    … …  
    738780}
    739781
     782
    740783CPUMDECL(RTSEL) CPUMGetGuestTR(PVM pVM)
    741784{
    … …  
    743786}
    744787
     788
    745789CPUMDECL(RTSEL) CPUMGetGuestCS(PVM pVM)
    746790{
    … …  
    748792}
    749793
     794
    750795CPUMDECL(RTSEL) CPUMGetGuestDS(PVM pVM)
    751796{
    … …  
    753798}
    754799
     800
    755801CPUMDECL(RTSEL) CPUMGetGuestES(PVM pVM)
    756802{
    … …  
    758804}
    759805
     806
    760807CPUMDECL(RTSEL) CPUMGetGuestFS(PVM pVM)
    761808{
    … …  
    763810}
    764811
     812
    765813CPUMDECL(RTSEL) CPUMGetGuestGS(PVM pVM)
    766814{
    … …  
    768816}
    769817
     818
    770819CPUMDECL(RTSEL) CPUMGetGuestSS(PVM pVM)
    771820{
    … …  
    773822}
    774823
     824
    775825CPUMDECL(RTSEL) CPUMGetGuestLDTR(PVM pVM)
    776826{
    … …  
    778828}
    779829
     830
    780831CPUMDECL(uint64_t) CPUMGetGuestCR0(PVM pVM)
    781832{
    … …  
    783834}
    784835
     836
    785837CPUMDECL(uint64_t) CPUMGetGuestCR2(PVM pVM)
    786838{
    … …  
    788840}
    789841
     842
    790843CPUMDECL(uint64_t) CPUMGetGuestCR3(PVM pVM)
    791844{
    … …  
    793846}
    794847
     848
    795849CPUMDECL(uint64_t) CPUMGetGuestCR4(PVM pVM)
    796850{
    … …  
    798852}
    799853
     854
    800855CPUMDECL(void) CPUMGetGuestGDTR(PVM pVM, PVBOXGDTR pGDTR)
    801856{
    … …  
    803858}
    804859
     860
    805861CPUMDECL(uint32_t) CPUMGetGuestEIP(PVM pVM)
    806862{
    … …  
    808864}
    809865
     866
    810867CPUMDECL(uint64_t) CPUMGetGuestRIP(PVM pVM)
    811868{
    … …  
    813870}
    814871
     872
    815873CPUMDECL(uint32_t) CPUMGetGuestEAX(PVM pVM)
    816874{
    … …  
    818876}
    819877
     878
    820879CPUMDECL(uint32_t) CPUMGetGuestEBX(PVM pVM)
    821880{
    … …  
    823882}
    824883
     884
    825885CPUMDECL(uint32_t) CPUMGetGuestECX(PVM pVM)
    826886{
    … …  
    828888}
    829889
     890
    830891CPUMDECL(uint32_t) CPUMGetGuestEDX(PVM pVM)
    831892{
    … …  
    833894}
    834895
     896
    835897CPUMDECL(uint32_t) CPUMGetGuestESI(PVM pVM)
    836898{
    … …  
    838900}
    839901
     902
    840903CPUMDECL(uint32_t) CPUMGetGuestEDI(PVM pVM)
    841904{
    … …  
    843906}
    844907
     908
    845909CPUMDECL(uint32_t) CPUMGetGuestESP(PVM pVM)
    846910{
    … …  
    848912}
    849913
     914
    850915CPUMDECL(uint32_t) CPUMGetGuestEBP(PVM pVM)
    851916{
    … …  
    853918}
    854919
     920
    855921CPUMDECL(uint32_t) CPUMGetGuestEFlags(PVM pVM)
    856922{
    … …  
    858924}
    859925
     926
    860927CPUMDECL(CPUMSELREGHID *) CPUMGetGuestTRHid(PVM pVM)
    861928{
    … …  
    863930}
    864931
    865 //@todo: crx should be an array
     932
     933///@todo: crx should be an array
    866934CPUMDECL(int) CPUMGetGuestCRx(PVM pVM, unsigned iReg, uint64_t *pValue)
    867935{
    … …  
    886954}
    887955
     956
    888957CPUMDECL(uint64_t) CPUMGetGuestDR0(PVM pVM)
    889958{
    … …  
    891960}
    892961
     962
    893963CPUMDECL(uint64_t) CPUMGetGuestDR1(PVM pVM)
    894964{
    … …  
    896966}
    897967
     968
    898969CPUMDECL(uint64_t) CPUMGetGuestDR2(PVM pVM)
    899970{
    … …  
    901972}
    902973
     974
    903975CPUMDECL(uint64_t) CPUMGetGuestDR3(PVM pVM)
    904976{
    … …  
    906978}
    907979
     980
    908981CPUMDECL(uint64_t) CPUMGetGuestDR6(PVM pVM)
    909982{
    … …  
    911984}
    912985
     986
    913987CPUMDECL(uint64_t) CPUMGetGuestDR7(PVM pVM)
    914988{
    … …  
    916990}
    917991
     992
    918993CPUMDECL(int) CPUMGetGuestDRx(PVM pVM, uint32_t iReg, uint64_t *pValue)
    919994{
    920995    AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
     996    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
     997    if (iReg == 4 || iReg == 5)
     998        iReg += 2;
    921999    *pValue = pVM->cpum.s.Guest.dr[iReg];
    9221000    return VINF_SUCCESS;
    9231001}
    9241002
     1003
    9251004CPUMDECL(uint64_t) CPUMGetGuestEFER(PVM pVM)
    9261005{
    9271006    return pVM->cpum.s.Guest.msrEFER;
    9281007}
     1008
    9291009
    9301010/**
    … …  
    9571037}
    9581038
     1039
    9591040/**
    9601041 * Gets a pointer to the array of standard CPUID leafs.
    … …  
    9711052}
    9721053
     1054
    9731055/**
    9741056 * Gets a pointer to the array of extended CPUID leafs.
    … …  
    9821064CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdExtGCPtr(PVM pVM)
    9831065{
    984     return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
    985 }
     1066    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdExt[0]);
     1067}
     1068
    9861069
    9871070/**
    … …  
    9961079CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdCentaurGCPtr(PVM pVM)
    9971080{
    998     return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
    999 }
     1081    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.aGuestCpuIdCentaur[0]);
     1082}
     1083
    10001084
    10011085/**
    … …  
    10081092CPUMDECL(RCPTRTYPE(PCCPUMCPUID)) CPUMGetGuestCpuIdDefGCPtr(PVM pVM)
    10091093{
    1010     return RCPTRTYPE(PCCPUMCPUID)VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
    1011 }
     1094    return (RCPTRTYPE(PCCPUMCPUID))VM_GUEST_ADDR(pVM, &pVM->cpum.s.GuestCpuIdDef);
     1095}
     1096
    10121097
    10131098/**
    … …  
    10231108}
    10241109
     1110
    10251111/**
    10261112 * Gets a number of extended CPUID leafs.
    … …  
    10351121}
    10361122
     1123
    10371124/**
    10381125 * Gets a number of centaur CPUID leafs.
    … …  
    10461133    return RT_ELEMENTS(pVM->cpum.s.aGuestCpuIdCentaur);
    10471134}
     1135
    10481136
    10491137/**
    … …  
    11961284}
    11971285
     1286
    11981287/**
    11991288 * Queries a CPUID feature bit.
    … …  
    12201309    return false;
    12211310}
     1311
    12221312
    12231313/**
    … …  
    12721362}
    12731363
     1364
    12741365/**
    12751366 * Gets the CPU vendor
    … …  
    12901381}
    12911382
     1383
    12921384CPUMDECL(int) CPUMSetGuestDR1(PVM pVM, uint64_t uDr1)
    12931385{
    … …  
    12961388}
    12971389
     1390
    12981391CPUMDECL(int) CPUMSetGuestDR2(PVM pVM, uint64_t uDr2)
    12991392{
    … …  
    13021395}
    13031396
     1397
    13041398CPUMDECL(int) CPUMSetGuestDR3(PVM pVM, uint64_t uDr3)
    13051399{
    … …  
    13081402}
    13091403
     1404
    13101405CPUMDECL(int) CPUMSetGuestDR6(PVM pVM, uint64_t uDr6)
    13111406{
    … …  
    13141409}
    13151410
     1411
    13161412CPUMDECL(int) CPUMSetGuestDR7(PVM pVM, uint64_t uDr7)
    13171413{
    … …  
    13201416}
    13211417
     1418
    13221419CPUMDECL(int) CPUMSetGuestDRx(PVM pVM, uint32_t iReg, uint64_t Value)
    13231420{
    13241421    AssertReturn(iReg <= USE_REG_DR7, VERR_INVALID_PARAMETER);
     1422    /* DR4 is an alias for DR6, and DR5 is an alias for DR7. */
     1423    if (iReg == 4 || iReg == 5)
     1424        iReg += 2;
    13251425    pVM->cpum.s.Guest.dr[iReg] = Value;
    13261426    return CPUMRecalcHyperDRx(pVM);
    … …  
    16391739
    16401740
    1641 
    1642 
    16431741/**
    16441742 * Gets and resets the changed flags (CPUM_CHANGED_*).
    … …  
    16611759}
    16621760
     1761
    16631762/**
    16641763 * Sets the specified changed flags (CPUM_CHANGED_*).
    … …  
    16701769    pVM->cpum.s.fChanged |= fChangedFlags;
    16711770}
     1771
    16721772
    16731773/**
    … …  
    17061806}
    17071807
    1708 
    17091808#ifndef IN_RING3
     1809
    17101810/**
    17111811 * Lazily sync in the FPU/XMM state
    … …  
    17311831    return CPUMRestoreHostFPUStateAsm(&pVM->cpum.s);
    17321832}
     1833
    17331834#endif /* !IN_RING3 */
    1734 
    17351835
    17361836/**
    … …  
    17561856
    17571857
    1758 
    17591858/**
    17601859 * Checks if the guest debug state is active
    … …  
    17681867}
    17691868
     1869
    17701870/**
    17711871 * Mark the guest's debug state as inactive
    … …  
    17741874 * @param   pVM         VM handle.
    17751875 */
    1776 CPUMDECL(void) CPUMDeactivateGuestDebugtate(PVM pVM)
     1876CPUMDECL(void) CPUMDeactivateGuestDebugState(PVM pVM)
    17771877{
    17781878    pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
    … …  
    18201920         * not affected by loading a conforming coding segment.
    18211921         *
    1822          * This only seems to apply to AMD-V; in the VT-x case we *do* need to look at SS. (ACP2 regression during install after a far call to ring 2)
     1922         * This only seems to apply to AMD-V; in the VT-x case we *do* need to look
     1923         * at SS. (ACP2 regression during install after a far call to ring 2)
    18231924         */
    18241925        cpl = pCtxCore->ssHid.Attr.n.u2Dpl;
    … …  
    18621963    if (!(pVM->cpum.s.Guest.cr0 & X86_CR0_PE))
    18631964        enmMode = CPUMMODE_REAL;
    1864     else
    1865     if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
     1965    else if (!(pVM->cpum.s.Guest.msrEFER & MSR_K6_EFER_LMA))
    18661966        enmMode = CPUMMODE_PROTECTED;
    18671967    else
    … …  
    18701970    return enmMode;
    18711971}
     1972

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r12307 r12657  
    298298    if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
    299299        return rc;
    300     /* 
    301      * The page pool cache may end up here in some cases because it 
    302      * flushed one of the shadow mappings used by the trapping 
     300    /*
     301     * The page pool cache may end up here in some cases because it
     302     * flushed one of the shadow mappings used by the trapping
    303303     * instruction and it either flushed the TLB or the CPU reused it.
    304304     */
    … …  
    319319    if (RT_LIKELY(rc != VERR_ACCESS_DENIED))
    320320        return rc;
    321     /* 
    322      * The page pool cache may end up here in some cases because it 
    323      * flushed one of the shadow mappings used by the trapping 
     321    /*
     322     * The page pool cache may end up here in some cases because it
     323     * flushed one of the shadow mappings used by the trapping
    324324     * instruction and it either flushed the TLB or the CPU reused it.
    325      * We want to play safe here, verifying that we've got write 
     325     * We want to play safe here, verifying that we've got write
    326326     * access doesn't cost us much (see PGMPhysGCPtr2GCPhys()).
    327327     */
    … …  
    331331    if (RT_FAILURE(rc))
    332332        return rc;
    333     if (    !(fFlags & X86_PTE_RW) 
     333    if (    !(fFlags & X86_PTE_RW)
    334334        &&  (CPUMGetGuestCR0(pVM) & X86_CR0_WP))
    335335        return VERR_ACCESS_DENIED;
    … …  
    351351
    352352#if defined(VBOX_STRICT) || defined(LOG_ENABLED)
    353 /** 
     353/**
    354354 * Get the mnemonic for the disassembled instruction.
    355  * 
    356  * GC/R0 doesn't include the strings in the DIS tables because 
    357  * of limited space. 
    358  */ 
     355 *
     356 * GC/R0 doesn't include the strings in the DIS tables because
     357 * of limited space.
     358 */
    359359static const char *emGetMnemonic(PDISCPUSTATE pCpu)
    360360{
    … …  
    803803 * LOCK XOR/OR/AND Emulation.
    804804 */
    805 static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
     805static int emInterpretLockOrXorAnd(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
    806806                                   uint32_t *pcbSize, PFNEMULATELOCKPARAM3 pfnEmulate)
    807807{
    … …  
    10971097 * LOCK BTR/C/S Emulation.
    10981098 */
    1099 static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault, 
     1099static int emInterpretLockBitTest(PVM pVM, PDISCPUSTATE pCpu, PCPUMCTXCORE pRegFrame, RTGCPTR pvFault,
    11001100                                  uint32_t *pcbSize, PFNEMULATELOCKPARAM2 pfnEmulate)
    11011101{
    … …  
    11411141#ifdef IN_GC
    11421142    Assert(TRPMHasTrap(pVM));
    1143     AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault, 
    1144                     ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault), 
     1143    AssertMsgReturn((RTGCPTR)((RTGCUINTPTR)GCPtrPar1 & ~(RTGCUINTPTR)3) == pvFault,
     1144                    ("GCPtrPar1=%VGv pvFault=%VGv\n", GCPtrPar1, pvFault),
    11451145                    VERR_EM_INTERPRETER);
    11461146#endif
    … …  
    11571157    if (RT_FAILURE(rc))
    11581158    {
    1159         Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n", 
     1159        Log(("emInterpretLockBitTest %s: %VGv imm%d=%RX64 -> emulation failed due to page fault!\n",
    11601160             emGetMnemonic(pCpu), GCPtrPar1, pCpu->param2.size*8, ValPar2));
    11611161        return VERR_EM_INTERPRETER;
    … …  
    13951395    }
    13961396    else
    1397     {   
    1398         if (!cTransfers) 
     1397    {
     1398        if (!cTransfers)
    13991399            return VINF_SUCCESS;
    14001400
    … …  
    15171517    else
    15181518        eflags = EMEmulateCmpXchg(pvParam1, &pRegFrame->rax, valpar, pCpu->param2.size);
    1519    
     1519
    15201520    LogFlow(("%s %VGv rax=%RX64 %RX64 ZF=%d\n", pszInstr, GCPtrPar1, pRegFrame->rax, valpar, !!(eflags & X86_EFL_ZF)));
    15211521
    … …  
    20432043        rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
    20442044    }
    2045     else 
     2045    else
    20462046    {
    20472047        uint32_t val32;
    … …  
    20592059#ifdef IN_GC
    20602060            /* CR0.WP and CR0.AM changes require a reschedule run in ring 3. */
    2061             if (    (val    & (X86_CR0_WP | X86_CR0_AM)) 
     2061            if (    (val    & (X86_CR0_WP | X86_CR0_AM))
    20622062                !=  (oldval & (X86_CR0_WP | X86_CR0_AM)))
    20632063                return VERR_EM_INTERPRETER;
    … …  
    22002200        rc = DISFetchReg64(pRegFrame, SrcRegGen, &val);
    22012201    }
    2202     else 
     2202    else
    22032203    {
    22042204        uint32_t val32;
    … …  
    22072207    }
    22082208
    2209     if (VBOX_SUCCESS(rc))
    2210     {
    2211         /* @todo: we don't fail if illegal bits are set/cleared for e.g. dr7 */
     2209    if (RT_SUCCESS(rc))
     2210    {
     2211        /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
    22122212        rc = CPUMSetGuestDRx(pVM, DestRegDrx, val);
    2213         if (VBOX_SUCCESS(rc))
     2213        if (RT_SUCCESS(rc))
    22142214            return rc;
    22152215        AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));

  • trunk/src/VBox/VMM/VMMGC/CPUMGCA.asm

    r9291 r12657  
    11; $Id$
    22;; @file
    3 ;
    43; CPUM - Guest Context Assembly Routines.
     4;
    55
    66; Copyright (C) 2006-2007 Sun Microsystems, Inc.
    … …  
    187187    TRPM_NP_GP_HANDLER NAME(cpumGCHandleNPAndGP), CPUM_HANDLER_IRET
    188188    iret
    189 
    190189ENDPROC CPUMGCCallGuestTrapHandler
     190
    191191
    192192;;
    … …  
    195195;
    196196; @param   pRegFrame   Original trap/interrupt context
    197 ; 
     197;
    198198; This function does not return!
    199 ; 
     199;
    200200;CPUMGCDECL(void) CPUMGCCallV86Code(PCPUMCTXCORE pRegFrame);
    201201align 16
    … …  
    204204
    205205    ; construct iret stack frame
    206     push    dword [ebp + CPUMCTXCORE.gs] 
    207     push    dword [ebp + CPUMCTXCORE.fs] 
    208     push    dword [ebp + CPUMCTXCORE.ds] 
    209     push    dword [ebp + CPUMCTXCORE.es] 
    210     push    dword [ebp + CPUMCTXCORE.ss] 
    211     push    dword [ebp + CPUMCTXCORE.esp] 
    212     push    dword [ebp + CPUMCTXCORE.eflags] 
    213     push    dword [ebp + CPUMCTXCORE.cs] 
    214     push    dword [ebp + CPUMCTXCORE.eip] 
     206    push    dword [ebp + CPUMCTXCORE.gs]
     207    push    dword [ebp + CPUMCTXCORE.fs]
     208    push    dword [ebp + CPUMCTXCORE.ds]
     209    push    dword [ebp + CPUMCTXCORE.es]
     210    push    dword [ebp + CPUMCTXCORE.ss]
     211    push    dword [ebp + CPUMCTXCORE.esp]
     212    push    dword [ebp + CPUMCTXCORE.eflags]
     213    push    dword [ebp + CPUMCTXCORE.cs]
     214    push    dword [ebp + CPUMCTXCORE.eip]
    215215
    216216    ;
    … …  
    235235    iret
    236236ENDPROC CPUMGCCallV86Code
     237
    237238
    238239;;
    … …  
    384385ENDPROC     CPUMGCResumeGuestV86
    385386
    386 
    387 
    388 

  • trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

    r12600 r12657  
    3636
    3737
    38 
    3938/**
    4039 * Does Ring-0 CPUM initialization.
    … …  
    5352     * Check CR0 & CR4 flags.
    5453     */
    55     uint32_t    u32CR0 = ASMGetCR0();
     54    uint32_t u32CR0 = ASMGetCR0();
    5655    if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
    5756    {
    … …  
    9998     * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
    10099     */
    101     uint32_t    u32DR7 = ASMGetDR7();
     100    uint32_t u32DR7 = ASMGetDR7();
    102101    if (u32DR7 & X86_DR7_ENABLED_MASK)
    103102    {
    … …  
    155154     */
    156155
    157     switch(pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
    158     {
    159     case X86_CR0_MP | X86_CR0_TS:
    160     case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
    161         return VINF_EM_RAW_GUEST_TRAP;
    162 
    163     default:
    164         break;
     156    switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
     157    {
     158        case X86_CR0_MP | X86_CR0_TS:
     159        case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
     160            return VINF_EM_RAW_GUEST_TRAP;
     161        default:
     162            break;
    165163    }
    166164
    … …  
    172170    if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
    173171    {
    174         /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
     172        /** @todo Do we really need to read this every time?? The host could change this on the fly though.
     173         *  bird: what about starting by skipping the ASMWrMsr below if we didn't
     174         *        change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
    175175        oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
    176 
    177176        if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
    178177        {
    … …  
    193192        /* CPUMHandleLazyFPU could have changed CR0; restore it. */
    194193    ASMSetCR0(oldCR0);
    195 #else
    196     /* Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
     194
     195#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
     196
     197    /*
     198     * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
    197199     * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
    198200     */
    … …  
    203205    CPUMLoadFPUAsm(pCtx);
    204206
    205     /* The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
     207    /*
     208     * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
    206209     *
    207210     * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
    … …  
    209212    if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
    210213    {
    211         /* @todo Do we really need to read this every time?? The host could change this on the fly though. */
     214        /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
    212215        uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
    213216
    … …  
    219222        }
    220223    }
    221 #endif
     224#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
    222225
    223226    pVM->cpum.s.fUseFlags |= CPUM_USED_FPU;
    … …  
    254257        ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
    255258
    256 #else
     259#else  /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
    257260    CPUMSaveFPUAsm(pCtx);
    258261    if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
    … …  
    261264        CPUMSaveXMMAsm(pCtx);
    262265    }
    263     /* Restore the original FPU control word and MXCSR.
     266
     267    /*
     268     * Restore the original FPU control word and MXCSR.
    264269     * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
    265270     */
    … …  
    267272    if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
    268273        CPUMSetMXCSR(pVM->cpum.s.Host.fpu.MXCSR);
    269 #endif
    270 
    271     pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU|CPUM_MANUAL_XMM_RESTORE);
     274#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
     275
     276    pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
    272277    return VINF_SUCCESS;
    273278}
    … …  
    294299        pCtx->dr[6] = ASMGetDR6();
    295300
    296     /* Restore the host's debug state. DR0-3, DR6 and only then DR7!
     301    /*
     302     * Restore the host's debug state. DR0-3, DR6 and only then DR7!
    297303     * DR7 contains 0x400 right now.
    298304     */
    … …  
    325331    pVM->cpum.s.Host.dr3 = ASMGetDR3();
    326332    pVM->cpum.s.Host.dr6 = ASMGetDR6();
    327     /* @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
     333    /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
    328334    pVM->cpum.s.Host.dr7 = ASMGetDR7();
    329335    /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
    … …  
    341347    return VINF_SUCCESS;
    342348}
     349

  • trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

    r12600 r12657  
    748748
    749749    /* Always load the guest's debug state on-demand. */
    750     CPUMDeactivateGuestDebugtate(pVM);
     750    CPUMDeactivateGuestDebugState(pVM);
    751751
    752752    /* Always reload the host context and the guest's CR0 register. (!!!!) */

  • trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp

    r12579 r12657  
    160160    }
    161161    CHECK_MEMBER_ALIGNMENT(VM, trpm.s.aIdt, 16);
    162     CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Host, 32);
    163     CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Guest, 32);
    164     CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Hyper, 32);
     162    CHECK_MEMBER_ALIGNMENT(VM, cpum, 64);
     163    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Host, 64);
     164    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Guest, 64);
     165    CHECK_MEMBER_ALIGNMENT(VM, cpum.s.Hyper, 64);
    165166    CHECK_MEMBER_ALIGNMENT(VM, vmm.s.CritSectVMLock, 8);
    166167    CHECK_MEMBER_ALIGNMENT(VM, vmm.s.CallHostR0JmpBuf, 8);
    … …  
    180181    CHECK_MEMBER_ALIGNMENT(CPUMCTX, idtr, 4);
    181182    CHECK_MEMBER_ALIGNMENT(CPUMCTX, SysEnter, 8);
    182     CHECK_SIZE_ALIGNMENT(CPUMCTX, 32);
    183183    CHECK_CPUMCTXCORE(eax);
    184184    CHECK_CPUMCTXCORE(ebx);
    … …  
    220220    }
    221221#endif
     222    CHECK_SIZE_ALIGNMENT(CPUMCTX, 64);
     223    CHECK_SIZE_ALIGNMENT(CPUMHOSTCTX, 64);
    222224
    223225    /* pdm */
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