Changeset 12970 in vbox
- Timestamp:
- Oct 3, 2008 7:04:11 AM (17 years ago)
- svn:sync-xref-src-repo-rev:
- 37403
- Location:
- trunk
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/pdmdev.h
r12895 r12970 1660 1660 * PDM Device API. 1661 1661 */ 1662 typedef struct PDMDEVHLP 1662 typedef struct PDMDEVHLPR3 1663 1663 { 1664 1664 /** Structure version. PDM_DEVHLP_VERSION defines the current version. */ … … 1780 1780 * @param pszFill Name of the GC function which is gonna handle Fill/memset operations. (optional) 1781 1781 * @param pszDesc Obsolete. NULL is fine. 1782 * @todo Remove pszDesc in the next major revision of PDMDEVHLP .1782 * @todo Remove pszDesc in the next major revision of PDMDEVHLPR3. 1783 1783 */ 1784 1784 DECLR3CALLBACKMEMBER(int, pfnMMIORegisterGC,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser, … … 1801 1801 * @param pszFill Name of the GC function which is gonna handle Fill/memset operations. (optional) 1802 1802 * @param pszDesc Obsolete. NULL is fine. 1803 * @todo Remove pszDesc in the next major revision of PDMDEVHLP .1803 * @todo Remove pszDesc in the next major revision of PDMDEVHLPR3. 1804 1804 */ 1805 1805 DECLR3CALLBACKMEMBER(int, pfnMMIORegisterR0,(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTR0PTR pvUser, … … 2716 2716 /** Just a safety precaution. (PDM_DEVHLP_VERSION) */ 2717 2717 uint32_t u32TheEnd; 2718 } PDMDEVHLP ;2718 } PDMDEVHLPR3; 2719 2719 #endif /* !IN_RING3 */ 2720 /** Pointer PDM Device API. */2721 typedef R3PTRTYPE(struct PDMDEVHLP *) PPDMDEVHLP;2722 /** Pointer PDM Device API. */2723 typedef R3PTRTYPE(const struct PDMDEVHLP *) PCPDMDEVHLP;2720 /** Pointer to the R3 PDM Device API. */ 2721 typedef R3PTRTYPE(struct PDMDEVHLPR3 *) PPDMDEVHLPR3; 2722 /** Pointer to the R3 PDM Device API, const variant. */ 2723 typedef R3PTRTYPE(const struct PDMDEVHLPR3 *) PCPDMDEVHLPR3; 2724 2724 2725 2725 /** Current PDMDEVHLP version number. */ … … 2728 2728 2729 2729 /** 2730 * PDM Device API - GC Variant.2731 */ 2732 typedef struct PDMDEVHLP GC2733 { 2734 /** Structure version. PDM_DEVHLP GC_VERSION defines the current version. */2730 * PDM Device API - RC Variant. 2731 */ 2732 typedef struct PDMDEVHLPRC 2733 { 2734 /** Structure version. PDM_DEVHLPRC_VERSION defines the current version. */ 2735 2735 uint32_t u32Version; 2736 2736 … … 2845 2845 /** Just a safety precaution. */ 2846 2846 uint32_t u32TheEnd; 2847 } PDMDEVHLP GC;2848 /** Pointer PDM Device GC API. */2849 typedef RCPTRTYPE(struct PDMDEVHLP GC *) PPDMDEVHLPGC;2850 /** Pointer PDM Device GC API. */2851 typedef RCPTRTYPE(const struct PDMDEVHLP GC *) PCPDMDEVHLPGC;2847 } PDMDEVHLPRC; 2848 /** Pointer PDM Device RC API. */ 2849 typedef RCPTRTYPE(struct PDMDEVHLPRC *) PPDMDEVHLPRC; 2850 /** Pointer PDM Device RC API. */ 2851 typedef RCPTRTYPE(const struct PDMDEVHLPRC *) PCPDMDEVHLPRC; 2852 2852 2853 2853 /** Current PDMDEVHLP version number. */ 2854 #define PDM_DEVHLP GC_VERSION 0xfb0100002854 #define PDM_DEVHLPRC_VERSION 0xfb010000 2855 2855 2856 2856 … … 2993 2993 /** Device instance number. */ 2994 2994 RTUINT iInstance; 2995 2996 /** Pointer the GC PDM Device API. */ 2997 PCPDMDEVHLPRC pDevHlpRC; 2998 /** Pointer to device instance data. */ 2999 RTRCPTR pvInstanceDataRC; 3000 3001 /** Pointer the R0 PDM Device API. */ 3002 PCPDMDEVHLPR0 pDevHlpR0; 3003 /** Pointer to device instance data (R0). */ 3004 RTR0PTR pvInstanceDataR0; 3005 3006 /** Pointer the HC PDM Device API. */ 3007 PCPDMDEVHLPR3 pDevHlpR3; 3008 /** Pointer to device instance data. */ 3009 RTR3PTR pvInstanceDataR3; 3010 3011 /** Pointer to device registration structure. */ 3012 R3PTRTYPE(PCPDMDEVREG) pDevReg; 3013 /** Configuration handle. */ 3014 R3PTRTYPE(PCFGMNODE) pCfgHandle; 3015 2995 3016 /** The base interface of the device. 2996 3017 * The device constructor initializes this if it has any … … 2998 3019 * call PDMR3QueryDevice(). */ 2999 3020 PDMIBASE IBase; 3021 /** Align the internal data more naturally. */ 3022 RTR3PTR R3PtrPadding; 3000 3023 3001 3024 /** Internal data. */ … … 3005 3028 PDMDEVINSINT s; 3006 3029 #endif 3007 uint8_t padding[HC_ARCH_BITS == 32 ? 48 : 96];3030 uint8_t padding[HC_ARCH_BITS == 32 ? 64 + 16 : 112]; 3008 3031 } Internal; 3009 3032 3010 /** Pointer the HC PDM Device API. */3011 R3PTRTYPE(PCPDMDEVHLP) pDevHlp;3012 /** Pointer the R0 PDM Device API. */3013 R0PTRTYPE(PCPDMDEVHLPR0) pDevHlpR0;3014 /** Pointer to device registration structure. */3015 R3PTRTYPE(PCPDMDEVREG) pDevReg;3016 /** Configuration handle. */3017 R3PTRTYPE(PCFGMNODE) pCfgHandle;3018 /** Pointer to device instance data. */3019 R3PTRTYPE(void *) pvInstanceDataR3;3020 /** Pointer to device instance data. */3021 R0PTRTYPE(void *) pvInstanceDataR0;3022 /** Pointer the GC PDM Device API. */3023 RCPTRTYPE(PCPDMDEVHLPGC) pDevHlpGC;3024 /** Pointer to device instance data. */3025 RCPTRTYPE(void *) pvInstanceDataGC;3026 /* padding to make achInstanceData aligned at 32 byte boundrary. */3027 uint32_t au32Padding[HC_ARCH_BITS == 32 ? 1 : 6];3028 3033 /** Device instance data. The size of this area is defined 3029 3034 * in the PDMDEVREG::cbInstanceData field. */ … … 3031 3036 } PDMDEVINS; 3032 3037 3033 /** Current DEVREGversion number. */3034 #define PDM_DEVINS_VERSION 0xf30 100003038 /** Current PDMDEVINS version number. */ 3039 #define PDM_DEVINS_VERSION 0xf3020000 3035 3040 3036 3041 /** Converts a pointer to the PDMDEVINS::IBase to a pointer to PDMDEVINS. */ … … 3042 3047 */ 3043 3048 #ifdef VBOX_STRICT 3044 # define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pDevHlp ->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__)3049 # define PDMDEV_ASSERT_EMT(pDevIns) pDevIns->pDevHlpR3->pfnAssertEMT(pDevIns, __FILE__, __LINE__, __FUNCTION__) 3045 3050 #else 3046 3051 # define PDMDEV_ASSERT_EMT(pDevIns) do { } while (0) … … 3051 3056 */ 3052 3057 #ifdef VBOX_STRICT 3053 # define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pDevHlp ->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__)3058 # define PDMDEV_ASSERT_OTHER(pDevIns) pDevIns->pDevHlpR3->pfnAssertOther(pDevIns, __FILE__, __LINE__, __FUNCTION__) 3054 3059 #else 3055 3060 # define PDMDEV_ASSERT_OTHER(pDevIns) do { } while (0) … … 3060 3065 */ 3061 3066 #ifdef VBOX_STRICT 3062 # define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pDevHlp ->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__)3067 # define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) pDevIns->pDevHlpR3->pfnAssertVMLock(pDevIns, __FILE__, __LINE__, __FUNCTION__) 3063 3068 #else 3064 3069 # define PDMDEV_ASSERT_VMLOCK_OWNER(pDevIns) do { } while (0) … … 3080 3085 * Converts a PDM Device instance pointer a RC PDM Device instance pointer. 3081 3086 */ 3082 #define PDMDEVINS_2_RCPTR(pDevIns) ( (RCPTRTYPE(PPDMDEVINS))((RTGCUINTPTR)(pDevIns)->pvInstanceData GC - RT_OFFSETOF(PDMDEVINS, achInstanceData)) )3087 #define PDMDEVINS_2_RCPTR(pDevIns) ( (RCPTRTYPE(PPDMDEVINS))((RTGCUINTPTR)(pDevIns)->pvInstanceDataRC - RT_OFFSETOF(PDMDEVINS, achInstanceData)) ) 3083 3088 3084 3089 /** @def PDMDEVINS_2_R3PTR … … 3109 3114 va_list args; 3110 3115 va_start(args, pszFormat); 3111 rc = pDevIns->pDevHlp ->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args);3116 rc = pDevIns->pDevHlpR3->pfnDBGFStopV(pDevIns, RT_SRC_POS_ARGS, pszFormat, args); 3112 3117 va_end(args); 3113 3118 return rc; … … 3128 3133 #ifdef IN_RING3 3129 3134 /** 3130 * @copydoc PDMDEVHLP ::pfnIOPortRegister3135 * @copydoc PDMDEVHLPR3::pfnIOPortRegister 3131 3136 */ 3132 3137 DECLINLINE(int) PDMDevHlpIOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTHCPTR pvUser, … … 3134 3139 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc) 3135 3140 { 3136 return pDevIns->pDevHlp ->pfnIOPortRegister(pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);3137 } 3138 3139 /** 3140 * @copydoc PDMDEVHLP ::pfnIOPortRegisterGC3141 return pDevIns->pDevHlpR3->pfnIOPortRegister(pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc); 3142 } 3143 3144 /** 3145 * @copydoc PDMDEVHLPR3::pfnIOPortRegisterGC 3141 3146 */ 3142 3147 DECLINLINE(int) PDMDevHlpIOPortRegisterGC(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTRCPTR pvUser, … … 3144 3149 const char *pszInStr, const char *pszDesc) 3145 3150 { 3146 return pDevIns->pDevHlp ->pfnIOPortRegisterGC(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);3147 } 3148 3149 /** 3150 * @copydoc PDMDEVHLP ::pfnIOPortRegisterR03151 return pDevIns->pDevHlpR3->pfnIOPortRegisterGC(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc); 3152 } 3153 3154 /** 3155 * @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0 3151 3156 */ 3152 3157 DECLINLINE(int) PDMDevHlpIOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTR0PTR pvUser, … … 3154 3159 const char *pszInStr, const char *pszDesc) 3155 3160 { 3156 return pDevIns->pDevHlp ->pfnIOPortRegisterR0(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc);3157 } 3158 3159 /** 3160 * @copydoc PDMDEVHLP ::pfnMMIORegister3161 return pDevIns->pDevHlpR3->pfnIOPortRegisterR0(pDevIns, Port, cPorts, pvUser, pszOut, pszIn, pszOutStr, pszInStr, pszDesc); 3162 } 3163 3164 /** 3165 * @copydoc PDMDEVHLPR3::pfnMMIORegister 3161 3166 */ 3162 3167 DECLINLINE(int) PDMDevHlpMMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTHCPTR pvUser, … … 3164 3169 const char *pszDesc) 3165 3170 { 3166 return pDevIns->pDevHlp ->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc);3167 } 3168 3169 /** 3170 * @copydoc PDMDEVHLP ::pfnMMIORegisterGC3171 return pDevIns->pDevHlpR3->pfnMMIORegister(pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc); 3172 } 3173 3174 /** 3175 * @copydoc PDMDEVHLPR3::pfnMMIORegisterGC 3171 3176 */ 3172 3177 DECLINLINE(int) PDMDevHlpMMIORegisterGC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser, 3173 3178 const char *pszWrite, const char *pszRead, const char *pszFill) 3174 3179 { 3175 return pDevIns->pDevHlp ->pfnMMIORegisterGC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill, NULL);3176 } 3177 3178 /** 3179 * @copydoc PDMDEVHLP ::pfnMMIORegisterR03180 return pDevIns->pDevHlpR3->pfnMMIORegisterGC(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill, NULL); 3181 } 3182 3183 /** 3184 * @copydoc PDMDEVHLPR3::pfnMMIORegisterR0 3180 3185 */ 3181 3186 DECLINLINE(int) PDMDevHlpMMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTR0PTR pvUser, 3182 3187 const char *pszWrite, const char *pszRead, const char *pszFill) 3183 3188 { 3184 return pDevIns->pDevHlp ->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill, NULL);3185 } 3186 3187 /** 3188 * @copydoc PDMDEVHLP ::pfnROMRegister3189 return pDevIns->pDevHlpR3->pfnMMIORegisterR0(pDevIns, GCPhysStart, cbRange, pvUser, pszWrite, pszRead, pszFill, NULL); 3190 } 3191 3192 /** 3193 * @copydoc PDMDEVHLPR3::pfnROMRegister 3189 3194 */ 3190 3195 DECLINLINE(int) PDMDevHlpROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, const void *pvBinary, bool fShadow, const char *pszDesc) 3191 3196 { 3192 return pDevIns->pDevHlp ->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, fShadow, pszDesc);3193 } 3194 /** 3195 * @copydoc PDMDEVHLP ::pfnROMProtectShadow3197 return pDevIns->pDevHlpR3->pfnROMRegister(pDevIns, GCPhysStart, cbRange, pvBinary, fShadow, pszDesc); 3198 } 3199 /** 3200 * @copydoc PDMDEVHLPR3::pfnROMProtectShadow 3196 3201 */ 3197 3202 DECLINLINE(int) PDMDevHlpROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange) 3198 3203 { 3199 return pDevIns->pDevHlp ->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange);3200 } 3201 3202 /** 3203 * @copydoc PDMDEVHLP ::pfnMMIO2Register3204 return pDevIns->pDevHlpR3->pfnROMProtectShadow(pDevIns, GCPhysStart, cbRange); 3205 } 3206 3207 /** 3208 * @copydoc PDMDEVHLPR3::pfnMMIO2Register 3204 3209 */ 3205 3210 DECLINLINE(int) PDMDevHlpMMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc) 3206 3211 { 3207 return pDevIns->pDevHlp ->pfnMMIO2Register(pDevIns, iRegion, cb, fFlags, ppv, pszDesc);3208 } 3209 3210 /** 3211 * @copydoc PDMDEVHLP ::pfnMMIO2Deregister3212 return pDevIns->pDevHlpR3->pfnMMIO2Register(pDevIns, iRegion, cb, fFlags, ppv, pszDesc); 3213 } 3214 3215 /** 3216 * @copydoc PDMDEVHLPR3::pfnMMIO2Deregister 3212 3217 */ 3213 3218 DECLINLINE(int) PDMDevHlpMMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion) 3214 3219 { 3215 return pDevIns->pDevHlp ->pfnMMIO2Deregister(pDevIns, iRegion);3216 } 3217 3218 /** 3219 * @copydoc PDMDEVHLP ::pfnMMIO2Map3220 return pDevIns->pDevHlpR3->pfnMMIO2Deregister(pDevIns, iRegion); 3221 } 3222 3223 /** 3224 * @copydoc PDMDEVHLPR3::pfnMMIO2Map 3220 3225 */ 3221 3226 DECLINLINE(int) PDMDevHlpMMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 3222 3227 { 3223 return pDevIns->pDevHlp ->pfnMMIO2Map(pDevIns, iRegion, GCPhys);3224 } 3225 3226 /** 3227 * @copydoc PDMDEVHLP ::pfnMMIO2Unmap3228 return pDevIns->pDevHlpR3->pfnMMIO2Map(pDevIns, iRegion, GCPhys); 3229 } 3230 3231 /** 3232 * @copydoc PDMDEVHLPR3::pfnMMIO2Unmap 3228 3233 */ 3229 3234 DECLINLINE(int) PDMDevHlpMMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 3230 3235 { 3231 return pDevIns->pDevHlp ->pfnMMIO2Unmap(pDevIns, iRegion, GCPhys);3232 } 3233 3234 /** 3235 * @copydoc PDMDEVHLP ::pfnMMHyperMapMMIO23236 return pDevIns->pDevHlpR3->pfnMMIO2Unmap(pDevIns, iRegion, GCPhys); 3237 } 3238 3239 /** 3240 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 3236 3241 */ 3237 3242 DECLINLINE(int) PDMDevHlpMMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, 3238 3243 const char *pszDesc, PRTRCPTR pRCPtr) 3239 3244 { 3240 return pDevIns->pDevHlp ->pfnMMHyperMapMMIO2(pDevIns, iRegion, off, cb, pszDesc, pRCPtr);3241 } 3242 3243 /** 3244 * @copydoc PDMDEVHLP ::pfnRegisterVMMDevHeap3245 return pDevIns->pDevHlpR3->pfnMMHyperMapMMIO2(pDevIns, iRegion, off, cb, pszDesc, pRCPtr); 3246 } 3247 3248 /** 3249 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap 3245 3250 */ 3246 3251 DECLINLINE(int) PDMDevHlpRegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize) 3247 3252 { 3248 return pDevIns->pDevHlp ->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbSize);3249 } 3250 3251 /** 3252 * @copydoc PDMDEVHLP ::pfnUnregisterVMMDevHeap3253 return pDevIns->pDevHlpR3->pfnRegisterVMMDevHeap(pDevIns, GCPhys, pvHeap, cbSize); 3254 } 3255 3256 /** 3257 * @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap 3253 3258 */ 3254 3259 DECLINLINE(int) PDMDevHlpUnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys) 3255 3260 { 3256 return pDevIns->pDevHlp ->pfnUnregisterVMMDevHeap(pDevIns, GCPhys);3257 } 3258 3259 /** 3260 * @copydoc PDMDEVHLP ::pfnSSMRegister3261 return pDevIns->pDevHlpR3->pfnUnregisterVMMDevHeap(pDevIns, GCPhys); 3262 } 3263 3264 /** 3265 * @copydoc PDMDEVHLPR3::pfnSSMRegister 3261 3266 */ 3262 3267 DECLINLINE(int) PDMDevHlpSSMRegister(PPDMDEVINS pDevIns, const char *pszName, uint32_t u32Instance, uint32_t u32Version, size_t cbGuess, … … 3264 3269 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone) 3265 3270 { 3266 return pDevIns->pDevHlp ->pfnSSMRegister(pDevIns, pszName, u32Instance, u32Version, cbGuess,3271 return pDevIns->pDevHlpR3->pfnSSMRegister(pDevIns, pszName, u32Instance, u32Version, cbGuess, 3267 3272 pfnSavePrep, pfnSaveExec, pfnSaveDone, 3268 3273 pfnLoadPrep, pfnLoadExec, pfnLoadDone); … … 3270 3275 3271 3276 /** 3272 * @copydoc PDMDEVHLP ::pfnTMTimerCreate3277 * @copydoc PDMDEVHLPR3::pfnTMTimerCreate 3273 3278 */ 3274 3279 DECLINLINE(int) PDMDevHlpTMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, const char *pszDesc, PPTMTIMERR3 ppTimer) 3275 3280 { 3276 return pDevIns->pDevHlp ->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pszDesc, ppTimer);3277 } 3278 3279 /** 3280 * @copydoc PDMDEVHLP ::pfnPCIRegister3281 return pDevIns->pDevHlpR3->pfnTMTimerCreate(pDevIns, enmClock, pfnCallback, pszDesc, ppTimer); 3282 } 3283 3284 /** 3285 * @copydoc PDMDEVHLPR3::pfnPCIRegister 3281 3286 */ 3282 3287 DECLINLINE(int) PDMDevHlpPCIRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev) 3283 3288 { 3284 return pDevIns->pDevHlp ->pfnPCIRegister(pDevIns, pPciDev);3285 } 3286 3287 /** 3288 * @copydoc PDMDEVHLP ::pfnPCIIORegionRegister3289 return pDevIns->pDevHlpR3->pfnPCIRegister(pDevIns, pPciDev); 3290 } 3291 3292 /** 3293 * @copydoc PDMDEVHLPR3::pfnPCIIORegionRegister 3289 3294 */ 3290 3295 DECLINLINE(int) PDMDevHlpPCIIORegionRegister(PPDMDEVINS pDevIns, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback) 3291 3296 { 3292 return pDevIns->pDevHlp ->pfnPCIIORegionRegister(pDevIns, iRegion, cbRegion, enmType, pfnCallback);3293 } 3294 3295 /** 3296 * @copydoc PDMDEVHLP ::pfnPCISetConfigCallbacks3297 return pDevIns->pDevHlpR3->pfnPCIIORegionRegister(pDevIns, iRegion, cbRegion, enmType, pfnCallback); 3298 } 3299 3300 /** 3301 * @copydoc PDMDEVHLPR3::pfnPCISetConfigCallbacks 3297 3302 */ 3298 3303 DECLINLINE(void) PDMDevHlpPCISetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 3299 3304 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld) 3300 3305 { 3301 pDevIns->pDevHlp ->pfnPCISetConfigCallbacks(pDevIns, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);3302 } 3303 3304 /** 3305 * @copydoc PDMDEVHLP ::pfnDriverAttach3306 pDevIns->pDevHlpR3->pfnPCISetConfigCallbacks(pDevIns, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld); 3307 } 3308 3309 /** 3310 * @copydoc PDMDEVHLPR3::pfnDriverAttach 3306 3311 */ 3307 3312 DECLINLINE(int) PDMDevHlpDriverAttach(PPDMDEVINS pDevIns, RTUINT iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc) 3308 3313 { 3309 return pDevIns->pDevHlp ->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc);3310 } 3311 3312 /** 3313 * @copydoc PDMDEVHLP ::pfnMMHeapAlloc3314 return pDevIns->pDevHlpR3->pfnDriverAttach(pDevIns, iLun, pBaseInterface, ppBaseInterface, pszDesc); 3315 } 3316 3317 /** 3318 * @copydoc PDMDEVHLPR3::pfnMMHeapAlloc 3314 3319 */ 3315 3320 DECLINLINE(void *) PDMDevHlpMMHeapAlloc(PPDMDEVINS pDevIns, size_t cb) 3316 3321 { 3317 return pDevIns->pDevHlp ->pfnMMHeapAlloc(pDevIns, cb);3318 } 3319 3320 /** 3321 * @copydoc PDMDEVHLP ::pfnMMHeapAllocZ3322 return pDevIns->pDevHlpR3->pfnMMHeapAlloc(pDevIns, cb); 3323 } 3324 3325 /** 3326 * @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ 3322 3327 */ 3323 3328 DECLINLINE(void *) PDMDevHlpMMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb) 3324 3329 { 3325 return pDevIns->pDevHlp ->pfnMMHeapAllocZ(pDevIns, cb);3326 } 3327 3328 /** 3329 * @copydoc PDMDEVHLP ::pfnMMHeapFree3330 return pDevIns->pDevHlpR3->pfnMMHeapAllocZ(pDevIns, cb); 3331 } 3332 3333 /** 3334 * @copydoc PDMDEVHLPR3::pfnMMHeapFree 3330 3335 */ 3331 3336 DECLINLINE(void) PDMDevHlpMMHeapFree(PPDMDEVINS pDevIns, void *pv) 3332 3337 { 3333 pDevIns->pDevHlp ->pfnMMHeapFree(pDevIns, pv);3334 } 3335 3336 /** 3337 * @copydoc PDMDEVHLP ::pfnDBGFInfoRegister3338 pDevIns->pDevHlpR3->pfnMMHeapFree(pDevIns, pv); 3339 } 3340 3341 /** 3342 * @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister 3338 3343 */ 3339 3344 DECLINLINE(int) PDMDevHlpDBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler) 3340 3345 { 3341 return pDevIns->pDevHlp ->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler);3342 } 3343 3344 /** 3345 * @copydoc PDMDEVHLP ::pfnSTAMRegister3346 return pDevIns->pDevHlpR3->pfnDBGFInfoRegister(pDevIns, pszName, pszDesc, pfnHandler); 3347 } 3348 3349 /** 3350 * @copydoc PDMDEVHLPR3::pfnSTAMRegister 3346 3351 */ 3347 3352 DECLINLINE(void) PDMDevHlpSTAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc) 3348 3353 { 3349 pDevIns->pDevHlp ->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);3350 } 3351 3352 /** 3353 * @copydoc PDMDEVHLP ::pfnSTAMRegisterF3354 pDevIns->pDevHlpR3->pfnSTAMRegister(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc); 3355 } 3356 3357 /** 3358 * @copydoc PDMDEVHLPR3::pfnSTAMRegisterF 3354 3359 */ 3355 3360 DECLINLINE(void) PDMDevHlpSTAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility, STAMUNIT enmUnit, … … 3358 3363 va_list va; 3359 3364 va_start(va, pszName); 3360 pDevIns->pDevHlp ->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va);3365 pDevIns->pDevHlpR3->pfnSTAMRegisterV(pDevIns, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, va); 3361 3366 va_end(va); 3362 3367 } 3363 3368 3364 3369 /** 3365 * @copydoc PDMDEVHLP ::pfnPDMQueueCreate3370 * @copydoc PDMDEVHLPR3::pfnPDMQueueCreate 3366 3371 */ 3367 3372 DECLINLINE(int) PDMDevHlpPDMQueueCreate(PPDMDEVINS pDevIns, RTUINT cbItem, RTUINT cItems, uint32_t cMilliesInterval, 3368 3373 PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, PPDMQUEUE *ppQueue) 3369 3374 { 3370 return pDevIns->pDevHlp ->pfnPDMQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue);3371 } 3372 3373 /** 3374 * @copydoc PDMDEVHLP ::pfnCritSectInit3375 return pDevIns->pDevHlpR3->pfnPDMQueueCreate(pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue); 3376 } 3377 3378 /** 3379 * @copydoc PDMDEVHLPR3::pfnCritSectInit 3375 3380 */ 3376 3381 DECLINLINE(int) PDMDevHlpCritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, const char *pszName) 3377 3382 { 3378 return pDevIns->pDevHlp ->pfnCritSectInit(pDevIns, pCritSect, pszName);3379 } 3380 3381 /** 3382 * @copydoc PDMDEVHLP ::pfnUTCNow3383 return pDevIns->pDevHlpR3->pfnCritSectInit(pDevIns, pCritSect, pszName); 3384 } 3385 3386 /** 3387 * @copydoc PDMDEVHLPR3::pfnUTCNow 3383 3388 */ 3384 3389 DECLINLINE(PRTTIMESPEC) PDMDevHlpUTCNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime) 3385 3390 { 3386 return pDevIns->pDevHlp ->pfnUTCNow(pDevIns, pTime);3387 } 3388 3389 /** 3390 * @copydoc PDMDEVHLP ::pfnGetVM3391 return pDevIns->pDevHlpR3->pfnUTCNow(pDevIns, pTime); 3392 } 3393 3394 /** 3395 * @copydoc PDMDEVHLPR3::pfnGetVM 3391 3396 */ 3392 3397 DECLINLINE(PVM) PDMDevHlpGetVM(PPDMDEVINS pDevIns) 3393 3398 { 3394 return pDevIns->pDevHlp ->pfnGetVM(pDevIns);3395 } 3396 3397 /** 3398 * @copydoc PDMDEVHLP ::pfnPhysReadGCVirt3399 return pDevIns->pDevHlpR3->pfnGetVM(pDevIns); 3400 } 3401 3402 /** 3403 * @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt 3399 3404 */ 3400 3405 DECLINLINE(int) PDMDevHlpPhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb) 3401 3406 { 3402 return pDevIns->pDevHlp ->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb);3403 } 3404 3405 /** 3406 * @copydoc PDMDEVHLP ::pfnPhysWriteGCVirt3407 return pDevIns->pDevHlpR3->pfnPhysReadGCVirt(pDevIns, pvDst, GCVirtSrc, cb); 3408 } 3409 3410 /** 3411 * @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt 3407 3412 */ 3408 3413 DECLINLINE(int) PDMDevHlpPhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb) 3409 3414 { 3410 return pDevIns->pDevHlp ->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb);3411 } 3412 3413 /** 3414 * @copydoc PDMDEVHLP ::pfnPhysReserve3415 return pDevIns->pDevHlpR3->pfnPhysWriteGCVirt(pDevIns, GCVirtDst, pvSrc, cb); 3416 } 3417 3418 /** 3419 * @copydoc PDMDEVHLPR3::pfnPhysReserve 3415 3420 */ 3416 3421 DECLINLINE(int) PDMDevHlpPhysReserve(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTUINT cbRange, const char *pszDesc) 3417 3422 { 3418 return pDevIns->pDevHlp ->pfnPhysReserve(pDevIns, GCPhys, cbRange, pszDesc);3419 } 3420 3421 /** 3422 * @copydoc PDMDEVHLP ::pfnPhysGCPtr2GCPhys3423 return pDevIns->pDevHlpR3->pfnPhysReserve(pDevIns, GCPhys, cbRange, pszDesc); 3424 } 3425 3426 /** 3427 * @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys 3423 3428 */ 3424 3429 DECLINLINE(int) PDMDevHlpPhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys) 3425 3430 { 3426 return pDevIns->pDevHlp ->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys);3427 } 3428 3429 /** 3430 * @copydoc PDMDEVHLP ::pfnVMState3431 return pDevIns->pDevHlpR3->pfnPhysGCPtr2GCPhys(pDevIns, GCPtr, pGCPhys); 3432 } 3433 3434 /** 3435 * @copydoc PDMDEVHLPR3::pfnVMState 3431 3436 */ 3432 3437 DECLINLINE(VMSTATE) PDMDevHlpVMState(PPDMDEVINS pDevIns) 3433 3438 { 3434 return pDevIns->pDevHlp ->pfnVMState(pDevIns);3435 } 3436 3437 /** 3438 * @copydoc PDMDEVHLP ::pfnA20Set3439 return pDevIns->pDevHlpR3->pfnVMState(pDevIns); 3440 } 3441 3442 /** 3443 * @copydoc PDMDEVHLPR3::pfnA20Set 3439 3444 */ 3440 3445 DECLINLINE(void) PDMDevHlpA20Set(PPDMDEVINS pDevIns, bool fEnable) 3441 3446 { 3442 pDevIns->pDevHlp ->pfnA20Set(pDevIns, fEnable);3443 } 3444 3445 /** 3446 * @copydoc PDMDEVHLP ::pfnVMReset3447 pDevIns->pDevHlpR3->pfnA20Set(pDevIns, fEnable); 3448 } 3449 3450 /** 3451 * @copydoc PDMDEVHLPR3::pfnVMReset 3447 3452 */ 3448 3453 DECLINLINE(int) PDMDevHlpVMReset(PPDMDEVINS pDevIns) 3449 3454 { 3450 return pDevIns->pDevHlp ->pfnVMReset(pDevIns);3451 } 3452 3453 /** 3454 * @copydoc PDMDEVHLP ::pfnVMSuspend3455 return pDevIns->pDevHlpR3->pfnVMReset(pDevIns); 3456 } 3457 3458 /** 3459 * @copydoc PDMDEVHLPR3::pfnVMSuspend 3455 3460 */ 3456 3461 DECLINLINE(int) PDMDevHlpVMSuspend(PPDMDEVINS pDevIns) 3457 3462 { 3458 return pDevIns->pDevHlp ->pfnVMSuspend(pDevIns);3459 } 3460 3461 /** 3462 * @copydoc PDMDEVHLP ::pfnVMPowerOff3463 return pDevIns->pDevHlpR3->pfnVMSuspend(pDevIns); 3464 } 3465 3466 /** 3467 * @copydoc PDMDEVHLPR3::pfnVMPowerOff 3463 3468 */ 3464 3469 DECLINLINE(int) PDMDevHlpVMPowerOff(PPDMDEVINS pDevIns) 3465 3470 { 3466 return pDevIns->pDevHlp ->pfnVMPowerOff(pDevIns);3467 } 3468 3469 /** 3470 * @copydoc PDMDEVHLP ::pfnDMARegister3471 return pDevIns->pDevHlpR3->pfnVMPowerOff(pDevIns); 3472 } 3473 3474 /** 3475 * @copydoc PDMDEVHLPR3::pfnDMARegister 3471 3476 */ 3472 3477 DECLINLINE(int) PDMDevHlpDMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser) 3473 3478 { 3474 return pDevIns->pDevHlp ->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser);3475 } 3476 3477 /** 3478 * @copydoc PDMDEVHLP ::pfnDMAReadMemory3479 return pDevIns->pDevHlpR3->pfnDMARegister(pDevIns, uChannel, pfnTransferHandler, pvUser); 3480 } 3481 3482 /** 3483 * @copydoc PDMDEVHLPR3::pfnDMAReadMemory 3479 3484 */ 3480 3485 DECLINLINE(int) PDMDevHlpDMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead) 3481 3486 { 3482 return pDevIns->pDevHlp ->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead);3483 } 3484 3485 /** 3486 * @copydoc PDMDEVHLP ::pfnDMAWriteMemory3487 return pDevIns->pDevHlpR3->pfnDMAReadMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbRead); 3488 } 3489 3490 /** 3491 * @copydoc PDMDEVHLPR3::pfnDMAWriteMemory 3487 3492 */ 3488 3493 DECLINLINE(int) PDMDevHlpDMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten) 3489 3494 { 3490 return pDevIns->pDevHlp ->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten);3491 } 3492 3493 /** 3494 * @copydoc PDMDEVHLP ::pfnDMASetDREQ3495 return pDevIns->pDevHlpR3->pfnDMAWriteMemory(pDevIns, uChannel, pvBuffer, off, cbBlock, pcbWritten); 3496 } 3497 3498 /** 3499 * @copydoc PDMDEVHLPR3::pfnDMASetDREQ 3495 3500 */ 3496 3501 DECLINLINE(int) PDMDevHlpDMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel) 3497 3502 { 3498 return pDevIns->pDevHlp ->pfnDMASetDREQ(pDevIns, uChannel, uLevel);3499 } 3500 3501 /** 3502 * @copydoc PDMDEVHLP ::pfnDMAGetChannelMode3503 return pDevIns->pDevHlpR3->pfnDMASetDREQ(pDevIns, uChannel, uLevel); 3504 } 3505 3506 /** 3507 * @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode 3503 3508 */ 3504 3509 DECLINLINE(uint8_t) PDMDevHlpDMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel) 3505 3510 { 3506 return pDevIns->pDevHlp ->pfnDMAGetChannelMode(pDevIns, uChannel);3507 } 3508 3509 /** 3510 * @copydoc PDMDEVHLP ::pfnDMASchedule3511 return pDevIns->pDevHlpR3->pfnDMAGetChannelMode(pDevIns, uChannel); 3512 } 3513 3514 /** 3515 * @copydoc PDMDEVHLPR3::pfnDMASchedule 3511 3516 */ 3512 3517 DECLINLINE(void) PDMDevHlpDMASchedule(PPDMDEVINS pDevIns) 3513 3518 { 3514 pDevIns->pDevHlp ->pfnDMASchedule(pDevIns);3515 } 3516 3517 /** 3518 * @copydoc PDMDEVHLP ::pfnCMOSWrite3519 pDevIns->pDevHlpR3->pfnDMASchedule(pDevIns); 3520 } 3521 3522 /** 3523 * @copydoc PDMDEVHLPR3::pfnCMOSWrite 3519 3524 */ 3520 3525 DECLINLINE(int) PDMDevHlpCMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value) 3521 3526 { 3522 return pDevIns->pDevHlp ->pfnCMOSWrite(pDevIns, iReg, u8Value);3523 } 3524 3525 /** 3526 * @copydoc PDMDEVHLP ::pfnCMOSRead3527 return pDevIns->pDevHlpR3->pfnCMOSWrite(pDevIns, iReg, u8Value); 3528 } 3529 3530 /** 3531 * @copydoc PDMDEVHLPR3::pfnCMOSRead 3527 3532 */ 3528 3533 DECLINLINE(int) PDMDevHlpCMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value) 3529 3534 { 3530 return pDevIns->pDevHlp ->pfnCMOSRead(pDevIns, iReg, pu8Value);3531 } 3532 3533 /** 3534 * @copydoc PDMDEVHLP ::pfnGetCpuId3535 return pDevIns->pDevHlpR3->pfnCMOSRead(pDevIns, iReg, pu8Value); 3536 } 3537 3538 /** 3539 * @copydoc PDMDEVHLPR3::pfnGetCpuId 3535 3540 */ 3536 3541 DECLINLINE(void) PDMDevHlpGetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx) 3537 3542 { 3538 pDevIns->pDevHlp ->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx);3539 } 3540 3541 /** 3542 * @copydoc PDMDEVHLP ::pfnPDMThreadCreate3543 pDevIns->pDevHlpR3->pfnGetCpuId(pDevIns, iLeaf, pEax, pEbx, pEcx, pEdx); 3544 } 3545 3546 /** 3547 * @copydoc PDMDEVHLPR3::pfnPDMThreadCreate 3543 3548 */ 3544 3549 DECLINLINE(int) PDMDevHlpPDMThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread, 3545 3550 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName) 3546 3551 { 3547 return pDevIns->pDevHlp ->pfnPDMThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);3552 return pDevIns->pDevHlpR3->pfnPDMThreadCreate(pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName); 3548 3553 } 3549 3554 #endif /* IN_RING3 */ … … 3551 3556 3552 3557 /** 3553 * @copydoc PDMDEVHLP ::pfnPCISetIrq3558 * @copydoc PDMDEVHLPR3::pfnPCISetIrq 3554 3559 */ 3555 3560 DECLINLINE(void) PDMDevHlpPCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 3556 3561 { 3557 #ifdef IN_GC 3558 pDevIns->pDevHlpGC->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3559 #elif defined(IN_RING0) 3560 pDevIns->pDevHlpR0->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3561 #else 3562 pDevIns->pDevHlp->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3563 #endif 3564 } 3565 3566 /** 3567 * @copydoc PDMDEVHLP::pfnPCISetIrqNoWait 3562 pDevIns->CTX_SUFF(pDevHlp)->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3563 } 3564 3565 /** 3566 * @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait 3568 3567 */ 3569 3568 DECLINLINE(void) PDMDevHlpPCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel) 3570 3569 { 3571 #ifdef IN_GC 3572 pDevIns->pDevHlpGC->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3573 #elif defined(IN_RING0) 3574 pDevIns->pDevHlpR0->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3575 #else 3576 pDevIns->pDevHlp->pfnPCISetIrqNoWait(pDevIns, iIrq, iLevel); 3577 #endif 3578 } 3579 3580 /** 3581 * @copydoc PDMDEVHLP::pfnISASetIrq 3570 pDevIns->CTX_SUFF(pDevHlp)->pfnPCISetIrq(pDevIns, iIrq, iLevel); 3571 } 3572 3573 /** 3574 * @copydoc PDMDEVHLPR3::pfnISASetIrq 3582 3575 */ 3583 3576 DECLINLINE(void) PDMDevHlpISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 3584 3577 { 3585 #ifdef IN_GC 3586 pDevIns->pDevHlpGC->pfnISASetIrq(pDevIns, iIrq, iLevel); 3587 #elif defined(IN_RING0) 3588 pDevIns->pDevHlpR0->pfnISASetIrq(pDevIns, iIrq, iLevel); 3589 #else 3590 pDevIns->pDevHlp->pfnISASetIrq(pDevIns, iIrq, iLevel); 3591 #endif 3592 } 3593 3594 /** 3595 * @copydoc PDMDEVHLP::pfnISASetIrqNoWait 3578 pDevIns->CTX_SUFF(pDevHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel); 3579 } 3580 3581 /** 3582 * @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait 3596 3583 */ 3597 3584 DECLINLINE(void) PDMDevHlpISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel) 3598 3585 { 3599 #ifdef IN_GC 3600 pDevIns->pDevHlpGC->pfnISASetIrq(pDevIns, iIrq, iLevel); 3601 #elif defined(IN_RING0) 3602 pDevIns->pDevHlpR0->pfnISASetIrq(pDevIns, iIrq, iLevel); 3603 #else 3604 pDevIns->pDevHlp->pfnISASetIrqNoWait(pDevIns, iIrq, iLevel); 3605 #endif 3606 } 3607 3608 /** 3609 * @copydoc PDMDEVHLP::pfnPhysRead 3586 pDevIns->CTX_SUFF(pDevHlp)->pfnISASetIrq(pDevIns, iIrq, iLevel); 3587 } 3588 3589 /** 3590 * @copydoc PDMDEVHLPR3::pfnPhysRead 3610 3591 */ 3611 3592 DECLINLINE(void) PDMDevHlpPhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 3612 3593 { 3613 #ifdef IN_GC 3614 pDevIns->pDevHlpGC->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead); 3615 #elif defined(IN_RING0) 3616 pDevIns->pDevHlpR0->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead); 3617 #else 3618 pDevIns->pDevHlp->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead); 3619 #endif 3620 } 3621 3622 /** 3623 * @copydoc PDMDEVHLP::pfnPhysWrite 3594 pDevIns->CTX_SUFF(pDevHlp)->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead); 3595 } 3596 3597 /** 3598 * @copydoc PDMDEVHLPR3::pfnPhysWrite 3624 3599 */ 3625 3600 DECLINLINE(void) PDMDevHlpPhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 3626 3601 { 3627 #ifdef IN_GC 3628 pDevIns->pDevHlpGC->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite); 3629 #elif defined(IN_RING0) 3630 pDevIns->pDevHlpR0->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite); 3631 #else 3632 pDevIns->pDevHlp->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite); 3633 #endif 3634 } 3635 3636 /** 3637 * @copydoc PDMDEVHLP::pfnA20IsEnabled 3602 pDevIns->CTX_SUFF(pDevHlp)->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite); 3603 } 3604 3605 /** 3606 * @copydoc PDMDEVHLPR3::pfnA20IsEnabled 3638 3607 */ 3639 3608 DECLINLINE(bool) PDMDevHlpA20IsEnabled(PPDMDEVINS pDevIns) 3640 3609 { 3641 #ifdef IN_GC 3642 return pDevIns->pDevHlpGC->pfnA20IsEnabled(pDevIns); 3643 #elif defined(IN_RING0) 3644 return pDevIns->pDevHlpR0->pfnA20IsEnabled(pDevIns); 3645 #else 3646 return pDevIns->pDevHlp->pfnA20IsEnabled(pDevIns); 3647 #endif 3648 } 3649 3650 /** 3651 * @copydoc PDMDEVHLP::pfnVMSetError 3610 return pDevIns->CTX_SUFF(pDevHlp)->pfnA20IsEnabled(pDevIns); 3611 } 3612 3613 /** 3614 * @copydoc PDMDEVHLPR3::pfnVMSetError 3652 3615 */ 3653 3616 DECLINLINE(int) PDMDevHlpVMSetError(PPDMDEVINS pDevIns, const int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) … … 3655 3618 va_list va; 3656 3619 va_start(va, pszFormat); 3657 #ifdef IN_GC 3658 pDevIns->pDevHlpGC->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va); 3659 #elif defined(IN_RING0) 3660 pDevIns->pDevHlpR0->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va); 3661 #else 3662 pDevIns->pDevHlp->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va); 3663 #endif 3620 pDevIns->CTX_SUFF(pDevHlp)->pfnVMSetErrorV(pDevIns, rc, RT_SRC_POS_ARGS, pszFormat, va); 3664 3621 va_end(va); 3665 3622 return rc; … … 3667 3624 3668 3625 /** 3669 * @copydoc PDMDEVHLP ::pfnVMSetRuntimeError3626 * @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError 3670 3627 */ 3671 3628 DECLINLINE(int) PDMDevHlpVMSetRuntimeError(PPDMDEVINS pDevIns, bool fFatal, const char *pszErrorID, const char *pszFormat, ...) … … 3674 3631 int rc; 3675 3632 va_start(va, pszFormat); 3676 #ifdef IN_GC 3677 rc = pDevIns->pDevHlpGC->pfnVMSetRuntimeErrorV(pDevIns, fFatal, pszErrorID, pszFormat, va); 3678 #elif defined(IN_RING0) 3679 rc = pDevIns->pDevHlpR0->pfnVMSetRuntimeErrorV(pDevIns, fFatal, pszErrorID, pszFormat, va); 3680 #else 3681 rc = pDevIns->pDevHlp->pfnVMSetRuntimeErrorV(pDevIns, fFatal, pszErrorID, pszFormat, va); 3682 #endif 3633 rc = pDevIns->CTX_SUFF(pDevHlp)->pfnVMSetRuntimeErrorV(pDevIns, fFatal, pszErrorID, pszFormat, va); 3683 3634 va_end(va); 3684 3635 return rc; -
trunk/include/VBox/pdmins.h
r12653 r12970 53 53 * Converts a PDM Device, USB Device, or Driver instance pointer to a RC pointer to the instance data. 54 54 */ 55 #define PDMINS_2_DATA_RCPTR(pIns) ( (pIns)->pvInstanceData GC )55 #define PDMINS_2_DATA_RCPTR(pIns) ( (pIns)->pvInstanceDataRC ) 56 56 57 57 /** @def PDMINS_2_DATA_R3PTR -
trunk/src/VBox/VMM/PDM.cpp
r12807 r12970 311 311 * Devices. 312 312 */ 313 RCPTRTYPE(PCPDMDEVHLPGC) pDevHlpGC;314 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_pdm GCDevHlp", &pDevHlpGC);315 AssertReleaseMsgRC(rc, ("rc=%Vrc when resolving g_pdm GCDevHlp\n", rc));316 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)313 PCPDMDEVHLPRC pDevHlpRC; 314 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_pdmRCDevHlp", &pDevHlpRC); 315 AssertReleaseMsgRC(rc, ("rc=%Vrc when resolving g_pdmRCDevHlp\n", rc)); 316 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 317 317 { 318 318 if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC) 319 319 { 320 pDevIns->pDevHlpGC = pDevHlpGC; 321 pDevIns->pvInstanceDataGC = MMHyperR3ToRC(pVM, pDevIns->pvInstanceDataR3); 322 pDevIns->pvInstanceDataR0 = MMHyperR3ToR0(pVM, pDevIns->pvInstanceDataR3); 323 pDevIns->Internal.s.pVMGC = pVM->pVMGC; 324 if (pDevIns->Internal.s.pPciBusHC) 325 pDevIns->Internal.s.pPciBusGC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciBusHC); 326 if (pDevIns->Internal.s.pPciDeviceHC) 327 pDevIns->Internal.s.pPciDeviceGC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciDeviceHC); 320 pDevIns->pDevHlpRC = pDevHlpRC; 321 pDevIns->pvInstanceDataRC = MMHyperR3ToRC(pVM, pDevIns->pvInstanceDataR3); 322 pDevIns->Internal.s.pVMRC = pVM->pVMRC; 323 if (pDevIns->Internal.s.pPciBusR3) 324 pDevIns->Internal.s.pPciBusRC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciBusR3); 325 if (pDevIns->Internal.s.pPciDeviceR3) 326 pDevIns->Internal.s.pPciDeviceRC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciDeviceR3); 328 327 if (pDevIns->pDevReg->pfnRelocate) 329 328 { … … 416 415 417 416 /* then the 'normal' ones. */ 418 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)419 { 420 pdmR3TermLuns(pVM, pDevIns->Internal.s.pLuns HC, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance);417 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 418 { 419 pdmR3TermLuns(pVM, pDevIns->Internal.s.pLunsR3, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance); 421 420 422 421 if (pDevIns->pDevReg->pfnDestruct) … … 508 507 /** @todo We might have to filter out some device classes, like USB attached devices. */ 509 508 uint32_t i = 0; 510 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC, i++)509 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3, i++) 511 510 { 512 511 SSMR3PutU32(pSSM, i); … … 626 625 uint32_t i = 0; 627 626 PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; 628 for (;;pDevIns = pDevIns->Internal.s.pNext HC, i++)627 for (;;pDevIns = pDevIns->Internal.s.pNextR3, i++) 629 628 { 630 629 /* Get the separator / terminator. */ … … 694 693 * The attached drivers are processed first. 695 694 */ 696 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)697 { 698 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)695 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 696 { 697 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 699 698 /** @todo Inverse the order here? */ 700 699 for (PPDMDRVINS pDrvIns = pLun->pTop; pDrvIns; pDrvIns = pDrvIns->Internal.s.pDown) … … 767 766 * The attached drivers are processed first. 768 767 */ 769 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)770 { 771 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)768 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 769 { 770 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 772 771 /** @todo Inverse the order here? */ 773 772 for (PPDMDRVINS pDrvIns = pLun->pTop; pDrvIns; pDrvIns = pDrvIns->Internal.s.pDown) … … 826 825 * The attached drivers are processed first. 827 826 */ 828 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)829 { 830 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)827 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 828 { 829 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 831 830 for (PPDMDRVINS pDrvIns = pLun->pTop; pDrvIns; pDrvIns = pDrvIns->Internal.s.pDown) 832 831 if (pDrvIns->pDrvReg->pfnSuspend) … … 889 888 * The attached drivers are processed first. 890 889 */ 891 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)892 { 893 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)890 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 891 { 892 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 894 893 for (PPDMDRVINS pDrvIns = pLun->pTop; pDrvIns; pDrvIns = pDrvIns->Internal.s.pDown) 895 894 if (pDrvIns->pDrvReg->pfnResume) … … 952 951 * The attached drivers are processed first. 953 952 */ 954 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)955 { 956 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)953 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 954 { 955 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 957 956 for (PPDMDRVINS pDrvIns = pLun->pTop; pDrvIns; pDrvIns = pDrvIns->Internal.s.pDown) 958 957 if (pDrvIns->pDrvReg->pfnPowerOff) … … 1031 1030 * Iterate device instances. 1032 1031 */ 1033 for (PPDMDEVINS pDevIns = pDev->pInstances; pDevIns; pDevIns = pDevIns->Internal.s.pPerDeviceNext HC)1032 for (PPDMDEVINS pDevIns = pDev->pInstances; pDevIns; pDevIns = pDevIns->Internal.s.pPerDeviceNextR3) 1034 1033 { 1035 1034 if (pDevIns->iInstance == iInstance) -
trunk/src/VBox/VMM/PDMDevice.cpp
r12807 r12970 80 80 /* VSlick regex: 81 81 search : \om/\*\*.+?\*\/\nDECLCALLBACKMEMBER\(([^,]*), *pfn([^)]*)\)\( 82 replace: \/\*\* @copydoc PDMDEVHLP ::pfn\2 \*\/\nstatic DECLCALLBACK\(\1\) pdmR3DevHlp_\2\(82 replace: \/\*\* @copydoc PDMDEVHLPR3::pfn\2 \*\/\nstatic DECLCALLBACK\(\1\) pdmR3DevHlp_\2\( 83 83 */ 84 84 … … 298 298 * The device helper structure for trusted devices. 299 299 */ 300 const PDMDEVHLP g_pdmR3DevHlpTrusted =300 const PDMDEVHLPR3 g_pdmR3DevHlpTrusted = 301 301 { 302 302 PDM_DEVHLP_VERSION, … … 394 394 * The device helper structure for non-trusted devices. 395 395 */ 396 const PDMDEVHLP g_pdmR3DevHlpUnTrusted =396 const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted = 397 397 { 398 398 PDM_DEVHLP_VERSION, … … 601 601 602 602 /* 603 * Get the GC & R0 devhlps and create the devhlp R3 task queue.604 */ 605 RCPTRTYPE(PCPDMDEVHLPGC) pDevHlpGC;606 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_pdm GCDevHlp", &pDevHlpGC);603 * Get the RC & R0 devhlps and create the devhlp R3 task queue. 604 */ 605 PCPDMDEVHLPRC pDevHlpRC; 606 int rc = PDMR3GetSymbolGC(pVM, NULL, "g_pdmRCDevHlp", &pDevHlpRC); 607 607 AssertReleaseRCReturn(rc, rc); 608 608 609 R0PTRTYPE(PCPDMDEVHLPR0)pDevHlpR0;609 PCPDMDEVHLPR0 pDevHlpR0; 610 610 rc = PDMR3GetSymbolR0(pVM, NULL, "g_pdmR0DevHlp", &pDevHlpR0); 611 611 AssertReleaseRCReturn(rc, rc); … … 883 883 */ 884 884 pDevIns->u32Version = PDM_DEVINS_VERSION; 885 //pDevIns->Internal.s.pNextHC = NULL; 886 //pDevIns->Internal.s.pPerDeviceNextHC = NULL; 887 pDevIns->Internal.s.pDevHC = paDevs[i].pDev; 888 pDevIns->Internal.s.pVMHC = pVM; 889 pDevIns->Internal.s.pVMGC = pVM->pVMGC; 890 //pDevIns->Internal.s.pLunsHC = NULL; 885 //pDevIns->Internal.s.pNextR3 = NULL; 886 //pDevIns->Internal.s.pPerDeviceNextR3 = NULL; 887 pDevIns->Internal.s.pDevR3 = paDevs[i].pDev; 888 pDevIns->Internal.s.pVMR3 = pVM; 889 pDevIns->Internal.s.pVMR0 = pVM->pVMR0; 890 pDevIns->Internal.s.pVMRC = pVM->pVMRC; 891 //pDevIns->Internal.s.pLunsR3 = NULL; 891 892 pDevIns->Internal.s.pCfgHandle = paDevs[i].pNode; 892 //pDevIns->Internal.s.pPciDevice = NULL; 893 //pDevIns->Internal.s.pPciBus = NULL; /** @todo pci bus selection. (in 2008 perhaps) */ 894 pDevIns->pDevHlp = fTrusted ? &g_pdmR3DevHlpTrusted : &g_pdmR3DevHlpUnTrusted; 895 pDevIns->pDevHlpGC = pDevHlpGC; 893 //pDevIns->Internal.s.pPciDeviceR3 = NULL; 894 //pDevIns->Internal.s.pPciBusR3 = NULL; /** @todo pci bus selection. (in 2008 perhaps) */ 895 //pDevIns->Internal.s.pPciDeviceR0 = 0; 896 //pDevIns->Internal.s.pPciBusR0 = 0; 897 //pDevIns->Internal.s.pPciDeviceRC = 0; 898 //pDevIns->Internal.s.pPciBusRC = 0; 899 pDevIns->pDevHlpR3 = fTrusted ? &g_pdmR3DevHlpTrusted : &g_pdmR3DevHlpUnTrusted; 900 pDevIns->pDevHlpRC = pDevHlpRC; 896 901 pDevIns->pDevHlpR0 = pDevHlpR0; 897 902 pDevIns->pDevReg = paDevs[i].pDev->pDevReg; … … 899 904 pDevIns->iInstance = paDevs[i].iInstance; 900 905 pDevIns->pvInstanceDataR3 = &pDevIns->achInstanceData[0]; 901 pDevIns->pvInstanceData GC =pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC902 ? MMHyperHC2GC(pVM, pDevIns->pvInstanceDataR3) : 0;903 pDevIns->pvInstanceDataR0 = 904 ? MMHyperR3ToR0(pVM, pDevIns->pvInstanceDataR3) : 0;906 pDevIns->pvInstanceDataRC = pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC 907 ? MMHyperR3ToRC(pVM, pDevIns->pvInstanceDataR3) : NIL_RTRCPTR; 908 pDevIns->pvInstanceDataR0 = pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0 909 ? MMHyperR3ToR0(pVM, pDevIns->pvInstanceDataR3) : NIL_RTR0PTR; 905 910 906 911 /* … … 913 918 else 914 919 { 915 while (pPrev1->Internal.s.pNext HC)916 pPrev1 = pPrev1->Internal.s.pNext HC;917 pPrev1->Internal.s.pNext HC= pDevIns;920 while (pPrev1->Internal.s.pNextR3) 921 pPrev1 = pPrev1->Internal.s.pNextR3; 922 pPrev1->Internal.s.pNextR3 = pDevIns; 918 923 } 919 924 … … 924 929 else 925 930 { 926 while (pPrev2->Internal.s.pPerDeviceNext HC)927 pPrev2 = pPrev2->Internal.s.pPerDeviceNext HC;928 pPrev2->Internal.s.pPerDeviceNext HC= pDevIns;931 while (pPrev2->Internal.s.pPerDeviceNextR3) 932 pPrev2 = pPrev2->Internal.s.pPerDeviceNextR3; 933 pPrev2->Internal.s.pPerDeviceNextR3 = pDevIns; 929 934 } 930 935 … … 967 972 } 968 973 969 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNext HC)974 for (PPDMDEVINS pDevIns = pVM->pdm.s.pDevInstances; pDevIns; pDevIns = pDevIns->Internal.s.pNextR3) 970 975 { 971 976 if (pDevIns->pDevReg->pfnInitComplete) … … 1222 1227 1223 1228 1224 /** @copydoc PDMDEVHLP ::pfnIOPortRegister */1229 /** @copydoc PDMDEVHLPR3::pfnIOPortRegister */ 1225 1230 static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn, 1226 1231 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc) … … 1229 1234 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 1230 1235 Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc)); 1231 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1232 1233 int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVM HC, pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);1236 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1237 1238 int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc); 1234 1239 1235 1240 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1238 1243 1239 1244 1240 /** @copydoc PDMDEVHLP ::pfnIOPortRegisterGC */1245 /** @copydoc PDMDEVHLPR3::pfnIOPortRegisterGC */ 1241 1246 static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterGC(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTRCPTR pvUser, 1242 1247 const char *pszOut, const char *pszIn, … … 1244 1249 { 1245 1250 PDMDEV_ASSERT_DEVINS(pDevIns); 1246 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1251 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1247 1252 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 1248 1253 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc)); … … 1258 1263 if (pszIn) 1259 1264 { 1260 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszIn, &GCPtrIn);1265 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszIn, &GCPtrIn); 1261 1266 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pDevReg->szGCMod, pszIn)); 1262 1267 } … … 1264 1269 if (pszOut && VBOX_SUCCESS(rc)) 1265 1270 { 1266 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszOut, &GCPtrOut);1271 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszOut, &GCPtrOut); 1267 1272 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pDevReg->szGCMod, pszOut)); 1268 1273 } … … 1270 1275 if (pszInStr && VBOX_SUCCESS(rc)) 1271 1276 { 1272 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszInStr, &GCPtrInStr);1277 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszInStr, &GCPtrInStr); 1273 1278 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pDevReg->szGCMod, pszInStr)); 1274 1279 } … … 1276 1281 if (pszOutStr && VBOX_SUCCESS(rc)) 1277 1282 { 1278 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszOutStr, &GCPtrOutStr);1283 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszOutStr, &GCPtrOutStr); 1279 1284 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pDevReg->szGCMod, pszOutStr)); 1280 1285 } 1281 1286 1282 1287 if (VBOX_SUCCESS(rc)) 1283 rc = IOMR3IOPortRegisterRC(pDevIns->Internal.s.pVM HC, pDevIns, Port, cPorts, pvUser, GCPtrOut, GCPtrIn, GCPtrOutStr, GCPtrInStr, pszDesc);1288 rc = IOMR3IOPortRegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, GCPtrOut, GCPtrIn, GCPtrOutStr, GCPtrInStr, pszDesc); 1284 1289 } 1285 1290 else … … 1294 1299 1295 1300 1296 /** @copydoc PDMDEVHLP ::pfnIOPortRegisterR0 */1301 /** @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0 */ 1297 1302 static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTR0PTR pvUser, 1298 1303 const char *pszOut, const char *pszIn, … … 1300 1305 { 1301 1306 PDMDEV_ASSERT_DEVINS(pDevIns); 1302 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1307 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1303 1308 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 1304 1309 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc)); … … 1314 1319 if (pszIn) 1315 1320 { 1316 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszIn, &pfnR0PtrIn);1321 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszIn, &pfnR0PtrIn); 1317 1322 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pDevReg->szR0Mod, pszIn)); 1318 1323 } … … 1320 1325 if (pszOut && VBOX_SUCCESS(rc)) 1321 1326 { 1322 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszOut, &pfnR0PtrOut);1327 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszOut, &pfnR0PtrOut); 1323 1328 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pDevReg->szR0Mod, pszOut)); 1324 1329 } … … 1326 1331 if (pszInStr && VBOX_SUCCESS(rc)) 1327 1332 { 1328 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszInStr, &pfnR0PtrInStr);1333 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszInStr, &pfnR0PtrInStr); 1329 1334 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pDevReg->szR0Mod, pszInStr)); 1330 1335 } … … 1332 1337 if (pszOutStr && VBOX_SUCCESS(rc)) 1333 1338 { 1334 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszOutStr, &pfnR0PtrOutStr);1339 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszOutStr, &pfnR0PtrOutStr); 1335 1340 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pDevReg->szR0Mod, pszOutStr)); 1336 1341 } 1337 1342 1338 1343 if (VBOX_SUCCESS(rc)) 1339 rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVM HC, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);1344 rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc); 1340 1345 } 1341 1346 else … … 1350 1355 1351 1356 1352 /** @copydoc PDMDEVHLP ::pfnIOPortDeregister */1357 /** @copydoc PDMDEVHLPR3::pfnIOPortDeregister */ 1353 1358 static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts) 1354 1359 { 1355 1360 PDMDEV_ASSERT_DEVINS(pDevIns); 1356 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1361 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1357 1362 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, 1358 1363 Port, cPorts)); 1359 1364 1360 int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVM HC, pDevIns, Port, cPorts);1365 int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts); 1361 1366 1362 1367 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1365 1370 1366 1371 1367 /** @copydoc PDMDEVHLP ::pfnMMIORegister */1372 /** @copydoc PDMDEVHLPR3::pfnMMIORegister */ 1368 1373 static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTHCPTR pvUser, 1369 1374 PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill, … … 1371 1376 { 1372 1377 PDMDEV_ASSERT_DEVINS(pDevIns); 1373 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1378 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1374 1379 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%VGp cbRange=%#x pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p pszDesc=%p:{%s}\n", 1375 1380 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, pszDesc)); 1376 1381 1377 int rc = IOMR3MMIORegisterR3(pDevIns->Internal.s.pVM HC, pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc);1382 int rc = IOMR3MMIORegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc); 1378 1383 1379 1384 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1382 1387 1383 1388 1384 /** @copydoc PDMDEVHLP ::pfnMMIORegisterGC */1389 /** @copydoc PDMDEVHLPR3::pfnMMIORegisterGC */ 1385 1390 static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterGC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser, 1386 1391 const char *pszWrite, const char *pszRead, const char *pszFill, … … 1388 1393 { 1389 1394 PDMDEV_ASSERT_DEVINS(pDevIns); 1390 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1395 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1391 1396 LogFlow(("pdmR3DevHlp_MMIORegisterGC: caller='%s'/%d: GCPhysStart=%VGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n", 1392 1397 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill)); … … 1402 1407 RTGCPTR32 GCPtrWrite = 0; 1403 1408 if (pszWrite) 1404 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszWrite, &GCPtrWrite);1409 rc = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszWrite, &GCPtrWrite); 1405 1410 RTGCPTR32 GCPtrRead = 0; 1406 1411 int rc2 = VINF_SUCCESS; 1407 1412 if (pszRead) 1408 rc2 = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszRead, &GCPtrRead);1413 rc2 = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszRead, &GCPtrRead); 1409 1414 RTGCPTR32 GCPtrFill = 0; 1410 1415 int rc3 = VINF_SUCCESS; 1411 1416 if (pszFill) 1412 rc3 = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szGCMod, pszFill, &GCPtrFill);1417 rc3 = PDMR3GetSymbolGCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szGCMod, pszFill, &GCPtrFill); 1413 1418 if (VBOX_SUCCESS(rc) && VBOX_SUCCESS(rc2) && VBOX_SUCCESS(rc3)) 1414 rc = IOMR3MMIORegisterRC(pDevIns->Internal.s.pVM HC, pDevIns, GCPhysStart, cbRange, pvUser, GCPtrWrite, GCPtrRead, GCPtrFill);1419 rc = IOMR3MMIORegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, GCPtrWrite, GCPtrRead, GCPtrFill); 1415 1420 else 1416 1421 { … … 1434 1439 } 1435 1440 1436 /** @copydoc PDMDEVHLP ::pfnMMIORegisterR0 */1441 /** @copydoc PDMDEVHLPR3::pfnMMIORegisterR0 */ 1437 1442 static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTR0PTR pvUser, 1438 1443 const char *pszWrite, const char *pszRead, const char *pszFill, … … 1440 1445 { 1441 1446 PDMDEV_ASSERT_DEVINS(pDevIns); 1442 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1447 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1443 1448 LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%VGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n", 1444 1449 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill)); … … 1454 1459 R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0; 1455 1460 if (pszWrite) 1456 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszWrite, &pfnR0PtrWrite);1461 rc = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszWrite, &pfnR0PtrWrite); 1457 1462 R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0; 1458 1463 int rc2 = VINF_SUCCESS; 1459 1464 if (pszRead) 1460 rc2 = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszRead, &pfnR0PtrRead);1465 rc2 = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszRead, &pfnR0PtrRead); 1461 1466 R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0; 1462 1467 int rc3 = VINF_SUCCESS; 1463 1468 if (pszFill) 1464 rc3 = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVM HC, pDevIns->pDevReg->szR0Mod, pszFill, &pfnR0PtrFill);1469 rc3 = PDMR3GetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszFill, &pfnR0PtrFill); 1465 1470 if (VBOX_SUCCESS(rc) && VBOX_SUCCESS(rc2) && VBOX_SUCCESS(rc3)) 1466 rc = IOMR3MMIORegisterR0(pDevIns->Internal.s.pVM HC, pDevIns, GCPhysStart, cbRange, pvUser, pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);1471 rc = IOMR3MMIORegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill); 1467 1472 else 1468 1473 { … … 1487 1492 1488 1493 1489 /** @copydoc PDMDEVHLP ::pfnMMIODeregister */1494 /** @copydoc PDMDEVHLPR3::pfnMMIODeregister */ 1490 1495 static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange) 1491 1496 { 1492 1497 PDMDEV_ASSERT_DEVINS(pDevIns); 1493 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1498 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1494 1499 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%VGp cbRange=%#x\n", 1495 1500 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange)); 1496 1501 1497 int rc = IOMR3MMIODeregister(pDevIns->Internal.s.pVM HC, pDevIns, GCPhysStart, cbRange);1502 int rc = IOMR3MMIODeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange); 1498 1503 1499 1504 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1502 1507 1503 1508 1504 /** @copydoc PDMDEVHLP ::pfnROMRegister */1509 /** @copydoc PDMDEVHLPR3::pfnROMRegister */ 1505 1510 static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, const void *pvBinary, bool fShadow, const char *pszDesc) 1506 1511 { 1507 1512 PDMDEV_ASSERT_DEVINS(pDevIns); 1508 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1513 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1509 1514 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%VGp cbRange=%#x pvBinary=%p fShadow=%RTbool pszDesc=%p:{%s}\n", 1510 1515 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, fShadow, pszDesc, pszDesc)); 1511 1516 1512 int rc = MMR3PhysRomRegister(pDevIns->Internal.s.pVM HC, pDevIns, GCPhysStart, cbRange, pvBinary, fShadow, pszDesc);1517 int rc = MMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, fShadow, pszDesc); 1513 1518 1514 1519 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1517 1522 1518 1523 1519 /** @copydoc PDMDEVHLP ::pfnSSMRegister */1524 /** @copydoc PDMDEVHLPR3::pfnSSMRegister */ 1520 1525 static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, const char *pszName, uint32_t u32Instance, uint32_t u32Version, size_t cbGuess, 1521 1526 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone, … … 1523 1528 { 1524 1529 PDMDEV_ASSERT_DEVINS(pDevIns); 1525 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1530 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1526 1531 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: pszName=%p:{%s} u32Instance=%#x u32Version=#x cbGuess=%#x pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoaddone=%p\n", 1527 1532 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, u32Instance, u32Version, cbGuess, pfnSavePrep, pfnSaveExec, pfnSaveDone, pfnLoadPrep, pfnLoadExec, pfnLoadDone)); 1528 1533 1529 int rc = SSMR3Register(pDevIns->Internal.s.pVM HC, pDevIns, pszName, u32Instance, u32Version, cbGuess,1534 int rc = SSMR3Register(pDevIns->Internal.s.pVMR3, pDevIns, pszName, u32Instance, u32Version, cbGuess, 1530 1535 pfnSavePrep, pfnSaveExec, pfnSaveDone, 1531 1536 pfnLoadPrep, pfnLoadExec, pfnLoadDone); … … 1536 1541 1537 1542 1538 /** @copydoc PDMDEVHLP ::pfnTMTimerCreate */1543 /** @copydoc PDMDEVHLPR3::pfnTMTimerCreate */ 1539 1544 static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, const char *pszDesc, PPTMTIMERR3 ppTimer) 1540 1545 { 1541 1546 PDMDEV_ASSERT_DEVINS(pDevIns); 1542 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1547 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1543 1548 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pszDesc=%p:{%s} ppTimer=%p\n", 1544 1549 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, enmClock, pfnCallback, pszDesc, pszDesc, ppTimer)); 1545 1550 1546 int rc = TMR3TimerCreateDevice(pDevIns->Internal.s.pVM HC, pDevIns, enmClock, pfnCallback, pszDesc, ppTimer);1551 int rc = TMR3TimerCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, enmClock, pfnCallback, pszDesc, ppTimer); 1547 1552 1548 1553 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 1551 1556 1552 1557 1553 /** @copydoc PDMDEVHLP ::pfnTMTimerCreateExternal */1558 /** @copydoc PDMDEVHLPR3::pfnTMTimerCreateExternal */ 1554 1559 static DECLCALLBACK(PTMTIMERR3) pdmR3DevHlp_TMTimerCreateExternal(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMEREXT pfnCallback, void *pvUser, const char *pszDesc) 1555 1560 { 1556 1561 PDMDEV_ASSERT_DEVINS(pDevIns); 1557 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);1558 1559 return TMR3TimerCreateExternal(pDevIns->Internal.s.pVM HC, enmClock, pfnCallback, pvUser, pszDesc);1560 } 1561 1562 /** @copydoc PDMDEVHLP ::pfnPCIRegister */1562 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 1563 1564 return TMR3TimerCreateExternal(pDevIns->Internal.s.pVMR3, enmClock, pfnCallback, pvUser, pszDesc); 1565 } 1566 1567 /** @copydoc PDMDEVHLPR3::pfnPCIRegister */ 1563 1568 static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev) 1564 1569 { 1565 1570 PDMDEV_ASSERT_DEVINS(pDevIns); 1566 PVM pVM = pDevIns->Internal.s.pVM HC;1571 PVM pVM = pDevIns->Internal.s.pVMR3; 1567 1572 VM_ASSERT_EMT(pVM); 1568 1573 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Vhxs}\n", … … 1584 1589 return VERR_INVALID_PARAMETER; 1585 1590 } 1586 if (pDevIns->Internal.s.pPciDevice HC)1591 if (pDevIns->Internal.s.pPciDeviceR3) 1587 1592 { 1588 1593 /** @todo the PCI device vs. PDM device designed is a bit flawed if we have to … … 1599 1604 * already have one. If not, we'll just take the first one. 1600 1605 */ 1601 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBus HC;1606 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; 1602 1607 if (!pBus) 1603 pBus = pDevIns->Internal.s.pPciBus HC= &pVM->pdm.s.aPciBuses[0];1608 pBus = pDevIns->Internal.s.pPciBusR3 = &pVM->pdm.s.aPciBuses[0]; 1604 1609 int rc; 1605 1610 if (pBus) 1606 1611 { 1607 1612 if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC) 1608 pDevIns->Internal.s.pPciBusGC = MMHyperHC2GC(pVM, pDevIns->Internal.s.pPciBusHC); 1613 pDevIns->Internal.s.pPciBusR0 = MMHyperR3ToR0(pVM, pDevIns->Internal.s.pPciBusR3); 1614 else 1615 pDevIns->Internal.s.pPciBusR0 = NIL_RTR0PTR; 1616 1617 if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC) 1618 pDevIns->Internal.s.pPciBusRC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciBusR3); 1619 else 1620 pDevIns->Internal.s.pPciBusRC = NIL_RTRCPTR; 1609 1621 1610 1622 /* … … 1654 1666 if (VBOX_SUCCESS(rc)) 1655 1667 { 1656 pDevIns->Internal.s.pPciDeviceHC = pPciDev; 1668 pPciDev->pDevIns = pDevIns; 1669 1670 pDevIns->Internal.s.pPciDeviceR3 = pPciDev; 1671 if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0) 1672 pDevIns->Internal.s.pPciDeviceR0 = MMHyperR3ToR0(pVM, pPciDev); 1673 else 1674 pDevIns->Internal.s.pPciDeviceR0 = NIL_RTR0PTR; 1675 1657 1676 if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_GC) 1658 pDevIns->Internal.s.pPciDevice GC = MMHyperHC2GC(pVM, pPciDev);1677 pDevIns->Internal.s.pPciDeviceRC = MMHyperR3ToRC(pVM, pPciDev); 1659 1678 else 1660 pDevIns->Internal.s.pPciDevice GC = 0;1661 pPciDev->pDevIns = pDevIns; 1679 pDevIns->Internal.s.pPciDeviceRC = NIL_RTRCPTR; 1680 1662 1681 Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n", 1663 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciDev->devfn, pDevIns->Internal.s.pPciBus HC->iBus));1682 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciDev->devfn, pDevIns->Internal.s.pPciBusR3->iBus)); 1664 1683 } 1665 1684 } … … 1675 1694 1676 1695 1677 /** @copydoc PDMDEVHLP ::pfnPCIIORegionRegister */1696 /** @copydoc PDMDEVHLPR3::pfnPCIIORegionRegister */ 1678 1697 static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback) 1679 1698 { 1680 1699 PDMDEV_ASSERT_DEVINS(pDevIns); 1681 PVM pVM = pDevIns->Internal.s.pVM HC;1700 PVM pVM = pDevIns->Internal.s.pVMR3; 1682 1701 VM_ASSERT_EMT(pVM); 1683 1702 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: iRegion=%d cbRegion=%#x enmType=%d pfnCallback=%p\n", … … 1716 1735 */ 1717 1736 int rc; 1718 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDevice HC;1737 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3; 1719 1738 if (pPciDev) 1720 1739 { … … 1730 1749 } 1731 1750 1732 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBus HC;1751 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; 1733 1752 Assert(pBus); 1734 1753 pdmLock(pVM); … … 1747 1766 1748 1767 1749 /** @copydoc PDMDEVHLP ::pfnPCISetConfigCallbacks */1768 /** @copydoc PDMDEVHLPR3::pfnPCISetConfigCallbacks */ 1750 1769 static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld, 1751 1770 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld) 1752 1771 { 1753 1772 PDMDEV_ASSERT_DEVINS(pDevIns); 1754 PVM pVM = pDevIns->Internal.s.pVM HC;1773 PVM pVM = pDevIns->Internal.s.pVMR3; 1755 1774 VM_ASSERT_EMT(pVM); 1756 1775 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n", … … 1767 1786 1768 1787 if (!pPciDev) 1769 pPciDev = pDevIns->Internal.s.pPciDevice HC;1788 pPciDev = pDevIns->Internal.s.pPciDeviceR3; 1770 1789 AssertReleaseMsg(pPciDev, ("You must register your device first!\n")); 1771 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBus HC;1790 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; 1772 1791 AssertRelease(pBus); 1773 1792 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING); … … 1784 1803 1785 1804 1786 /** @copydoc PDMDEVHLP ::pfnPCISetIrq */1805 /** @copydoc PDMDEVHLPR3::pfnPCISetIrq */ 1787 1806 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 1788 1807 { … … 1798 1817 * Must have a PCI device registered! 1799 1818 */ 1800 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDevice HC;1819 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3; 1801 1820 if (pPciDev) 1802 1821 { 1803 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBus HC; /** @todo the bus should be associated with the PCI device not the PDM device. */1822 PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; /** @todo the bus should be associated with the PCI device not the PDM device. */ 1804 1823 Assert(pBus); 1805 PVM pVM = pDevIns->Internal.s.pVM HC;1824 PVM pVM = pDevIns->Internal.s.pVMR3; 1806 1825 pdmLock(pVM); 1807 1826 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel); … … 1815 1834 1816 1835 1817 /** @copydoc PDMDEVHLP ::pfnPCISetIrqNoWait */1836 /** @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait */ 1818 1837 static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel) 1819 1838 { … … 1822 1841 1823 1842 1824 /** @copydoc PDMDEVHLP ::pfnISASetIrq */1843 /** @copydoc PDMDEVHLPR3::pfnISASetIrq */ 1825 1844 static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 1826 1845 { … … 1833 1852 /** @todo iIrq and iLevel checks. */ 1834 1853 1835 PVM pVM = pDevIns->Internal.s.pVM HC;1854 PVM pVM = pDevIns->Internal.s.pVMR3; 1836 1855 PDMIsaSetIrq(pVM, iIrq, iLevel); /* (The API takes the lock.) */ 1837 1856 … … 1840 1859 1841 1860 1842 /** @copydoc PDMDEVHLP ::pfnISASetIrqNoWait */1861 /** @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait */ 1843 1862 static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel) 1844 1863 { … … 1847 1866 1848 1867 1849 /** @copydoc PDMDEVHLP ::pfnDriverAttach */1868 /** @copydoc PDMDEVHLPR3::pfnDriverAttach */ 1850 1869 static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, RTUINT iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc) 1851 1870 { 1852 1871 PDMDEV_ASSERT_DEVINS(pDevIns); 1853 PVM pVM = pDevIns->Internal.s.pVM HC;1872 PVM pVM = pDevIns->Internal.s.pVMR3; 1854 1873 VM_ASSERT_EMT(pVM); 1855 1874 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n", … … 1860 1879 */ 1861 1880 PPDMLUN pLunPrev = NULL; 1862 PPDMLUN pLun = pDevIns->Internal.s.pLuns HC;1881 PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; 1863 1882 for (; pLun; pLunPrev = pLun, pLun = pLun->pNext) 1864 1883 if (pLun->iLun == iLun) … … 1891 1910 pLun->pBase = pBaseInterface; 1892 1911 if (!pLunPrev) 1893 pDevIns->Internal.s.pLuns HC= pLun;1912 pDevIns->Internal.s.pLunsR3 = pLun; 1894 1913 else 1895 1914 pLunPrev->pNext = pLun; … … 2018 2037 2019 2038 2020 /** @copydoc PDMDEVHLP ::pfnMMHeapAlloc */2039 /** @copydoc PDMDEVHLPR3::pfnMMHeapAlloc */ 2021 2040 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb) 2022 2041 { … … 2024 2043 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 2025 2044 2026 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVM HC, MM_TAG_PDM_DEVICE_USER, cb);2045 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 2027 2046 2028 2047 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); … … 2031 2050 2032 2051 2033 /** @copydoc PDMDEVHLP ::pfnMMHeapAllocZ */2052 /** @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ */ 2034 2053 static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb) 2035 2054 { … … 2037 2056 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb)); 2038 2057 2039 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVM HC, MM_TAG_PDM_DEVICE_USER, cb);2058 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb); 2040 2059 2041 2060 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv)); … … 2044 2063 2045 2064 2046 /** @copydoc PDMDEVHLP ::pfnMMHeapFree */2065 /** @copydoc PDMDEVHLPR3::pfnMMHeapFree */ 2047 2066 static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv) 2048 2067 { … … 2056 2075 2057 2076 2058 /** @copydoc PDMDEVHLP ::pfnVMSetError */2077 /** @copydoc PDMDEVHLPR3::pfnVMSetError */ 2059 2078 static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) 2060 2079 { … … 2062 2081 va_list args; 2063 2082 va_start(args, pszFormat); 2064 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM HC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);2083 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2); 2065 2084 va_end(args); 2066 2085 return rc; … … 2068 2087 2069 2088 2070 /** @copydoc PDMDEVHLP ::pfnVMSetErrorV */2089 /** @copydoc PDMDEVHLPR3::pfnVMSetErrorV */ 2071 2090 static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) 2072 2091 { 2073 2092 PDMDEV_ASSERT_DEVINS(pDevIns); 2074 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM HC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);2075 return rc; 2076 } 2077 2078 2079 /** @copydoc PDMDEVHLP ::pfnVMSetRuntimeError */2093 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2); 2094 return rc; 2095 } 2096 2097 2098 /** @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError */ 2080 2099 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, bool fFatal, const char *pszErrorID, const char *pszFormat, ...) 2081 2100 { … … 2083 2102 va_list args; 2084 2103 va_start(args, pszFormat); 2085 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM HC, fFatal, pszErrorID, pszFormat, args);2104 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFatal, pszErrorID, pszFormat, args); 2086 2105 va_end(args); 2087 2106 return rc; … … 2089 2108 2090 2109 2091 /** @copydoc PDMDEVHLP ::pfnVMSetRuntimeErrorV */2110 /** @copydoc PDMDEVHLPR3::pfnVMSetRuntimeErrorV */ 2092 2111 static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, bool fFatal, const char *pszErrorID, const char *pszFormat, va_list va) 2093 2112 { 2094 2113 PDMDEV_ASSERT_DEVINS(pDevIns); 2095 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM HC, fFatal, pszErrorID, pszFormat, va);2096 return rc; 2097 } 2098 2099 2100 /** @copydoc PDMDEVHLP ::pfnAssertEMT */2114 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFatal, pszErrorID, pszFormat, va); 2115 return rc; 2116 } 2117 2118 2119 /** @copydoc PDMDEVHLPR3::pfnAssertEMT */ 2101 2120 static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction) 2102 2121 { 2103 2122 PDMDEV_ASSERT_DEVINS(pDevIns); 2104 if (VM_IS_EMT(pDevIns->Internal.s.pVM HC))2123 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3)) 2105 2124 return true; 2106 2125 … … 2113 2132 2114 2133 2115 /** @copydoc PDMDEVHLP ::pfnAssertOther */2134 /** @copydoc PDMDEVHLPR3::pfnAssertOther */ 2116 2135 static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction) 2117 2136 { 2118 2137 PDMDEV_ASSERT_DEVINS(pDevIns); 2119 if (!VM_IS_EMT(pDevIns->Internal.s.pVM HC))2138 if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3)) 2120 2139 return true; 2121 2140 … … 2128 2147 2129 2148 2130 /** @copydoc PDMDEVHLP ::pfnDBGFStopV */2149 /** @copydoc PDMDEVHLPR3::pfnDBGFStopV */ 2131 2150 static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args) 2132 2151 { … … 2140 2159 #endif 2141 2160 2142 PVM pVM = pDevIns->Internal.s.pVM HC;2161 PVM pVM = pDevIns->Internal.s.pVMR3; 2143 2162 VM_ASSERT_EMT(pVM); 2144 2163 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args); … … 2149 2168 2150 2169 2151 /** @copydoc PDMDEVHLP ::pfnDBGFInfoRegister */2170 /** @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister */ 2152 2171 static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler) 2153 2172 { … … 2156 2175 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler)); 2157 2176 2158 PVM pVM = pDevIns->Internal.s.pVM HC;2177 PVM pVM = pDevIns->Internal.s.pVMR3; 2159 2178 VM_ASSERT_EMT(pVM); 2160 2179 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns); … … 2165 2184 2166 2185 2167 /** @copydoc PDMDEVHLP ::pfnSTAMRegister */2186 /** @copydoc PDMDEVHLPR3::pfnSTAMRegister */ 2168 2187 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName, STAMUNIT enmUnit, const char *pszDesc) 2169 2188 { 2170 2189 PDMDEV_ASSERT_DEVINS(pDevIns); 2171 PVM pVM = pDevIns->Internal.s.pVM HC;2190 PVM pVM = pDevIns->Internal.s.pVMR3; 2172 2191 VM_ASSERT_EMT(pVM); 2173 2192 … … 2178 2197 2179 2198 2180 /** @copydoc PDMDEVHLP ::pfnSTAMRegisterF */2199 /** @copydoc PDMDEVHLPR3::pfnSTAMRegisterF */ 2181 2200 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility, 2182 2201 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...) 2183 2202 { 2184 2203 PDMDEV_ASSERT_DEVINS(pDevIns); 2185 PVM pVM = pDevIns->Internal.s.pVM HC;2204 PVM pVM = pDevIns->Internal.s.pVMR3; 2186 2205 VM_ASSERT_EMT(pVM); 2187 2206 … … 2196 2215 2197 2216 2198 /** @copydoc PDMDEVHLP ::pfnSTAMRegisterV */2217 /** @copydoc PDMDEVHLPR3::pfnSTAMRegisterV */ 2199 2218 static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility, 2200 2219 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args) 2201 2220 { 2202 2221 PDMDEV_ASSERT_DEVINS(pDevIns); 2203 PVM pVM = pDevIns->Internal.s.pVM HC;2222 PVM pVM = pDevIns->Internal.s.pVMR3; 2204 2223 VM_ASSERT_EMT(pVM); 2205 2224 … … 2211 2230 2212 2231 2213 /** @copydoc PDMDEVHLP ::pfnRTCRegister */2232 /** @copydoc PDMDEVHLPR3::pfnRTCRegister */ 2214 2233 static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp) 2215 2234 { 2216 2235 PDMDEV_ASSERT_DEVINS(pDevIns); 2217 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);2236 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2218 2237 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n", 2219 2238 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite, … … 2252 2271 * Only one DMA device. 2253 2272 */ 2254 PVM pVM = pDevIns->Internal.s.pVM HC;2273 PVM pVM = pDevIns->Internal.s.pVMR3; 2255 2274 if (pVM->pdm.s.pRtc) 2256 2275 { … … 2265 2284 */ 2266 2285 int rc = VINF_SUCCESS; 2267 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVM HC, MM_TAG_PDM_DEVICE, sizeof(*pRtc));2286 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc)); 2268 2287 if (pRtc) 2269 2288 { … … 2286 2305 2287 2306 2288 /** @copydoc PDMDEVHLP ::pfnPDMQueueCreate */2307 /** @copydoc PDMDEVHLPR3::pfnPDMQueueCreate */ 2289 2308 static DECLCALLBACK(int) pdmR3DevHlp_PDMQueueCreate(PPDMDEVINS pDevIns, RTUINT cbItem, RTUINT cItems, uint32_t cMilliesInterval, 2290 2309 PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, PPDMQUEUE *ppQueue) … … 2294 2313 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue)); 2295 2314 2296 PVM pVM = pDevIns->Internal.s.pVM HC;2315 PVM pVM = pDevIns->Internal.s.pVMR3; 2297 2316 VM_ASSERT_EMT(pVM); 2298 2317 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue); … … 2303 2322 2304 2323 2305 /** @copydoc PDMDEVHLP ::pfnCritSectInit */2324 /** @copydoc PDMDEVHLPR3::pfnCritSectInit */ 2306 2325 static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, const char *pszName) 2307 2326 { … … 2310 2329 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pCritSect, pszName, pszName)); 2311 2330 2312 PVM pVM = pDevIns->Internal.s.pVM HC;2331 PVM pVM = pDevIns->Internal.s.pVMR3; 2313 2332 VM_ASSERT_EMT(pVM); 2314 2333 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, pszName); … … 2319 2338 2320 2339 2321 /** @copydoc PDMDEVHLP ::pfnUTCNow */2340 /** @copydoc PDMDEVHLPR3::pfnUTCNow */ 2322 2341 static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_UTCNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime) 2323 2342 { … … 2326 2345 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pTime)); 2327 2346 2328 pTime = TMR3UTCNow(pDevIns->Internal.s.pVM HC, pTime);2347 pTime = TMR3UTCNow(pDevIns->Internal.s.pVMR3, pTime); 2329 2348 2330 2349 LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: returns %RU64\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, RTTimeSpecGetNano(pTime))); … … 2333 2352 2334 2353 2335 /** @copydoc PDMDEVHLP ::pfnPDMThreadCreate */2354 /** @copydoc PDMDEVHLPR3::pfnPDMThreadCreate */ 2336 2355 static DECLCALLBACK(int) pdmR3DevHlp_PDMThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread, 2337 2356 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName) 2338 2357 { 2339 2358 PDMDEV_ASSERT_DEVINS(pDevIns); 2340 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);2359 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2341 2360 LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n", 2342 2361 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName)); 2343 2362 2344 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVM HC, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);2363 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName); 2345 2364 2346 2365 LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: returns %Vrc *ppThread=%RTthrd\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, … … 2350 2369 2351 2370 2352 /** @copydoc PDMDEVHLP ::pfnGetVM */2371 /** @copydoc PDMDEVHLPR3::pfnGetVM */ 2353 2372 static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns) 2354 2373 { 2355 2374 PDMDEV_ASSERT_DEVINS(pDevIns); 2356 LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns->Internal.s.pVM HC));2357 return pDevIns->Internal.s.pVM HC;2358 } 2359 2360 2361 /** @copydoc PDMDEVHLP ::pfnPCIBusRegister */2375 LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3)); 2376 return pDevIns->Internal.s.pVMR3; 2377 } 2378 2379 2380 /** @copydoc PDMDEVHLPR3::pfnPCIBusRegister */ 2362 2381 static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3) 2363 2382 { 2364 2383 PDMDEV_ASSERT_DEVINS(pDevIns); 2365 PVM pVM = pDevIns->Internal.s.pVM HC;2384 PVM pVM = pDevIns->Internal.s.pVMR3; 2366 2385 VM_ASSERT_EMT(pVM); 2367 2386 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, .pfnSetIrqR3=%p, " … … 2494 2513 2495 2514 2496 /** @copydoc PDMDEVHLP ::pfnPICRegister */2515 /** @copydoc PDMDEVHLPR3::pfnPICRegister */ 2497 2516 static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3) 2498 2517 { 2499 2518 PDMDEV_ASSERT_DEVINS(pDevIns); 2500 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);2519 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2501 2520 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n", 2502 2521 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3, … … 2557 2576 * Only one PIC device. 2558 2577 */ 2559 PVM pVM = pDevIns->Internal.s.pVM HC;2578 PVM pVM = pDevIns->Internal.s.pVMR3; 2560 2579 if (pVM->pdm.s.Pic.pDevInsR3) 2561 2580 { … … 2633 2652 2634 2653 2635 /** @copydoc PDMDEVHLP ::pfnAPICRegister */2654 /** @copydoc PDMDEVHLPR3::pfnAPICRegister */ 2636 2655 static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3) 2637 2656 { 2638 2657 PDMDEV_ASSERT_DEVINS(pDevIns); 2639 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);2658 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2640 2659 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseR3=%p, .pfnGetBaseR3=%p, " 2641 2660 ".pfnSetTPRR3=%p, .pfnGetTPRR3=%p, .pfnBusDeliverR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseRC=%p:{%s}, pszGetBaseRC=%p:{%s}, " … … 2736 2755 * Only one APIC device. (malc: only in UP case actually) 2737 2756 */ 2738 PVM pVM = pDevIns->Internal.s.pVM HC;2757 PVM pVM = pDevIns->Internal.s.pVMR3; 2739 2758 if (pVM->pdm.s.Apic.pDevInsR3) 2740 2759 { … … 2877 2896 2878 2897 2879 /** @copydoc PDMDEVHLP ::pfnIOAPICRegister */2898 /** @copydoc PDMDEVHLPR3::pfnIOAPICRegister */ 2880 2899 static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3) 2881 2900 { 2882 2901 PDMDEV_ASSERT_DEVINS(pDevIns); 2883 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);2902 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 2884 2903 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n", 2885 2904 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3, … … 2926 2945 * If the I/O APIC does GC stuff so must the APIC. 2927 2946 */ 2928 PVM pVM = pDevIns->Internal.s.pVM HC;2947 PVM pVM = pDevIns->Internal.s.pVMR3; 2929 2948 if (!pVM->pdm.s.Apic.pDevInsR3) 2930 2949 { … … 3006 3025 3007 3026 3008 /** @copydoc PDMDEVHLP ::pfnDMACRegister */3027 /** @copydoc PDMDEVHLPR3::pfnDMACRegister */ 3009 3028 static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp) 3010 3029 { 3011 3030 PDMDEV_ASSERT_DEVINS(pDevIns); 3012 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3031 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3013 3032 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n", 3014 3033 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister, … … 3055 3074 * Only one DMA device. 3056 3075 */ 3057 PVM pVM = pDevIns->Internal.s.pVM HC;3076 PVM pVM = pDevIns->Internal.s.pVMR3; 3058 3077 if (pVM->pdm.s.pDmac) 3059 3078 { … … 3068 3087 */ 3069 3088 int rc = VINF_SUCCESS; 3070 PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVM HC, MM_TAG_PDM_DEVICE, sizeof(*pDmac));3089 PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac)); 3071 3090 if (pDmac) 3072 3091 { … … 3089 3108 3090 3109 3091 /** @copydoc PDMDEVHLP ::pfnPhysRead */3110 /** @copydoc PDMDEVHLPR3::pfnPhysRead */ 3092 3111 static DECLCALLBACK(void) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 3093 3112 { … … 3101 3120 */ 3102 3121 #ifdef PDM_PHYS_READWRITE_FROM_ANY_THREAD 3103 PGMPhysRead(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbRead);3122 PGMPhysRead(pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbRead); 3104 3123 #else 3105 if (VM_IS_EMT(pDevIns->Internal.s.pVM HC) || VMMR3LockIsOwner(pDevIns->Internal.s.pVMHC))3106 PGMPhysRead(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbRead);3124 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3) || VMMR3LockIsOwner(pDevIns->Internal.s.pVMR3)) 3125 PGMPhysRead(pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbRead); 3107 3126 else 3108 3127 { … … 3110 3129 PVMREQ pReq; 3111 3130 AssertCompileSize(RTGCPHYS, 4); 3112 int rc = VMR3ReqCallVoid(pDevIns->Internal.s.pVM HC, &pReq, RT_INDEFINITE_WAIT,3113 (PFNRT)PGMPhysRead, 4, pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbRead);3131 int rc = VMR3ReqCallVoid(pDevIns->Internal.s.pVMR3, &pReq, RT_INDEFINITE_WAIT, 3132 (PFNRT)PGMPhysRead, 4, pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbRead); 3114 3133 while (rc == VERR_TIMEOUT) 3115 3134 rc = VMR3ReqWait(pReq, RT_INDEFINITE_WAIT); … … 3122 3141 3123 3142 3124 /** @copydoc PDMDEVHLP ::pfnPhysWrite */3143 /** @copydoc PDMDEVHLPR3::pfnPhysWrite */ 3125 3144 static DECLCALLBACK(void) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 3126 3145 { … … 3134 3153 */ 3135 3154 #ifdef PDM_PHYS_READWRITE_FROM_ANY_THREAD 3136 PGMPhysWrite(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbWrite);3155 PGMPhysWrite(pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbWrite); 3137 3156 #else 3138 if (VM_IS_EMT(pDevIns->Internal.s.pVM HC) || VMMR3LockIsOwner(pDevIns->Internal.s.pVMHC))3139 PGMPhysWrite(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbWrite);3157 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3) || VMMR3LockIsOwner(pDevIns->Internal.s.pVMR3)) 3158 PGMPhysWrite(pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbWrite); 3140 3159 else 3141 3160 { … … 3143 3162 PVMREQ pReq; 3144 3163 AssertCompileSize(RTGCPHYS, 4); 3145 int rc = VMR3ReqCallVoid(pDevIns->Internal.s.pVM HC, &pReq, RT_INDEFINITE_WAIT,3146 (PFNRT)PGMPhysWrite, 4, pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbWrite);3164 int rc = VMR3ReqCallVoid(pDevIns->Internal.s.pVMR3, &pReq, RT_INDEFINITE_WAIT, 3165 (PFNRT)PGMPhysWrite, 4, pDevIns->Internal.s.pVMR3, GCPhys, pvBuf, cbWrite); 3147 3166 while (rc == VERR_TIMEOUT) 3148 3167 rc = VMR3ReqWait(pReq, RT_INDEFINITE_WAIT); … … 3155 3174 3156 3175 3157 /** @copydoc PDMDEVHLP ::pfnPhysReadGCVirt */3176 /** @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt */ 3158 3177 static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb) 3159 3178 { 3160 3179 PDMDEV_ASSERT_DEVINS(pDevIns); 3161 PVM pVM = pDevIns->Internal.s.pVM HC;3180 PVM pVM = pDevIns->Internal.s.pVMR3; 3162 3181 VM_ASSERT_EMT(pVM); 3163 3182 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%VGv cb=%#x\n", … … 3175 3194 3176 3195 3177 /** @copydoc PDMDEVHLP ::pfnPhysWriteGCVirt */3196 /** @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt */ 3178 3197 static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb) 3179 3198 { 3180 3199 PDMDEV_ASSERT_DEVINS(pDevIns); 3181 PVM pVM = pDevIns->Internal.s.pVM HC;3200 PVM pVM = pDevIns->Internal.s.pVMR3; 3182 3201 VM_ASSERT_EMT(pVM); 3183 3202 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%VGv pvSrc=%p cb=%#x\n", … … 3195 3214 3196 3215 3197 /** @copydoc PDMDEVHLP ::pfnPhysReserve */3216 /** @copydoc PDMDEVHLPR3::pfnPhysReserve */ 3198 3217 static DECLCALLBACK(int) pdmR3DevHlp_PhysReserve(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTUINT cbRange, const char *pszDesc) 3199 3218 { 3200 3219 PDMDEV_ASSERT_DEVINS(pDevIns); 3201 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3220 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3202 3221 LogFlow(("pdmR3DevHlp_PhysReserve: caller='%s'/%d: GCPhys=%VGp cbRange=%#x pszDesc=%p:{%s}\n", 3203 3222 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, cbRange, pszDesc, pszDesc)); 3204 3223 3205 int rc = MMR3PhysReserve(pDevIns->Internal.s.pVM HC, GCPhys, cbRange, pszDesc);3224 int rc = MMR3PhysReserve(pDevIns->Internal.s.pVMR3, GCPhys, cbRange, pszDesc); 3206 3225 3207 3226 LogFlow(("pdmR3DevHlp_PhysReserve: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3211 3230 3212 3231 3213 /** @copydoc PDMDEVHLP ::pfnPhysGCPtr2GCPhys */3232 /** @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys */ 3214 3233 static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys) 3215 3234 { 3216 3235 PDMDEV_ASSERT_DEVINS(pDevIns); 3217 PVM pVM = pDevIns->Internal.s.pVM HC;3236 PVM pVM = pDevIns->Internal.s.pVMR3; 3218 3237 VM_ASSERT_EMT(pVM); 3219 3238 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%VGv pGCPhys=%p\n", … … 3231 3250 3232 3251 3233 /** @copydoc PDMDEVHLP ::pfnVMState */3252 /** @copydoc PDMDEVHLPR3::pfnVMState */ 3234 3253 static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns) 3235 3254 { 3236 3255 PDMDEV_ASSERT_DEVINS(pDevIns); 3237 3256 3238 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVM HC);3257 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3); 3239 3258 3240 3259 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, … … 3244 3263 3245 3264 3246 /** @copydoc PDMDEVHLP ::pfnA20IsEnabled */3265 /** @copydoc PDMDEVHLPR3::pfnA20IsEnabled */ 3247 3266 static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns) 3248 3267 { 3249 3268 PDMDEV_ASSERT_DEVINS(pDevIns); 3250 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3251 3252 bool fRc = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVM HC);3269 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3270 3271 bool fRc = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVMR3); 3253 3272 3254 3273 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fRc)); … … 3257 3276 3258 3277 3259 /** @copydoc PDMDEVHLP ::pfnA20Set */3278 /** @copydoc PDMDEVHLPR3::pfnA20Set */ 3260 3279 static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable) 3261 3280 { 3262 3281 PDMDEV_ASSERT_DEVINS(pDevIns); 3263 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3282 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3264 3283 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fEnable)); 3265 3284 //Assert(*(unsigned *)&fEnable <= 1); 3266 PGMR3PhysSetA20(pDevIns->Internal.s.pVM HC, fEnable);3267 } 3268 3269 3270 /** @copydoc PDMDEVHLP ::pfnVMReset */3285 PGMR3PhysSetA20(pDevIns->Internal.s.pVMR3, fEnable); 3286 } 3287 3288 3289 /** @copydoc PDMDEVHLPR3::pfnVMReset */ 3271 3290 static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns) 3272 3291 { 3273 3292 PDMDEV_ASSERT_DEVINS(pDevIns); 3274 PVM pVM = pDevIns->Internal.s.pVM HC;3293 PVM pVM = pDevIns->Internal.s.pVMR3; 3275 3294 VM_ASSERT_EMT(pVM); 3276 3295 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: VM_FF_RESET %d -> 1\n", … … 3300 3319 3301 3320 3302 /** @copydoc PDMDEVHLP ::pfnVMSuspend */3321 /** @copydoc PDMDEVHLPR3::pfnVMSuspend */ 3303 3322 static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns) 3304 3323 { 3305 3324 PDMDEV_ASSERT_DEVINS(pDevIns); 3306 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3325 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3307 3326 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n", 3308 3327 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 3309 3328 3310 int rc = VMR3Suspend(pDevIns->Internal.s.pVM HC);3329 int rc = VMR3Suspend(pDevIns->Internal.s.pVMR3); 3311 3330 3312 3331 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3315 3334 3316 3335 3317 /** @copydoc PDMDEVHLP ::pfnVMPowerOff */3336 /** @copydoc PDMDEVHLPR3::pfnVMPowerOff */ 3318 3337 static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns) 3319 3338 { 3320 3339 PDMDEV_ASSERT_DEVINS(pDevIns); 3321 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3340 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3322 3341 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n", 3323 3342 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance)); 3324 3343 3325 int rc = VMR3PowerOff(pDevIns->Internal.s.pVM HC);3344 int rc = VMR3PowerOff(pDevIns->Internal.s.pVMR3); 3326 3345 3327 3346 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3330 3349 3331 3350 3332 /** @copydoc PDMDEVHLP ::pfnLockVM */3351 /** @copydoc PDMDEVHLPR3::pfnLockVM */ 3333 3352 static DECLCALLBACK(int) pdmR3DevHlp_LockVM(PPDMDEVINS pDevIns) 3334 3353 { 3335 return VMMR3Lock(pDevIns->Internal.s.pVM HC);3336 } 3337 3338 3339 /** @copydoc PDMDEVHLP ::pfnUnlockVM */3354 return VMMR3Lock(pDevIns->Internal.s.pVMR3); 3355 } 3356 3357 3358 /** @copydoc PDMDEVHLPR3::pfnUnlockVM */ 3340 3359 static DECLCALLBACK(int) pdmR3DevHlp_UnlockVM(PPDMDEVINS pDevIns) 3341 3360 { 3342 return VMMR3Unlock(pDevIns->Internal.s.pVM HC);3343 } 3344 3345 3346 /** @copydoc PDMDEVHLP ::pfnAssertVMLock */3361 return VMMR3Unlock(pDevIns->Internal.s.pVMR3); 3362 } 3363 3364 3365 /** @copydoc PDMDEVHLPR3::pfnAssertVMLock */ 3347 3366 static DECLCALLBACK(bool) pdmR3DevHlp_AssertVMLock(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction) 3348 3367 { 3349 PVM pVM = pDevIns->Internal.s.pVM HC;3368 PVM pVM = pDevIns->Internal.s.pVMR3; 3350 3369 if (VMMR3LockIsOwner(pVM)) 3351 3370 return true; … … 3362 3381 } 3363 3382 3364 /** @copydoc PDMDEVHLP ::pfnDMARegister */3383 /** @copydoc PDMDEVHLPR3::pfnDMARegister */ 3365 3384 static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser) 3366 3385 { 3367 3386 PDMDEV_ASSERT_DEVINS(pDevIns); 3368 PVM pVM = pDevIns->Internal.s.pVM HC;3387 PVM pVM = pDevIns->Internal.s.pVMR3; 3369 3388 VM_ASSERT_EMT(pVM); 3370 3389 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n", … … 3383 3402 } 3384 3403 3385 /** @copydoc PDMDEVHLP ::pfnDMAReadMemory */3404 /** @copydoc PDMDEVHLPR3::pfnDMAReadMemory */ 3386 3405 static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead) 3387 3406 { 3388 3407 PDMDEV_ASSERT_DEVINS(pDevIns); 3389 PVM pVM = pDevIns->Internal.s.pVM HC;3408 PVM pVM = pDevIns->Internal.s.pVMR3; 3390 3409 VM_ASSERT_EMT(pVM); 3391 3410 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n", … … 3408 3427 } 3409 3428 3410 /** @copydoc PDMDEVHLP ::pfnDMAWriteMemory */3429 /** @copydoc PDMDEVHLPR3::pfnDMAWriteMemory */ 3411 3430 static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten) 3412 3431 { 3413 3432 PDMDEV_ASSERT_DEVINS(pDevIns); 3414 PVM pVM = pDevIns->Internal.s.pVM HC;3433 PVM pVM = pDevIns->Internal.s.pVMR3; 3415 3434 VM_ASSERT_EMT(pVM); 3416 3435 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n", … … 3433 3452 } 3434 3453 3435 /** @copydoc PDMDEVHLP ::pfnDMASetDREQ */3454 /** @copydoc PDMDEVHLPR3::pfnDMASetDREQ */ 3436 3455 static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel) 3437 3456 { 3438 3457 PDMDEV_ASSERT_DEVINS(pDevIns); 3439 PVM pVM = pDevIns->Internal.s.pVM HC;3458 PVM pVM = pDevIns->Internal.s.pVMR3; 3440 3459 VM_ASSERT_EMT(pVM); 3441 3460 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n", … … 3454 3473 } 3455 3474 3456 /** @copydoc PDMDEVHLP ::pfnDMAGetChannelMode */3475 /** @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode */ 3457 3476 static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel) 3458 3477 { 3459 3478 PDMDEV_ASSERT_DEVINS(pDevIns); 3460 PVM pVM = pDevIns->Internal.s.pVM HC;3479 PVM pVM = pDevIns->Internal.s.pVMR3; 3461 3480 VM_ASSERT_EMT(pVM); 3462 3481 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n", … … 3475 3494 } 3476 3495 3477 /** @copydoc PDMDEVHLP ::pfnDMASchedule */3496 /** @copydoc PDMDEVHLPR3::pfnDMASchedule */ 3478 3497 static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns) 3479 3498 { 3480 3499 PDMDEV_ASSERT_DEVINS(pDevIns); 3481 PVM pVM = pDevIns->Internal.s.pVM HC;3500 PVM pVM = pDevIns->Internal.s.pVMR3; 3482 3501 VM_ASSERT_EMT(pVM); 3483 3502 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n", … … 3491 3510 3492 3511 3493 /** @copydoc PDMDEVHLP ::pfnCMOSWrite */3512 /** @copydoc PDMDEVHLPR3::pfnCMOSWrite */ 3494 3513 static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value) 3495 3514 { 3496 3515 PDMDEV_ASSERT_DEVINS(pDevIns); 3497 PVM pVM = pDevIns->Internal.s.pVM HC;3516 PVM pVM = pDevIns->Internal.s.pVMR3; 3498 3517 VM_ASSERT_EMT(pVM); 3499 3518 … … 3512 3531 3513 3532 3514 /** @copydoc PDMDEVHLP ::pfnCMOSRead */3533 /** @copydoc PDMDEVHLPR3::pfnCMOSRead */ 3515 3534 static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value) 3516 3535 { 3517 3536 PDMDEV_ASSERT_DEVINS(pDevIns); 3518 PVM pVM = pDevIns->Internal.s.pVM HC;3537 PVM pVM = pDevIns->Internal.s.pVMR3; 3519 3538 VM_ASSERT_EMT(pVM); 3520 3539 … … 3533 3552 3534 3553 3535 /** @copydoc PDMDEVHLP ::pfnGetCpuId */3554 /** @copydoc PDMDEVHLPR3::pfnGetCpuId */ 3536 3555 static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, 3537 3556 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx) … … 3542 3561 AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx); 3543 3562 3544 CPUMGetGuestCpuId(pDevIns->Internal.s.pVM HC, iLeaf, pEax, pEbx, pEcx, pEdx);3563 CPUMGetGuestCpuId(pDevIns->Internal.s.pVMR3, iLeaf, pEax, pEbx, pEcx, pEdx); 3545 3564 3546 3565 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - *pEax=%#x *pEbx=%#x *pEcx=%#x *pEdx=%#x\n", … … 3549 3568 3550 3569 3551 /** @copydoc PDMDEVHLP ::pfnROMProtectShadow */3570 /** @copydoc PDMDEVHLPR3::pfnROMProtectShadow */ 3552 3571 static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange) 3553 3572 { … … 3556 3575 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange)); 3557 3576 3558 int rc = MMR3PhysRomProtect(pDevIns->Internal.s.pVM HC, GCPhysStart, cbRange);3577 int rc = MMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange); 3559 3578 3560 3579 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Vrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3564 3583 3565 3584 /** 3566 * @copydoc PDMDEVHLP ::pfnMMIO2Register3585 * @copydoc PDMDEVHLPR3::pfnMMIO2Register 3567 3586 */ 3568 3587 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc) 3569 3588 { 3570 3589 PDMDEV_ASSERT_DEVINS(pDevIns); 3571 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3590 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3572 3591 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: iRegion=#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n", 3573 3592 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, cb, fFlags, ppv, pszDesc, pszDesc)); 3574 3593 3575 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVM HC, pDevIns, iRegion, cb, fFlags, ppv, pszDesc);3594 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, cb, fFlags, ppv, pszDesc); 3576 3595 3577 3596 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3581 3600 3582 3601 /** 3583 * @copydoc PDMDEVHLP ::pfnMMIO2Deregister3602 * @copydoc PDMDEVHLPR3::pfnMMIO2Deregister 3584 3603 */ 3585 3604 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion) 3586 3605 { 3587 3606 PDMDEV_ASSERT_DEVINS(pDevIns); 3588 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3607 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3589 3608 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: iRegion=#x\n", 3590 3609 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion)); … … 3592 3611 AssertReturn(iRegion == UINT32_MAX, VERR_INVALID_PARAMETER); 3593 3612 3594 int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVM HC, pDevIns, iRegion);3613 int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, iRegion); 3595 3614 3596 3615 LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3600 3619 3601 3620 /** 3602 * @copydoc PDMDEVHLP ::pfnMMIO2Map3621 * @copydoc PDMDEVHLPR3::pfnMMIO2Map 3603 3622 */ 3604 3623 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 3605 3624 { 3606 3625 PDMDEV_ASSERT_DEVINS(pDevIns); 3607 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3626 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3608 3627 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: iRegion=#x GCPhys=%#RGp\n", 3609 3628 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys)); 3610 3629 3611 int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVM HC, pDevIns, iRegion, GCPhys);3630 int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys); 3612 3631 3613 3632 LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3617 3636 3618 3637 /** 3619 * @copydoc PDMDEVHLP ::pfnMMIO2Unmap3638 * @copydoc PDMDEVHLPR3::pfnMMIO2Unmap 3620 3639 */ 3621 3640 static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 3622 3641 { 3623 3642 PDMDEV_ASSERT_DEVINS(pDevIns); 3624 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3643 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3625 3644 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: iRegion=#x GCPhys=%#RGp\n", 3626 3645 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys)); 3627 3646 3628 int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVM HC, pDevIns, iRegion, GCPhys);3647 int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys); 3629 3648 3630 3649 LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc)); … … 3634 3653 3635 3654 /** 3636 * @copydoc PDMDEVHLP ::pfnMMHyperMapMMIO23655 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 3637 3656 */ 3638 3657 static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, … … 3640 3659 { 3641 3660 PDMDEV_ASSERT_DEVINS(pDevIns); 3642 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3661 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3643 3662 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: iRegion=#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n", 3644 3663 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pRCPtr)); 3645 3664 3646 int rc = MMR3HyperMapMMIO2(pDevIns->Internal.s.pVM HC, pDevIns, iRegion, off, cb, pszDesc, pRCPtr);3665 int rc = MMR3HyperMapMMIO2(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, off, cb, pszDesc, pRCPtr); 3647 3666 3648 3667 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, *pRCPtr)); … … 3652 3671 3653 3672 /** 3654 * @copydoc PDMDEVHLP ::pfnRegisterVMMDevHeap3673 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap 3655 3674 */ 3656 3675 static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize) 3657 3676 { 3658 3677 PDMDEV_ASSERT_DEVINS(pDevIns); 3659 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3660 3661 int rc = PDMR3RegisterVMMDevHeap(pDevIns->Internal.s.pVM HC, GCPhys, pvHeap, cbSize);3678 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3679 3680 int rc = PDMR3RegisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys, pvHeap, cbSize); 3662 3681 return rc; 3663 3682 } … … 3665 3684 3666 3685 /** 3667 * @copydoc PDMDEVHLP ::pfnUnregisterVMMDevHeap3686 * @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap 3668 3687 */ 3669 3688 static DECLCALLBACK(int) pdmR3DevHlp_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys) 3670 3689 { 3671 3690 PDMDEV_ASSERT_DEVINS(pDevIns); 3672 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);3673 3674 int rc = PDMR3UnregisterVMMDevHeap(pDevIns->Internal.s.pVM HC, GCPhys);3675 return rc; 3676 } 3677 3678 3679 3680 3681 3682 /** @copydoc PDMDEVHLP ::pfnGetVM */3691 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 3692 3693 int rc = PDMR3UnregisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys); 3694 return rc; 3695 } 3696 3697 3698 3699 3700 3701 /** @copydoc PDMDEVHLPR3::pfnGetVM */ 3683 3702 static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns) 3684 3703 { … … 3689 3708 3690 3709 3691 /** @copydoc PDMDEVHLP ::pfnPCIBusRegister */3710 /** @copydoc PDMDEVHLPR3::pfnPCIBusRegister */ 3692 3711 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3) 3693 3712 { … … 3700 3719 3701 3720 3702 /** @copydoc PDMDEVHLP ::pfnPICRegister */3721 /** @copydoc PDMDEVHLPR3::pfnPICRegister */ 3703 3722 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3) 3704 3723 { … … 3711 3730 3712 3731 3713 /** @copydoc PDMDEVHLP ::pfnAPICRegister */3732 /** @copydoc PDMDEVHLPR3::pfnAPICRegister */ 3714 3733 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3) 3715 3734 { … … 3722 3741 3723 3742 3724 /** @copydoc PDMDEVHLP ::pfnIOAPICRegister */3743 /** @copydoc PDMDEVHLPR3::pfnIOAPICRegister */ 3725 3744 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3) 3726 3745 { … … 3733 3752 3734 3753 3735 /** @copydoc PDMDEVHLP ::pfnDMACRegister */3754 /** @copydoc PDMDEVHLPR3::pfnDMACRegister */ 3736 3755 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp) 3737 3756 { … … 3744 3763 3745 3764 3746 /** @copydoc PDMDEVHLP ::pfnPhysRead */3765 /** @copydoc PDMDEVHLPR3::pfnPhysRead */ 3747 3766 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 3748 3767 { … … 3755 3774 3756 3775 3757 /** @copydoc PDMDEVHLP ::pfnPhysWrite */3776 /** @copydoc PDMDEVHLPR3::pfnPhysWrite */ 3758 3777 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 3759 3778 { … … 3766 3785 3767 3786 3768 /** @copydoc PDMDEVHLP ::pfnPhysReadGCVirt */3787 /** @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt */ 3769 3788 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb) 3770 3789 { … … 3778 3797 3779 3798 3780 /** @copydoc PDMDEVHLP ::pfnPhysWriteGCVirt */3799 /** @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt */ 3781 3800 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb) 3782 3801 { … … 3790 3809 3791 3810 3792 /** @copydoc PDMDEVHLP ::pfnPhysReserve */3811 /** @copydoc PDMDEVHLPR3::pfnPhysReserve */ 3793 3812 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysReserve(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTUINT cbRange, const char *pszDesc) 3794 3813 { … … 3801 3820 3802 3821 3803 /** @copydoc PDMDEVHLP ::pfnObsoletePhys2HCVirt */3822 /** @copydoc PDMDEVHLPR3::pfnObsoletePhys2HCVirt */ 3804 3823 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_Obsolete_Phys2HCVirt(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTUINT cbRange, PRTHCPTR ppvHC) 3805 3824 { … … 3813 3832 3814 3833 3815 /** @copydoc PDMDEVHLP ::pfnObsoletePhysGCPtr2HCPtr */3834 /** @copydoc PDMDEVHLPR3::pfnObsoletePhysGCPtr2HCPtr */ 3816 3835 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_Obsolete_PhysGCPtr2HCPtr(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTHCPTR pHCPtr) 3817 3836 { … … 3824 3843 3825 3844 3826 /** @copydoc PDMDEVHLP ::pfnA20IsEnabled */3845 /** @copydoc PDMDEVHLPR3::pfnA20IsEnabled */ 3827 3846 static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns) 3828 3847 { … … 3833 3852 3834 3853 3835 /** @copydoc PDMDEVHLP ::pfnA20Set */3854 /** @copydoc PDMDEVHLPR3::pfnA20Set */ 3836 3855 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable) 3837 3856 { … … 3842 3861 3843 3862 3844 /** @copydoc PDMDEVHLP ::pfnVMReset */3863 /** @copydoc PDMDEVHLPR3::pfnVMReset */ 3845 3864 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns) 3846 3865 { … … 3851 3870 3852 3871 3853 /** @copydoc PDMDEVHLP ::pfnVMSuspend */3872 /** @copydoc PDMDEVHLPR3::pfnVMSuspend */ 3854 3873 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns) 3855 3874 { … … 3860 3879 3861 3880 3862 /** @copydoc PDMDEVHLP ::pfnVMPowerOff */3881 /** @copydoc PDMDEVHLPR3::pfnVMPowerOff */ 3863 3882 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns) 3864 3883 { … … 3869 3888 3870 3889 3871 /** @copydoc PDMDEVHLP ::pfnLockVM */3890 /** @copydoc PDMDEVHLPR3::pfnLockVM */ 3872 3891 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_LockVM(PPDMDEVINS pDevIns) 3873 3892 { … … 3878 3897 3879 3898 3880 /** @copydoc PDMDEVHLP ::pfnUnlockVM */3899 /** @copydoc PDMDEVHLPR3::pfnUnlockVM */ 3881 3900 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnlockVM(PPDMDEVINS pDevIns) 3882 3901 { … … 3887 3906 3888 3907 3889 /** @copydoc PDMDEVHLP ::pfnAssertVMLock */3908 /** @copydoc PDMDEVHLPR3::pfnAssertVMLock */ 3890 3909 static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_AssertVMLock(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction) 3891 3910 { … … 3896 3915 3897 3916 3898 /** @copydoc PDMDEVHLP ::pfnDMARegister */3917 /** @copydoc PDMDEVHLPR3::pfnDMARegister */ 3899 3918 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser) 3900 3919 { … … 3905 3924 3906 3925 3907 /** @copydoc PDMDEVHLP ::pfnDMAReadMemory */3926 /** @copydoc PDMDEVHLPR3::pfnDMAReadMemory */ 3908 3927 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead) 3909 3928 { … … 3916 3935 3917 3936 3918 /** @copydoc PDMDEVHLP ::pfnDMAWriteMemory */3937 /** @copydoc PDMDEVHLPR3::pfnDMAWriteMemory */ 3919 3938 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten) 3920 3939 { … … 3927 3946 3928 3947 3929 /** @copydoc PDMDEVHLP ::pfnDMASetDREQ */3948 /** @copydoc PDMDEVHLPR3::pfnDMASetDREQ */ 3930 3949 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel) 3931 3950 { … … 3936 3955 3937 3956 3938 /** @copydoc PDMDEVHLP ::pfnDMAGetChannelMode */3957 /** @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode */ 3939 3958 static DECLCALLBACK(uint8_t) pdmR3DevHlp_Untrusted_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel) 3940 3959 { … … 3945 3964 3946 3965 3947 /** @copydoc PDMDEVHLP ::pfnDMASchedule */3966 /** @copydoc PDMDEVHLPR3::pfnDMASchedule */ 3948 3967 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_DMASchedule(PPDMDEVINS pDevIns) 3949 3968 { … … 3953 3972 3954 3973 3955 /** @copydoc PDMDEVHLP ::pfnCMOSWrite */3974 /** @copydoc PDMDEVHLPR3::pfnCMOSWrite */ 3956 3975 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value) 3957 3976 { … … 3962 3981 3963 3982 3964 /** @copydoc PDMDEVHLP ::pfnCMOSRead */3983 /** @copydoc PDMDEVHLPR3::pfnCMOSRead */ 3965 3984 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value) 3966 3985 { … … 3971 3990 3972 3991 3973 /** @copydoc PDMDEVHLP ::pfnGetCpuId */3992 /** @copydoc PDMDEVHLPR3::pfnGetCpuId */ 3974 3993 static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf, 3975 3994 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx) … … 3980 3999 3981 4000 3982 /** @copydoc PDMDEVHLP ::pfnROMProtectShadow */4001 /** @copydoc PDMDEVHLPR3::pfnROMProtectShadow */ 3983 4002 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange) 3984 4003 { … … 3989 4008 3990 4009 3991 /** @copydoc PDMDEVHLP ::pfnMMIO2Register */4010 /** @copydoc PDMDEVHLPR3::pfnMMIO2Register */ 3992 4011 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void **ppv, const char *pszDesc) 3993 4012 { … … 3998 4017 3999 4018 4000 /** @copydoc PDMDEVHLP ::pfnMMIO2Deregister */4019 /** @copydoc PDMDEVHLPR3::pfnMMIO2Deregister */ 4001 4020 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion) 4002 4021 { … … 4007 4026 4008 4027 4009 /** @copydoc PDMDEVHLP ::pfnMMIO2Map */4028 /** @copydoc PDMDEVHLPR3::pfnMMIO2Map */ 4010 4029 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 4011 4030 { … … 4016 4035 4017 4036 4018 /** @copydoc PDMDEVHLP ::pfnMMIO2Unmap */4037 /** @copydoc PDMDEVHLPR3::pfnMMIO2Unmap */ 4019 4038 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys) 4020 4039 { … … 4025 4044 4026 4045 4027 /** @copydoc PDMDEVHLP ::pfnMMHyperMapMMIO2 */4046 /** @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 */ 4028 4047 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr) 4029 4048 { … … 4034 4053 4035 4054 4036 /** @copydoc PDMDEVHLP ::pfnRegisterVMMDevHeap */4055 /** @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap */ 4037 4056 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize) 4038 4057 { … … 4043 4062 4044 4063 4045 /** @copydoc PDMDEVHLP ::pfnUnregisterVMMDevHeap */4064 /** @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap */ 4046 4065 static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys) 4047 4066 { … … 4059 4078 { 4060 4079 PDMDEV_ASSERT_DEVINS(pDevIns); 4061 PVM pVM = pDevIns->Internal.s.pVM HC;4080 PVM pVM = pDevIns->Internal.s.pVMR3; 4062 4081 LogFlow(("pdmR3PicHlp_SetInterruptFF: caller='%s'/%d: VM_FF_INTERRUPT_PIC %d -> 1\n", 4063 4082 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pVM, 0, VM_FF_INTERRUPT_PIC))); … … 4074 4093 PDMDEV_ASSERT_DEVINS(pDevIns); 4075 4094 LogFlow(("pdmR3PicHlp_ClearInterruptFF: caller='%s'/%d: VM_FF_INTERRUPT_PIC %d -> 0\n", 4076 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC)));4095 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR3, 0, VM_FF_INTERRUPT_PIC))); 4077 4096 /* for PIC we always deliver to CPU 0, MP use APIC */ 4078 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC);4079 REMR3NotifyInterruptClear(pDevIns->Internal.s.pVM HC);4097 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR3, 0, VM_FF_INTERRUPT_PIC); 4098 REMR3NotifyInterruptClear(pDevIns->Internal.s.pVMR3); 4080 4099 } 4081 4100 … … 4085 4104 { 4086 4105 PDMDEV_ASSERT_DEVINS(pDevIns); 4087 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);4106 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc); 4088 4107 } 4089 4108 … … 4093 4112 { 4094 4113 PDMDEV_ASSERT_DEVINS(pDevIns); 4095 pdmUnlock(pDevIns->Internal.s.pVM HC);4114 pdmUnlock(pDevIns->Internal.s.pVMR3); 4096 4115 } 4097 4116 … … 4101 4120 { 4102 4121 PDMDEV_ASSERT_DEVINS(pDevIns); 4103 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4122 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4104 4123 RTRCPTR pRCHelpers = 0; 4105 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVM HC, NULL, "g_pdmRCPicHlp", &pRCHelpers);4124 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVMR3, NULL, "g_pdmRCPicHlp", &pRCHelpers); 4106 4125 AssertReleaseRC(rc); 4107 4126 AssertRelease(pRCHelpers); … … 4116 4135 { 4117 4136 PDMDEV_ASSERT_DEVINS(pDevIns); 4118 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4137 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4119 4138 PCPDMPICHLPR0 pR0Helpers = 0; 4120 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVM HC, NULL, "g_pdmR0PicHlp", &pR0Helpers);4139 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVMR3, NULL, "g_pdmR0PicHlp", &pR0Helpers); 4121 4140 AssertReleaseRC(rc); 4122 4141 AssertRelease(pR0Helpers); … … 4131 4150 { 4132 4151 PDMDEV_ASSERT_DEVINS(pDevIns); 4133 PVM pVM = pDevIns->Internal.s.pVM HC;4152 PVM pVM = pDevIns->Internal.s.pVMR3; 4134 4153 LogFlow(("pdmR3ApicHlp_SetInterruptFF: caller='%s'/%d: VM_FF_INTERRUPT %d -> 1\n", 4135 4154 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pVM, idCpu, VM_FF_INTERRUPT_APIC))); … … 4145 4164 PDMDEV_ASSERT_DEVINS(pDevIns); 4146 4165 LogFlow(("pdmR3ApicHlp_ClearInterruptFF: caller='%s'/%d: VM_FF_INTERRUPT %d -> 0\n", 4147 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC)));4148 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC);4149 REMR3NotifyInterruptClear(pDevIns->Internal.s.pVM HC);4166 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR3, idCpu, VM_FF_INTERRUPT_APIC))); 4167 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR3, idCpu, VM_FF_INTERRUPT_APIC); 4168 REMR3NotifyInterruptClear(pDevIns->Internal.s.pVMR3); 4150 4169 } 4151 4170 … … 4158 4177 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fEnabled)); 4159 4178 if (fEnabled) 4160 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVM HC, CPUMCPUIDFEATURE_APIC);4179 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC); 4161 4180 else 4162 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVM HC, CPUMCPUIDFEATURE_APIC);4181 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR3, CPUMCPUIDFEATURE_APIC); 4163 4182 } 4164 4183 … … 4167 4186 { 4168 4187 PDMDEV_ASSERT_DEVINS(pDevIns); 4169 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);4188 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc); 4170 4189 } 4171 4190 … … 4175 4194 { 4176 4195 PDMDEV_ASSERT_DEVINS(pDevIns); 4177 pdmUnlock(pDevIns->Internal.s.pVM HC);4196 pdmUnlock(pDevIns->Internal.s.pVMR3); 4178 4197 } 4179 4198 … … 4183 4202 { 4184 4203 PDMDEV_ASSERT_DEVINS(pDevIns); 4185 return VMMGetCpuId(pDevIns->Internal.s.pVM HC);4204 return VMMGetCpuId(pDevIns->Internal.s.pVMR3); 4186 4205 } 4187 4206 … … 4191 4210 { 4192 4211 PDMDEV_ASSERT_DEVINS(pDevIns); 4193 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4212 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4194 4213 RTRCPTR pRCHelpers = 0; 4195 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVM HC, NULL, "g_pdmRCApicHlp", &pRCHelpers);4214 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVMR3, NULL, "g_pdmRCApicHlp", &pRCHelpers); 4196 4215 AssertReleaseRC(rc); 4197 4216 AssertRelease(pRCHelpers); … … 4206 4225 { 4207 4226 PDMDEV_ASSERT_DEVINS(pDevIns); 4208 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4227 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4209 4228 PCPDMAPICHLPR0 pR0Helpers = 0; 4210 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVM HC, NULL, "g_pdmR0ApicHlp", &pR0Helpers);4229 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVMR3, NULL, "g_pdmR0ApicHlp", &pR0Helpers); 4211 4230 AssertReleaseRC(rc); 4212 4231 AssertRelease(pR0Helpers); … … 4222 4241 { 4223 4242 PDMDEV_ASSERT_DEVINS(pDevIns); 4224 PVM pVM = pDevIns->Internal.s.pVM HC;4243 PVM pVM = pDevIns->Internal.s.pVMR3; 4225 4244 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n", 4226 4245 pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode)); … … 4234 4253 { 4235 4254 PDMDEV_ASSERT_DEVINS(pDevIns); 4236 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);4255 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc); 4237 4256 } 4238 4257 … … 4242 4261 { 4243 4262 PDMDEV_ASSERT_DEVINS(pDevIns); 4244 pdmUnlock(pDevIns->Internal.s.pVM HC);4263 pdmUnlock(pDevIns->Internal.s.pVMR3); 4245 4264 } 4246 4265 … … 4250 4269 { 4251 4270 PDMDEV_ASSERT_DEVINS(pDevIns); 4252 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4271 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4253 4272 RTRCPTR pRCHelpers = 0; 4254 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVM HC, NULL, "g_pdmRCIoApicHlp", &pRCHelpers);4273 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVMR3, NULL, "g_pdmRCIoApicHlp", &pRCHelpers); 4255 4274 AssertReleaseRC(rc); 4256 4275 AssertRelease(pRCHelpers); … … 4265 4284 { 4266 4285 PDMDEV_ASSERT_DEVINS(pDevIns); 4267 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4286 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4268 4287 PCPDMIOAPICHLPR0 pR0Helpers = 0; 4269 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVM HC, NULL, "g_pdmR0IoApicHlp", &pR0Helpers);4288 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVMR3, NULL, "g_pdmR0IoApicHlp", &pR0Helpers); 4270 4289 AssertReleaseRC(rc); 4271 4290 AssertRelease(pR0Helpers); … … 4281 4300 PDMDEV_ASSERT_DEVINS(pDevIns); 4282 4301 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 4283 PDMIsaSetIrq(pDevIns->Internal.s.pVM HC, iIrq, iLevel);4302 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel); 4284 4303 } 4285 4304 … … 4290 4309 PDMDEV_ASSERT_DEVINS(pDevIns); 4291 4310 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 4292 PDMIoApicSetIrq(pDevIns->Internal.s.pVM HC, iIrq, iLevel);4311 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel); 4293 4312 } 4294 4313 … … 4298 4317 { 4299 4318 PDMDEV_ASSERT_DEVINS(pDevIns); 4300 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4301 bool fRc = PGMR3PhysMMIO2IsBase(pDevIns->Internal.s.pVM HC, pOwner, GCPhys);4319 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4320 bool fRc = PGMR3PhysMMIO2IsBase(pDevIns->Internal.s.pVMR3, pOwner, GCPhys); 4302 4321 Log4(("pdmR3PciHlp_IsMMIO2Base: pOwner=%p GCPhys=%RGp -> %RTbool\n", pOwner, GCPhys, fRc)); 4303 4322 return fRc; … … 4309 4328 { 4310 4329 PDMDEV_ASSERT_DEVINS(pDevIns); 4311 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);4330 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc); 4312 4331 } 4313 4332 … … 4317 4336 { 4318 4337 PDMDEV_ASSERT_DEVINS(pDevIns); 4319 pdmUnlock(pDevIns->Internal.s.pVM HC);4338 pdmUnlock(pDevIns->Internal.s.pVMR3); 4320 4339 } 4321 4340 … … 4325 4344 { 4326 4345 PDMDEV_ASSERT_DEVINS(pDevIns); 4327 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4346 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4328 4347 RTRCPTR pRCHelpers = 0; 4329 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVM HC, NULL, "g_pdmRCPciHlp", &pRCHelpers);4348 int rc = PDMR3GetSymbolGC(pDevIns->Internal.s.pVMR3, NULL, "g_pdmRCPciHlp", &pRCHelpers); 4330 4349 AssertReleaseRC(rc); 4331 4350 AssertRelease(pRCHelpers); … … 4340 4359 { 4341 4360 PDMDEV_ASSERT_DEVINS(pDevIns); 4342 VM_ASSERT_EMT(pDevIns->Internal.s.pVM HC);4361 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3); 4343 4362 PCPDMPCIHLPR0 pR0Helpers = 0; 4344 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVM HC, NULL, "g_pdmR0PciHlp", &pR0Helpers);4363 int rc = PDMR3GetSymbolR0(pDevIns->Internal.s.pVMR3, NULL, "g_pdmR0PciHlp", &pR0Helpers); 4345 4364 AssertReleaseRC(rc); 4346 4365 AssertRelease(pR0Helpers); … … 4376 4395 * Iterate device instances. 4377 4396 */ 4378 for (PPDMDEVINS pDevIns = pDev->pInstances; pDevIns; pDevIns = pDevIns->Internal.s.pPerDeviceNext HC)4397 for (PPDMDEVINS pDevIns = pDev->pInstances; pDevIns; pDevIns = pDevIns->Internal.s.pPerDeviceNextR3) 4379 4398 { 4380 4399 if (pDevIns->iInstance == iInstance) … … 4383 4402 * Iterate luns. 4384 4403 */ 4385 for (PPDMLUN pLun = pDevIns->Internal.s.pLuns HC; pLun; pLun = pLun->pNext)4404 for (PPDMLUN pLun = pDevIns->Internal.s.pLunsR3; pLun; pLun = pLun->pNext) 4386 4405 { 4387 4406 if (pLun->iLun == iLun) -
trunk/src/VBox/VMM/PDMDriver.cpp
r11311 r12970 1087 1087 1088 1088 1089 /** @copydoc PDMDEVHLP ::pfnVMState */1089 /** @copydoc PDMDEVHLPR3::pfnVMState */ 1090 1090 static DECLCALLBACK(VMSTATE) pdmR3DrvHlp_VMState(PPDMDRVINS pDrvIns) 1091 1091 { -
trunk/src/VBox/VMM/PDMInternal.h
r12807 r12970 85 85 /** Pointer to the next instance (HC Ptr). 86 86 * (Head is pointed to by PDM::pDevInstances.) */ 87 R3PTRTYPE(PPDMDEVINS) pNext HC;87 R3PTRTYPE(PPDMDEVINS) pNextR3; 88 88 /** Pointer to the next per device instance (HC Ptr). 89 89 * (Head is pointed to by PDMDEV::pInstances.) */ 90 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextHC; 91 90 R3PTRTYPE(PPDMDEVINS) pPerDeviceNextR3; 92 91 /** Pointer to device structure - HC Ptr. */ 93 R3PTRTYPE(PPDMDEV) pDevHC; 94 95 /** Pointer to the VM this instance was created for - HC Ptr. */ 96 R3R0PTRTYPE(PVM) pVMHC; 92 R3PTRTYPE(PPDMDEV) pDevR3; 97 93 /** Pointer to the list of logical units associated with the device. (FIFO) */ 98 R3PTRTYPE(PPDMLUN) pLuns HC;94 R3PTRTYPE(PPDMLUN) pLunsR3; 99 95 /** Configuration handle to the instance node. */ 100 96 R3PTRTYPE(PCFGMNODE) pCfgHandle; 101 /** HC pointer to associated PCI device structure. */ 102 R3R0PTRTYPE(struct PCIDevice *) pPciDeviceHC; 103 /** HC pointer to associated PCI bus structure. */ 104 R3R0PTRTYPE(PPDMPCIBUS) pPciBusHC; 105 106 /** GC pointer to associated PCI device structure. */ 107 RCPTRTYPE(struct PCIDevice *) pPciDeviceGC; 108 /** Pointer to the VM this instance was created for - GC Ptr. */ 109 RCPTRTYPE(PVM) pVMGC; 110 /** GC pointer to associated PCI bus structure. */ 111 RCPTRTYPE(PPDMPCIBUS) pPciBusGC; 97 98 /** R3 pointer to the VM this instance was created for. */ 99 PVMR3 pVMR3; 100 /** R3 pointer to associated PCI device structure. */ 101 R3PTRTYPE(struct PCIDevice *) pPciDeviceR3; 102 /** R3 pointer to associated PCI bus structure. */ 103 R3PTRTYPE(PPDMPCIBUS) pPciBusR3; 104 105 /** R0 pointer to the VM this instance was created for. */ 106 PVMR0 pVMR0; 107 /** R0 pointer to associated PCI device structure. */ 108 R0PTRTYPE(struct PCIDevice *) pPciDeviceR0; 109 /** R0 pointer to associated PCI bus structure. */ 110 R0PTRTYPE(PPDMPCIBUS) pPciBusR0; 112 111 /** Alignment padding. */ 113 uint32_t Alignment0; 112 RTR0PTR Alignment0; 113 114 /** RC pointer to the VM this instance was created for. */ 115 PVMRC pVMRC; 116 /** RC pointer to associated PCI device structure. */ 117 RCPTRTYPE(struct PCIDevice *) pPciDeviceRC; 118 /** RC pointer to associated PCI bus structure. */ 119 RCPTRTYPE(PPDMPCIBUS) pPciBusRC; 120 /** Alignment padding. */ 121 RTRCPTR Alignment1; 114 122 } PDMDEVINSINT; 115 123 … … 161 169 /** Pointer to the driver instance above. 162 170 * This is NULL for the topmost drive. */ 163 PPDMDRVINS pUp;171 PPDMDRVINS pUp; 164 172 /** Pointer to the driver instance below. 165 173 * This is NULL for the bottommost driver. */ 166 PPDMDRVINS pDown;174 PPDMDRVINS pDown; 167 175 /** Pointer to the logical unit this driver chained on. */ 168 PPDMLUN pLun;176 PPDMLUN pLun; 169 177 /** Pointer to driver structure from which this was instantiated. */ 170 PPDMDRV pDrv;178 PPDMDRV pDrv; 171 179 /** Pointer to the VM this instance was created for. */ 172 PVM pVM;180 PVM pVM; 173 181 /** Flag indicating that the driver is being detached and destroyed. 174 182 * (Helps detect potential recursive detaching.) */ 175 bool fDetaching;183 bool fDetaching; 176 184 /** Configuration handle to the instance node. */ 177 PCFGMNODE pCfgHandle;185 PCFGMNODE pCfgHandle; 178 186 179 187 } PDMDRVINSINT; … … 186 194 { 187 195 /** The critical section core which is shared with IPRT. */ 188 RTCRITSECT Core;196 RTCRITSECT Core; 189 197 /** Pointer to the next critical section. 190 198 * This chain is used for relocating pVMGC and device cleanup. */ … … 193 201 * This is pDevIns if the owner is a device. Similarily for a driver or service. 194 202 * PDMR3CritSectInit() sets this to point to the critsect itself. */ 195 RTR3PTR pvKey;203 RTR3PTR pvKey; 196 204 /** Pointer to the VM - R3Ptr. */ 197 R3PTRTYPE(PVM) pVMR3;205 R3PTRTYPE(PVM) pVMR3; 198 206 /** Pointer to the VM - R0Ptr. */ 199 R0PTRTYPE(PVM) pVMR0;207 R0PTRTYPE(PVM) pVMR0; 200 208 /** Pointer to the VM - GCPtr. */ 201 RCPTRTYPE(PVM) pVMGC;209 RCPTRTYPE(PVM) pVMGC; 202 210 #if HC_ARCH_BITS == 64 203 211 uint32_t padding; … … 205 213 /** Event semaphore that is scheduled to be signaled upon leaving the 206 214 * critical section. This is Ring-3 only of course. */ 207 RTSEMEVENT EventToSignal;215 RTSEMEVENT EventToSignal; 208 216 /** R0/GC lock contention. */ 209 STAMCOUNTER StatContentionR0GCLock;217 STAMCOUNTER StatContentionR0GCLock; 210 218 /** R0/GC unlock contention. */ 211 STAMCOUNTER StatContentionR0GCUnlock;219 STAMCOUNTER StatContentionR0GCUnlock; 212 220 /** R3 lock contention. */ 213 STAMCOUNTER StatContentionR3;221 STAMCOUNTER StatContentionR3; 214 222 /** Profiling the time the section is locked. */ 215 STAMPROFILEADV StatLocked;223 STAMPROFILEADV StatLocked; 216 224 } PDMCRITSECTINT, *PPDMCRITSECTINT; 217 225 … … 277 285 * device, like for instance the PS/2 keyboard port on the 278 286 * keyboard controller device. The LUNs are chained on the 279 * device the belong to (PDMDEVINSINT::pLuns HC).287 * device the belong to (PDMDEVINSINT::pLunsR3). 280 288 */ 281 289 typedef struct PDMLUN -
trunk/src/VBox/VMM/VMMGC/PDMGCDevice.cpp
r12799 r12970 48 48 # define PDMDEV_ASSERT_DEVINS(pDevIns) do { Assert(VALID_PTR(pDevIns)); \ 49 49 Assert(pDevIns->u32Version == PDM_DEVINS_VERSION); \ 50 Assert(pDevIns->pvInstanceData GC == (void *)&pDevIns->achInstanceData[0]); \50 Assert(pDevIns->pvInstanceDataRC == (void *)&pDevIns->achInstanceData[0]); \ 51 51 } while (0) 52 52 #else … … 59 59 *******************************************************************************/ 60 60 __BEGIN_DECLS 61 extern DECLEXPORT(const PDMDEVHLP GC) g_pdmGCDevHlp;61 extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp; 62 62 extern DECLEXPORT(const PDMPICHLPRC) g_pdmRCPicHlp; 63 63 extern DECLEXPORT(const PDMAPICHLPRC) g_pdmRCApicHlp; … … 136 136 * The Guest Context Device Helper Callbacks. 137 137 */ 138 extern DECLEXPORT(const PDMDEVHLP GC) g_pdmGCDevHlp =139 { 140 PDM_DEVHLP GC_VERSION,138 extern DECLEXPORT(const PDMDEVHLPRC) g_pdmRCDevHlp = 139 { 140 PDM_DEVHLPRC_VERSION, 141 141 pdmGCDevHlp_PCISetIrq, 142 142 pdmGCDevHlp_ISASetIrq, … … 149 149 pdmGCDevHlp_VMSetRuntimeErrorV, 150 150 pdmGCDevHlp_PATMSetMMIOPatchInfo, 151 PDM_DEVHLP GC_VERSION151 PDM_DEVHLPRC_VERSION 152 152 }; 153 153 … … 211 211 212 212 213 /** @copydoc PDMDEVHLP GC::pfnPCISetIrq */213 /** @copydoc PDMDEVHLPRC::pfnPCISetIrq */ 214 214 static DECLCALLBACK(void) pdmGCDevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 215 215 { … … 217 217 LogFlow(("pdmGCDevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel)); 218 218 219 PVM pVM = pDevIns->Internal.s.pVM GC;220 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDevice GC;221 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBus GC;219 PVM pVM = pDevIns->Internal.s.pVMRC; 220 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceRC; 221 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusRC; 222 222 if ( pPciDev 223 223 && pPciBus … … 249 249 250 250 251 /** @copydoc PDMDEVHLP GC::pfnPCISetIrq */251 /** @copydoc PDMDEVHLPRC::pfnPCISetIrq */ 252 252 static DECLCALLBACK(void) pdmGCDevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel) 253 253 { … … 255 255 LogFlow(("pdmGCDevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel)); 256 256 257 pdmGCIsaSetIrq(pDevIns->Internal.s.pVM GC, iIrq, iLevel);257 pdmGCIsaSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel); 258 258 259 259 LogFlow(("pdmGCDevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 261 261 262 262 263 /** @copydoc PDMDEVHLP GC::pfnPhysRead */263 /** @copydoc PDMDEVHLPRC::pfnPhysRead */ 264 264 static DECLCALLBACK(void) pdmGCDevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead) 265 265 { … … 268 268 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead)); 269 269 270 PGMPhysRead(pDevIns->Internal.s.pVM GC, GCPhys, pvBuf, cbRead);270 PGMPhysRead(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbRead); 271 271 272 272 Log(("pdmGCDevHlp_PhysRead: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 274 274 275 275 276 /** @copydoc PDMDEVHLP GC::pfnPhysWrite */276 /** @copydoc PDMDEVHLPRC::pfnPhysWrite */ 277 277 static DECLCALLBACK(void) pdmGCDevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite) 278 278 { … … 281 281 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite)); 282 282 283 PGMPhysWrite(pDevIns->Internal.s.pVM GC, GCPhys, pvBuf, cbWrite);283 PGMPhysWrite(pDevIns->Internal.s.pVMRC, GCPhys, pvBuf, cbWrite); 284 284 285 285 Log(("pdmGCDevHlp_PhysWrite: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 287 287 288 288 289 /** @copydoc PDMDEVHLP GC::pfnA20IsEnabled */289 /** @copydoc PDMDEVHLPRC::pfnA20IsEnabled */ 290 290 static DECLCALLBACK(bool) pdmGCDevHlp_A20IsEnabled(PPDMDEVINS pDevIns) 291 291 { … … 293 293 LogFlow(("pdmGCDevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance)); 294 294 295 bool fEnabled = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVM GC);295 bool fEnabled = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVMRC); 296 296 297 297 Log(("pdmGCDevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled)); … … 300 300 301 301 302 /** @copydoc PDMDEVHLP GC::pfnVMSetError */302 /** @copydoc PDMDEVHLPRC::pfnVMSetError */ 303 303 static DECLCALLBACK(int) pdmGCDevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...) 304 304 { … … 306 306 va_list args; 307 307 va_start(args, pszFormat); 308 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM GC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);308 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2); 309 309 va_end(args); 310 310 return rc; … … 312 312 313 313 314 /** @copydoc PDMDEVHLP GC::pfnVMSetErrorV */314 /** @copydoc PDMDEVHLPRC::pfnVMSetErrorV */ 315 315 static DECLCALLBACK(int) pdmGCDevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va) 316 316 { 317 317 PDMDEV_ASSERT_DEVINS(pDevIns); 318 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM GC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);318 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMRC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2); 319 319 return rc; 320 320 } 321 321 322 322 323 /** @copydoc PDMDEVHLP GC::pfnVMSetRuntimeError */323 /** @copydoc PDMDEVHLPRC::pfnVMSetRuntimeError */ 324 324 static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, bool fFatal, const char *pszErrorID, const char *pszFormat, ...) 325 325 { … … 327 327 va_list args; 328 328 va_start(args, pszFormat); 329 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM GC, fFatal, pszErrorID, pszFormat, args);329 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFatal, pszErrorID, pszFormat, args); 330 330 va_end(args); 331 331 return rc; … … 333 333 334 334 335 /** @copydoc PDMDEVHLP GC::pfnVMSetErrorV */335 /** @copydoc PDMDEVHLPRC::pfnVMSetErrorV */ 336 336 static DECLCALLBACK(int) pdmGCDevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, bool fFatal, const char *pszErrorID, const char *pszFormat, va_list va) 337 337 { 338 338 PDMDEV_ASSERT_DEVINS(pDevIns); 339 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM GC, fFatal, pszErrorID, pszFormat, va);339 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMRC, fFatal, pszErrorID, pszFormat, va); 340 340 return rc; 341 341 } 342 342 343 343 344 /** @copydoc PDMDEVHLP GC::pfnPATMSetMMIOPatchInfo */344 /** @copydoc PDMDEVHLPRC::pfnPATMSetMMIOPatchInfo */ 345 345 static DECLCALLBACK(int) pdmGCDevHlp_PATMSetMMIOPatchInfo(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTGCPTR pCachedData) 346 346 { … … 348 348 LogFlow(("pdmGCDevHlp_PATMSetMMIOPatchInfo: caller=%p/%d:\n", pDevIns, pDevIns->iInstance)); 349 349 350 return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVM GC, GCPhys, (RTRCPTR)pCachedData);350 return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMRC, GCPhys, (RTRCPTR)pCachedData); 351 351 } 352 352 … … 359 359 PDMDEV_ASSERT_DEVINS(pDevIns); 360 360 LogFlow(("pdmRCPicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 1\n", 361 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM GC, 0, VM_FF_INTERRUPT_PIC)));361 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMRC, 0, VM_FF_INTERRUPT_PIC))); 362 362 /* for PIC we always deliver to CPU 0, MP use APIC */ 363 VMCPU_FF_SET(pDevIns->Internal.s.pVM GC, 0, VM_FF_INTERRUPT_PIC);363 VMCPU_FF_SET(pDevIns->Internal.s.pVMRC, 0, VM_FF_INTERRUPT_PIC); 364 364 } 365 365 … … 370 370 PDMDEV_ASSERT_DEVINS(pDevIns); 371 371 LogFlow(("pdmRCPicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 0\n", 372 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM GC, 0, VM_FF_INTERRUPT_PIC)));372 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMRC, 0, VM_FF_INTERRUPT_PIC))); 373 373 /* for PIC we always deliver to CPU 0, MP use APIC */ 374 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM GC, 0, VM_FF_INTERRUPT_PIC);374 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMRC, 0, VM_FF_INTERRUPT_PIC); 375 375 } 376 376 … … 380 380 { 381 381 PDMDEV_ASSERT_DEVINS(pDevIns); 382 return pdmLockEx(pDevIns->Internal.s.pVM GC, rc);382 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc); 383 383 } 384 384 … … 388 388 { 389 389 PDMDEV_ASSERT_DEVINS(pDevIns); 390 pdmUnlock(pDevIns->Internal.s.pVM GC);390 pdmUnlock(pDevIns->Internal.s.pVMRC); 391 391 } 392 392 … … 399 399 PDMDEV_ASSERT_DEVINS(pDevIns); 400 400 LogFlow(("pdmRCApicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 1\n", 401 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM GC, idCpu, VM_FF_INTERRUPT_APIC)));402 VMCPU_FF_SET(pDevIns->Internal.s.pVM GC, idCpu, VM_FF_INTERRUPT_APIC);401 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMRC, idCpu, VM_FF_INTERRUPT_APIC))); 402 VMCPU_FF_SET(pDevIns->Internal.s.pVMRC, idCpu, VM_FF_INTERRUPT_APIC); 403 403 } 404 404 … … 409 409 PDMDEV_ASSERT_DEVINS(pDevIns); 410 410 LogFlow(("pdmRCApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n", 411 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM GC, idCpu, VM_FF_INTERRUPT_APIC)));412 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM GC, idCpu, VM_FF_INTERRUPT_APIC);411 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMRC, idCpu, VM_FF_INTERRUPT_APIC))); 412 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMRC, idCpu, VM_FF_INTERRUPT_APIC); 413 413 } 414 414 … … 420 420 LogFlow(("pdmRCApicHlp_ChangeFeature: caller=%p/%d: fEnabled=%RTbool\n", pDevIns, pDevIns->iInstance, fEnabled)); 421 421 if (fEnabled) 422 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVM GC, CPUMCPUIDFEATURE_APIC);422 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC); 423 423 else 424 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVM GC, CPUMCPUIDFEATURE_APIC);424 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMRC, CPUMCPUIDFEATURE_APIC); 425 425 } 426 426 … … 430 430 { 431 431 PDMDEV_ASSERT_DEVINS(pDevIns); 432 return pdmLockEx(pDevIns->Internal.s.pVM GC, rc);432 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc); 433 433 } 434 434 … … 438 438 { 439 439 PDMDEV_ASSERT_DEVINS(pDevIns); 440 pdmUnlock(pDevIns->Internal.s.pVM GC);440 pdmUnlock(pDevIns->Internal.s.pVMRC); 441 441 } 442 442 … … 446 446 { 447 447 PDMDEV_ASSERT_DEVINS(pDevIns); 448 return VMMGetCpuId(pDevIns->Internal.s.pVM GC);448 return VMMGetCpuId(pDevIns->Internal.s.pVMRC); 449 449 } 450 450 … … 454 454 { 455 455 PDMDEV_ASSERT_DEVINS(pDevIns); 456 PVM pVM = pDevIns->Internal.s.pVM GC;456 PVM pVM = pDevIns->Internal.s.pVMRC; 457 457 LogFlow(("pdmRCIoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n", 458 458 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode)); … … 466 466 { 467 467 PDMDEV_ASSERT_DEVINS(pDevIns); 468 return pdmLockEx(pDevIns->Internal.s.pVM GC, rc);468 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc); 469 469 } 470 470 … … 474 474 { 475 475 PDMDEV_ASSERT_DEVINS(pDevIns); 476 pdmUnlock(pDevIns->Internal.s.pVM GC);476 pdmUnlock(pDevIns->Internal.s.pVMRC); 477 477 } 478 478 … … 485 485 PDMDEV_ASSERT_DEVINS(pDevIns); 486 486 Log4(("pdmRCPciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 487 pdmGCIsaSetIrq(pDevIns->Internal.s.pVM GC, iIrq, iLevel);487 pdmGCIsaSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel); 488 488 } 489 489 … … 494 494 PDMDEV_ASSERT_DEVINS(pDevIns); 495 495 Log4(("pdmRCPciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 496 pdmGCIoApicSetIrq(pDevIns->Internal.s.pVM GC, iIrq, iLevel);496 pdmGCIoApicSetIrq(pDevIns->Internal.s.pVMRC, iIrq, iLevel); 497 497 } 498 498 … … 502 502 { 503 503 PDMDEV_ASSERT_DEVINS(pDevIns); 504 return pdmLockEx(pDevIns->Internal.s.pVM GC, rc);504 return pdmLockEx(pDevIns->Internal.s.pVMRC, rc); 505 505 } 506 506 … … 510 510 { 511 511 PDMDEV_ASSERT_DEVINS(pDevIns); 512 pdmUnlock(pDevIns->Internal.s.pVM GC);512 pdmUnlock(pDevIns->Internal.s.pVMRC); 513 513 } 514 514 -
trunk/src/VBox/VMM/VMMR0/PDMR0Device.cpp
r12799 r12970 217 217 LogFlow(("pdmR0DevHlp_PCISetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel)); 218 218 219 PVM pVM = pDevIns->Internal.s.pVM HC;220 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDevice HC;221 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBus HC;219 PVM pVM = pDevIns->Internal.s.pVMR0; 220 PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR0; 221 PPDMPCIBUS pPciBus = pDevIns->Internal.s.pPciBusR0; 222 222 if ( pPciDev 223 223 && pPciBus … … 255 255 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: iIrq=%d iLevel=%d\n", pDevIns, pDevIns->iInstance, iIrq, iLevel)); 256 256 257 pdmR0IsaSetIrq(pDevIns->Internal.s.pVM HC, iIrq, iLevel);257 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel); 258 258 259 259 LogFlow(("pdmR0DevHlp_ISASetIrq: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 268 268 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbRead)); 269 269 270 PGMPhysRead(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbRead);270 PGMPhysRead(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbRead); 271 271 272 272 Log(("pdmR0DevHlp_PhysRead: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 281 281 pDevIns, pDevIns->iInstance, GCPhys, pvBuf, cbWrite)); 282 282 283 PGMPhysWrite(pDevIns->Internal.s.pVM HC, GCPhys, pvBuf, cbWrite);283 PGMPhysWrite(pDevIns->Internal.s.pVMR0, GCPhys, pvBuf, cbWrite); 284 284 285 285 Log(("pdmR0DevHlp_PhysWrite: caller=%p/%d: returns void\n", pDevIns, pDevIns->iInstance)); … … 293 293 LogFlow(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d:\n", pDevIns, pDevIns->iInstance)); 294 294 295 bool fEnabled = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVM HC);295 bool fEnabled = PGMPhysIsA20Enabled(pDevIns->Internal.s.pVMR0); 296 296 297 297 Log(("pdmR0DevHlp_A20IsEnabled: caller=%p/%d: returns %RTbool\n", pDevIns, pDevIns->iInstance, fEnabled)); … … 306 306 va_list args; 307 307 va_start(args, pszFormat); 308 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM HC, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);308 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2); 309 309 va_end(args); 310 310 return rc; … … 316 316 { 317 317 PDMDEV_ASSERT_DEVINS(pDevIns); 318 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVM HC, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);318 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR0, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2); 319 319 return rc; 320 320 } … … 327 327 va_list args; 328 328 va_start(args, pszFormat); 329 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM HC, fFatal, pszErrorID, pszFormat, args);329 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFatal, pszErrorID, pszFormat, args); 330 330 va_end(args); 331 331 return rc; … … 337 337 { 338 338 PDMDEV_ASSERT_DEVINS(pDevIns); 339 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVM HC, fFatal, pszErrorID, pszFormat, va);339 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR0, fFatal, pszErrorID, pszFormat, va); 340 340 return rc; 341 341 } … … 350 350 AssertFailed(); 351 351 352 /* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVM HC, GCPhys, pCachedData); */352 /* return PATMSetMMIOPatchInfo(pDevIns->Internal.s.pVMR0, GCPhys, pCachedData); */ 353 353 return VINF_SUCCESS; 354 354 } … … 363 363 PDMDEV_ASSERT_DEVINS(pDevIns); 364 364 LogFlow(("pdmR0PicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 1\n", 365 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC)));365 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC))); 366 366 /* for PIC we always deliver to CPU 0, MP use APIC */ 367 VMCPU_FF_SET(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC);367 VMCPU_FF_SET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC); 368 368 } 369 369 … … 374 374 PDMDEV_ASSERT_DEVINS(pDevIns); 375 375 LogFlow(("pdmR0PicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT_PIC %d -> 0\n", 376 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC)));376 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC))); 377 377 /* for PIC we always deliver to CPU 0, MP use APIC */ 378 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM HC, 0, VM_FF_INTERRUPT_PIC);378 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR0, 0, VM_FF_INTERRUPT_PIC); 379 379 } 380 380 … … 384 384 { 385 385 PDMDEV_ASSERT_DEVINS(pDevIns); 386 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);386 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc); 387 387 } 388 388 … … 392 392 { 393 393 PDMDEV_ASSERT_DEVINS(pDevIns); 394 pdmUnlock(pDevIns->Internal.s.pVM HC);394 pdmUnlock(pDevIns->Internal.s.pVMR0); 395 395 } 396 396 … … 403 403 404 404 LogFlow(("pdmR0ApicHlp_SetInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 1\n", 405 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC)));406 VMCPU_FF_SET(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC);405 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC))); 406 VMCPU_FF_SET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC); 407 407 } 408 408 … … 414 414 415 415 LogFlow(("pdmR0ApicHlp_ClearInterruptFF: caller=%p/%d: VM_FF_INTERRUPT %d -> 0\n", 416 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC)));417 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVM HC, idCpu, VM_FF_INTERRUPT_APIC);416 pDevIns, pDevIns->iInstance, VMCPU_FF_ISSET(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC))); 417 VMCPU_FF_CLEAR(pDevIns->Internal.s.pVMR0, idCpu, VM_FF_INTERRUPT_APIC); 418 418 } 419 419 … … 425 425 LogFlow(("pdmR0ApicHlp_ChangeFeature: caller=%p/%d: fEnabled=%RTbool\n", pDevIns, pDevIns->iInstance, fEnabled)); 426 426 if (fEnabled) 427 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVM HC, CPUMCPUIDFEATURE_APIC);427 CPUMSetGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC); 428 428 else 429 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVM HC, CPUMCPUIDFEATURE_APIC);429 CPUMClearGuestCpuIdFeature(pDevIns->Internal.s.pVMR0, CPUMCPUIDFEATURE_APIC); 430 430 } 431 431 … … 435 435 { 436 436 PDMDEV_ASSERT_DEVINS(pDevIns); 437 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);437 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc); 438 438 } 439 439 … … 443 443 { 444 444 PDMDEV_ASSERT_DEVINS(pDevIns); 445 pdmUnlock(pDevIns->Internal.s.pVM HC);445 pdmUnlock(pDevIns->Internal.s.pVMR0); 446 446 } 447 447 … … 451 451 { 452 452 PDMDEV_ASSERT_DEVINS(pDevIns); 453 return VMMGetCpuId(pDevIns->Internal.s.pVM HC);453 return VMMGetCpuId(pDevIns->Internal.s.pVMR0); 454 454 } 455 455 … … 460 460 { 461 461 PDMDEV_ASSERT_DEVINS(pDevIns); 462 PVM pVM = pDevIns->Internal.s.pVM HC;462 PVM pVM = pDevIns->Internal.s.pVMR0; 463 463 LogFlow(("pdmR0IoApicHlp_ApicBusDeliver: caller=%p/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 iVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8\n", 464 464 pDevIns, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, iVector, u8Polarity, u8TriggerMode)); … … 473 473 { 474 474 PDMDEV_ASSERT_DEVINS(pDevIns); 475 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);475 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc); 476 476 } 477 477 … … 481 481 { 482 482 PDMDEV_ASSERT_DEVINS(pDevIns); 483 pdmUnlock(pDevIns->Internal.s.pVM HC);483 pdmUnlock(pDevIns->Internal.s.pVMR0); 484 484 } 485 485 … … 493 493 PDMDEV_ASSERT_DEVINS(pDevIns); 494 494 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 495 pdmR0IsaSetIrq(pDevIns->Internal.s.pVM HC, iIrq, iLevel);495 pdmR0IsaSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel); 496 496 } 497 497 … … 502 502 PDMDEV_ASSERT_DEVINS(pDevIns); 503 503 Log4(("pdmR0PciHlp_IsaSetIrq: iIrq=%d iLevel=%d\n", iIrq, iLevel)); 504 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVM HC, iIrq, iLevel);504 pdmR0IoApicSetIrq(pDevIns->Internal.s.pVMR0, iIrq, iLevel); 505 505 } 506 506 … … 510 510 { 511 511 PDMDEV_ASSERT_DEVINS(pDevIns); 512 return pdmLockEx(pDevIns->Internal.s.pVM HC, rc);512 return pdmLockEx(pDevIns->Internal.s.pVMR0, rc); 513 513 } 514 514 … … 518 518 { 519 519 PDMDEV_ASSERT_DEVINS(pDevIns); 520 pdmUnlock(pDevIns->Internal.s.pVM HC);520 pdmUnlock(pDevIns->Internal.s.pVMR0); 521 521 } 522 522 -
trunk/src/VBox/VMM/testcase/tstVMStructGC.cpp
r12815 r12970 318 318 GEN_CHECK_OFF(PDM, StatQueuedCritSectLeaves); 319 319 GEN_CHECK_SIZE(PDMDEVINSINT); 320 GEN_CHECK_OFF(PDMDEVINSINT, pNextHC); 321 GEN_CHECK_OFF(PDMDEVINSINT, pPerDeviceNextHC); 322 GEN_CHECK_OFF(PDMDEVINSINT, pDevHC); 323 GEN_CHECK_OFF(PDMDEVINSINT, pVMHC); 324 GEN_CHECK_OFF(PDMDEVINSINT, pVMGC); 325 GEN_CHECK_OFF(PDMDEVINSINT, pLunsHC); 320 GEN_CHECK_OFF(PDMDEVINSINT, pNextR3); 321 GEN_CHECK_OFF(PDMDEVINSINT, pPerDeviceNextR3); 322 GEN_CHECK_OFF(PDMDEVINSINT, pDevR3); 323 GEN_CHECK_OFF(PDMDEVINSINT, pVMR3); 324 GEN_CHECK_OFF(PDMDEVINSINT, pVMR0); 325 GEN_CHECK_OFF(PDMDEVINSINT, pVMRC); 326 GEN_CHECK_OFF(PDMDEVINSINT, pLunsR3); 326 327 GEN_CHECK_OFF(PDMDEVINSINT, pCfgHandle); 327 GEN_CHECK_OFF(PDMDEVINSINT, pPciDeviceHC); 328 GEN_CHECK_OFF(PDMDEVINSINT, pPciDeviceGC); 329 GEN_CHECK_OFF(PDMDEVINSINT, pPciBusHC); 330 GEN_CHECK_OFF(PDMDEVINSINT, pPciBusGC); 328 GEN_CHECK_OFF(PDMDEVINSINT, pPciDeviceR3); 329 GEN_CHECK_OFF(PDMDEVINSINT, pPciDeviceR0); 330 GEN_CHECK_OFF(PDMDEVINSINT, pPciDeviceRC); 331 GEN_CHECK_OFF(PDMDEVINSINT, pPciBusR3); 332 GEN_CHECK_OFF(PDMDEVINSINT, pPciBusR0); 333 GEN_CHECK_OFF(PDMDEVINSINT, pPciBusRC); 331 334 GEN_CHECK_SIZE(PDMCRITSECTINT); 332 335 GEN_CHECK_OFF(PDMCRITSECTINT, Core); -
trunk/src/VBox/VMM/testcase/tstVMStructSize.cpp
r12702 r12970 224 224 225 225 /* pdm */ 226 CHECK_MEMBER_ALIGNMENT(PDMDEVINS, achInstanceData, 16);226 CHECK_MEMBER_ALIGNMENT(PDMDEVINS, achInstanceData, 64); 227 227 CHECK_PADDING(PDMDEVINS, Internal); 228 228 CHECK_MEMBER_ALIGNMENT(PDMUSBINS, achInstanceData, 16);
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