Changeset 12989 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Oct 6, 2008 2:15:39 AM (16 years ago)

Author:

vboxsync

Message:

VMM + VBox/cdefs.h: consolidated all the XYZ*DECLS of the VMM into VMM*DECL. Removed dead DECL and IN_XYZ* macros.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• CPUMR0.cpp (modified) (5 diffs)
• DBGFR0.cpp (modified) (2 diffs)
• HWACCMR0.cpp (modified) (13 diffs)
• HWSVMR0.cpp (modified) (12 diffs)
• HWSVMR0.h (modified) (10 diffs)
• HWVMXR0.cpp (modified) (12 diffs)
• HWVMXR0.h (modified) (10 diffs)
• PGMR0.cpp (modified) (3 diffs)
• TRPMR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

@@ -45 +45 @@
  * @param   pVM         The VM to operate on.
  */
-CPUMR0DECL(int) CPUMR0Init(PVM pVM)
+VMMR0DECL(int) CPUMR0Init(PVM pVM)
 {
     LogFlow(("CPUMR0Init: %p\n", pVM));
@@ -116 +116 @@
  * @param   pCtx        CPU context
  */
-CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx)
 {
     Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
@@ -236 +236 @@
  * @param   pCtx        CPU context
  */
-CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx)
 {
     Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
@@ -287 +287 @@
  * @param   fDR6        Include DR6 or not
  */
-CPUMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
+VMMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
 {
     Assert(pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
@@ -323 +323 @@
  * @param   fDR6        Include DR6 or not
  */
-CPUMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
+VMMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
 {
     /* Save the host state. */

trunk/src/VBox/VMM/VMMR0/DBGFR0.cpp

@@ -47 +47 @@
  * @param   uDr6        The DR6 register value.
  */
-DBGFR0DECL(int) DBGFR0Trap01Handler(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6)
+VMMR0DECL(int) DBGFR0Trap01Handler(PVM pVM, PCPUMCTXCORE pRegFrame, RTGCUINTREG uDr6)
 {
     /** @todo Intel docs say that X86_DR6_BS has the highest priority... */
@@ -105 +105 @@
  * @param   pRegFrame   Pointer to the register frame for the trap.
  */
-DBGFR0DECL(int) DBGFR0Trap03Handler(PVM pVM, PCPUMCTXCORE pRegFrame)
+VMMR0DECL(int) DBGFR0Trap03Handler(PVM pVM, PCPUMCTXCORE pRegFrame)
 {
     /*

trunk/src/VBox/VMM/VMMR0/HWACCMR0.cpp

@@ -136 +136 @@
  * @returns VBox status code.
  */
-HWACCMR0DECL(int) HWACCMR0Init(void)
+VMMR0DECL(int) HWACCMR0Init(void)
 {
     int        rc;
@@ -415 +415 @@
  * @returns VBox status code.
  */
-HWACCMR0DECL(int) HWACCMR0Term(void)
+VMMR0DECL(int) HWACCMR0Term(void)
 {
     int aRc[RTCPUSET_MAX_CPUS];
@@ -512 +512 @@
  *
  */
-HWACCMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
+VMMR0DECL(int) HWACCMR0EnableAllCpus(PVM pVM, HWACCMSTATE enmNewHwAccmState)
 {
     Assert(sizeof(HWACCMR0Globals.enmHwAccmState) == sizeof(uint32_t));
@@ -649 +649 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0InitVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0InitVM(PVM pVM)
 {
     AssertReturn(pVM, VERR_INVALID_PARAMETER);
@@ -696 +696 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0TermVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0TermVM(PVM pVM)
 {
     AssertReturn(pVM, VERR_INVALID_PARAMETER);
@@ -715 +715 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0SetupVM(PVM pVM)
 {
     AssertReturn(pVM, VERR_INVALID_PARAMETER);
@@ -734 +734 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0Enter(PVM pVM)
+VMMR0DECL(int) HWACCMR0Enter(PVM pVM)
 {
     CPUMCTX *pCtx;
@@ -785 +785 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0Leave(PVM pVM)
+VMMR0DECL(int) HWACCMR0Leave(PVM pVM)
 {
     CPUMCTX *pCtx;
@@ -825 +825 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
+VMMR0DECL(int) HWACCMR0RunGuestCode(PVM pVM)
 {
     CPUMCTX *pCtx;
@@ -848 +848 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
+VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu()
 {
     RTCPUID  idCpu = RTMpCpuId();
@@ -864 +864 @@
  * @param   pszMsg  Message to prepend the log entry with.
  */
-HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
+VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC pDesc, RTSEL Sel, const char *pszMsg)
 {
     /*
@@ -985 +985 @@
  * @param   pCtx        The context to format.
  */
-HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx)
 {
     /*
@@ -1127 +1127 @@
 
 /* Dummy callback handlers. */
-HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
+VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PCPUMCTX pCtx)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
+VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
+VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM)
 {
     return VINF_SUCCESS;
 }
 
-HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx)
 {
     return VINF_SUCCESS;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -66 +66 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
@@ -99 +99 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
@@ -125 +125 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0InitVM(PVM pVM)
+VMMR0DECL(int) SVMR0InitVM(PVM pVM)
 {
     int rc;
@@ -218 +218 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0TermVM(PVM pVM)
+VMMR0DECL(int) SVMR0TermVM(PVM pVM)
 {
     if (pVM->hwaccm.s.svm.pMemObjVMCB != NIL_RTR0MEMOBJ)
@@ -257 +257 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM)
+VMMR0DECL(int) SVMR0SetupVM(PVM pVM)
 {
     int         rc = VINF_SUCCESS;
@@ -525 +525 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM)
+VMMR0DECL(int) SVMR0SaveHostState(PVM pVM)
 {
     /* Nothing to do here. */
@@ -540 +540 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
 {
     RTGCUINTPTR val;
@@ -799 +799 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
 {
     int         rc = VINF_SUCCESS;
@@ -2055 +2055 @@
  * @param   pCpu        CPU info struct
  */
-HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
+VMMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
 {
     Assert(pVM->hwaccm.s.svm.fSupported);
@@ -2076 +2076 @@
  * @param   pCtx        CPU context
  */
-HWACCMR0DECL(int) SVMR0Leave(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(int) SVMR0Leave(PVM pVM, PCPUMCTX pCtx)
 {
     SVM_VMCB *pVMCB = (SVM_VMCB *)pVM->hwaccm.s.svm.pVMCB;
@@ -2193 +2193 @@
  * @param   GCVirt      Page to invalidate
  */
-HWACCMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
+VMMR0DECL(int) SVMR0InvalidatePage(PVM pVM, RTGCPTR GCVirt)
 {
     bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;
@@ -2225 +2225 @@
  * @param   GCPhys      Page to invalidate
  */
-HWACCMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
+VMMR0DECL(int) SVMR0InvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys)
 {
     bool fFlushPending = pVM->hwaccm.s.svm.fAlwaysFlushTLB | pVM->hwaccm.s.svm.fForceTLBFlush;

trunk/src/VBox/VMM/VMMR0/HWSVMR0.h

@@ -49 +49 @@
  * @param   pCpu        CPU info struct
  */
-HWACCMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu);
+VMMR0DECL(int) SVMR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu);
 
 /**
@@ -58 +58 @@
  * @param   pCtx        CPU context
  */
-HWACCMR0DECL(int) SVMR0Leave(PVM pVM, PCPUMCTX pCtx);
+VMMR0DECL(int) SVMR0Leave(PVM pVM, PCPUMCTX pCtx);
 
 /**
@@ -69 +69 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int) SVMR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 
 /**
@@ -79 +79 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int) SVMR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 
 /**
@@ -87 +87 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0InitVM(PVM pVM);
+VMMR0DECL(int) SVMR0InitVM(PVM pVM);
 
 /**
@@ -95 +95 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0TermVM(PVM pVM);
+VMMR0DECL(int) SVMR0TermVM(PVM pVM);
 
 /**
@@ -103 +103 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0SetupVM(PVM pVM);
+VMMR0DECL(int) SVMR0SetupVM(PVM pVM);
 
 
@@ -113 +113 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx);
+VMMR0DECL(int) SVMR0RunGuestCode(PVM pVM, CPUMCTX *pCtx);
 
 
@@ -122 +122 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) SVMR0SaveHostState(PVM pVM);
+VMMR0DECL(int) SVMR0SaveHostState(PVM pVM);
 
 /**
@@ -131 +131 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx);
+VMMR0DECL(int) SVMR0LoadGuestState(PVM pVM, CPUMCTX *pCtx);
 
 

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -71 +71 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
@@ -112 +112 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
+VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys)
 {
     AssertReturn(pPageCpuPhys, VERR_INVALID_PARAMETER);
@@ -135 +135 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0InitVM(PVM pVM)
+VMMR0DECL(int) VMXR0InitVM(PVM pVM)
 {
     int rc;
@@ -203 +203 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0TermVM(PVM pVM)
+VMMR0DECL(int) VMXR0TermVM(PVM pVM)
 {
     if (pVM->hwaccm.s.vmx.pMemObjVMCS != NIL_RTR0MEMOBJ)
@@ -235 +235 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM)
+VMMR0DECL(int) VMXR0SetupVM(PVM pVM)
 {
     int rc = VINF_SUCCESS;
@@ -476 +476 @@
     if (CPUMIsGuestInRealModeEx(pCtx))
     {
-        /* Injecting events doesn't work right with real mode emulation.  
+        /* Injecting events doesn't work right with real mode emulation.
          * (#GP if we try to inject external hardware interrupts)
          * Fake an 'int x' instruction. Note that we need to take special precautions when
@@ -637 +637 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM)
+VMMR0DECL(int) VMXR0SaveHostState(PVM pVM)
 {
     int rc = VINF_SUCCESS;
@@ -749 +749 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx)
 {
     int         rc = VINF_SUCCESS;
@@ -1230 +1230 @@
 # endif /* HWACCM_VMX_EMULATE_REALMODE */
     rc = VMXWriteVMCS(VMX_VMCS_CTRL_EXCEPTION_BITMAP, pVM->hwaccm.s.vmx.u32TrapMask);
-    AssertRC(rc);    
+    AssertRC(rc);
 #endif
 
@@ -1246 +1246 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
+VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx)
 {
     int         rc = VINF_SUCCESS;
@@ -2637 +2637 @@
  * @param   pCpu        CPU info struct
  */
-HWACCMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
+VMMR0DECL(int) VMXR0Enter(PVM pVM, PHWACCM_CPUINFO pCpu)
 {
     Assert(pVM->hwaccm.s.vmx.fSupported);
@@ -2665 +2665 @@
  * @param   pCtx        CPU context
  */
-HWACCMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
+VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx)
 {
     Assert(pVM->hwaccm.s.vmx.fSupported);

trunk/src/VBox/VMM/VMMR0/HWVMXR0.h

@@ -49 +49 @@
  * @param   pCpu        CPU info struct
  */
-HWACCMR0DECL(int) VMXR0Enter(PVM pVMm, PHWACCM_CPUINFO pCpu);
+VMMR0DECL(int) VMXR0Enter(PVM pVMm, PHWACCM_CPUINFO pCpu);
 
 /**
@@ -58 +58 @@
  * @param   pCtx        CPU context
  */
-HWACCMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx);
+VMMR0DECL(int) VMXR0Leave(PVM pVM, PCPUMCTX pCtx);
 
 
@@ -70 +70 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int) VMXR0EnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 
 /**
@@ -80 +80 @@
  * @param   pPageCpuPhys    Physical address of the global cpu page
  */
-HWACCMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
+VMMR0DECL(int) VMXR0DisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
 
 /**
@@ -88 +88 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0InitVM(PVM pVM);
+VMMR0DECL(int) VMXR0InitVM(PVM pVM);
 
 /**
@@ -96 +96 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0TermVM(PVM pVM);
+VMMR0DECL(int) VMXR0TermVM(PVM pVM);
 
 /**
@@ -104 +104 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0SetupVM(PVM pVM);
+VMMR0DECL(int) VMXR0SetupVM(PVM pVM);
 
 
@@ -113 +113 @@
  * @param   pVM         The VM to operate on.
  */
-HWACCMR0DECL(int) VMXR0SaveHostState(PVM pVM);
+VMMR0DECL(int) VMXR0SaveHostState(PVM pVM);
 
 /**
@@ -122 +122 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx);
+VMMR0DECL(int) VMXR0LoadGuestState(PVM pVM, CPUMCTX *pCtx);
 
 
@@ -132 +132 @@
  * @param   pCtx        Guest context
  */
-HWACCMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx);
+VMMR0DECL(int) VMXR0RunGuestCode(PVM pVM, CPUMCTX *pCtx);
 
 

trunk/src/VBox/VMM/VMMR0/PGMR0.cpp

@@ -58 +58 @@
  * @remarks Must be called from within the PGM critical section.
  */
-PGMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM)
+VMMR0DECL(int) PGMR0PhysAllocateHandyPages(PVM pVM)
 {
     return VERR_NOT_IMPLEMENTED;
@@ -74 +74 @@
  * @param   pvFault             The fault address.
  */
-PGMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault)
+VMMR0DECL(int) PGMR0Trap0eHandlerNestedPaging(PVM pVM, PGMMODE enmShwPagingMode, RTGCUINT uErr, PCPUMCTXCORE pRegFrame, RTGCPHYS pvFault)
 {
     int rc;
@@ -128 +128 @@
      * Call the worker.
      *
-     * We pretend the guest is in protected mode without paging, so we can use existing code to build the 
+     * We pretend the guest is in protected mode without paging, so we can use existing code to build the
      * nested page tables.
      */

trunk/src/VBox/VMM/VMMR0/TRPMR0.cpp

@@ -40 +40 @@
  * @remark  Must be called with interrupts disabled.
  */
-TRPMR0DECL(void) TRPMR0DispatchHostInterrupt(PVM pVM)
+VMMR0DECL(void) TRPMR0DispatchHostInterrupt(PVM pVM)
 {
     RTUINT uActiveVector = pVM->trpm.s.uActiveVector;
@@ -115 +115 @@
  * @param   pvRet       Pointer to the return address of VMMR0Entry() on the stack.
  */
-TRPMR0DECL(void) TRPMR0SetupInterruptDispatcherFrame(PVM pVM, void *pvRet)
+VMMR0DECL(void) TRPMR0SetupInterruptDispatcherFrame(PVM pVM, void *pvRet)
 {
     RTUINT uActiveVector = pVM->trpm.s.uActiveVector;