VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp@ 12657

Last change on this file since 12657 was 12657, checked in by vboxsync, 16 years ago

#1865: CPUM. Also added missing aliasing for DR4&5 to the guest DRx setter and getter.
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1/* $Id: CPUMR0.cpp 12657 2008-09-22 18:29:06Z vboxsync $ */
2/** @file
3 * CPUM - Host Context Ring 0.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22
23/*******************************************************************************
24* Header Files *
25*******************************************************************************/
26#define LOG_GROUP LOG_GROUP_CPUM
27#include <VBox/cpum.h>
28#include "CPUMInternal.h"
29#include <VBox/vm.h>
30#include <VBox/x86.h>
31#include <VBox/err.h>
32#include <VBox/log.h>
33#include <iprt/assert.h>
34#include <iprt/asm.h>
35
36
37
38/**
39 * Does Ring-0 CPUM initialization.
40 *
41 * This is mainly to check that the Host CPU mode is compatible
42 * with VBox.
43 *
44 * @returns VBox status code.
45 * @param pVM The VM to operate on.
46 */
47CPUMR0DECL(int) CPUMR0Init(PVM pVM)
48{
49 LogFlow(("CPUMR0Init: %p\n", pVM));
50
51 /*
52 * Check CR0 & CR4 flags.
53 */
54 uint32_t u32CR0 = ASMGetCR0();
55 if ((u32CR0 & (X86_CR0_PE | X86_CR0_PG)) != (X86_CR0_PE | X86_CR0_PG)) /* a bit paranoid perhaps.. */
56 {
57 Log(("CPUMR0Init: PE or PG not set. cr0=%#x\n", u32CR0));
58 return VERR_UNSUPPORTED_CPU_MODE;
59 }
60
61 /*
62 * Check for sysenter if it's used.
63 */
64 if (ASMHasCpuId())
65 {
66 uint32_t u32CpuVersion;
67 uint32_t u32Dummy;
68 uint32_t u32Features;
69 ASMCpuId(1, &u32CpuVersion, &u32Dummy, &u32Dummy, &u32Features);
70 uint32_t u32Family = u32CpuVersion >> 8;
71 uint32_t u32Model = (u32CpuVersion >> 4) & 0xF;
72 uint32_t u32Stepping = u32CpuVersion & 0xF;
73
74 /*
75 * Intel docs claim you should test both the flag and family, model & stepping.
76 * Some Pentium Pro cpus have the SEP cpuid flag set, but don't support it.
77 */
78 if ( (u32Features & X86_CPUID_FEATURE_EDX_SEP)
79 && !(u32Family == 6 && u32Model < 3 && u32Stepping < 3))
80 {
81 /*
82 * Read the MSR and see if it's in use or not.
83 */
84 uint32_t u32 = ASMRdMsr_Low(MSR_IA32_SYSENTER_CS);
85 if (u32)
86 {
87 pVM->cpum.s.fUseFlags |= CPUM_USE_SYSENTER;
88 Log(("CPUMR0Init: host uses sysenter cs=%08x%08x\n", ASMRdMsr_High(MSR_IA32_SYSENTER_CS), u32));
89 }
90 }
91
92 /** @todo check for AMD and syscall!!!!!! */
93 }
94
95
96 /*
97 * Check if debug registers are armed.
98 * This ASSUMES that DR7.GD is not set, or that it's handled transparently!
99 */
100 uint32_t u32DR7 = ASMGetDR7();
101 if (u32DR7 & X86_DR7_ENABLED_MASK)
102 {
103 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS_HOST;
104 Log(("CPUMR0Init: host uses debug registers (dr7=%x)\n", u32DR7));
105 }
106
107 return VINF_SUCCESS;
108}
109
110
111/**
112 * Lazily sync in the FPU/XMM state
113 *
114 * @returns VBox status code.
115 * @param pVM VM handle.
116 * @param pCtx CPU context
117 */
118CPUMR0DECL(int) CPUMR0LoadGuestFPU(PVM pVM, PCPUMCTX pCtx)
119{
120 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
121 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
122
123 /* If the FPU state has already been loaded, then it's a guest trap. */
124 if (pVM->cpum.s.fUseFlags & CPUM_USED_FPU)
125 {
126 Assert( ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
127 || ((pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)));
128 return VINF_EM_RAW_GUEST_TRAP;
129 }
130
131 /*
132 * There are two basic actions:
133 * 1. Save host fpu and restore guest fpu.
134 * 2. Generate guest trap.
135 *
136 * When entering the hypervisor we'll always enable MP (for proper wait
137 * trapping) and TS (for intercepting all fpu/mmx/sse stuff). The EM flag
138 * is taken from the guest OS in order to get proper SSE handling.
139 *
140 *
141 * Actions taken depending on the guest CR0 flags:
142 *
143 * 3 2 1
144 * TS | EM | MP | FPUInstr | WAIT :: VMM Action
145 * ------------------------------------------------------------------------
146 * 0 | 0 | 0 | Exec | Exec :: Clear TS & MP, Save HC, Load GC.
147 * 0 | 0 | 1 | Exec | Exec :: Clear TS, Save HC, Load GC.
148 * 0 | 1 | 0 | #NM | Exec :: Clear TS & MP, Save HC, Load GC.
149 * 0 | 1 | 1 | #NM | Exec :: Clear TS, Save HC, Load GC.
150 * 1 | 0 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already cleared.)
151 * 1 | 0 | 1 | #NM | #NM :: Go to guest taking trap there.
152 * 1 | 1 | 0 | #NM | Exec :: Clear MP, Save HC, Load GC. (EM is already set.)
153 * 1 | 1 | 1 | #NM | #NM :: Go to guest taking trap there.
154 */
155
156 switch (pCtx->cr0 & (X86_CR0_MP | X86_CR0_EM | X86_CR0_TS))
157 {
158 case X86_CR0_MP | X86_CR0_TS:
159 case X86_CR0_MP | X86_CR0_EM | X86_CR0_TS:
160 return VINF_EM_RAW_GUEST_TRAP;
161 default:
162 break;
163 }
164
165#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
166 uint64_t oldMsrEFERHost;
167 uint32_t oldCR0 = ASMGetCR0();
168
169 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
170 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
171 {
172 /** @todo Do we really need to read this every time?? The host could change this on the fly though.
173 * bird: what about starting by skipping the ASMWrMsr below if we didn't
174 * change anything? Ditto for the stuff in CPUMR0SaveGuestFPU. */
175 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
176 if (oldMsrEFERHost & MSR_K6_EFER_FFXSR)
177 {
178 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
179 pVM->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
180 }
181 }
182
183 /* If we sync the FPU/XMM state on-demand, then we can continue execution as if nothing has happened. */
184 int rc = CPUMHandleLazyFPU(pVM);
185 AssertRC(rc);
186 Assert(CPUMIsGuestFPUStateActive(pVM));
187
188 /* Restore EFER MSR */
189 if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
190 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost);
191
192 /* CPUMHandleLazyFPU could have changed CR0; restore it. */
193 ASMSetCR0(oldCR0);
194
195#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
196
197 /*
198 * Save the FPU control word and MXCSR, so we can restore the state properly afterwards.
199 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
200 */
201 pVM->cpum.s.Host.fpu.FCW = CPUMGetFCW();
202 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
203 pVM->cpum.s.Host.fpu.MXCSR = CPUMGetMXCSR();
204
205 CPUMLoadFPUAsm(pCtx);
206
207 /*
208 * The MSR_K6_EFER_FFXSR feature is AMD only so far, but check the cpuid just in case Intel adds it in the future.
209 *
210 * MSR_K6_EFER_FFXSR changes the behaviour of fxsave and fxrstore: the XMM state isn't saved/restored
211 */
212 if (pVM->cpum.s.CPUFeaturesExt.edx & X86_CPUID_AMD_FEATURE_EDX_FFXSR)
213 {
214 /** @todo Do we really need to read this every time?? The host could change this on the fly though. */
215 uint64_t msrEFERHost = ASMRdMsr(MSR_K6_EFER);
216
217 if (msrEFERHost & MSR_K6_EFER_FFXSR)
218 {
219 /* fxrstor doesn't restore the XMM state! */
220 CPUMLoadXMMAsm(pCtx);
221 pVM->cpum.s.fUseFlags |= CPUM_MANUAL_XMM_RESTORE;
222 }
223 }
224#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
225
226 pVM->cpum.s.fUseFlags |= CPUM_USED_FPU;
227 return VINF_SUCCESS;
228}
229
230
231/**
232 * Save guest FPU/XMM state
233 *
234 * @returns VBox status code.
235 * @param pVM VM handle.
236 * @param pCtx CPU context
237 */
238CPUMR0DECL(int) CPUMR0SaveGuestFPU(PVM pVM, PCPUMCTX pCtx)
239{
240 Assert(pVM->cpum.s.CPUFeatures.edx.u1FXSR);
241 Assert(ASMGetCR4() & X86_CR4_OSFSXR);
242 AssertReturn((pVM->cpum.s.fUseFlags & CPUM_USED_FPU), VINF_SUCCESS);
243
244#ifndef CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE
245 uint64_t oldMsrEFERHost;
246
247 /* Clear MSR_K6_EFER_FFXSR or else we'll be unable to save/restore the XMM state with fxsave/fxrstor. */
248 if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
249 {
250 oldMsrEFERHost = ASMRdMsr(MSR_K6_EFER);
251 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost & ~MSR_K6_EFER_FFXSR);
252 }
253 CPUMRestoreHostFPUState(pVM);
254
255 /* Restore EFER MSR */
256 if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
257 ASMWrMsr(MSR_K6_EFER, oldMsrEFERHost | MSR_K6_EFER_FFXSR);
258
259#else /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
260 CPUMSaveFPUAsm(pCtx);
261 if (pVM->cpum.s.fUseFlags & CPUM_MANUAL_XMM_RESTORE)
262 {
263 /* fxsave doesn't save the XMM state! */
264 CPUMSaveXMMAsm(pCtx);
265 }
266
267 /*
268 * Restore the original FPU control word and MXCSR.
269 * We don't want the guest to be able to trigger floating point/SSE exceptions on the host.
270 */
271 CPUMSetFCW(pVM->cpum.s.Host.fpu.FCW);
272 if (pVM->cpum.s.CPUFeatures.edx.u1SSE)
273 CPUMSetMXCSR(pVM->cpum.s.Host.fpu.MXCSR);
274#endif /* CPUM_CAN_HANDLE_NM_TRAPS_IN_KERNEL_MODE */
275
276 pVM->cpum.s.fUseFlags &= ~(CPUM_USED_FPU | CPUM_MANUAL_XMM_RESTORE);
277 return VINF_SUCCESS;
278}
279
280
281/**
282 * Save guest debug state
283 *
284 * @returns VBox status code.
285 * @param pVM VM handle.
286 * @param pCtx CPU context
287 * @param fDR6 Include DR6 or not
288 */
289CPUMR0DECL(int) CPUMR0SaveGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
290{
291 Assert(pVM->cpum.s.fUseFlags & CPUM_USE_DEBUG_REGS);
292
293 /* Save the guest's debug state. The caller is responsible for DR7. */
294 pCtx->dr[0] = ASMGetDR0();
295 pCtx->dr[1] = ASMGetDR1();
296 pCtx->dr[2] = ASMGetDR2();
297 pCtx->dr[3] = ASMGetDR3();
298 if (fDR6)
299 pCtx->dr[6] = ASMGetDR6();
300
301 /*
302 * Restore the host's debug state. DR0-3, DR6 and only then DR7!
303 * DR7 contains 0x400 right now.
304 */
305 ASMSetDR0(pVM->cpum.s.Host.dr0);
306 ASMSetDR1(pVM->cpum.s.Host.dr1);
307 ASMSetDR2(pVM->cpum.s.Host.dr2);
308 ASMSetDR3(pVM->cpum.s.Host.dr3);
309 ASMSetDR6(pVM->cpum.s.Host.dr6);
310 ASMSetDR7(pVM->cpum.s.Host.dr7);
311
312 pVM->cpum.s.fUseFlags &= ~CPUM_USE_DEBUG_REGS;
313 return VINF_SUCCESS;
314}
315
316
317/**
318 * Lazily sync in the debug state
319 *
320 * @returns VBox status code.
321 * @param pVM VM handle.
322 * @param pCtx CPU context
323 * @param fDR6 Include DR6 or not
324 */
325CPUMR0DECL(int) CPUMR0LoadGuestDebugState(PVM pVM, PCPUMCTX pCtx, bool fDR6)
326{
327 /* Save the host state. */
328 pVM->cpum.s.Host.dr0 = ASMGetDR0();
329 pVM->cpum.s.Host.dr1 = ASMGetDR1();
330 pVM->cpum.s.Host.dr2 = ASMGetDR2();
331 pVM->cpum.s.Host.dr3 = ASMGetDR3();
332 pVM->cpum.s.Host.dr6 = ASMGetDR6();
333 /** @todo dr7 might already have been changed to 0x400; don't care right now as it's harmless. */
334 pVM->cpum.s.Host.dr7 = ASMGetDR7();
335 /* Make sure DR7 is harmless or else we could trigger breakpoints when restoring dr0-3 (!) */
336 ASMSetDR7(X86_DR7_INIT_VAL);
337
338 /* Activate the guest state DR0-3; DR7 is left to the caller. */
339 ASMSetDR0(pCtx->dr[0]);
340 ASMSetDR1(pCtx->dr[1]);
341 ASMSetDR2(pCtx->dr[2]);
342 ASMSetDR3(pCtx->dr[3]);
343 if (fDR6)
344 ASMSetDR6(pCtx->dr[6]);
345
346 pVM->cpum.s.fUseFlags |= CPUM_USE_DEBUG_REGS;
347 return VINF_SUCCESS;
348}
349
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