Changeset 13020 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Oct 6, 2008 4:27:16 PM (16 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r13013 r13020 2579 2579 /* In X2APIC specification this range is reserved for APIC control. */ 2580 2580 if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END)) 2581 { 2582 rc = PDMApicRDMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val); 2583 } 2581 rc = PDMApicReadMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, &val); 2584 2582 else 2585 {2586 2583 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */ 2587 2584 val = 0; 2588 break; 2589 } 2585 break; 2590 2586 } 2591 2587 Log(("EMInterpretRdmsr %s (%x) -> val=%VX64\n", emMSRtoString(pRegFrame->ecx), pRegFrame->ecx, val)); … … 2728 2724 /* In X2APIC specification this range is reserved for APIC control. */ 2729 2725 if ((pRegFrame->ecx >= MSR_IA32_APIC_START) && (pRegFrame->ecx < MSR_IA32_APIC_END)) 2730 { 2731 return PDMApicWRMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val); 2732 } 2726 return PDMApicWriteMSR(pVM, VMMGetCpuId(pVM), pRegFrame->ecx, val); 2727 2733 2728 /* We should actually trigger a #GP here, but don't as that might cause more trouble. */ 2734 2729 break; -
trunk/src/VBox/VMM/VMMAll/PDMAll.cpp
r13013 r13020 254 254 255 255 /** 256 * W RMSR in APIC range.256 * Write MSR in APIC range. 257 257 * 258 258 * @returns VBox status code. … … 262 262 * @param u64Value Value to write. 263 263 */ 264 VMMDECL(int) PDMApicW RMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value)265 { 266 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) 267 { 268 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnW RMSR));269 pdmLock(pVM); 270 pVM->pdm.s.Apic.CTX_SUFF(pfnW RMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value);271 pdmUnlock(pVM); 272 return VINF_SUCCESS; 273 } 274 return VERR_PDM_NO_APIC_INSTANCE; 275 } 276 277 /** 278 * R DMSR in APIC range.264 VMMDECL(int) PDMApicWriteMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t u64Value) 265 { 266 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) 267 { 268 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)); 269 pdmLock(pVM); 270 pVM->pdm.s.Apic.CTX_SUFF(pfnWriteMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, u64Value); 271 pdmUnlock(pVM); 272 return VINF_SUCCESS; 273 } 274 return VERR_PDM_NO_APIC_INSTANCE; 275 } 276 277 /** 278 * Read MSR in APIC range. 279 279 * 280 280 * @returns VBox status code. … … 284 284 * @param pu64Value Value read. 285 285 */ 286 VMMDECL(int) PDMApicR DMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value)287 { 288 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) 289 { 290 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnR DMSR));291 pdmLock(pVM); 292 pVM->pdm.s.Apic.CTX_SUFF(pfnR DMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value);286 VMMDECL(int) PDMApicReadMSR(PVM pVM, VMCPUID iCpu, uint32_t u32Reg, uint64_t *pu64Value) 287 { 288 if (pVM->pdm.s.Apic.CTX_SUFF(pDevIns)) 289 { 290 Assert(pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)); 291 pdmLock(pVM); 292 pVM->pdm.s.Apic.CTX_SUFF(pfnReadMSR)(pVM->pdm.s.Apic.CTX_SUFF(pDevIns), iCpu, u32Reg, pu64Value); 293 293 pdmUnlock(pVM); 294 294 return VINF_SUCCESS;
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