Changeset 13839 in vbox for trunk/src/recompiler_new/target-i386/translate.c
- Timestamp:
- Nov 5, 2008 3:27:47 AM (16 years ago)
- File:
-
- 1 edited
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trunk/src/recompiler_new/target-i386/translate.c
r13672 r13839 519 519 } 520 520 #endif 521 521 522 522 static void gen_add_A0_im(DisasContext *s, int val) 523 523 { … … 624 624 { 625 625 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); 626 if (shift != 0) 626 if (shift != 0) 627 627 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); 628 628 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); … … 690 690 { 691 691 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUState, regs[reg])); 692 if (shift != 0) 692 if (shift != 0) 693 693 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift); 694 694 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0); … … 826 826 int skip_label; 827 827 TCGv t0; 828 828 829 829 skip_label = gen_new_label(); 830 830 /* t0 = tcg_temp_local_new(TCG_TYPE_TL); */ 831 t0 = cpu_tmp0; 831 t0 = cpu_tmp0; 832 832 833 833 tcg_gen_ld32u_tl(t0, cpu_env, offsetof(CPUState, interrupt_request)); 834 834 /* Keep in sync with helper_check_external_event() */ 835 tcg_gen_andi_tl(t0, t0, 835 tcg_gen_andi_tl(t0, t0, 836 836 CPU_INTERRUPT_EXTERNAL_EXIT 837 837 | CPU_INTERRUPT_EXTERNAL_TIMER … … 923 923 924 924 #ifndef VBOX 925 static inline void gen_op_movl_T0_Dshift(int ot) 925 static inline void gen_op_movl_T0_Dshift(int ot) 926 926 #else /* VBOX */ 927 DECLINLINE(void) gen_op_movl_T0_Dshift(int ot) 927 DECLINLINE(void) gen_op_movl_T0_Dshift(int ot) 928 928 #endif /* VBOX */ 929 929 { … … 1109 1109 #if TCG_TARGET_REG_BITS == 32 1110 1110 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); 1111 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1111 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1112 1112 (long)cc_table + offsetof(CCTable, compute_c)); 1113 1113 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); 1114 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1114 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1115 1115 1, &cpu_tmp2_i32, 0, NULL); 1116 1116 #else 1117 1117 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); 1118 1118 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); 1119 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1119 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1120 1120 (long)cc_table + offsetof(CCTable, compute_c)); 1121 1121 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); 1122 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1122 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1123 1123 1, &cpu_tmp2_i32, 0, NULL); 1124 1124 #endif … … 1131 1131 #if TCG_TARGET_REG_BITS == 32 1132 1132 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_cc_op, 3); 1133 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1133 tcg_gen_addi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 1134 1134 (long)cc_table + offsetof(CCTable, compute_all)); 1135 1135 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0); 1136 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1136 tcg_gen_call(&tcg_ctx, cpu_tmp2_i32, TCG_CALL_PURE, 1137 1137 1, &cpu_tmp2_i32, 0, NULL); 1138 1138 #else 1139 1139 tcg_gen_extu_i32_tl(cpu_tmp1_i64, cpu_cc_op); 1140 1140 tcg_gen_shli_i64(cpu_tmp1_i64, cpu_tmp1_i64, 4); 1141 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1141 tcg_gen_addi_i64(cpu_tmp1_i64, cpu_tmp1_i64, 1142 1142 (long)cc_table + offsetof(CCTable, compute_all)); 1143 1143 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_tmp1_i64, 0); 1144 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1144 tcg_gen_call(&tcg_ctx, cpu_tmp1_i64, TCG_CALL_PURE, 1145 1145 1, &cpu_tmp2_i32, 0, NULL); 1146 1146 #endif … … 1277 1277 case CC_OP_SUBL: 1278 1278 case CC_OP_SUBQ: 1279 1279 1280 1280 size = cc_op - CC_OP_SUBB; 1281 1281 switch(jcc_op) { … … 1308 1308 case 0: 1309 1309 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80); 1310 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1310 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1311 1311 0, l1); 1312 1312 break; 1313 1313 case 1: 1314 1314 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000); 1315 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1315 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1316 1316 0, l1); 1317 1317 break; … … 1319 1319 case 2: 1320 1320 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000); 1321 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1321 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0, 1322 1322 0, l1); 1323 1323 break; 1324 1324 #endif 1325 1325 default: 1326 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 1326 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst, 1327 1327 0, l1); 1328 1328 break; 1329 1329 } 1330 1330 break; 1331 1331 1332 1332 case JCC_B: 1333 1333 cond = inv ? TCG_COND_GEU : TCG_COND_LTU; … … 1361 1361 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); 1362 1362 break; 1363 1363 1364 1364 case JCC_L: 1365 1365 cond = inv ? TCG_COND_GE : TCG_COND_LT; … … 1393 1393 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1); 1394 1394 break; 1395 1395 1396 1396 default: 1397 1397 goto slow_jcc; 1398 1398 } 1399 1399 break; 1400 1400 1401 1401 /* some jumps are easy to compute */ 1402 1402 case CC_OP_ADDB: … … 1404 1404 case CC_OP_ADDL: 1405 1405 case CC_OP_ADDQ: 1406 1406 1407 1407 case CC_OP_ADCB: 1408 1408 case CC_OP_ADCW: 1409 1409 case CC_OP_ADCL: 1410 1410 case CC_OP_ADCQ: 1411 1411 1412 1412 case CC_OP_SBBB: 1413 1413 case CC_OP_SBBW: 1414 1414 case CC_OP_SBBL: 1415 1415 case CC_OP_SBBQ: 1416 1416 1417 1417 case CC_OP_LOGICB: 1418 1418 case CC_OP_LOGICW: 1419 1419 case CC_OP_LOGICL: 1420 1420 case CC_OP_LOGICQ: 1421 1421 1422 1422 case CC_OP_INCB: 1423 1423 case CC_OP_INCW: 1424 1424 case CC_OP_INCL: 1425 1425 case CC_OP_INCQ: 1426 1426 1427 1427 case CC_OP_DECB: 1428 1428 case CC_OP_DECW: 1429 1429 case CC_OP_DECL: 1430 1430 case CC_OP_DECQ: 1431 1431 1432 1432 case CC_OP_SHLB: 1433 1433 case CC_OP_SHLW: 1434 1434 case CC_OP_SHLL: 1435 1435 case CC_OP_SHLQ: 1436 1436 1437 1437 case CC_OP_SARB: 1438 1438 case CC_OP_SARW: … … 1453 1453 slow_jcc: 1454 1454 gen_setcc_slow_T0(s, jcc_op); 1455 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 1455 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, 1456 1456 cpu_T[0], 0, l1); 1457 1457 break; … … 1802 1802 } 1803 1803 1804 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, 1804 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1, 1805 1805 int is_right, int is_arith) 1806 1806 { … … 1844 1844 else 1845 1845 gen_op_mov_reg_T0(ot, op1); 1846 1846 1847 1847 /* update eflags if non zero shift */ 1848 1848 if (s->cc_op != CC_OP_DYNAMIC) … … 1865 1865 else 1866 1866 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot); 1867 1867 1868 1868 gen_set_label(shift_label); 1869 1869 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 1877 1877 { 1878 1878 int mask; 1879 1879 1880 1880 if (ot == OT_QUAD) 1881 1881 mask = 0x3f; … … 1912 1912 else 1913 1913 gen_op_mov_reg_T0(ot, op1); 1914 1914 1915 1915 /* update eflags if non zero shift */ 1916 1916 if (op2 != 0) { … … 1937 1937 1938 1938 /* XXX: add faster immediate case */ 1939 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, 1939 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1, 1940 1940 int is_right) 1941 1941 { … … 1971 1971 label1 = gen_new_label(); 1972 1972 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1); 1973 1973 1974 1974 if (ot <= OT_WORD) 1975 1975 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1); 1976 1976 else 1977 1977 tcg_gen_mov_tl(cpu_tmp0, t1); 1978 1978 1979 1979 gen_extu(ot, t0); 1980 1980 tcg_gen_mov_tl(t2, t0); … … 2001 2001 gen_op_mov_reg_v(ot, op1, t0); 2002 2002 } 2003 2003 2004 2004 /* update eflags */ 2005 2005 if (s->cc_op != CC_OP_DYNAMIC) … … 2020 2020 tcg_gen_andi_tl(t0, t0, CC_C); 2021 2021 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0); 2022 2022 2023 2023 tcg_gen_discard_tl(cpu_cc_dst); 2024 2024 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); 2025 2025 2026 2026 gen_set_label(label2); 2027 2027 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 2045 2045 2046 2046 /* XXX: add faster immediate = 1 case */ 2047 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, 2047 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1, 2048 2048 int is_right) 2049 2049 { … … 2058 2058 else 2059 2059 gen_op_mov_TN_reg(ot, 0, op1); 2060 2060 2061 2061 tcg_gen_helper_1_2(helper_rotc[ot + (is_right * 4)], 2062 2062 cpu_T[0], cpu_T[0], cpu_T[1]); … … 2074 2074 tcg_gen_discard_tl(cpu_cc_dst); 2075 2075 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS); 2076 2076 2077 2077 gen_set_label(label1); 2078 2078 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */ … … 2080 2080 2081 2081 /* XXX: add faster immediate case */ 2082 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, 2082 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1, 2083 2083 int is_right) 2084 2084 { … … 2114 2114 label1 = gen_new_label(); 2115 2115 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1); 2116 2116 2117 2117 tcg_gen_addi_tl(cpu_tmp5, t2, -1); 2118 2118 if (ot == OT_WORD) { … … 2125 2125 2126 2126 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5); 2127 2127 2128 2128 /* only needed if count > 16, but a test would complicate */ 2129 2129 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(32), t2); … … 2139 2139 tcg_gen_or_tl(t1, t1, t0); 2140 2140 tcg_gen_ext32u_tl(t1, t1); 2141 2141 2142 2142 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); 2143 2143 tcg_gen_sub_tl(cpu_tmp0, tcg_const_tl(32), cpu_tmp5); … … 2162 2162 tcg_gen_shl_tl(t1, t1, cpu_tmp5); 2163 2163 tcg_gen_or_tl(t0, t0, t1); 2164 2164 2165 2165 } else { 2166 2166 if (ot == OT_LONG) … … 2168 2168 2169 2169 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5); 2170 2170 2171 2171 tcg_gen_shl_tl(t0, t0, t2); 2172 2172 tcg_gen_sub_tl(cpu_tmp5, tcg_const_tl(data_bits), t2); … … 2184 2184 gen_op_mov_reg_v(ot, op1, t0); 2185 2185 } 2186 2186 2187 2187 /* update eflags */ 2188 2188 if (s->cc_op != CC_OP_DYNAMIC) … … 2632 2632 l1 = gen_new_label(); 2633 2633 gen_jcc1(s, cc_op, b, l1); 2634 2634 2635 2635 gen_goto_tb(s, 0, next_eip); 2636 2636 … … 2689 2689 #endif /* VBOX */ 2690 2690 { 2691 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 2691 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 2692 2692 offsetof(CPUX86State,segs[seg_reg].selector)); 2693 2693 } … … 2700 2700 { 2701 2701 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff); 2702 tcg_gen_st32_tl(cpu_T[0], cpu_env, 2702 tcg_gen_st32_tl(cpu_T[0], cpu_env, 2703 2703 offsetof(CPUX86State,segs[seg_reg].selector)); 2704 2704 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4); 2705 tcg_gen_st_tl(cpu_T[0], cpu_env, 2705 tcg_gen_st_tl(cpu_T[0], cpu_env, 2706 2706 offsetof(CPUX86State,segs[seg_reg].base)); 2707 2707 #ifdef VBOX … … 2761 2761 gen_op_set_cc_op(s->cc_op); 2762 2762 gen_jmp_im(pc_start - s->cs_base); 2763 tcg_gen_helper_0_2(helper_svm_check_intercept_param, 2763 tcg_gen_helper_0_2(helper_svm_check_intercept_param, 2764 2764 tcg_const_i32(type), tcg_const_i64(param)); 2765 2765 } … … 3031 3031 gen_op_set_cc_op(s->cc_op); 3032 3032 gen_jmp_im(cur_eip); 3033 tcg_gen_helper_0_2(helper_raise_interrupt, 3034 tcg_const_i32(intno), 3033 tcg_gen_helper_0_2(helper_raise_interrupt, 3034 tcg_const_i32(intno), 3035 3035 tcg_const_i32(next_eip - cur_eip)); 3036 3036 s->is_jmp = 3; … … 3558 3558 { 3559 3559 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); 3560 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3560 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3561 3561 offsetof(CPUX86State,fpregs[reg].mmx)); 3562 3562 tcg_gen_helper_0_2(helper_movl_mm_T0_mmx, cpu_ptr0, cpu_T[0]); … … 3567 3567 if (s->dflag == 2) { 3568 3568 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); 3569 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3569 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3570 3570 offsetof(CPUX86State,xmm_regs[reg])); 3571 3571 tcg_gen_helper_0_2(helper_movq_mm_T0_xmm, cpu_ptr0, cpu_T[0]); … … 3574 3574 { 3575 3575 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); 3576 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3576 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3577 3577 offsetof(CPUX86State,xmm_regs[reg])); 3578 3578 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); … … 3706 3706 #ifdef TARGET_X86_64 3707 3707 if (s->dflag == 2) { 3708 tcg_gen_ld_i64(cpu_T[0], cpu_env, 3708 tcg_gen_ld_i64(cpu_T[0], cpu_env, 3709 3709 offsetof(CPUX86State,fpregs[reg].mmx)); 3710 3710 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); … … 3712 3712 #endif 3713 3713 { 3714 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 3714 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 3715 3715 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); 3716 3716 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); … … 3720 3720 #ifdef TARGET_X86_64 3721 3721 if (s->dflag == 2) { 3722 tcg_gen_ld_i64(cpu_T[0], cpu_env, 3722 tcg_gen_ld_i64(cpu_T[0], cpu_env, 3723 3723 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); 3724 3724 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); … … 3726 3726 #endif 3727 3727 { 3728 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 3728 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 3729 3729 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); 3730 3730 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); … … 3842 3842 case 0x050: /* movmskps */ 3843 3843 rm = (modrm & 7) | REX_B(s); 3844 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3844 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3845 3845 offsetof(CPUX86State,xmm_regs[rm])); 3846 3846 tcg_gen_helper_1_1(helper_movmskps, cpu_tmp2_i32, cpu_ptr0); … … 3850 3850 case 0x150: /* movmskpd */ 3851 3851 rm = (modrm & 7) | REX_B(s); 3852 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3852 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 3853 3853 offsetof(CPUX86State,xmm_regs[rm])); 3854 3854 tcg_gen_helper_1_1(helper_movmskpd, cpu_tmp2_i32, cpu_ptr0); … … 4541 4541 /* illegal sequence. The s->pc is past the lock prefix and that 4542 4542 is sufficient for the TB, I think. */ 4543 Log(("illegal lock sequence % VGv (b=%#x)\n", pc_start, b));4543 Log(("illegal lock sequence %RGv (b=%#x)\n", pc_start, b)); 4544 4544 return true; 4545 4545 } … … 5136 5136 tcg_gen_helper_0_4(helper_lcall_protected, 5137 5137 cpu_tmp2_i32, cpu_T[1], 5138 tcg_const_i32(dflag), 5138 tcg_const_i32(dflag), 5139 5139 tcg_const_i32(s->pc - pc_start)); 5140 5140 } else { … … 5142 5142 tcg_gen_helper_0_4(helper_lcall_real, 5143 5143 cpu_tmp2_i32, cpu_T[1], 5144 tcg_const_i32(dflag), 5144 tcg_const_i32(dflag), 5145 5145 tcg_const_i32(s->pc - s->cs_base)); 5146 5146 } … … 5411 5411 tcg_gen_helper_0_1(helper_cmpxchg16b, cpu_A0); 5412 5412 } else 5413 #endif 5413 #endif 5414 5414 { 5415 5415 if (!(s->cpuid_features & CPUID_CX8)) … … 5990 5990 break; 5991 5991 case 2: 5992 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 5992 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 5993 5993 (s->mem_index >> 2) - 1); 5994 5994 tcg_gen_helper_0_1(helper_fldl_FT0, cpu_tmp1_i64); … … 6029 6029 break; 6030 6030 case 2: 6031 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 6031 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 6032 6032 (s->mem_index >> 2) - 1); 6033 6033 tcg_gen_helper_0_1(helper_fldl_ST0, cpu_tmp1_i64); … … 6051 6051 case 2: 6052 6052 tcg_gen_helper_1_0(helper_fisttll_ST0, cpu_tmp1_i64); 6053 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6053 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6054 6054 (s->mem_index >> 2) - 1); 6055 6055 break; … … 6077 6077 case 2: 6078 6078 tcg_gen_helper_1_0(helper_fstl_ST0, cpu_tmp1_i64); 6079 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6079 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6080 6080 (s->mem_index >> 2) - 1); 6081 6081 break; … … 6096 6096 gen_op_set_cc_op(s->cc_op); 6097 6097 gen_jmp_im(pc_start - s->cs_base); 6098 tcg_gen_helper_0_2(helper_fldenv, 6098 tcg_gen_helper_0_2(helper_fldenv, 6099 6099 cpu_A0, tcg_const_i32(s->dflag)); 6100 6100 break; … … 6162 6162 break; 6163 6163 case 0x3d: /* fildll */ 6164 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 6164 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, 6165 6165 (s->mem_index >> 2) - 1); 6166 6166 tcg_gen_helper_0_1(helper_fildll_ST0, cpu_tmp1_i64); … … 6168 6168 case 0x3f: /* fistpll */ 6169 6169 tcg_gen_helper_1_0(helper_fistll_ST0, cpu_tmp1_i64); 6170 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6170 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, 6171 6171 (s->mem_index >> 2) - 1); 6172 6172 tcg_gen_helper_0_0(helper_fpop); … … 6556 6556 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX); 6557 6557 gen_op_andl_T0_ffff(); 6558 gen_check_io(s, ot, pc_start - s->cs_base, 6558 gen_check_io(s, ot, pc_start - s->cs_base, 6559 6559 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4); 6560 6560 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { … … 6712 6712 gen_jmp_im(pc_start - s->cs_base); 6713 6713 tcg_gen_helper_0_2(helper_lret_protected, 6714 tcg_const_i32(s->dflag), 6714 tcg_const_i32(s->dflag), 6715 6715 tcg_const_i32(val)); 6716 6716 } else { … … 6757 6757 gen_jmp_im(pc_start - s->cs_base); 6758 6758 tcg_gen_helper_0_2(helper_iret_protected, 6759 tcg_const_i32(s->dflag), 6759 tcg_const_i32(s->dflag), 6760 6760 tcg_const_i32(s->pc - s->cs_base)); 6761 6761 s->cc_op = CC_OP_EFLAGS; … … 7315 7315 TCGv tmp0; 7316 7316 gen_op_mov_TN_reg(OT_LONG, 0, reg); 7317 7317 7318 7318 tmp0 = tcg_temp_new(TCG_TYPE_I32); 7319 7319 tcg_gen_trunc_i64_i32(tmp0, cpu_T[0]); … … 7662 7662 break; 7663 7663 } else { 7664 tcg_gen_helper_0_2(helper_vmrun, 7664 tcg_gen_helper_0_2(helper_vmrun, 7665 7665 tcg_const_i32(s->aflag), 7666 7666 tcg_const_i32(s->pc - pc_start)); … … 7698 7698 case 4: /* STGI */ 7699 7699 if ((!(s->flags & HF_SVME_MASK) && 7700 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || 7700 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || 7701 7701 !s->pe) 7702 7702 goto illegal_op; … … 7719 7719 break; 7720 7720 case 6: /* SKINIT */ 7721 if ((!(s->flags & HF_SVME_MASK) && 7722 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || 7721 if ((!(s->flags & HF_SVME_MASK) && 7722 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) || 7723 7723 !s->pe) 7724 7724 goto illegal_op; … … 7966 7966 if (b & 2) { 7967 7967 gen_op_mov_TN_reg(ot, 0, rm); 7968 tcg_gen_helper_0_2(helper_write_crN, 7968 tcg_gen_helper_0_2(helper_write_crN, 7969 7969 tcg_const_i32(reg), cpu_T[0]); 7970 7970 gen_jmp_im(s->pc - s->cs_base); 7971 7971 gen_eob(s); 7972 7972 } else { 7973 tcg_gen_helper_1_1(helper_read_crN, 7973 tcg_gen_helper_1_1(helper_read_crN, 7974 7974 cpu_T[0], tcg_const_i32(reg)); 7975 7975 gen_op_mov_reg_T0(ot, rm); … … 8053 8053 gen_op_set_cc_op(s->cc_op); 8054 8054 gen_jmp_im(pc_start - s->cs_base); 8055 tcg_gen_helper_0_2(helper_fxsave, 8055 tcg_gen_helper_0_2(helper_fxsave, 8056 8056 cpu_A0, tcg_const_i32((s->dflag == 2))); 8057 8057 break;
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