VirtualBox

Changeset 16376 in vbox


Ignore:
Timestamp:
Jan 29, 2009 4:46:31 PM (16 years ago)
Author:
vboxsync
Message:

Paging updates. Deal with mode switches and cr3 updates.

Location:
trunk/src/VBox/VMM
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/PGM.cpp

    r16317 r16376  
    685685#define PGM_BTH_NAME_R0_STR(name)   PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
    686686#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_32BIT_PT_FOR_PHYS
     687#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_32BIT_PD_PHYS_REAL
    687688#include "PGMBth.h"
    688689#include "PGMGst.h"
    689690#undef BTH_PGMPOOLKIND_PT_FOR_PT
     691#undef BTH_PGMPOOLKIND_ROOT
    690692#undef PGM_BTH_NAME
    691693#undef PGM_BTH_NAME_RC_STR
    … …  
    705707#define PGM_BTH_NAME_R0_STR(name)   PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
    706708#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_32BIT_PT_FOR_PHYS
     709#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_32BIT_PD_PHYS_PROT
    707710#include "PGMBth.h"
    708711#include "PGMGst.h"
    709712#undef BTH_PGMPOOLKIND_PT_FOR_PT
     713#undef BTH_PGMPOOLKIND_ROOT
    710714#undef PGM_BTH_NAME
    711715#undef PGM_BTH_NAME_RC_STR
    … …  
    726730#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
    727731#define BTH_PGMPOOLKIND_PT_FOR_BIG  PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
     732#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_32BIT_PD
    728733#include "PGMBth.h"
    729734#include "PGMGst.h"
    730735#undef BTH_PGMPOOLKIND_PT_FOR_BIG
    731736#undef BTH_PGMPOOLKIND_PT_FOR_PT
     737#undef BTH_PGMPOOLKIND_ROOT
    732738#undef PGM_BTH_NAME
    733739#undef PGM_BTH_NAME_RC_STR
    … …  
    763769#define PGM_BTH_NAME_R0_STR(name)   PGM_BTH_NAME_R0_PAE_REAL_STR(name)
    764770#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_PAE_PT_FOR_PHYS
     771#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_PAE_PDPT_PHYS_REAL
    765772#include "PGMBth.h"
    766773#undef BTH_PGMPOOLKIND_PT_FOR_PT
     774#undef BTH_PGMPOOLKIND_ROOT
    767775#undef PGM_BTH_NAME
    768776#undef PGM_BTH_NAME_RC_STR
    … …  
    782790#define PGM_BTH_NAME_R0_STR(name)   PGM_BTH_NAME_R0_PAE_PROT_STR(name)
    783791#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_PAE_PT_FOR_PHYS
     792#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_PAE_PDPT_PHYS_PROT
    784793#include "PGMBth.h"
    785794#undef BTH_PGMPOOLKIND_PT_FOR_PT
     795#undef BTH_PGMPOOLKIND_ROOT
    786796#undef PGM_BTH_NAME
    787797#undef PGM_BTH_NAME_RC_STR
    … …  
    802812#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
    803813#define BTH_PGMPOOLKIND_PT_FOR_BIG  PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
     814#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_PAE_PDPT_FOR_32BIT
    804815#include "PGMBth.h"
    805816#undef BTH_PGMPOOLKIND_PT_FOR_BIG
    806817#undef BTH_PGMPOOLKIND_PT_FOR_PT
     818#undef BTH_PGMPOOLKIND_ROOT
    807819#undef PGM_BTH_NAME
    808820#undef PGM_BTH_NAME_RC_STR
    … …  
    823835#define BTH_PGMPOOLKIND_PT_FOR_PT   PGMPOOLKIND_PAE_PT_FOR_PAE_PT
    824836#define BTH_PGMPOOLKIND_PT_FOR_BIG  PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
     837#define BTH_PGMPOOLKIND_ROOT        PGMPOOLKIND_PAE_PDPT
    825838#include "PGMBth.h"
    826839#include "PGMGst.h"
    827840#undef BTH_PGMPOOLKIND_PT_FOR_BIG
    828841#undef BTH_PGMPOOLKIND_PT_FOR_PT
     842#undef BTH_PGMPOOLKIND_ROOT
    829843#undef PGM_BTH_NAME
    830844#undef PGM_BTH_NAME_RC_STR
    … …  
    861875# define BTH_PGMPOOLKIND_PT_FOR_PT  PGMPOOLKIND_PAE_PT_FOR_PAE_PT
    862876# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
     877# define BTH_PGMPOOLKIND_ROOT       PGMPOOLKIND_64BIT_PML4
    863878# include "PGMBth.h"
    864879# include "PGMGst.h"
    865880# undef BTH_PGMPOOLKIND_PT_FOR_BIG
    866881# undef BTH_PGMPOOLKIND_PT_FOR_PT
     882# undef BTH_PGMPOOLKIND_ROOT
    867883# undef PGM_BTH_NAME
    868884# undef PGM_BTH_NAME_RC_STR

  • trunk/src/VBox/VMM/PGMBth.h

    r16317 r16376  
    130130PGM_BTH_DECL(int, Enter)(PVM pVM, RTGCPHYS GCPhysCR3)
    131131{
     132#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     133    /* Here we deal with allocation of the root shadow page table for real and protected mode during mode switches;
     134     * Other modes rely on MapCR3/UnmapCR3 to setup the shadow root page tables.
     135     */
     136# if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BITS \
     137           || PGM_SHW_TYPE == PGM_TYPE_PAE    \
     138           || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
     139       && (   PGM_GST_TYPE == PGM_TYPE_REAL   \
     140           && PGM_GST_TYPE == PGM_TYPE_PROT))
     141
     142    Assert(!HWACCMIsNestedPagingActive(pVM));
     143    /* We only need shadow paging in real and protected mode for VT-x and AMD-V (excluding nested paging/EPT modes) */
     144    if (HWACCMR3IsActive(pVM))
     145    {
     146        /* Free the previous root mapping if still active. */
     147        PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
     148        if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
     149        {
     150            /* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
     151            /** @todo Coordinate this better with the pool. */
     152            if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
     153                pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUser, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUserTable);
     154            pVM->pgm.s.pShwPageCR3R3 = 0;
     155            pVM->pgm.s.pShwPageCR3R0 = 0;
     156            pVM->pgm.s.pShwRootR3    = 0;
     157#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     158            pVM->pgm.s.pShwRootR0    = 0;
     159#  endif
     160            pVM->pgm.s.HCPhysShwCR3  = 0;
     161        }
     162
     163        /* contruct a fake address */
     164#  if PGM_GST_TYPE == PGM_TYPE_REAL
     165        RTGCPHYS GCPhysCR3 = RT_BIT_64(63);
     166#  else
     167        RTGCPHYS GCPhysCR3 = RT_BIT_64(63) | RT_BIT_64(62);
     168#  endif
     169        int rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     170        if (rc == VERR_PGM_POOL_FLUSHED)
     171        {
     172            Log(("Bth-Enter: PGM pool flushed -> signal sync cr3\n"));
     173            Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
     174            return VINF_PGM_SYNC_CR3;
     175        }
     176        AssertRCReturn(rc, rc);
     177#  ifdef IN_RING0
     178        pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     179#  else
     180        pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     181#  endif
     182        pVM->pgm.s.pShwRootR3    = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
     183        Assert(pVM->pgm.s.pShwRootR3);
     184#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
     185        pVM->pgm.s.pShwRootR0    = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     186#  endif
     187        pVM->pgm.s.HCPhysShwCR3  = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
     188    }
     189# endif
     190#else
    132191    /* nothing special to do here - InitData does the job. */
     192#endif
    133193    return VINF_SUCCESS;
    134194}

  • trunk/src/VBox/VMM/PGMInternal.h

    r16321 r16376  
    16231623    uint16_t            iAgePrev;
    16241624#endif /* PGMPOOL_WITH_CACHE */
     1625    /* The shadow page pool index of the user table as specified during allocation; useful for freeing root pages */
     1626    uint16_t            iUser;
     1627    /* The index into the user table (shadowed) as specified during allocation; useful for freeing root pages. */
     1628    uint32_t            iUserTable;
    16251629    /** Used to indicate that the page is zeroed. */
    16261630    bool                fZeroed;

  • trunk/src/VBox/VMM/PGMShw.h

    r16172 r16376  
    3737#undef SHW_PT_SHIFT
    3838#undef SHW_PT_MASK
     39#undef SHW_TOTAL_PD_ENTRIES
     40#undef SHW_PDPT_SHIFT
     41#undef SHW_PDPT_MASK
     42#undef SHW_PDPE_PG_MASK
    3943#undef SHW_POOL_ROOT_IDX
    4044
    … …  
    5155# define SHW_PD_SHIFT           X86_PD_SHIFT
    5256# define SHW_PD_MASK            X86_PD_MASK
     57# define SHW_TOTAL_PD_ENTRIES   X86_PG_ENTRIES
    5358# define SHW_PTE_PG_MASK        X86_PTE_PG_MASK
    5459# define SHW_PT_SHIFT           X86_PT_SHIFT
    5560# define SHW_PT_MASK            X86_PT_MASK
    5661# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PD
     62
     63#elif PGM_SHW_TYPE == PGM_TYPE_EPT
     64# define SHWPT                  EPTPT
     65# define PSHWPT                 PEPTPT
     66# define SHWPTE                 EPTPTE
     67# define PSHWPTE                PEPTPTE
     68# define SHWPD                  EPTPD
     69# define PSHWPD                 PEPTPD
     70# define SHWPDE                 EPTPDE
     71# define PSHWPDE                PEPTPDE
     72# define SHW_PDE_PG_MASK        EPT_PDE_PG_MASK
     73# define SHW_PD_SHIFT           EPT_PD_SHIFT
     74# define SHW_PD_MASK            EPT_PD_MASK
     75# define SHW_PTE_PG_MASK        EPT_PTE_PG_MASK
     76# define SHW_PT_SHIFT           EPT_PT_SHIFT
     77# define SHW_PT_MASK            EPT_PT_MASK
     78# define SHW_PDPT_SHIFT         EPT_PDPT_SHIFT
     79# define SHW_PDPT_MASK          EPT_PDPT_MASK
     80# define SHW_PDPE_PG_MASK       EPT_PDPE_PG_MASK
     81# define SHW_TOTAL_PD_ENTRIES   (EPT_PG_AMD64_ENTRIES*EPT_PG_AMD64_PDPE_ENTRIES)
     82# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_NESTED_ROOT      /* do not use! exception is real mode & protected mode without paging. */
     83
    5784#else
    5885# define SHWPT                  X86PTPAE
    … …  
    7097# define SHW_PT_SHIFT           X86_PT_PAE_SHIFT
    7198# define SHW_PT_MASK            X86_PT_PAE_MASK
    72 # define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD
     99
     100# if PGM_SHW_TYPE == PGM_TYPE_AMD64
     101#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
     102#  define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
     103#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
     104#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
     105#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_AMD64_CR3
     106
     107# else /* 32 bits PAE mode */
     108#  define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
     109#  define SHW_PDPT_MASK         X86_PDPT_MASK_PAE
     110#  define SHW_PDPE_PG_MASK      X86_PDPE_PG_MASK
     111#  define SHW_TOTAL_PD_ENTRIES  (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
     112#  ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
     113#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PDPT
     114#  else
     115#  define SHW_POOL_ROOT_IDX     PGMPOOL_IDX_PAE_PD
     116#  endif
     117
     118# endif
    73119#endif
    74120

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r16321 r16376  
    45564556
    45574557#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    4558     /* Update shadow paging info. */
    4559 # if    PGM_SHW_TYPE == PGM_TYPE_32BITS \
    4560      || PGM_SHW_TYPE == PGM_TYPE_PAE    \
    4561      || PGM_SHW_TYPE == PGM_TYPE_AMD64
    4562 
    4563     if (!HWACCMIsNestedPagingActive(pVM))
    4564     {
    4565         /* Apply all hypervisor mappings to the new CR3. */
    4566         PGMMapActivateAll(pVM);
    4567 
    4568         /*
    4569          * Update the shadow root page as well since that's not fixed.
    4570          */
    4571         PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
    4572         if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
    4573         {
    4574             /* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
    4575             /** @todo Coordinate this better with the pool. */
    4576             if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
    4577                 pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), SHW_POOL_ROOT_IDX, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
    4578             pVM->pgm.s.pShwPageCR3R3 = 0;
    4579             pVM->pgm.s.pShwPageCR3R0 = 0;
    4580             pVM->pgm.s.pShwRootR3    = 0;
     4558    /* Update shadow paging info for guest modes with paging (32, pae, 64). */
     4559# if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BITS \
     4560           || PGM_SHW_TYPE == PGM_TYPE_PAE    \
     4561           || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
     4562       && (   PGM_GST_TYPE != PGM_TYPE_REAL   \
     4563           && PGM_GST_TYPE != PGM_TYPE_PROT))
     4564
     4565    Assert(!HWACCMIsNestedPagingActive(pVM));
     4566
     4567    /* Apply all hypervisor mappings to the new CR3. */
     4568    PGMMapActivateAll(pVM);
     4569
     4570    /*
     4571     * Update the shadow root page as well since that's not fixed.
     4572     */
     4573    PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
     4574    if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
     4575    {
     4576        /* It might have been freed already by a pool flush (see e.g. PGMR3MappingsUnfix). */
     4577        /** @todo Coordinate this better with the pool. */
     4578        if (pVM->pgm.s.CTX_SUFF(pShwPageCR3)->enmKind != PGMPOOLKIND_FREE)
     4579            pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUser, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUserTable);
     4580        pVM->pgm.s.pShwPageCR3R3 = 0;
     4581        pVM->pgm.s.pShwPageCR3R0 = 0;
     4582        pVM->pgm.s.pShwRootR3    = 0;
    45814583#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    4582             pVM->pgm.s.pShwRootR0    = 0;
    4583 #  endif
    4584             pVM->pgm.s.HCPhysShwCR3  = 0;
    4585         }
    4586 
    4587         Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
    4588         rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
    4589         if (rc == VERR_PGM_POOL_FLUSHED)
    4590         {
    4591             Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
    4592             Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
    4593             return VINF_PGM_SYNC_CR3;
    4594         }
    4595         AssertRCReturn(rc, rc);
     4584        pVM->pgm.s.pShwRootR0    = 0;
     4585#  endif
     4586        pVM->pgm.s.HCPhysShwCR3  = 0;
     4587    }
     4588
     4589    Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
     4590    rc = pgmPoolAlloc(pVM, GCPhysCR3, BTH_PGMPOOLKIND_ROOT, SHW_POOL_ROOT_IDX, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     4591    if (rc == VERR_PGM_POOL_FLUSHED)
     4592    {
     4593        Log(("MapCR3: PGM pool flushed -> signal sync cr3\n"));
     4594        Assert(VM_FF_ISSET(pVM, VM_FF_PGM_SYNC_CR3));
     4595        return VINF_PGM_SYNC_CR3;
     4596    }
     4597    AssertRCReturn(rc, rc);
    45964598#  ifdef IN_RING0
    4597         pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     4599    pVM->pgm.s.pShwPageCR3R3 = MMHyperCCToR3(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
    45984600#  else
    4599         pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
    4600 #  endif
    4601         pVM->pgm.s.pShwRootR3    = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
    4602         Assert(pVM->pgm.s.pShwRootR3);
     4601    pVM->pgm.s.pShwPageCR3R0 = MMHyperCCToR0(pVM, pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     4602#  endif
     4603    pVM->pgm.s.pShwRootR3    = (R3PTRTYPE(void *))pVM->pgm.s.CTX_SUFF(pShwPageCR3)->pvPageR3;
     4604    Assert(pVM->pgm.s.pShwRootR3);
    46034605#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    4604         pVM->pgm.s.pShwRootR0    = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
    4605 #  endif
    4606         pVM->pgm.s.HCPhysShwCR3  = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
    4607         rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
    4608     }
     4606    pVM->pgm.s.pShwRootR0    = (R0PTRTYPE(void *))PGMPOOL_PAGE_2_PTR(pPool->CTX_SUFF(pVM), pVM->pgm.s.CTX_SUFF(pShwPageCR3));
     4607#  endif
     4608    pVM->pgm.s.HCPhysShwCR3  = pVM->pgm.s.CTX_SUFF(pShwPageCR3)->Core.Key;
     4609    rc = VINF_SUCCESS; /* clear it - pgmPoolAlloc returns hints. */
    46094610# endif
    46104611#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
    … …  
    46784679#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    46794680    /* Update shadow paging info. */
    4680 # if    PGM_SHW_TYPE == PGM_TYPE_32BITS \
    4681      || PGM_SHW_TYPE == PGM_TYPE_PAE    \
    4682      || PGM_SHW_TYPE == PGM_TYPE_AMD64
    4683 
    4684     if (!HWACCMIsNestedPagingActive(pVM))
    4685     {
    4686         /* @todo: dangerous as it's the current CR3! */
    4687         /* Remove the hypervisor mappings from the shadow page table. */
    4688         PGMMapDeactivateAll(pVM);
    4689 
    4690         pVM->pgm.s.pShwRootR3 = 0;
     4681# if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BITS \
     4682           || PGM_SHW_TYPE == PGM_TYPE_PAE    \
     4683           || PGM_SHW_TYPE == PGM_TYPE_AMD64) \
     4684       && (   PGM_GST_TYPE != PGM_TYPE_REAL   \
     4685           && PGM_GST_TYPE != PGM_TYPE_PROT))
     4686
     4687    Assert(!HWACCMIsNestedPagingActive(pVM));
     4688
     4689    /* @todo: dangerous as it's the current CR3! */
     4690    /* Remove the hypervisor mappings from the shadow page table. */
     4691    PGMMapDeactivateAll(pVM);
     4692
     4693    pVM->pgm.s.pShwRootR3 = 0;
    46914694#  ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
    4692         pVM->pgm.s.pShwRootR0 = 0;
    4693 #  endif
    4694         pVM->pgm.s.HCPhysShwCR3 = 0;
    4695         if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
    4696         {
    4697             PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
    4698             pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), SHW_POOL_ROOT_IDX, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->GCPhys >> PAGE_SHIFT);
    4699             pVM->pgm.s.pShwPageCR3R3 = 0;
    4700             pVM->pgm.s.pShwPageCR3R0 = 0;
    4701         }
     4695    pVM->pgm.s.pShwRootR0 = 0;
     4696#  endif
     4697    pVM->pgm.s.HCPhysShwCR3 = 0;
     4698    if (pVM->pgm.s.CTX_SUFF(pShwPageCR3))
     4699    {
     4700        PPGMPOOL pPool = pVM->pgm.s.CTX_SUFF(pPool);
     4701        pgmPoolFreeByPage(pPool, pVM->pgm.s.CTX_SUFF(pShwPageCR3), pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUser, pVM->pgm.s.CTX_SUFF(pShwPageCR3)->iUserTable);
     4702        pVM->pgm.s.pShwPageCR3R3 = 0;
     4703        pVM->pgm.s.pShwPageCR3R0 = 0;
    47024704    }
    47034705# endif

  • trunk/src/VBox/VMM/VMMAll/PGMAllMap.cpp

    r16321 r16376  
    374374        return VINF_SUCCESS;
    375375
     376    Assert(PGMGetGuestMode(pVM) >= PGMMODE_32_BIT && PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
     377
    376378    /*
    377379     * Iterate mappings.
    … …  
    401403        return VINF_SUCCESS;
    402404
     405    Assert(PGMGetGuestMode(pVM) >= PGMMODE_32_BIT && PGMGetGuestMode(pVM) <= PGMMODE_PAE_NX);
     406
    403407    /*
    404408     * Iterate mappings.

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r16317 r16376  
    40184018    if (PGMGetHyperCR3(pPool->CTX_SUFF(pVM)) == pPage->Core.Key)
    40194019    {
     4020#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
    40204021        AssertMsg(pPage->enmKind == PGMPOOLKIND_64BIT_PML4,
    40214022                  ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(pPool->CTX_SUFF(pVM)), pPage->Core.Key, pPage->enmKind));
     4023#endif
    40224024        Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%d idx=%d\n", pPage->enmKind, pPage->idx));
    40234025        return VINF_SUCCESS;
    … …  
    42424244    pPage->fReusedFlushPending = false;
    42434245    pPage->fCR3Mix = false;
     4246    pPage->iUser = iUser;
     4247    pPage->iUserTable = iUserTable;
    42444248#ifdef PGMPOOL_WITH_MONITORING
    42454249    pPage->cModifications = 0;
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